* [PATCH v5 0/3] Add riscv semihosting support in u-boot
@ 2022-09-23 7:03 Kautuk Consul
2022-09-23 7:03 ` [PATCH v5 1/3] lib: Add common semihosting library Kautuk Consul
` (3 more replies)
0 siblings, 4 replies; 29+ messages in thread
From: Kautuk Consul @ 2022-09-23 7:03 UTC (permalink / raw)
To: Rayagonda Kokatanur, Sean Anderson, Rick Chen, Leo, Bin Meng,
Simon Glass, Ilias Apalodimas, Alexandru Gagniuc,
Philippe Reynes, Heinrich Schuchardt, Rasmus Villemoes,
Eugen Hristev, Stefan Roese, Loic Poulain, Peng Fan,
Michal Simek
Cc: u-boot, Kautuk Consul
Semihosting is a mechanism that enables code running on
a target to communicate and use the Input/Output
facilities on a host computer that is running a debugger.
This patchset adds support for semihosting in u-boot
for RISCV64 targets.
CHANGES since v4:
- Check arch dependencies for SEMIHOSTING as well as SPL_SEMIHOSTING
config options as per Sean's comment.
- arch/riscv/lib/interrupts.c: Check for post and pre instructions
of the ebreak statement whether they are as per the RISCV
semihosting specification. Only then do a disable_semihosting
and epc += 4 and return.
Compilation and test commands for SPL and S-mode configurations
=================================================================
U-Boot S-mode on QEMU virt
----------------------------
// Compilation of S-mode u-boot
ARCH=riscv
CROSS_COMPILE=riscv64-unknown-linux-gnu-
make qemu-riscv64_smode_defconfig
make
// Run riscv 64-bit u-boot with opensbi on qemu
qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\
opensbi/build/platform/generic/firmware/fw_jump.bin -kernel\
u-boot/u-boot.bin
U-Boot SPL on QEMU virt
------------------------
// Compilation of u-boot-spl
ARCH=riscv
CROSS_COMPILE=riscv64-unknown-linux-gnu-
make qemu-riscv64_spl_defconfig
make OPENSBI=opensbi/build/platform/generic/firmware/fw_dynamic.bin
// Run 64-bit u-boot-spl in qemu
qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\
u-boot/spl/u-boot-spl.bin -device\
loader,file=u-boot/u-boot.itb,addr=0x80200000
Kautuk Consul (3):
lib: Add common semihosting library
arch/riscv: add semihosting support for RISC-V
board: qemu-riscv: enable semihosting
arch/arm/Kconfig | 46 -------
arch/arm/lib/semihosting.c | 181 +-------------------------
arch/riscv/include/asm/spl.h | 1 +
arch/riscv/lib/Makefile | 2 +
arch/riscv/lib/interrupts.c | 25 ++++
arch/riscv/lib/semihosting.c | 24 ++++
configs/qemu-riscv32_defconfig | 4 +
configs/qemu-riscv32_smode_defconfig | 4 +
configs/qemu-riscv32_spl_defconfig | 7 +
configs/qemu-riscv64_defconfig | 4 +
configs/qemu-riscv64_smode_defconfig | 4 +
configs/qemu-riscv64_spl_defconfig | 7 +
include/semihosting.h | 11 ++
lib/Kconfig | 47 +++++++
lib/Makefile | 2 +
lib/semihosting.c | 186 +++++++++++++++++++++++++++
16 files changed, 329 insertions(+), 226 deletions(-)
create mode 100644 arch/riscv/lib/semihosting.c
create mode 100644 lib/semihosting.c
--
2.34.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v5 1/3] lib: Add common semihosting library
2022-09-23 7:03 [PATCH v5 0/3] Add riscv semihosting support in u-boot Kautuk Consul
@ 2022-09-23 7:03 ` Kautuk Consul
2022-10-10 15:39 ` Sean Anderson
2022-09-23 7:03 ` [PATCH v5 2/3] arch/riscv: add semihosting support for RISC-V Kautuk Consul
` (2 subsequent siblings)
3 siblings, 1 reply; 29+ messages in thread
From: Kautuk Consul @ 2022-09-23 7:03 UTC (permalink / raw)
To: Rayagonda Kokatanur, Sean Anderson, Rick Chen, Leo, Bin Meng,
Simon Glass, Ilias Apalodimas, Alexandru Gagniuc,
Philippe Reynes, Heinrich Schuchardt, Rasmus Villemoes,
Eugen Hristev, Stefan Roese, Loic Poulain, Peng Fan,
Michal Simek
Cc: u-boot, Kautuk Consul
We factor out the arch-independent parts of the ARM semihosting
implementation as a common library so that it can be shared
with RISC-V.
Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
---
arch/arm/Kconfig | 46 ---------
arch/arm/lib/semihosting.c | 181 +-----------------------------------
include/semihosting.h | 11 +++
lib/Kconfig | 47 ++++++++++
lib/Makefile | 2 +
lib/semihosting.c | 186 +++++++++++++++++++++++++++++++++++++
6 files changed, 247 insertions(+), 226 deletions(-)
create mode 100644 lib/semihosting.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 82cd456f51..ee6a9fadd9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -413,52 +413,6 @@ config ARM_SMCCC
This should be enabled if U-Boot needs to communicate with system
firmware (for example, PSCI) according to SMCCC.
-config SEMIHOSTING
- bool "Support ARM semihosting"
- help
- Semihosting is a method for a target to communicate with a host
- debugger. It uses special instructions which the debugger will trap
- on and interpret. This allows U-Boot to read/write files, print to
- the console, and execute arbitrary commands on the host system.
-
- Enabling this option will add support for reading and writing files
- on the host system. If you don't have a debugger attached then trying
- to do this will likely cause U-Boot to hang. Say 'n' if you are unsure.
-
-config SEMIHOSTING_FALLBACK
- bool "Recover gracefully when semihosting fails"
- depends on SEMIHOSTING && ARM64
- default y
- help
- Normally, if U-Boot makes a semihosting call and no debugger is
- attached, then it will panic due to a synchronous abort
- exception. This config adds an exception handler which will allow
- U-Boot to recover. Say 'y' if unsure.
-
-config SPL_SEMIHOSTING
- bool "Support ARM semihosting in SPL"
- depends on SPL
- help
- Semihosting is a method for a target to communicate with a host
- debugger. It uses special instructions which the debugger will trap
- on and interpret. This allows U-Boot to read/write files, print to
- the console, and execute arbitrary commands on the host system.
-
- Enabling this option will add support for reading and writing files
- on the host system. If you don't have a debugger attached then trying
- to do this will likely cause U-Boot to hang. Say 'n' if you are unsure.
-
-config SPL_SEMIHOSTING_FALLBACK
- bool "Recover gracefully when semihosting fails in SPL"
- depends on SPL_SEMIHOSTING && ARM64
- select ARMV8_SPL_EXCEPTION_VECTORS
- default y
- help
- Normally, if U-Boot makes a semihosting call and no debugger is
- attached, then it will panic due to a synchronous abort
- exception. This config adds an exception handler which will allow
- U-Boot to recover. Say 'y' if unsure.
-
config SYS_THUMB_BUILD
bool "Build U-Boot using the Thumb instruction set"
depends on !ARM64
diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c
index 01d652a6b8..11e7b85ee6 100644
--- a/arch/arm/lib/semihosting.c
+++ b/arch/arm/lib/semihosting.c
@@ -10,25 +10,11 @@
* available in silicon now, fastmodel usage makes less sense for them.
*/
#include <common.h>
-#include <log.h>
-#include <semihosting.h>
-
-#define SYSOPEN 0x01
-#define SYSCLOSE 0x02
-#define SYSWRITEC 0x03
-#define SYSWRITE0 0x04
-#define SYSWRITE 0x05
-#define SYSREAD 0x06
-#define SYSREADC 0x07
-#define SYSISERROR 0x08
-#define SYSSEEK 0x0A
-#define SYSFLEN 0x0C
-#define SYSERRNO 0x13
/*
* Call the handler
*/
-static noinline long smh_trap(unsigned int sysnum, void *addr)
+long smh_trap(unsigned int sysnum, void *addr)
{
register long result asm("r0");
#if defined(CONFIG_ARM64)
@@ -41,168 +27,3 @@ static noinline long smh_trap(unsigned int sysnum, void *addr)
#endif
return result;
}
-
-#if CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK)
-static bool _semihosting_enabled = true;
-static bool try_semihosting = true;
-
-bool semihosting_enabled(void)
-{
- if (try_semihosting) {
- smh_trap(SYSERRNO, NULL);
- try_semihosting = false;
- }
-
- return _semihosting_enabled;
-}
-
-void disable_semihosting(void)
-{
- _semihosting_enabled = false;
-}
-#endif
-
-/**
- * smh_errno() - Read the host's errno
- *
- * This gets the value of the host's errno and negates it. The host's errno may
- * or may not be set, so only call this function if a previous semihosting call
- * has failed.
- *
- * Return: a negative error value
- */
-static int smh_errno(void)
-{
- long ret = smh_trap(SYSERRNO, NULL);
-
- if (ret > 0 && ret < INT_MAX)
- return -ret;
- return -EIO;
-}
-
-long smh_open(const char *fname, enum smh_open_mode mode)
-{
- long fd;
- struct smh_open_s {
- const char *fname;
- unsigned long mode;
- size_t len;
- } open;
-
- debug("%s: file \'%s\', mode \'%u\'\n", __func__, fname, mode);
-
- open.fname = fname;
- open.len = strlen(fname);
- open.mode = mode;
-
- /* Open the file on the host */
- fd = smh_trap(SYSOPEN, &open);
- if (fd == -1)
- return smh_errno();
- return fd;
-}
-
-/**
- * struct smg_rdwr_s - Arguments for read and write
- * @fd: A file descriptor returned from smh_open()
- * @memp: Pointer to a buffer of memory of at least @len bytes
- * @len: The number of bytes to read or write
- */
-struct smh_rdwr_s {
- long fd;
- void *memp;
- size_t len;
-};
-
-long smh_read(long fd, void *memp, size_t len)
-{
- long ret;
- struct smh_rdwr_s read;
-
- debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len);
-
- read.fd = fd;
- read.memp = memp;
- read.len = len;
-
- ret = smh_trap(SYSREAD, &read);
- if (ret < 0)
- return smh_errno();
- return len - ret;
-}
-
-long smh_write(long fd, const void *memp, size_t len, ulong *written)
-{
- long ret;
- struct smh_rdwr_s write;
-
- debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len);
-
- write.fd = fd;
- write.memp = (void *)memp;
- write.len = len;
-
- ret = smh_trap(SYSWRITE, &write);
- *written = len - ret;
- if (ret)
- return smh_errno();
- return 0;
-}
-
-long smh_close(long fd)
-{
- long ret;
-
- debug("%s: fd %ld\n", __func__, fd);
-
- ret = smh_trap(SYSCLOSE, &fd);
- if (ret == -1)
- return smh_errno();
- return 0;
-}
-
-long smh_flen(long fd)
-{
- long ret;
-
- debug("%s: fd %ld\n", __func__, fd);
-
- ret = smh_trap(SYSFLEN, &fd);
- if (ret == -1)
- return smh_errno();
- return ret;
-}
-
-long smh_seek(long fd, long pos)
-{
- long ret;
- struct smh_seek_s {
- long fd;
- long pos;
- } seek;
-
- debug("%s: fd %ld pos %ld\n", __func__, fd, pos);
-
- seek.fd = fd;
- seek.pos = pos;
-
- ret = smh_trap(SYSSEEK, &seek);
- if (ret)
- return smh_errno();
- return 0;
-}
-
-int smh_getc(void)
-{
- return smh_trap(SYSREADC, NULL);
-}
-
-void smh_putc(char ch)
-{
- smh_trap(SYSWRITEC, &ch);
-}
-
-void smh_puts(const char *s)
-{
- smh_trap(SYSWRITE0, (char *)s);
-}
diff --git a/include/semihosting.h b/include/semihosting.h
index f1f73464e4..4e844cbad8 100644
--- a/include/semihosting.h
+++ b/include/semihosting.h
@@ -17,6 +17,17 @@
#define SMH_T32_SVC 0xDFAB
#define SMH_T32_HLT 0xBABC
+/**
+ * smh_trap() - ARCH-specific semihosting call.
+ *
+ * Semihosting library/driver can use this function to do the
+ * actual semihosting calls.
+ *
+ * Return: Error code defined by semihosting spec.
+ */
+
+long smh_trap(unsigned int sysnum, void *addr);
+
#if CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK)
/**
* semihosting_enabled() - Determine whether semihosting is supported
diff --git a/lib/Kconfig b/lib/Kconfig
index 6121c80dc8..de7e797f11 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -71,6 +71,53 @@ config HAVE_PRIVATE_LIBGCC
config LIB_UUID
bool
+config SEMIHOSTING
+ bool "Support semihosting"
+ depends on ARM
+ help
+ Semihosting is a method for a target to communicate with a host
+ debugger. It uses special instructions which the debugger will trap
+ on and interpret. This allows U-Boot to read/write files, print to
+ the console, and execute arbitrary commands on the host system.
+
+ Enabling this option will add support for reading and writing files
+ on the host system. If you don't have a debugger attached then trying
+ to do this will likely cause U-Boot to hang. Say 'n' if you are unsure.
+
+config SEMIHOSTING_FALLBACK
+ bool "Recover gracefully when semihosting fails"
+ depends on SEMIHOSTING && ARM64
+ default y
+ help
+ Normally, if U-Boot makes a semihosting call and no debugger is
+ attached, then it will panic due to a synchronous abort
+ exception. This config adds an exception handler which will allow
+ U-Boot to recover. Say 'y' if unsure.
+
+config SPL_SEMIHOSTING
+ bool "Support semihosting in SPL"
+ depends on SPL && ARM
+ help
+ Semihosting is a method for a target to communicate with a host
+ debugger. It uses special instructions which the debugger will trap
+ on and interpret. This allows U-Boot to read/write files, print to
+ the console, and execute arbitrary commands on the host system.
+
+ Enabling this option will add support for reading and writing files
+ on the host system. If you don't have a debugger attached then trying
+ to do this will likely cause U-Boot to hang. Say 'n' if you are unsure.
+
+config SPL_SEMIHOSTING_FALLBACK
+ bool "Recover gracefully when semihosting fails in SPL"
+ depends on SPL_SEMIHOSTING && ARM64
+ select ARMV8_SPL_EXCEPTION_VECTORS
+ default y
+ help
+ Normally, if U-Boot makes a semihosting call and no debugger is
+ attached, then it will panic due to a synchronous abort
+ exception. This config adds an exception handler which will allow
+ U-Boot to recover. Say 'y' if unsure.
+
config PRINTF
bool
default y
diff --git a/lib/Makefile b/lib/Makefile
index e3deb15287..134c4319cd 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -145,6 +145,8 @@ obj-y += date.o
obj-y += rtc-lib.o
obj-$(CONFIG_LIB_ELF) += elf.o
+obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o
+
#
# Build a fast OID lookup registry from include/linux/oid_registry.h
#
diff --git a/lib/semihosting.c b/lib/semihosting.c
new file mode 100644
index 0000000000..831774e356
--- /dev/null
+++ b/lib/semihosting.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Sean Anderson <sean.anderson@seco.com>
+ * Copyright 2014 Broadcom Corporation
+ */
+
+#include <common.h>
+#include <log.h>
+#include <semihosting.h>
+
+#define SYSOPEN 0x01
+#define SYSCLOSE 0x02
+#define SYSWRITEC 0x03
+#define SYSWRITE0 0x04
+#define SYSWRITE 0x05
+#define SYSREAD 0x06
+#define SYSREADC 0x07
+#define SYSISERROR 0x08
+#define SYSSEEK 0x0A
+#define SYSFLEN 0x0C
+#define SYSERRNO 0x13
+
+#if CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK)
+static bool _semihosting_enabled = true;
+static bool try_semihosting = true;
+
+bool semihosting_enabled(void)
+{
+ if (try_semihosting) {
+ smh_trap(SYSERRNO, NULL);
+ try_semihosting = false;
+ }
+
+ return _semihosting_enabled;
+}
+
+void disable_semihosting(void)
+{
+ _semihosting_enabled = false;
+}
+#endif
+
+/**
+ * smh_errno() - Read the host's errno
+ *
+ * This gets the value of the host's errno and negates it. The host's errno may
+ * or may not be set, so only call this function if a previous semihosting call
+ * has failed.
+ *
+ * Return: a negative error value
+ */
+static int smh_errno(void)
+{
+ long ret = smh_trap(SYSERRNO, NULL);
+
+ if (ret > 0 && ret < INT_MAX)
+ return -ret;
+ return -EIO;
+}
+
+long smh_open(const char *fname, enum smh_open_mode mode)
+{
+ long fd;
+ struct smh_open_s {
+ const char *fname;
+ unsigned long mode;
+ size_t len;
+ } open;
+
+ debug("%s: file \'%s\', mode \'%u\'\n", __func__, fname, mode);
+
+ open.fname = fname;
+ open.len = strlen(fname);
+ open.mode = mode;
+
+ /* Open the file on the host */
+ fd = smh_trap(SYSOPEN, &open);
+ if (fd == -1)
+ return smh_errno();
+ return fd;
+}
+
+/**
+ * struct smg_rdwr_s - Arguments for read and write
+ * @fd: A file descriptor returned from smh_open()
+ * @memp: Pointer to a buffer of memory of at least @len bytes
+ * @len: The number of bytes to read or write
+ */
+struct smh_rdwr_s {
+ long fd;
+ void *memp;
+ size_t len;
+};
+
+long smh_read(long fd, void *memp, size_t len)
+{
+ long ret;
+ struct smh_rdwr_s read;
+
+ debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len);
+
+ read.fd = fd;
+ read.memp = memp;
+ read.len = len;
+
+ ret = smh_trap(SYSREAD, &read);
+ if (ret < 0)
+ return smh_errno();
+ return len - ret;
+}
+
+long smh_write(long fd, const void *memp, size_t len, ulong *written)
+{
+ long ret;
+ struct smh_rdwr_s write;
+
+ debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len);
+
+ write.fd = fd;
+ write.memp = (void *)memp;
+ write.len = len;
+
+ ret = smh_trap(SYSWRITE, &write);
+ *written = len - ret;
+ if (ret)
+ return smh_errno();
+ return 0;
+}
+
+long smh_close(long fd)
+{
+ long ret;
+
+ debug("%s: fd %ld\n", __func__, fd);
+
+ ret = smh_trap(SYSCLOSE, &fd);
+ if (ret == -1)
+ return smh_errno();
+ return 0;
+}
+
+long smh_flen(long fd)
+{
+ long ret;
+
+ debug("%s: fd %ld\n", __func__, fd);
+
+ ret = smh_trap(SYSFLEN, &fd);
+ if (ret == -1)
+ return smh_errno();
+ return ret;
+}
+
+long smh_seek(long fd, long pos)
+{
+ long ret;
+ struct smh_seek_s {
+ long fd;
+ long pos;
+ } seek;
+
+ debug("%s: fd %ld pos %ld\n", __func__, fd, pos);
+
+ seek.fd = fd;
+ seek.pos = pos;
+
+ ret = smh_trap(SYSSEEK, &seek);
+ if (ret)
+ return smh_errno();
+ return 0;
+}
+
+int smh_getc(void)
+{
+ return smh_trap(SYSREADC, NULL);
+}
+
+void smh_putc(char ch)
+{
+ smh_trap(SYSWRITEC, &ch);
+}
+
+void smh_puts(const char *s)
+{
+ smh_trap(SYSWRITE0, (char *)s);
+}
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v5 2/3] arch/riscv: add semihosting support for RISC-V
2022-09-23 7:03 [PATCH v5 0/3] Add riscv semihosting support in u-boot Kautuk Consul
2022-09-23 7:03 ` [PATCH v5 1/3] lib: Add common semihosting library Kautuk Consul
@ 2022-09-23 7:03 ` Kautuk Consul
2022-10-10 15:43 ` Sean Anderson
[not found] ` <HK0PR03MB2994013C655E85AF1F3D2CFBC1229@HK0PR03MB2994.apcprd03.prod.outlook.com>
2022-09-23 7:03 ` [PATCH v5 3/3] board: qemu-riscv: enable semihosting Kautuk Consul
2022-11-29 6:29 ` [PATCH v5 0/3] Add riscv semihosting support in u-boot Kautuk Consul
3 siblings, 2 replies; 29+ messages in thread
From: Kautuk Consul @ 2022-09-23 7:03 UTC (permalink / raw)
To: Rayagonda Kokatanur, Sean Anderson, Rick Chen, Leo, Bin Meng,
Simon Glass, Ilias Apalodimas, Alexandru Gagniuc,
Philippe Reynes, Heinrich Schuchardt, Rasmus Villemoes,
Eugen Hristev, Stefan Roese, Loic Poulain, Peng Fan,
Michal Simek
Cc: u-boot, Kautuk Consul, Anup Patel
We add RISC-V semihosting based serial console for JTAG based early
debugging.
The RISC-V semihosting specification is available at:
https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
---
arch/riscv/include/asm/spl.h | 1 +
arch/riscv/lib/Makefile | 2 ++
arch/riscv/lib/interrupts.c | 25 +++++++++++++++++++++++++
arch/riscv/lib/semihosting.c | 24 ++++++++++++++++++++++++
lib/Kconfig | 10 +++++-----
5 files changed, 57 insertions(+), 5 deletions(-)
create mode 100644 arch/riscv/lib/semihosting.c
diff --git a/arch/riscv/include/asm/spl.h b/arch/riscv/include/asm/spl.h
index e8a94fcb1f..2898a770ee 100644
--- a/arch/riscv/include/asm/spl.h
+++ b/arch/riscv/include/asm/spl.h
@@ -25,6 +25,7 @@ enum {
BOOT_DEVICE_DFU,
BOOT_DEVICE_XIP,
BOOT_DEVICE_BOOTROM,
+ BOOT_DEVICE_SMH,
BOOT_DEVICE_NONE
};
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 06020fcc2a..64e29804c1 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -42,3 +42,5 @@ extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC)
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMMOVE) += memmove.o
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o
+
+obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index 100be2e966..e966afa7e3 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -9,6 +9,7 @@
* Copyright (C) 2019 Sean Anderson <seanga2@gmail.com>
*/
+#include <linux/compat.h>
#include <common.h>
#include <efi_loader.h>
#include <hang.h>
@@ -17,6 +18,7 @@
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/encoding.h>
+#include <semihosting.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -149,6 +151,29 @@ ulong handle_trap(ulong cause, ulong epc, ulong tval, struct pt_regs *regs)
/* An UEFI application may have changed gd. Restore U-Boot's gd. */
efi_restore_gd();
+ if (cause == CAUSE_BREAKPOINT &&
+ CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK)) {
+ ulong pre_addr = epc - 4, post_addr = epc + 4;
+
+ /* Check for prior and post addresses to be in same page. */
+ if ((pre_addr & ~(PAGE_SIZE - 1)) ==
+ (post_addr & ~(PAGE_SIZE - 1))) {
+ u32 pre = *(u32 *)pre_addr;
+ u32 post = *(u32 *)post_addr;
+
+ /* Check for semihosting, i.e.:
+ * slli zero,zero,0x1f
+ * ebreak
+ * srai zero,zero,0x7
+ */
+ if (pre == 0x01f01013 && post == 0x40705013) {
+ disable_semihosting();
+ epc += 4;
+ return epc;
+ }
+ }
+ }
+
is_irq = (cause & MCAUSE_INT);
irq = (cause & ~MCAUSE_INT);
diff --git a/arch/riscv/lib/semihosting.c b/arch/riscv/lib/semihosting.c
new file mode 100644
index 0000000000..d6593b02a6
--- /dev/null
+++ b/arch/riscv/lib/semihosting.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Ventana Micro Systems Inc.
+ */
+
+#include <common.h>
+
+long smh_trap(int sysnum, void *addr)
+{
+ register int ret asm ("a0") = sysnum;
+ register void *param0 asm ("a1") = addr;
+
+ asm volatile (".align 4\n"
+ ".option push\n"
+ ".option norvc\n"
+
+ "slli zero, zero, 0x1f\n"
+ "ebreak\n"
+ "srai zero, zero, 7\n"
+ ".option pop\n"
+ : "+r" (ret) : "r" (param0) : "memory");
+
+ return ret;
+}
diff --git a/lib/Kconfig b/lib/Kconfig
index de7e797f11..2cc556ee8a 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -73,7 +73,7 @@ config LIB_UUID
config SEMIHOSTING
bool "Support semihosting"
- depends on ARM
+ depends on ARM || RISCV
help
Semihosting is a method for a target to communicate with a host
debugger. It uses special instructions which the debugger will trap
@@ -86,7 +86,7 @@ config SEMIHOSTING
config SEMIHOSTING_FALLBACK
bool "Recover gracefully when semihosting fails"
- depends on SEMIHOSTING && ARM64
+ depends on SEMIHOSTING && (ARM64 || RISCV)
default y
help
Normally, if U-Boot makes a semihosting call and no debugger is
@@ -96,7 +96,7 @@ config SEMIHOSTING_FALLBACK
config SPL_SEMIHOSTING
bool "Support semihosting in SPL"
- depends on SPL && ARM
+ depends on SPL && (ARM || RISCV)
help
Semihosting is a method for a target to communicate with a host
debugger. It uses special instructions which the debugger will trap
@@ -109,8 +109,8 @@ config SPL_SEMIHOSTING
config SPL_SEMIHOSTING_FALLBACK
bool "Recover gracefully when semihosting fails in SPL"
- depends on SPL_SEMIHOSTING && ARM64
- select ARMV8_SPL_EXCEPTION_VECTORS
+ depends on SPL_SEMIHOSTING && (ARM64 || RISCV)
+ select ARMV8_SPL_EXCEPTION_VECTORS if ARM64
default y
help
Normally, if U-Boot makes a semihosting call and no debugger is
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v5 3/3] board: qemu-riscv: enable semihosting
2022-09-23 7:03 [PATCH v5 0/3] Add riscv semihosting support in u-boot Kautuk Consul
2022-09-23 7:03 ` [PATCH v5 1/3] lib: Add common semihosting library Kautuk Consul
2022-09-23 7:03 ` [PATCH v5 2/3] arch/riscv: add semihosting support for RISC-V Kautuk Consul
@ 2022-09-23 7:03 ` Kautuk Consul
2022-10-05 6:17 ` Leo Liang
` (2 more replies)
2022-11-29 6:29 ` [PATCH v5 0/3] Add riscv semihosting support in u-boot Kautuk Consul
3 siblings, 3 replies; 29+ messages in thread
From: Kautuk Consul @ 2022-09-23 7:03 UTC (permalink / raw)
To: Rayagonda Kokatanur, Sean Anderson, Rick Chen, Leo, Bin Meng,
Simon Glass, Ilias Apalodimas, Alexandru Gagniuc,
Philippe Reynes, Heinrich Schuchardt, Rasmus Villemoes,
Eugen Hristev, Stefan Roese, Loic Poulain, Peng Fan,
Michal Simek
Cc: u-boot, Kautuk Consul
To enable semihosting we also need to enable the following
configs in defconfigs:
CONFIG_SEMIHOSTING
CONFIG_SPL_SEMIHOSTING
CONFIG_SEMIHOSTING_SERIAL
CONFIG_SERIAL_PROBE_ALL
CONFIG_SPL_FS_EXT4
CONFIG_SPL_FS_FAT
Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
---
configs/qemu-riscv32_defconfig | 4 ++++
configs/qemu-riscv32_smode_defconfig | 4 ++++
configs/qemu-riscv32_spl_defconfig | 7 +++++++
configs/qemu-riscv64_defconfig | 4 ++++
configs/qemu-riscv64_smode_defconfig | 4 ++++
configs/qemu-riscv64_spl_defconfig | 7 +++++++
6 files changed, 30 insertions(+)
diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig
index 9634d7f77f..4961652548 100644
--- a/configs/qemu-riscv32_defconfig
+++ b/configs/qemu-riscv32_defconfig
@@ -1,4 +1,5 @@
CONFIG_RISCV=y
+CONFIG_SEMIHOSTING=y
CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
@@ -20,3 +21,6 @@ CONFIG_CMD_NVEDIT_EFI=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_SYS_MAX_FLASH_BANKS=2
+# CONFIG_SERIAL_PUTS is not set
+CONFIG_SERIAL_PROBE_ALL=y
+CONFIG_SEMIHOSTING_SERIAL=y
diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig
index 1c5a0617aa..91e4ffebc2 100644
--- a/configs/qemu-riscv32_smode_defconfig
+++ b/configs/qemu-riscv32_smode_defconfig
@@ -1,4 +1,5 @@
CONFIG_RISCV=y
+CONFIG_SEMIHOSTING=y
CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
@@ -21,4 +22,7 @@ CONFIG_CMD_NVEDIT_EFI=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_SYS_MAX_FLASH_BANKS=2
+# CONFIG_SERIAL_PUTS is not set
+CONFIG_SERIAL_PROBE_ALL=y
+CONFIG_SEMIHOSTING_SERIAL=y
CONFIG_SYSRESET_SBI=y
diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig
index 2421c9a371..5fd28fc58c 100644
--- a/configs/qemu-riscv32_spl_defconfig
+++ b/configs/qemu-riscv32_spl_defconfig
@@ -1,9 +1,12 @@
CONFIG_RISCV=y
+CONFIG_SEMIHOSTING=y
+CONFIG_SPL_SEMIHOSTING=y
CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32"
CONFIG_SPL=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_RISCV_SMODE=y
@@ -18,6 +21,7 @@ CONFIG_DISPLAY_BOARDINFO=y
CONFIG_SPL_MAX_SIZE=0x100000
CONFIG_SPL_BSS_START_ADDR=0x84000000
CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x4000000
@@ -25,5 +29,8 @@ CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_SYS_MAX_FLASH_BANKS=2
+# CONFIG_SERIAL_PUTS is not set
+CONFIG_SERIAL_PROBE_ALL=y
+CONFIG_SEMIHOSTING_SERIAL=y
CONFIG_SYSRESET_SBI=y
# CONFIG_BINMAN_FDT is not set
diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig
index d5eae95c80..87478f4481 100644
--- a/configs/qemu-riscv64_defconfig
+++ b/configs/qemu-riscv64_defconfig
@@ -1,4 +1,5 @@
CONFIG_RISCV=y
+CONFIG_SEMIHOSTING=y
CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
@@ -21,3 +22,6 @@ CONFIG_CMD_NVEDIT_EFI=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_SYS_MAX_FLASH_BANKS=2
+# CONFIG_SERIAL_PUTS is not set
+CONFIG_SERIAL_PROBE_ALL=y
+CONFIG_SEMIHOSTING_SERIAL=y
diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig
index 2861d07f97..5e9d6af3be 100644
--- a/configs/qemu-riscv64_smode_defconfig
+++ b/configs/qemu-riscv64_smode_defconfig
@@ -1,4 +1,5 @@
CONFIG_RISCV=y
+CONFIG_SEMIHOSTING=y
CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
@@ -24,4 +25,7 @@ CONFIG_CMD_NVEDIT_EFI=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_SYS_MAX_FLASH_BANKS=2
+# CONFIG_SERIAL_PUTS is not set
+CONFIG_SERIAL_PROBE_ALL=y
+CONFIG_SEMIHOSTING_SERIAL=y
CONFIG_SYSRESET_SBI=y
diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig
index 1ecfa27ce2..e5d817b783 100644
--- a/configs/qemu-riscv64_spl_defconfig
+++ b/configs/qemu-riscv64_spl_defconfig
@@ -1,9 +1,12 @@
CONFIG_RISCV=y
+CONFIG_SEMIHOSTING=y
+CONFIG_SPL_SEMIHOSTING=y
CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64"
CONFIG_SPL=y
+CONFIG_SPL_FS_FAT=y
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_ARCH_RV64I=y
@@ -18,6 +21,7 @@ CONFIG_DISPLAY_BOARDINFO=y
CONFIG_SPL_MAX_SIZE=0x100000
CONFIG_SPL_BSS_START_ADDR=0x84000000
CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_FS_EXT4=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x4000000
@@ -25,5 +29,8 @@ CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_SYS_MAX_FLASH_BANKS=2
+# CONFIG_SERIAL_PUTS is not set
+CONFIG_SERIAL_PROBE_ALL=y
+CONFIG_SEMIHOSTING_SERIAL=y
CONFIG_SYSRESET_SBI=y
# CONFIG_BINMAN_FDT is not set
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* Re: [PATCH v5 3/3] board: qemu-riscv: enable semihosting
2022-09-23 7:03 ` [PATCH v5 3/3] board: qemu-riscv: enable semihosting Kautuk Consul
@ 2022-10-05 6:17 ` Leo Liang
2022-10-06 5:13 ` Kautuk Consul
[not found] ` <HK0PR03MB29949257906C387D549119EBC1229@HK0PR03MB2994.apcprd03.prod.outlook.com>
2022-12-03 4:14 ` Bin Meng
2 siblings, 1 reply; 29+ messages in thread
From: Leo Liang @ 2022-10-05 6:17 UTC (permalink / raw)
To: Kautuk Consul
Cc: Rayagonda Kokatanur, Sean Anderson, Rick Chen, Bin Meng,
Simon Glass, Ilias Apalodimas, Alexandru Gagniuc,
Philippe Reynes, Heinrich Schuchardt, Rasmus Villemoes,
Eugen Hristev, Stefan Roese, Loic Poulain, Peng Fan,
Michal Simek, u-boot
Hi Kautuk,
On Fri, Sep 23, 2022 at 12:33:20PM +0530, Kautuk Consul wrote:
> To enable semihosting we also need to enable the following
> configs in defconfigs:
> CONFIG_SEMIHOSTING
> CONFIG_SPL_SEMIHOSTING
> CONFIG_SEMIHOSTING_SERIAL
> CONFIG_SERIAL_PROBE_ALL
> CONFIG_SPL_FS_EXT4
> CONFIG_SPL_FS_FAT
>
> Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
> ---
> configs/qemu-riscv32_defconfig | 4 ++++
> configs/qemu-riscv32_smode_defconfig | 4 ++++
> configs/qemu-riscv32_spl_defconfig | 7 +++++++
> configs/qemu-riscv64_defconfig | 4 ++++
> configs/qemu-riscv64_smode_defconfig | 4 ++++
> configs/qemu-riscv64_spl_defconfig | 7 +++++++
> 6 files changed, 30 insertions(+)
This patch set seems to cause some CI error.
(https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13667)
Could you please take a look at it?
Besides, will anything go wrong if we do not attach a debugger but enable semihosting on qemu?
Best regards,
Leo
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v5 3/3] board: qemu-riscv: enable semihosting
2022-10-05 6:17 ` Leo Liang
@ 2022-10-06 5:13 ` Kautuk Consul
0 siblings, 0 replies; 29+ messages in thread
From: Kautuk Consul @ 2022-10-06 5:13 UTC (permalink / raw)
To: Leo Liang
Cc: Rayagonda Kokatanur, Sean Anderson, Rick Chen, Bin Meng,
Simon Glass, Ilias Apalodimas, Alexandru Gagniuc,
Philippe Reynes, Heinrich Schuchardt, Rasmus Villemoes,
Eugen Hristev, Stefan Roese, Loic Poulain, Peng Fan,
Michal Simek, u-boot
Hi Leo,
I took a look at the raw log.
It seems that the test-case is outputting too many characters onto the
u-boot prompt
due to which the log size has gotten exceeded. Can you somehow increase the log
size and then try ?
Thanks.
On Wed, Oct 5, 2022 at 11:47 AM Leo Liang <ycliang@andestech.com> wrote:
>
> Hi Kautuk,
>
> On Fri, Sep 23, 2022 at 12:33:20PM +0530, Kautuk Consul wrote:
> > To enable semihosting we also need to enable the following
> > configs in defconfigs:
> > CONFIG_SEMIHOSTING
> > CONFIG_SPL_SEMIHOSTING
> > CONFIG_SEMIHOSTING_SERIAL
> > CONFIG_SERIAL_PROBE_ALL
> > CONFIG_SPL_FS_EXT4
> > CONFIG_SPL_FS_FAT
> >
> > Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
> > ---
> > configs/qemu-riscv32_defconfig | 4 ++++
> > configs/qemu-riscv32_smode_defconfig | 4 ++++
> > configs/qemu-riscv32_spl_defconfig | 7 +++++++
> > configs/qemu-riscv64_defconfig | 4 ++++
> > configs/qemu-riscv64_smode_defconfig | 4 ++++
> > configs/qemu-riscv64_spl_defconfig | 7 +++++++
> > 6 files changed, 30 insertions(+)
>
> This patch set seems to cause some CI error.
> (https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13667)
> Could you please take a look at it?
>
> Besides, will anything go wrong if we do not attach a debugger but enable semihosting on qemu?
>
> Best regards,
> Leo
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v5 1/3] lib: Add common semihosting library
2022-09-23 7:03 ` [PATCH v5 1/3] lib: Add common semihosting library Kautuk Consul
@ 2022-10-10 15:39 ` Sean Anderson
0 siblings, 0 replies; 29+ messages in thread
From: Sean Anderson @ 2022-10-10 15:39 UTC (permalink / raw)
To: Kautuk Consul, Rayagonda Kokatanur, Rick Chen, Leo, Bin Meng,
Simon Glass, Ilias Apalodimas, Alexandru Gagniuc,
Philippe Reynes, Heinrich Schuchardt, Rasmus Villemoes,
Eugen Hristev, Stefan Roese, Loic Poulain, Peng Fan,
Michal Simek
Cc: u-boot
On 9/23/22 3:03 AM, Kautuk Consul wrote:
> We factor out the arch-independent parts of the ARM semihosting
> implementation as a common library so that it can be shared
> with RISC-V.
>
> Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
> ---
> arch/arm/Kconfig | 46 ---------
> arch/arm/lib/semihosting.c | 181 +-----------------------------------
> include/semihosting.h | 11 +++
> lib/Kconfig | 47 ++++++++++
> lib/Makefile | 2 +
> lib/semihosting.c | 186 +++++++++++++++++++++++++++++++++++++
> 6 files changed, 247 insertions(+), 226 deletions(-)
> create mode 100644 lib/semihosting.c
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 82cd456f51..ee6a9fadd9 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -413,52 +413,6 @@ config ARM_SMCCC
> This should be enabled if U-Boot needs to communicate with system
> firmware (for example, PSCI) according to SMCCC.
>
> -config SEMIHOSTING
> - bool "Support ARM semihosting"
> - help
> - Semihosting is a method for a target to communicate with a host
> - debugger. It uses special instructions which the debugger will trap
> - on and interpret. This allows U-Boot to read/write files, print to
> - the console, and execute arbitrary commands on the host system.
> -
> - Enabling this option will add support for reading and writing files
> - on the host system. If you don't have a debugger attached then trying
> - to do this will likely cause U-Boot to hang. Say 'n' if you are unsure.
> -
> -config SEMIHOSTING_FALLBACK
> - bool "Recover gracefully when semihosting fails"
> - depends on SEMIHOSTING && ARM64
> - default y
> - help
> - Normally, if U-Boot makes a semihosting call and no debugger is
> - attached, then it will panic due to a synchronous abort
> - exception. This config adds an exception handler which will allow
> - U-Boot to recover. Say 'y' if unsure.
> -
> -config SPL_SEMIHOSTING
> - bool "Support ARM semihosting in SPL"
> - depends on SPL
> - help
> - Semihosting is a method for a target to communicate with a host
> - debugger. It uses special instructions which the debugger will trap
> - on and interpret. This allows U-Boot to read/write files, print to
> - the console, and execute arbitrary commands on the host system.
> -
> - Enabling this option will add support for reading and writing files
> - on the host system. If you don't have a debugger attached then trying
> - to do this will likely cause U-Boot to hang. Say 'n' if you are unsure.
> -
> -config SPL_SEMIHOSTING_FALLBACK
> - bool "Recover gracefully when semihosting fails in SPL"
> - depends on SPL_SEMIHOSTING && ARM64
> - select ARMV8_SPL_EXCEPTION_VECTORS
> - default y
> - help
> - Normally, if U-Boot makes a semihosting call and no debugger is
> - attached, then it will panic due to a synchronous abort
> - exception. This config adds an exception handler which will allow
> - U-Boot to recover. Say 'y' if unsure.
> -
> config SYS_THUMB_BUILD
> bool "Build U-Boot using the Thumb instruction set"
> depends on !ARM64
> diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c
> index 01d652a6b8..11e7b85ee6 100644
> --- a/arch/arm/lib/semihosting.c
> +++ b/arch/arm/lib/semihosting.c
> @@ -10,25 +10,11 @@
> * available in silicon now, fastmodel usage makes less sense for them.
> */
> #include <common.h>
> -#include <log.h>
> -#include <semihosting.h>
> -
> -#define SYSOPEN 0x01
> -#define SYSCLOSE 0x02
> -#define SYSWRITEC 0x03
> -#define SYSWRITE0 0x04
> -#define SYSWRITE 0x05
> -#define SYSREAD 0x06
> -#define SYSREADC 0x07
> -#define SYSISERROR 0x08
> -#define SYSSEEK 0x0A
> -#define SYSFLEN 0x0C
> -#define SYSERRNO 0x13
>
> /*
> * Call the handler
> */
> -static noinline long smh_trap(unsigned int sysnum, void *addr)
> +long smh_trap(unsigned int sysnum, void *addr)
> {
> register long result asm("r0");
> #if defined(CONFIG_ARM64)
> @@ -41,168 +27,3 @@ static noinline long smh_trap(unsigned int sysnum, void *addr)
> #endif
> return result;
> }
> -
> -#if CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK)
> -static bool _semihosting_enabled = true;
> -static bool try_semihosting = true;
> -
> -bool semihosting_enabled(void)
> -{
> - if (try_semihosting) {
> - smh_trap(SYSERRNO, NULL);
> - try_semihosting = false;
> - }
> -
> - return _semihosting_enabled;
> -}
> -
> -void disable_semihosting(void)
> -{
> - _semihosting_enabled = false;
> -}
> -#endif
> -
> -/**
> - * smh_errno() - Read the host's errno
> - *
> - * This gets the value of the host's errno and negates it. The host's errno may
> - * or may not be set, so only call this function if a previous semihosting call
> - * has failed.
> - *
> - * Return: a negative error value
> - */
> -static int smh_errno(void)
> -{
> - long ret = smh_trap(SYSERRNO, NULL);
> -
> - if (ret > 0 && ret < INT_MAX)
> - return -ret;
> - return -EIO;
> -}
> -
> -long smh_open(const char *fname, enum smh_open_mode mode)
> -{
> - long fd;
> - struct smh_open_s {
> - const char *fname;
> - unsigned long mode;
> - size_t len;
> - } open;
> -
> - debug("%s: file \'%s\', mode \'%u\'\n", __func__, fname, mode);
> -
> - open.fname = fname;
> - open.len = strlen(fname);
> - open.mode = mode;
> -
> - /* Open the file on the host */
> - fd = smh_trap(SYSOPEN, &open);
> - if (fd == -1)
> - return smh_errno();
> - return fd;
> -}
> -
> -/**
> - * struct smg_rdwr_s - Arguments for read and write
> - * @fd: A file descriptor returned from smh_open()
> - * @memp: Pointer to a buffer of memory of at least @len bytes
> - * @len: The number of bytes to read or write
> - */
> -struct smh_rdwr_s {
> - long fd;
> - void *memp;
> - size_t len;
> -};
> -
> -long smh_read(long fd, void *memp, size_t len)
> -{
> - long ret;
> - struct smh_rdwr_s read;
> -
> - debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len);
> -
> - read.fd = fd;
> - read.memp = memp;
> - read.len = len;
> -
> - ret = smh_trap(SYSREAD, &read);
> - if (ret < 0)
> - return smh_errno();
> - return len - ret;
> -}
> -
> -long smh_write(long fd, const void *memp, size_t len, ulong *written)
> -{
> - long ret;
> - struct smh_rdwr_s write;
> -
> - debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len);
> -
> - write.fd = fd;
> - write.memp = (void *)memp;
> - write.len = len;
> -
> - ret = smh_trap(SYSWRITE, &write);
> - *written = len - ret;
> - if (ret)
> - return smh_errno();
> - return 0;
> -}
> -
> -long smh_close(long fd)
> -{
> - long ret;
> -
> - debug("%s: fd %ld\n", __func__, fd);
> -
> - ret = smh_trap(SYSCLOSE, &fd);
> - if (ret == -1)
> - return smh_errno();
> - return 0;
> -}
> -
> -long smh_flen(long fd)
> -{
> - long ret;
> -
> - debug("%s: fd %ld\n", __func__, fd);
> -
> - ret = smh_trap(SYSFLEN, &fd);
> - if (ret == -1)
> - return smh_errno();
> - return ret;
> -}
> -
> -long smh_seek(long fd, long pos)
> -{
> - long ret;
> - struct smh_seek_s {
> - long fd;
> - long pos;
> - } seek;
> -
> - debug("%s: fd %ld pos %ld\n", __func__, fd, pos);
> -
> - seek.fd = fd;
> - seek.pos = pos;
> -
> - ret = smh_trap(SYSSEEK, &seek);
> - if (ret)
> - return smh_errno();
> - return 0;
> -}
> -
> -int smh_getc(void)
> -{
> - return smh_trap(SYSREADC, NULL);
> -}
> -
> -void smh_putc(char ch)
> -{
> - smh_trap(SYSWRITEC, &ch);
> -}
> -
> -void smh_puts(const char *s)
> -{
> - smh_trap(SYSWRITE0, (char *)s);
> -}
> diff --git a/include/semihosting.h b/include/semihosting.h
> index f1f73464e4..4e844cbad8 100644
> --- a/include/semihosting.h
> +++ b/include/semihosting.h
> @@ -17,6 +17,17 @@
> #define SMH_T32_SVC 0xDFAB
> #define SMH_T32_HLT 0xBABC
>
> +/**
> + * smh_trap() - ARCH-specific semihosting call.
> + *
> + * Semihosting library/driver can use this function to do the
> + * actual semihosting calls.
> + *
> + * Return: Error code defined by semihosting spec.
> + */
> +
> +long smh_trap(unsigned int sysnum, void *addr);
> +
> #if CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK)
> /**
> * semihosting_enabled() - Determine whether semihosting is supported
> diff --git a/lib/Kconfig b/lib/Kconfig
> index 6121c80dc8..de7e797f11 100644
> --- a/lib/Kconfig
> +++ b/lib/Kconfig
> @@ -71,6 +71,53 @@ config HAVE_PRIVATE_LIBGCC
> config LIB_UUID
> bool
>
> +config SEMIHOSTING
> + bool "Support semihosting"
> + depends on ARM
> + help
> + Semihosting is a method for a target to communicate with a host
> + debugger. It uses special instructions which the debugger will trap
> + on and interpret. This allows U-Boot to read/write files, print to
> + the console, and execute arbitrary commands on the host system.
> +
> + Enabling this option will add support for reading and writing files
> + on the host system. If you don't have a debugger attached then trying
> + to do this will likely cause U-Boot to hang. Say 'n' if you are unsure.
> +
> +config SEMIHOSTING_FALLBACK
> + bool "Recover gracefully when semihosting fails"
> + depends on SEMIHOSTING && ARM64
> + default y
> + help
> + Normally, if U-Boot makes a semihosting call and no debugger is
> + attached, then it will panic due to a synchronous abort
> + exception. This config adds an exception handler which will allow
> + U-Boot to recover. Say 'y' if unsure.
> +
> +config SPL_SEMIHOSTING
> + bool "Support semihosting in SPL"
> + depends on SPL && ARM
> + help
> + Semihosting is a method for a target to communicate with a host
> + debugger. It uses special instructions which the debugger will trap
> + on and interpret. This allows U-Boot to read/write files, print to
> + the console, and execute arbitrary commands on the host system.
> +
> + Enabling this option will add support for reading and writing files
> + on the host system. If you don't have a debugger attached then trying
> + to do this will likely cause U-Boot to hang. Say 'n' if you are unsure.
> +
> +config SPL_SEMIHOSTING_FALLBACK
> + bool "Recover gracefully when semihosting fails in SPL"
> + depends on SPL_SEMIHOSTING && ARM64
> + select ARMV8_SPL_EXCEPTION_VECTORS
> + default y
> + help
> + Normally, if U-Boot makes a semihosting call and no debugger is
> + attached, then it will panic due to a synchronous abort
> + exception. This config adds an exception handler which will allow
> + U-Boot to recover. Say 'y' if unsure.
> +
> config PRINTF
> bool
> default y
> diff --git a/lib/Makefile b/lib/Makefile
> index e3deb15287..134c4319cd 100644
> --- a/lib/Makefile
> +++ b/lib/Makefile
> @@ -145,6 +145,8 @@ obj-y += date.o
> obj-y += rtc-lib.o
> obj-$(CONFIG_LIB_ELF) += elf.o
>
> +obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o
> +
> #
> # Build a fast OID lookup registry from include/linux/oid_registry.h
> #
> diff --git a/lib/semihosting.c b/lib/semihosting.c
> new file mode 100644
> index 0000000000..831774e356
> --- /dev/null
> +++ b/lib/semihosting.c
> @@ -0,0 +1,186 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2022 Sean Anderson <sean.anderson@seco.com>
> + * Copyright 2014 Broadcom Corporation
> + */
> +
> +#include <common.h>
> +#include <log.h>
> +#include <semihosting.h>
> +
> +#define SYSOPEN 0x01
> +#define SYSCLOSE 0x02
> +#define SYSWRITEC 0x03
> +#define SYSWRITE0 0x04
> +#define SYSWRITE 0x05
> +#define SYSREAD 0x06
> +#define SYSREADC 0x07
> +#define SYSISERROR 0x08
> +#define SYSSEEK 0x0A
> +#define SYSFLEN 0x0C
> +#define SYSERRNO 0x13
> +
> +#if CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK)
> +static bool _semihosting_enabled = true;
> +static bool try_semihosting = true;
> +
> +bool semihosting_enabled(void)
> +{
> + if (try_semihosting) {
> + smh_trap(SYSERRNO, NULL);
> + try_semihosting = false;
> + }
> +
> + return _semihosting_enabled;
> +}
> +
> +void disable_semihosting(void)
> +{
> + _semihosting_enabled = false;
> +}
> +#endif
> +
> +/**
> + * smh_errno() - Read the host's errno
> + *
> + * This gets the value of the host's errno and negates it. The host's errno may
> + * or may not be set, so only call this function if a previous semihosting call
> + * has failed.
> + *
> + * Return: a negative error value
> + */
> +static int smh_errno(void)
> +{
> + long ret = smh_trap(SYSERRNO, NULL);
> +
> + if (ret > 0 && ret < INT_MAX)
> + return -ret;
> + return -EIO;
> +}
> +
> +long smh_open(const char *fname, enum smh_open_mode mode)
> +{
> + long fd;
> + struct smh_open_s {
> + const char *fname;
> + unsigned long mode;
> + size_t len;
> + } open;
> +
> + debug("%s: file \'%s\', mode \'%u\'\n", __func__, fname, mode);
> +
> + open.fname = fname;
> + open.len = strlen(fname);
> + open.mode = mode;
> +
> + /* Open the file on the host */
> + fd = smh_trap(SYSOPEN, &open);
> + if (fd == -1)
> + return smh_errno();
> + return fd;
> +}
> +
> +/**
> + * struct smg_rdwr_s - Arguments for read and write
> + * @fd: A file descriptor returned from smh_open()
> + * @memp: Pointer to a buffer of memory of at least @len bytes
> + * @len: The number of bytes to read or write
> + */
> +struct smh_rdwr_s {
> + long fd;
> + void *memp;
> + size_t len;
> +};
> +
> +long smh_read(long fd, void *memp, size_t len)
> +{
> + long ret;
> + struct smh_rdwr_s read;
> +
> + debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len);
> +
> + read.fd = fd;
> + read.memp = memp;
> + read.len = len;
> +
> + ret = smh_trap(SYSREAD, &read);
> + if (ret < 0)
> + return smh_errno();
> + return len - ret;
> +}
> +
> +long smh_write(long fd, const void *memp, size_t len, ulong *written)
> +{
> + long ret;
> + struct smh_rdwr_s write;
> +
> + debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len);
> +
> + write.fd = fd;
> + write.memp = (void *)memp;
> + write.len = len;
> +
> + ret = smh_trap(SYSWRITE, &write);
> + *written = len - ret;
> + if (ret)
> + return smh_errno();
> + return 0;
> +}
> +
> +long smh_close(long fd)
> +{
> + long ret;
> +
> + debug("%s: fd %ld\n", __func__, fd);
> +
> + ret = smh_trap(SYSCLOSE, &fd);
> + if (ret == -1)
> + return smh_errno();
> + return 0;
> +}
> +
> +long smh_flen(long fd)
> +{
> + long ret;
> +
> + debug("%s: fd %ld\n", __func__, fd);
> +
> + ret = smh_trap(SYSFLEN, &fd);
> + if (ret == -1)
> + return smh_errno();
> + return ret;
> +}
> +
> +long smh_seek(long fd, long pos)
> +{
> + long ret;
> + struct smh_seek_s {
> + long fd;
> + long pos;
> + } seek;
> +
> + debug("%s: fd %ld pos %ld\n", __func__, fd, pos);
> +
> + seek.fd = fd;
> + seek.pos = pos;
> +
> + ret = smh_trap(SYSSEEK, &seek);
> + if (ret)
> + return smh_errno();
> + return 0;
> +}
> +
> +int smh_getc(void)
> +{
> + return smh_trap(SYSREADC, NULL);
> +}
> +
> +void smh_putc(char ch)
> +{
> + smh_trap(SYSWRITEC, &ch);
> +}
> +
> +void smh_puts(const char *s)
> +{
> + smh_trap(SYSWRITE0, (char *)s);
> +}
>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v5 2/3] arch/riscv: add semihosting support for RISC-V
2022-09-23 7:03 ` [PATCH v5 2/3] arch/riscv: add semihosting support for RISC-V Kautuk Consul
@ 2022-10-10 15:43 ` Sean Anderson
[not found] ` <HK0PR03MB2994013C655E85AF1F3D2CFBC1229@HK0PR03MB2994.apcprd03.prod.outlook.com>
1 sibling, 0 replies; 29+ messages in thread
From: Sean Anderson @ 2022-10-10 15:43 UTC (permalink / raw)
To: Kautuk Consul, Rayagonda Kokatanur, Rick Chen, Leo, Bin Meng,
Simon Glass, Ilias Apalodimas, Alexandru Gagniuc,
Philippe Reynes, Heinrich Schuchardt, Rasmus Villemoes,
Eugen Hristev, Stefan Roese, Loic Poulain, Peng Fan,
Michal Simek
Cc: u-boot, Anup Patel
On 9/23/22 3:03 AM, Kautuk Consul wrote:
> We add RISC-V semihosting based serial console for JTAG based early
> debugging.
>
> The RISC-V semihosting specification is available at:
> https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
> ---
> arch/riscv/include/asm/spl.h | 1 +
> arch/riscv/lib/Makefile | 2 ++
> arch/riscv/lib/interrupts.c | 25 +++++++++++++++++++++++++
> arch/riscv/lib/semihosting.c | 24 ++++++++++++++++++++++++
> lib/Kconfig | 10 +++++-----
> 5 files changed, 57 insertions(+), 5 deletions(-)
> create mode 100644 arch/riscv/lib/semihosting.c
>
> diff --git a/arch/riscv/include/asm/spl.h b/arch/riscv/include/asm/spl.h
> index e8a94fcb1f..2898a770ee 100644
> --- a/arch/riscv/include/asm/spl.h
> +++ b/arch/riscv/include/asm/spl.h
> @@ -25,6 +25,7 @@ enum {
> BOOT_DEVICE_DFU,
> BOOT_DEVICE_XIP,
> BOOT_DEVICE_BOOTROM,
> + BOOT_DEVICE_SMH,
> BOOT_DEVICE_NONE
> };
>
> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> index 06020fcc2a..64e29804c1 100644
> --- a/arch/riscv/lib/Makefile
> +++ b/arch/riscv/lib/Makefile
> @@ -42,3 +42,5 @@ extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC)
> obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o
> obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMMOVE) += memmove.o
> obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o
> +
> +obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o
> diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
> index 100be2e966..e966afa7e3 100644
> --- a/arch/riscv/lib/interrupts.c
> +++ b/arch/riscv/lib/interrupts.c
> @@ -9,6 +9,7 @@
> * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com>
> */
>
> +#include <linux/compat.h>
> #include <common.h>
> #include <efi_loader.h>
> #include <hang.h>
> @@ -17,6 +18,7 @@
> #include <asm/ptrace.h>
> #include <asm/system.h>
> #include <asm/encoding.h>
> +#include <semihosting.h>
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -149,6 +151,29 @@ ulong handle_trap(ulong cause, ulong epc, ulong tval, struct pt_regs *regs)
> /* An UEFI application may have changed gd. Restore U-Boot's gd. */
> efi_restore_gd();
>
> + if (cause == CAUSE_BREAKPOINT &&
> + CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK)) {
> + ulong pre_addr = epc - 4, post_addr = epc + 4;
> +
> + /* Check for prior and post addresses to be in same page. */
> + if ((pre_addr & ~(PAGE_SIZE - 1)) ==
> + (post_addr & ~(PAGE_SIZE - 1))) {
> + u32 pre = *(u32 *)pre_addr;
> + u32 post = *(u32 *)post_addr;
> +
> + /* Check for semihosting, i.e.:
> + * slli zero,zero,0x1f
> + * ebreak
> + * srai zero,zero,0x7
> + */
> + if (pre == 0x01f01013 && post == 0x40705013) {
> + disable_semihosting();
> + epc += 4;
> + return epc;
> + }
> + }
> + }
> +
> is_irq = (cause & MCAUSE_INT);
> irq = (cause & ~MCAUSE_INT);
>
> diff --git a/arch/riscv/lib/semihosting.c b/arch/riscv/lib/semihosting.c
> new file mode 100644
> index 0000000000..d6593b02a6
> --- /dev/null
> +++ b/arch/riscv/lib/semihosting.c
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2022 Ventana Micro Systems Inc.
> + */
> +
> +#include <common.h>
> +
> +long smh_trap(int sysnum, void *addr)
> +{
> + register int ret asm ("a0") = sysnum;
> + register void *param0 asm ("a1") = addr;
> +
> + asm volatile (".align 4\n"
> + ".option push\n"
> + ".option norvc\n"
> +
> + "slli zero, zero, 0x1f\n"
> + "ebreak\n"
> + "srai zero, zero, 7\n"
> + ".option pop\n"
> + : "+r" (ret) : "r" (param0) : "memory");
> +
> + return ret;
> +}
> diff --git a/lib/Kconfig b/lib/Kconfig
> index de7e797f11..2cc556ee8a 100644
> --- a/lib/Kconfig
> +++ b/lib/Kconfig
> @@ -73,7 +73,7 @@ config LIB_UUID
>
> config SEMIHOSTING
> bool "Support semihosting"
> - depends on ARM
> + depends on ARM || RISCV
> help
> Semihosting is a method for a target to communicate with a host
> debugger. It uses special instructions which the debugger will trap
> @@ -86,7 +86,7 @@ config SEMIHOSTING
>
> config SEMIHOSTING_FALLBACK
> bool "Recover gracefully when semihosting fails"
> - depends on SEMIHOSTING && ARM64
> + depends on SEMIHOSTING && (ARM64 || RISCV)
> default y
> help
> Normally, if U-Boot makes a semihosting call and no debugger is
> @@ -96,7 +96,7 @@ config SEMIHOSTING_FALLBACK
>
> config SPL_SEMIHOSTING
> bool "Support semihosting in SPL"
> - depends on SPL && ARM
> + depends on SPL && (ARM || RISCV)
> help
> Semihosting is a method for a target to communicate with a host
> debugger. It uses special instructions which the debugger will trap
> @@ -109,8 +109,8 @@ config SPL_SEMIHOSTING
>
> config SPL_SEMIHOSTING_FALLBACK
> bool "Recover gracefully when semihosting fails in SPL"
> - depends on SPL_SEMIHOSTING && ARM64
> - select ARMV8_SPL_EXCEPTION_VECTORS
> + depends on SPL_SEMIHOSTING && (ARM64 || RISCV)
> + select ARMV8_SPL_EXCEPTION_VECTORS if ARM64
> default y
> help
> Normally, if U-Boot makes a semihosting call and no debugger is
>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v5 3/3] board: qemu-riscv: enable semihosting
[not found] ` <HK0PR03MB29949257906C387D549119EBC1229@HK0PR03MB2994.apcprd03.prod.outlook.com>
@ 2022-10-12 1:33 ` Rick Chen
0 siblings, 0 replies; 29+ messages in thread
From: Rick Chen @ 2022-10-12 1:33 UTC (permalink / raw)
To: kconsul, rayagonda.kokatanur, sean.anderson, rick, Leo Liang,
Bin Meng, Simon Glass, ilias.apalodimas, mr.nuke.me,
philippe.reynes, Heinrich Schuchardt, rasmus.villemoes,
eugen.hristev, Stefan Roese, loic.poulain, Peng Fan,
michal.simek
Cc: U-Boot Mailing List
> From: Kautuk Consul <kconsul@ventanamicro.com>
> Sent: Friday, September 23, 2022 3:03 PM
> To: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>; Sean Anderson <sean.anderson@seco.com>; Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; Bin Meng <bmeng.cn@gmail.com>; Simon Glass <sjg@chromium.org>; Ilias Apalodimas <ilias.apalodimas@linaro.org>; Alexandru Gagniuc <mr.nuke.me@gmail.com>; Philippe Reynes <philippe.reynes@softathome.com>; Heinrich Schuchardt <xypron.glpk@gmx.de>; Rasmus Villemoes <rasmus.villemoes@prevas.dk>; Eugen Hristev <eugen.hristev@microchip.com>; Stefan Roese <sr@denx.de>; Loic Poulain <loic.poulain@linaro.org>; Peng Fan <peng.fan@nxp.com>; Michal Simek <michal.simek@amd.com>
> Cc: u-boot@lists.denx.de; Kautuk Consul <kconsul@ventanamicro.com>
> Subject: [PATCH v5 3/3] board: qemu-riscv: enable semihosting
>
> To enable semihosting we also need to enable the following configs in defconfigs:
> CONFIG_SEMIHOSTING
> CONFIG_SPL_SEMIHOSTING
> CONFIG_SEMIHOSTING_SERIAL
> CONFIG_SERIAL_PROBE_ALL
> CONFIG_SPL_FS_EXT4
> CONFIG_SPL_FS_FAT
>
> Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
> ---
> configs/qemu-riscv32_defconfig | 4 ++++
> configs/qemu-riscv32_smode_defconfig | 4 ++++
> configs/qemu-riscv32_spl_defconfig | 7 +++++++
> configs/qemu-riscv64_defconfig | 4 ++++
> configs/qemu-riscv64_smode_defconfig | 4 ++++
> configs/qemu-riscv64_spl_defconfig | 7 +++++++
> 6 files changed, 30 insertions(+)
Reviewed-by: Rick Chen <rick@andestech.com>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v5 2/3] arch/riscv: add semihosting support for RISC-V
[not found] ` <HK0PR03MB2994013C655E85AF1F3D2CFBC1229@HK0PR03MB2994.apcprd03.prod.outlook.com>
@ 2022-10-12 1:40 ` Rick Chen
0 siblings, 0 replies; 29+ messages in thread
From: Rick Chen @ 2022-10-12 1:40 UTC (permalink / raw)
To: kconsul, rayagonda.kokatanur, sean.anderson, rick, Leo Liang,
Bin Meng, Simon Glass, ilias.apalodimas, mr.nuke.me,
philippe.reynes, Heinrich Schuchardt
Cc: U-Boot Mailing List, rasmus.villemoes, eugen.hristev,
Stefan Roese, loic.poulain, Peng Fan, michal.simek
> From: Kautuk Consul <kconsul@ventanamicro.com>
> Sent: Friday, September 23, 2022 3:03 PM
> To: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>; Sean Anderson <sean.anderson@seco.com>; Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; Bin Meng <bmeng.cn@gmail.com>; Simon Glass <sjg@chromium.org>; Ilias Apalodimas <ilias.apalodimas@linaro.org>; Alexandru Gagniuc <mr.nuke.me@gmail.com>; Philippe Reynes <philippe.reynes@softathome.com>; Heinrich Schuchardt <xypron.glpk@gmx.de>; Rasmus Villemoes <rasmus.villemoes@prevas.dk>; Eugen Hristev <eugen.hristev@microchip.com>; Stefan Roese <sr@denx.de>; Loic Poulain <loic.poulain@linaro.org>; Peng Fan <peng.fan@nxp.com>; Michal Simek <michal.simek@amd.com>
> Cc: u-boot@lists.denx.de; Kautuk Consul <kconsul@ventanamicro.com>; Anup Patel <apatel@ventanamicro.com>
> Subject: [PATCH v5 2/3] arch/riscv: add semihosting support for RISC-V
>
> We add RISC-V semihosting based serial console for JTAG based early debugging.
>
> The RISC-V semihosting specification is available at:
> https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
> ---
> arch/riscv/include/asm/spl.h | 1 +
> arch/riscv/lib/Makefile | 2 ++
> arch/riscv/lib/interrupts.c | 25 +++++++++++++++++++++++++ arch/riscv/lib/semihosting.c | 24 ++++++++++++++++++++++++
> lib/Kconfig | 10 +++++-----
> 5 files changed, 57 insertions(+), 5 deletions(-) create mode 100644 arch/riscv/lib/semihosting.c
Reviewed-by: Rick Chen <rick@andestech.com>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v5 0/3] Add riscv semihosting support in u-boot
2022-09-23 7:03 [PATCH v5 0/3] Add riscv semihosting support in u-boot Kautuk Consul
` (2 preceding siblings ...)
2022-09-23 7:03 ` [PATCH v5 3/3] board: qemu-riscv: enable semihosting Kautuk Consul
@ 2022-11-29 6:29 ` Kautuk Consul
2022-11-29 6:36 ` Bin Meng
3 siblings, 1 reply; 29+ messages in thread
From: Kautuk Consul @ 2022-11-29 6:29 UTC (permalink / raw)
To: Rayagonda Kokatanur, Sean Anderson, Rick Chen, Leo, Bin Meng,
Simon Glass, Ilias Apalodimas, Alexandru Gagniuc,
Philippe Reynes, Heinrich Schuchardt, Rasmus Villemoes,
Eugen Hristev, Stefan Roese, Loic Poulain, Peng Fan,
Michal Simek
Cc: u-boot
Hi,
Can someone pick this patchset up ?
It has been reviewed and there has been no comment on this in recent days.
Thanks.
On Fri, Sep 23, 2022 at 12:33 PM Kautuk Consul <kconsul@ventanamicro.com>
wrote:
> Semihosting is a mechanism that enables code running on
> a target to communicate and use the Input/Output
> facilities on a host computer that is running a debugger.
> This patchset adds support for semihosting in u-boot
> for RISCV64 targets.
>
> CHANGES since v4:
> - Check arch dependencies for SEMIHOSTING as well as SPL_SEMIHOSTING
> config options as per Sean's comment.
> - arch/riscv/lib/interrupts.c: Check for post and pre instructions
> of the ebreak statement whether they are as per the RISCV
> semihosting specification. Only then do a disable_semihosting
> and epc += 4 and return.
>
> Compilation and test commands for SPL and S-mode configurations
> =================================================================
>
> U-Boot S-mode on QEMU virt
> ----------------------------
> // Compilation of S-mode u-boot
> ARCH=riscv
> CROSS_COMPILE=riscv64-unknown-linux-gnu-
> make qemu-riscv64_smode_defconfig
> make
> // Run riscv 64-bit u-boot with opensbi on qemu
> qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\
> opensbi/build/platform/generic/firmware/fw_jump.bin -kernel\
> u-boot/u-boot.bin
>
> U-Boot SPL on QEMU virt
> ------------------------
> // Compilation of u-boot-spl
> ARCH=riscv
> CROSS_COMPILE=riscv64-unknown-linux-gnu-
> make qemu-riscv64_spl_defconfig
> make OPENSBI=opensbi/build/platform/generic/firmware/fw_dynamic.bin
> // Run 64-bit u-boot-spl in qemu
> qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\
> u-boot/spl/u-boot-spl.bin -device\
> loader,file=u-boot/u-boot.itb,addr=0x80200000
>
> Kautuk Consul (3):
> lib: Add common semihosting library
> arch/riscv: add semihosting support for RISC-V
> board: qemu-riscv: enable semihosting
>
> arch/arm/Kconfig | 46 -------
> arch/arm/lib/semihosting.c | 181 +-------------------------
> arch/riscv/include/asm/spl.h | 1 +
> arch/riscv/lib/Makefile | 2 +
> arch/riscv/lib/interrupts.c | 25 ++++
> arch/riscv/lib/semihosting.c | 24 ++++
> configs/qemu-riscv32_defconfig | 4 +
> configs/qemu-riscv32_smode_defconfig | 4 +
> configs/qemu-riscv32_spl_defconfig | 7 +
> configs/qemu-riscv64_defconfig | 4 +
> configs/qemu-riscv64_smode_defconfig | 4 +
> configs/qemu-riscv64_spl_defconfig | 7 +
> include/semihosting.h | 11 ++
> lib/Kconfig | 47 +++++++
> lib/Makefile | 2 +
> lib/semihosting.c | 186 +++++++++++++++++++++++++++
> 16 files changed, 329 insertions(+), 226 deletions(-)
> create mode 100644 arch/riscv/lib/semihosting.c
> create mode 100644 lib/semihosting.c
>
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v5 0/3] Add riscv semihosting support in u-boot
2022-11-29 6:29 ` [PATCH v5 0/3] Add riscv semihosting support in u-boot Kautuk Consul
@ 2022-11-29 6:36 ` Bin Meng
2022-11-29 6:57 ` Kautuk Consul
0 siblings, 1 reply; 29+ messages in thread
From: Bin Meng @ 2022-11-29 6:36 UTC (permalink / raw)
To: Kautuk Consul
Cc: Rayagonda Kokatanur, Sean Anderson, Rick Chen, Leo, Simon Glass,
Ilias Apalodimas, Alexandru Gagniuc, Philippe Reynes,
Heinrich Schuchardt, Rasmus Villemoes, Eugen Hristev,
Stefan Roese, Loic Poulain, Peng Fan, Michal Simek, u-boot
Hi Kautuk,
On Tue, Nov 29, 2022 at 2:29 PM Kautuk Consul <kconsul@ventanamicro.com> wrote:
>
> Hi,
>
> Can someone pick this patchset up ?
>
> It has been reviewed and there has been no comment on this in recent days.
>
> Thanks.
>
> On Fri, Sep 23, 2022 at 12:33 PM Kautuk Consul <kconsul@ventanamicro.com> wrote:
>>
>> Semihosting is a mechanism that enables code running on
>> a target to communicate and use the Input/Output
>> facilities on a host computer that is running a debugger.
>> This patchset adds support for semihosting in u-boot
>> for RISCV64 targets.
>>
>> CHANGES since v4:
>> - Check arch dependencies for SEMIHOSTING as well as SPL_SEMIHOSTING
>> config options as per Sean's comment.
>> - arch/riscv/lib/interrupts.c: Check for post and pre instructions
>> of the ebreak statement whether they are as per the RISCV
>> semihosting specification. Only then do a disable_semihosting
>> and epc += 4 and return.
>>
>> Compilation and test commands for SPL and S-mode configurations
>> =================================================================
>>
>> U-Boot S-mode on QEMU virt
>> ----------------------------
>> // Compilation of S-mode u-boot
>> ARCH=riscv
>> CROSS_COMPILE=riscv64-unknown-linux-gnu-
>> make qemu-riscv64_smode_defconfig
>> make
>> // Run riscv 64-bit u-boot with opensbi on qemu
>> qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\
>> opensbi/build/platform/generic/firmware/fw_jump.bin -kernel\
>> u-boot/u-boot.bin
>>
>> U-Boot SPL on QEMU virt
>> ------------------------
>> // Compilation of u-boot-spl
>> ARCH=riscv
>> CROSS_COMPILE=riscv64-unknown-linux-gnu-
>> make qemu-riscv64_spl_defconfig
>> make OPENSBI=opensbi/build/platform/generic/firmware/fw_dynamic.bin
>> // Run 64-bit u-boot-spl in qemu
>> qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\
>> u-boot/spl/u-boot-spl.bin -device\
>> loader,file=u-boot/u-boot.itb,addr=0x80200000
>>
Do you have instructions on how to actually test semihosting? Does it
require a JTAG debugger? But I see you are using QEMU?
Regards,
Bin
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v5 0/3] Add riscv semihosting support in u-boot
2022-11-29 6:36 ` Bin Meng
@ 2022-11-29 6:57 ` Kautuk Consul
2022-12-02 8:46 ` Leo Liang
2022-12-03 4:28 ` Bin Meng
0 siblings, 2 replies; 29+ messages in thread
From: Kautuk Consul @ 2022-11-29 6:57 UTC (permalink / raw)
To: Bin Meng
Cc: Rayagonda Kokatanur, Sean Anderson, Rick Chen, Leo, Simon Glass,
Ilias Apalodimas, Alexandru Gagniuc, Philippe Reynes,
Heinrich Schuchardt, Rasmus Villemoes, Eugen Hristev,
Stefan Roese, Loic Poulain, Peng Fan, Michal Simek, u-boot
I have tested it both on Qemu and Ventana's internal simulator.
On Tue, Nov 29, 2022 at 12:06 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Kautuk,
>
> On Tue, Nov 29, 2022 at 2:29 PM Kautuk Consul <kconsul@ventanamicro.com>
> wrote:
> >
> > Hi,
> >
> > Can someone pick this patchset up ?
> >
> > It has been reviewed and there has been no comment on this in recent
> days.
> >
> > Thanks.
> >
> > On Fri, Sep 23, 2022 at 12:33 PM Kautuk Consul <kconsul@ventanamicro.com>
> wrote:
> >>
> >> Semihosting is a mechanism that enables code running on
> >> a target to communicate and use the Input/Output
> >> facilities on a host computer that is running a debugger.
> >> This patchset adds support for semihosting in u-boot
> >> for RISCV64 targets.
> >>
> >> CHANGES since v4:
> >> - Check arch dependencies for SEMIHOSTING as well as
> SPL_SEMIHOSTING
> >> config options as per Sean's comment.
> >> - arch/riscv/lib/interrupts.c: Check for post and pre instructions
> >> of the ebreak statement whether they are as per the RISCV
> >> semihosting specification. Only then do a disable_semihosting
> >> and epc += 4 and return.
> >>
> >> Compilation and test commands for SPL and S-mode configurations
> >> =================================================================
> >>
> >> U-Boot S-mode on QEMU virt
> >> ----------------------------
> >> // Compilation of S-mode u-boot
> >> ARCH=riscv
> >> CROSS_COMPILE=riscv64-unknown-linux-gnu-
> >> make qemu-riscv64_smode_defconfig
> >> make
> >> // Run riscv 64-bit u-boot with opensbi on qemu
> >> qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\
> >> opensbi/build/platform/generic/firmware/fw_jump.bin -kernel\
> >> u-boot/u-boot.bin
> >>
> >> U-Boot SPL on QEMU virt
> >> ------------------------
> >> // Compilation of u-boot-spl
> >> ARCH=riscv
> >> CROSS_COMPILE=riscv64-unknown-linux-gnu-
> >> make qemu-riscv64_spl_defconfig
> >> make OPENSBI=opensbi/build/platform/generic/firmware/fw_dynamic.bin
> >> // Run 64-bit u-boot-spl in qemu
> >> qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\
> >> u-boot/spl/u-boot-spl.bin -device\
> >> loader,file=u-boot/u-boot.itb,addr=0x80200000
> >>
>
> Do you have instructions on how to actually test semihosting? Does it
> require a JTAG debugger? But I see you are using QEMU?
>
> Regards,
> Bin
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v5 0/3] Add riscv semihosting support in u-boot
2022-11-29 6:57 ` Kautuk Consul
@ 2022-12-02 8:46 ` Leo Liang
2022-12-02 9:52 ` Kautuk Consul
2022-12-03 4:28 ` Bin Meng
1 sibling, 1 reply; 29+ messages in thread
From: Leo Liang @ 2022-12-02 8:46 UTC (permalink / raw)
To: Kautuk Consul; +Cc: Bin Meng, Rick Chen, u-boot, peterlin, ycliang
Hi Kautuk,
Sorry for the late reply.
The CI failure still exists and
if tested on QEMU(7.0.0) without a gdb attached,
it is possible that we get weird output on console.[1]
Another thing is that with your patch,
QEMU could not exit with Ctrl a + x.
This might be the reason for CI failure (timeout).
Could you take a look at this?
Yet with a gdb attached, everything works as expected,
So maybe we could disable semihosting as default?
Best regards,
Leo
[1] The weird console output looks like below,
it outputs random character without us typing anything.
U-Boot 2022.10-rc5 (Dec 02 2022 - 16:27:43 +0800)
CPU: rv64imafdcsuh
Model: riscv-virtio,qemu
DRAM: 2 GiB
Core: 35 devices, 15 uclasses, devicetree: board
Flash: 32 MiB
Loading Environment from nowhere... OK
In: serial_semihosting
Out: serial_semihosting
Err: serial_semihosting
Net: eth0: virtio-net#1
Hit any key to stop autoboot: 0
=> 55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555
55555555555555555555555555555555555555555555555555555555555555555555
On Tue, Nov 29, 2022 at 12:27:51PM +0530, Kautuk Consul wrote:
> I have tested it both on Qemu and Ventana's internal simulator.
>
> On Tue, Nov 29, 2022 at 12:06 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> > Hi Kautuk,
> >
> > On Tue, Nov 29, 2022 at 2:29 PM Kautuk Consul <kconsul@ventanamicro.com>
> > wrote:
> > >
> > > Hi,
> > >
> > > Can someone pick this patchset up ?
> > >
> > > It has been reviewed and there has been no comment on this in recent
> > days.
> > >
> > > Thanks.
> > >
> > > On Fri, Sep 23, 2022 at 12:33 PM Kautuk Consul <kconsul@ventanamicro.com>
> > wrote:
> > >>
> > >> Semihosting is a mechanism that enables code running on
> > >> a target to communicate and use the Input/Output
> > >> facilities on a host computer that is running a debugger.
> > >> This patchset adds support for semihosting in u-boot
> > >> for RISCV64 targets.
> > >>
> > >> CHANGES since v4:
> > >> - Check arch dependencies for SEMIHOSTING as well as
> > SPL_SEMIHOSTING
> > >> config options as per Sean's comment.
> > >> - arch/riscv/lib/interrupts.c: Check for post and pre instructions
> > >> of the ebreak statement whether they are as per the RISCV
> > >> semihosting specification. Only then do a disable_semihosting
> > >> and epc += 4 and return.
> > >>
> > >> Compilation and test commands for SPL and S-mode configurations
> > >> =================================================================
> > >>
> > >> U-Boot S-mode on QEMU virt
> > >> ----------------------------
> > >> // Compilation of S-mode u-boot
> > >> ARCH=riscv
> > >> CROSS_COMPILE=riscv64-unknown-linux-gnu-
> > >> make qemu-riscv64_smode_defconfig
> > >> make
> > >> // Run riscv 64-bit u-boot with opensbi on qemu
> > >> qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\
> > >> opensbi/build/platform/generic/firmware/fw_jump.bin -kernel\
> > >> u-boot/u-boot.bin
> > >>
> > >> U-Boot SPL on QEMU virt
> > >> ------------------------
> > >> // Compilation of u-boot-spl
> > >> ARCH=riscv
> > >> CROSS_COMPILE=riscv64-unknown-linux-gnu-
> > >> make qemu-riscv64_spl_defconfig
> > >> make OPENSBI=opensbi/build/platform/generic/firmware/fw_dynamic.bin
> > >> // Run 64-bit u-boot-spl in qemu
> > >> qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\
> > >> u-boot/spl/u-boot-spl.bin -device\
> > >> loader,file=u-boot/u-boot.itb,addr=0x80200000
> > >>
> >
> > Do you have instructions on how to actually test semihosting? Does it
> > require a JTAG debugger? But I see you are using QEMU?
> >
> > Regards,
> > Bin
> >
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v5 0/3] Add riscv semihosting support in u-boot
2022-12-02 8:46 ` Leo Liang
@ 2022-12-02 9:52 ` Kautuk Consul
2022-12-02 12:01 ` Leo Liang
0 siblings, 1 reply; 29+ messages in thread
From: Kautuk Consul @ 2022-12-02 9:52 UTC (permalink / raw)
To: Leo Liang; +Cc: Bin Meng, Rick Chen, u-boot, peterlin
Hi Leo,
What Qemu version are you using.
Can you please try with QEMU 7.1 or later ?
There is a fix which was merged after 7.0.
Thanks.
On Fri, Dec 2, 2022 at 2:16 PM Leo Liang <ycliang@andestech.com> wrote:
> Hi Kautuk,
>
> Sorry for the late reply.
> The CI failure still exists and
> if tested on QEMU(7.0.0) without a gdb attached,
> it is possible that we get weird output on console.[1]
>
> Another thing is that with your patch,
> QEMU could not exit with Ctrl a + x.
> This might be the reason for CI failure (timeout).
> Could you take a look at this?
>
> Yet with a gdb attached, everything works as expected,
> So maybe we could disable semihosting as default?
>
> Best regards,
> Leo
>
> [1] The weird console output looks like below,
> it outputs random character without us typing anything.
>
> U-Boot 2022.10-rc5 (Dec 02 2022 - 16:27:43 +0800)
> CPU: rv64imafdcsuh
> Model: riscv-virtio,qemu
> DRAM: 2 GiB
> Core: 35 devices, 15 uclasses, devicetree: board
> Flash: 32 MiB
> Loading Environment from nowhere... OK
> In: serial_semihosting
> Out: serial_semihosting
> Err: serial_semihosting
> Net: eth0: virtio-net#1
> Hit any key to stop autoboot: 0
> =>
> 55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555
> 55555555555555555555555555555555555555555555555555555555555555555555
>
>
>
> On Tue, Nov 29, 2022 at 12:27:51PM +0530, Kautuk Consul wrote:
> > I have tested it both on Qemu and Ventana's internal simulator.
> >
> > On Tue, Nov 29, 2022 at 12:06 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > > Hi Kautuk,
> > >
> > > On Tue, Nov 29, 2022 at 2:29 PM Kautuk Consul <
> kconsul@ventanamicro.com>
> > > wrote:
> > > >
> > > > Hi,
> > > >
> > > > Can someone pick this patchset up ?
> > > >
> > > > It has been reviewed and there has been no comment on this in recent
> > > days.
> > > >
> > > > Thanks.
> > > >
> > > > On Fri, Sep 23, 2022 at 12:33 PM Kautuk Consul <
> kconsul@ventanamicro.com>
> > > wrote:
> > > >>
> > > >> Semihosting is a mechanism that enables code running on
> > > >> a target to communicate and use the Input/Output
> > > >> facilities on a host computer that is running a debugger.
> > > >> This patchset adds support for semihosting in u-boot
> > > >> for RISCV64 targets.
> > > >>
> > > >> CHANGES since v4:
> > > >> - Check arch dependencies for SEMIHOSTING as well as
> > > SPL_SEMIHOSTING
> > > >> config options as per Sean's comment.
> > > >> - arch/riscv/lib/interrupts.c: Check for post and pre
> instructions
> > > >> of the ebreak statement whether they are as per the RISCV
> > > >> semihosting specification. Only then do a
> disable_semihosting
> > > >> and epc += 4 and return.
> > > >>
> > > >> Compilation and test commands for SPL and S-mode configurations
> > > >> =================================================================
> > > >>
> > > >> U-Boot S-mode on QEMU virt
> > > >> ----------------------------
> > > >> // Compilation of S-mode u-boot
> > > >> ARCH=riscv
> > > >> CROSS_COMPILE=riscv64-unknown-linux-gnu-
> > > >> make qemu-riscv64_smode_defconfig
> > > >> make
> > > >> // Run riscv 64-bit u-boot with opensbi on qemu
> > > >> qemu-system-riscv64 -M virt -m 256M -display none -serial stdio
> -bios\
> > > >> opensbi/build/platform/generic/firmware/fw_jump.bin -kernel\
> > > >> u-boot/u-boot.bin
> > > >>
> > > >> U-Boot SPL on QEMU virt
> > > >> ------------------------
> > > >> // Compilation of u-boot-spl
> > > >> ARCH=riscv
> > > >> CROSS_COMPILE=riscv64-unknown-linux-gnu-
> > > >> make qemu-riscv64_spl_defconfig
> > > >> make OPENSBI=opensbi/build/platform/generic/firmware/fw_dynamic.bin
> > > >> // Run 64-bit u-boot-spl in qemu
> > > >> qemu-system-riscv64 -M virt -m 256M -display none -serial stdio
> -bios\
> > > >> u-boot/spl/u-boot-spl.bin -device\
> > > >> loader,file=u-boot/u-boot.itb,addr=0x80200000
> > > >>
> > >
> > > Do you have instructions on how to actually test semihosting? Does it
> > > require a JTAG debugger? But I see you are using QEMU?
> > >
> > > Regards,
> > > Bin
> > >
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v5 0/3] Add riscv semihosting support in u-boot
2022-12-02 9:52 ` Kautuk Consul
@ 2022-12-02 12:01 ` Leo Liang
0 siblings, 0 replies; 29+ messages in thread
From: Leo Liang @ 2022-12-02 12:01 UTC (permalink / raw)
To: Kautuk Consul; +Cc: Bin Meng, Rick Chen, u-boot, peterlin
Hi Kautuk,
On Fri, Dec 02, 2022 at 03:22:56PM +0530, Kautuk Consul wrote:
> Hi Leo,
>
> What Qemu version are you using.
> Can you please try with QEMU 7.1 or later ?
> There is a fix which was merged after 7.0.
Got it!
I'll try with QEMU 7.1 and see if the issue still exists.
Thanks!
Best regards,
Leo
>
> Thanks.
>
> On Fri, Dec 2, 2022 at 2:16 PM Leo Liang <ycliang@andestech.com> wrote:
>
> > Hi Kautuk,
> >
> > Sorry for the late reply.
> > The CI failure still exists and
> > if tested on QEMU(7.0.0) without a gdb attached,
> > it is possible that we get weird output on console.[1]
> >
> > Another thing is that with your patch,
> > QEMU could not exit with Ctrl a + x.
> > This might be the reason for CI failure (timeout).
> > Could you take a look at this?
> >
> > Yet with a gdb attached, everything works as expected,
> > So maybe we could disable semihosting as default?
> >
> > Best regards,
> > Leo
> >
> > [1] The weird console output looks like below,
> > it outputs random character without us typing anything.
> >
> > U-Boot 2022.10-rc5 (Dec 02 2022 - 16:27:43 +0800)
> > CPU: rv64imafdcsuh
> > Model: riscv-virtio,qemu
> > DRAM: 2 GiB
> > Core: 35 devices, 15 uclasses, devicetree: board
> > Flash: 32 MiB
> > Loading Environment from nowhere... OK
> > In: serial_semihosting
> > Out: serial_semihosting
> > Err: serial_semihosting
> > Net: eth0: virtio-net#1
> > Hit any key to stop autoboot: 0
> > =>
> > 55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555
> > 55555555555555555555555555555555555555555555555555555555555555555555
> >
> >
> >
> > On Tue, Nov 29, 2022 at 12:27:51PM +0530, Kautuk Consul wrote:
> > > I have tested it both on Qemu and Ventana's internal simulator.
> > >
> > > On Tue, Nov 29, 2022 at 12:06 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > > Hi Kautuk,
> > > >
> > > > On Tue, Nov 29, 2022 at 2:29 PM Kautuk Consul <
> > kconsul@ventanamicro.com>
> > > > wrote:
> > > > >
> > > > > Hi,
> > > > >
> > > > > Can someone pick this patchset up ?
> > > > >
> > > > > It has been reviewed and there has been no comment on this in recent
> > > > days.
> > > > >
> > > > > Thanks.
> > > > >
> > > > > On Fri, Sep 23, 2022 at 12:33 PM Kautuk Consul <
> > kconsul@ventanamicro.com>
> > > > wrote:
> > > > >>
> > > > >> Semihosting is a mechanism that enables code running on
> > > > >> a target to communicate and use the Input/Output
> > > > >> facilities on a host computer that is running a debugger.
> > > > >> This patchset adds support for semihosting in u-boot
> > > > >> for RISCV64 targets.
> > > > >>
> > > > >> CHANGES since v4:
> > > > >> - Check arch dependencies for SEMIHOSTING as well as
> > > > SPL_SEMIHOSTING
> > > > >> config options as per Sean's comment.
> > > > >> - arch/riscv/lib/interrupts.c: Check for post and pre
> > instructions
> > > > >> of the ebreak statement whether they are as per the RISCV
> > > > >> semihosting specification. Only then do a
> > disable_semihosting
> > > > >> and epc += 4 and return.
> > > > >>
> > > > >> Compilation and test commands for SPL and S-mode configurations
> > > > >> =================================================================
> > > > >>
> > > > >> U-Boot S-mode on QEMU virt
> > > > >> ----------------------------
> > > > >> // Compilation of S-mode u-boot
> > > > >> ARCH=riscv
> > > > >> CROSS_COMPILE=riscv64-unknown-linux-gnu-
> > > > >> make qemu-riscv64_smode_defconfig
> > > > >> make
> > > > >> // Run riscv 64-bit u-boot with opensbi on qemu
> > > > >> qemu-system-riscv64 -M virt -m 256M -display none -serial stdio
> > -bios\
> > > > >> opensbi/build/platform/generic/firmware/fw_jump.bin -kernel\
> > > > >> u-boot/u-boot.bin
> > > > >>
> > > > >> U-Boot SPL on QEMU virt
> > > > >> ------------------------
> > > > >> // Compilation of u-boot-spl
> > > > >> ARCH=riscv
> > > > >> CROSS_COMPILE=riscv64-unknown-linux-gnu-
> > > > >> make qemu-riscv64_spl_defconfig
> > > > >> make OPENSBI=opensbi/build/platform/generic/firmware/fw_dynamic.bin
> > > > >> // Run 64-bit u-boot-spl in qemu
> > > > >> qemu-system-riscv64 -M virt -m 256M -display none -serial stdio
> > -bios\
> > > > >> u-boot/spl/u-boot-spl.bin -device\
> > > > >> loader,file=u-boot/u-boot.itb,addr=0x80200000
> > > > >>
> > > >
> > > > Do you have instructions on how to actually test semihosting? Does it
> > > > require a JTAG debugger? But I see you are using QEMU?
> > > >
> > > > Regards,
> > > > Bin
> > > >
> >
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v5 3/3] board: qemu-riscv: enable semihosting
2022-09-23 7:03 ` [PATCH v5 3/3] board: qemu-riscv: enable semihosting Kautuk Consul
2022-10-05 6:17 ` Leo Liang
[not found] ` <HK0PR03MB29949257906C387D549119EBC1229@HK0PR03MB2994.apcprd03.prod.outlook.com>
@ 2022-12-03 4:14 ` Bin Meng
2022-12-05 5:51 ` Kautuk Consul
2 siblings, 1 reply; 29+ messages in thread
From: Bin Meng @ 2022-12-03 4:14 UTC (permalink / raw)
To: Kautuk Consul
Cc: Rayagonda Kokatanur, Sean Anderson, Rick Chen, Leo, Simon Glass,
Ilias Apalodimas, Alexandru Gagniuc, Philippe Reynes,
Heinrich Schuchardt, Rasmus Villemoes, Eugen Hristev,
Stefan Roese, Loic Poulain, Peng Fan, Michal Simek, u-boot
On Fri, Sep 23, 2022 at 3:03 PM Kautuk Consul <kconsul@ventanamicro.com> wrote:
>
> To enable semihosting we also need to enable the following
> configs in defconfigs:
> CONFIG_SEMIHOSTING
> CONFIG_SPL_SEMIHOSTING
> CONFIG_SEMIHOSTING_SERIAL
> CONFIG_SERIAL_PROBE_ALL
> CONFIG_SPL_FS_EXT4
> CONFIG_SPL_FS_FAT
Why should these _SPL_FS_xxx be required? If it's required by
SEMIHOSTING, could the dependency be fixed there?
>
> Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
> ---
> configs/qemu-riscv32_defconfig | 4 ++++
> configs/qemu-riscv32_smode_defconfig | 4 ++++
> configs/qemu-riscv32_spl_defconfig | 7 +++++++
> configs/qemu-riscv64_defconfig | 4 ++++
> configs/qemu-riscv64_smode_defconfig | 4 ++++
> configs/qemu-riscv64_spl_defconfig | 7 +++++++
> 6 files changed, 30 insertions(+)
>
Regards,
Bin
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v5 0/3] Add riscv semihosting support in u-boot
2022-11-29 6:57 ` Kautuk Consul
2022-12-02 8:46 ` Leo Liang
@ 2022-12-03 4:28 ` Bin Meng
2022-12-03 6:01 ` Bin Meng
1 sibling, 1 reply; 29+ messages in thread
From: Bin Meng @ 2022-12-03 4:28 UTC (permalink / raw)
To: Kautuk Consul
Cc: Rayagonda Kokatanur, Sean Anderson, Rick Chen, Leo, Simon Glass,
Ilias Apalodimas, Alexandru Gagniuc, Philippe Reynes,
Heinrich Schuchardt, Rasmus Villemoes, Eugen Hristev,
Stefan Roese, Loic Poulain, Peng Fan, Michal Simek, u-boot
On Tue, Nov 29, 2022 at 2:58 PM Kautuk Consul <kconsul@ventanamicro.com> wrote:
>
> I have tested it both on Qemu and Ventana's internal simulator.
How to verify this? I used your instructions and U-Boot says: No match
for driver 'serial_semihosting'
U-Boot 2023.01-rc2-00113-g2a4accaf5e (Dec 03 2022 - 12:20:20 +0800)
CPU: rv64imafdch_zicsr_zifencei_zihintpause_zba_zbb_zbc_zbs_sstc
Model: riscv-virtio,qemu
DRAM: 256 MiB
No match for driver 'serial_semihosting'
Some drivers were not found
Core: 25 devices, 12 uclasses, devicetree: board
Flash: 32 MiB
Loading Environment from nowhere... OK
In: serial@10000000
Out: serial@10000000
Err: serial@10000000
Net: No ethernet found.
Working FDT set to 8f734950
Hit any key to stop autoboot: 0
=>
>
> On Tue, Nov 29, 2022 at 12:06 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>>
>> Hi Kautuk,
>>
>> On Tue, Nov 29, 2022 at 2:29 PM Kautuk Consul <kconsul@ventanamicro.com> wrote:
>> >
>> > Hi,
>> >
>> > Can someone pick this patchset up ?
>> >
>> > It has been reviewed and there has been no comment on this in recent days.
>> >
>> > Thanks.
>> >
>> > On Fri, Sep 23, 2022 at 12:33 PM Kautuk Consul <kconsul@ventanamicro.com> wrote:
>> >>
>> >> Semihosting is a mechanism that enables code running on
>> >> a target to communicate and use the Input/Output
>> >> facilities on a host computer that is running a debugger.
>> >> This patchset adds support for semihosting in u-boot
>> >> for RISCV64 targets.
>> >>
>> >> CHANGES since v4:
>> >> - Check arch dependencies for SEMIHOSTING as well as SPL_SEMIHOSTING
>> >> config options as per Sean's comment.
>> >> - arch/riscv/lib/interrupts.c: Check for post and pre instructions
>> >> of the ebreak statement whether they are as per the RISCV
>> >> semihosting specification. Only then do a disable_semihosting
>> >> and epc += 4 and return.
>> >>
>> >> Compilation and test commands for SPL and S-mode configurations
>> >> =================================================================
>> >>
>> >> U-Boot S-mode on QEMU virt
>> >> ----------------------------
>> >> // Compilation of S-mode u-boot
>> >> ARCH=riscv
>> >> CROSS_COMPILE=riscv64-unknown-linux-gnu-
>> >> make qemu-riscv64_smode_defconfig
>> >> make
>> >> // Run riscv 64-bit u-boot with opensbi on qemu
>> >> qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\
>> >> opensbi/build/platform/generic/firmware/fw_jump.bin -kernel\
>> >> u-boot/u-boot.bin
>> >>
>> >> U-Boot SPL on QEMU virt
>> >> ------------------------
>> >> // Compilation of u-boot-spl
>> >> ARCH=riscv
>> >> CROSS_COMPILE=riscv64-unknown-linux-gnu-
>> >> make qemu-riscv64_spl_defconfig
>> >> make OPENSBI=opensbi/build/platform/generic/firmware/fw_dynamic.bin
>> >> // Run 64-bit u-boot-spl in qemu
>> >> qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\
>> >> u-boot/spl/u-boot-spl.bin -device\
>> >> loader,file=u-boot/u-boot.itb,addr=0x80200000
>> >>
>>
>> Do you have instructions on how to actually test semihosting? Does it
>> require a JTAG debugger? But I see you are using QEMU?
>>
Regards,
Bin
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v5 0/3] Add riscv semihosting support in u-boot
2022-12-03 4:28 ` Bin Meng
@ 2022-12-03 6:01 ` Bin Meng
2022-12-05 5:50 ` Kautuk Consul
0 siblings, 1 reply; 29+ messages in thread
From: Bin Meng @ 2022-12-03 6:01 UTC (permalink / raw)
To: Kautuk Consul
Cc: Rayagonda Kokatanur, Sean Anderson, Rick Chen, Leo, Simon Glass,
Ilias Apalodimas, Alexandru Gagniuc, Philippe Reynes,
Heinrich Schuchardt, Rasmus Villemoes, Eugen Hristev,
Stefan Roese, Loic Poulain, Peng Fan, Michal Simek, u-boot
Hi Kautuk,
On Sat, Dec 3, 2022 at 12:28 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Tue, Nov 29, 2022 at 2:58 PM Kautuk Consul <kconsul@ventanamicro.com> wrote:
> >
> > I have tested it both on Qemu and Ventana's internal simulator.
>
> How to verify this? I used your instructions and U-Boot says: No match
> for driver 'serial_semihosting'
>
> U-Boot 2023.01-rc2-00113-g2a4accaf5e (Dec 03 2022 - 12:20:20 +0800)
> CPU: rv64imafdch_zicsr_zifencei_zihintpause_zba_zbb_zbc_zbs_sstc
> Model: riscv-virtio,qemu
> DRAM: 256 MiB
> No match for driver 'serial_semihosting'
> Some drivers were not found
> Core: 25 devices, 12 uclasses, devicetree: board
> Flash: 32 MiB
> Loading Environment from nowhere... OK
> In: serial@10000000
> Out: serial@10000000
> Err: serial@10000000
> Net: No ethernet found.
> Working FDT set to 8f734950
> Hit any key to stop autoboot: 0
> =>
>
> >
> > On Tue, Nov 29, 2022 at 12:06 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >>
> >> Hi Kautuk,
> >>
> >> On Tue, Nov 29, 2022 at 2:29 PM Kautuk Consul <kconsul@ventanamicro.com> wrote:
> >> >
> >> > Hi,
> >> >
> >> > Can someone pick this patchset up ?
> >> >
> >> > It has been reviewed and there has been no comment on this in recent days.
> >> >
> >> > Thanks.
> >> >
> >> > On Fri, Sep 23, 2022 at 12:33 PM Kautuk Consul <kconsul@ventanamicro.com> wrote:
> >> >>
> >> >> Semihosting is a mechanism that enables code running on
> >> >> a target to communicate and use the Input/Output
> >> >> facilities on a host computer that is running a debugger.
> >> >> This patchset adds support for semihosting in u-boot
> >> >> for RISCV64 targets.
> >> >>
> >> >> CHANGES since v4:
> >> >> - Check arch dependencies for SEMIHOSTING as well as SPL_SEMIHOSTING
> >> >> config options as per Sean's comment.
> >> >> - arch/riscv/lib/interrupts.c: Check for post and pre instructions
> >> >> of the ebreak statement whether they are as per the RISCV
> >> >> semihosting specification. Only then do a disable_semihosting
> >> >> and epc += 4 and return.
> >> >>
> >> >> Compilation and test commands for SPL and S-mode configurations
> >> >> =================================================================
> >> >>
> >> >> U-Boot S-mode on QEMU virt
> >> >> ----------------------------
> >> >> // Compilation of S-mode u-boot
> >> >> ARCH=riscv
> >> >> CROSS_COMPILE=riscv64-unknown-linux-gnu-
> >> >> make qemu-riscv64_smode_defconfig
> >> >> make
> >> >> // Run riscv 64-bit u-boot with opensbi on qemu
> >> >> qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\
> >> >> opensbi/build/platform/generic/firmware/fw_jump.bin -kernel\
> >> >> u-boot/u-boot.bin
It turns out your instructions missed "-semihosting" in the QEMU command line.
With that I can see U-Boot boots with the serial_semihosting driver.
> >> >>
> >> >> U-Boot SPL on QEMU virt
> >> >> ------------------------
> >> >> // Compilation of u-boot-spl
> >> >> ARCH=riscv
> >> >> CROSS_COMPILE=riscv64-unknown-linux-gnu-
> >> >> make qemu-riscv64_spl_defconfig
> >> >> make OPENSBI=opensbi/build/platform/generic/firmware/fw_dynamic.bin
> >> >> // Run 64-bit u-boot-spl in qemu
> >> >> qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\
> >> >> u-boot/spl/u-boot-spl.bin -device\
> >> >> loader,file=u-boot/u-boot.itb,addr=0x80200000
> >> >>
> >>
> >> Do you have instructions on how to actually test semihosting? Does it
> >> require a JTAG debugger? But I see you are using QEMU?
> >>
>
Regards,
Bin
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v5 0/3] Add riscv semihosting support in u-boot
2022-12-03 6:01 ` Bin Meng
@ 2022-12-05 5:50 ` Kautuk Consul
0 siblings, 0 replies; 29+ messages in thread
From: Kautuk Consul @ 2022-12-05 5:50 UTC (permalink / raw)
To: Bin Meng
Cc: Rayagonda Kokatanur, Sean Anderson, Rick Chen, Leo, Simon Glass,
Ilias Apalodimas, Alexandru Gagniuc, Philippe Reynes,
Heinrich Schuchardt, Rasmus Villemoes, Eugen Hristev,
Stefan Roese, Loic Poulain, Peng Fan, Michal Simek, u-boot
Sorry about that! I assumed everyone would know the option and decided to
just upt the ordinary command
to show that the semihosting changes don't impact the non-semihosting
scenarios.
On Sat, Dec 3, 2022 at 11:32 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Kautuk,
>
> On Sat, Dec 3, 2022 at 12:28 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > On Tue, Nov 29, 2022 at 2:58 PM Kautuk Consul <kconsul@ventanamicro.com>
> wrote:
> > >
> > > I have tested it both on Qemu and Ventana's internal simulator.
> >
> > How to verify this? I used your instructions and U-Boot says: No match
> > for driver 'serial_semihosting'
> >
> > U-Boot 2023.01-rc2-00113-g2a4accaf5e (Dec 03 2022 - 12:20:20 +0800)
> > CPU: rv64imafdch_zicsr_zifencei_zihintpause_zba_zbb_zbc_zbs_sstc
> > Model: riscv-virtio,qemu
> > DRAM: 256 MiB
> > No match for driver 'serial_semihosting'
> > Some drivers were not found
> > Core: 25 devices, 12 uclasses, devicetree: board
> > Flash: 32 MiB
> > Loading Environment from nowhere... OK
> > In: serial@10000000
> > Out: serial@10000000
> > Err: serial@10000000
> > Net: No ethernet found.
> > Working FDT set to 8f734950
> > Hit any key to stop autoboot: 0
> > =>
> >
> > >
> > > On Tue, Nov 29, 2022 at 12:06 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> > >>
> > >> Hi Kautuk,
> > >>
> > >> On Tue, Nov 29, 2022 at 2:29 PM Kautuk Consul <
> kconsul@ventanamicro.com> wrote:
> > >> >
> > >> > Hi,
> > >> >
> > >> > Can someone pick this patchset up ?
> > >> >
> > >> > It has been reviewed and there has been no comment on this in
> recent days.
> > >> >
> > >> > Thanks.
> > >> >
> > >> > On Fri, Sep 23, 2022 at 12:33 PM Kautuk Consul <
> kconsul@ventanamicro.com> wrote:
> > >> >>
> > >> >> Semihosting is a mechanism that enables code running on
> > >> >> a target to communicate and use the Input/Output
> > >> >> facilities on a host computer that is running a debugger.
> > >> >> This patchset adds support for semihosting in u-boot
> > >> >> for RISCV64 targets.
> > >> >>
> > >> >> CHANGES since v4:
> > >> >> - Check arch dependencies for SEMIHOSTING as well as
> SPL_SEMIHOSTING
> > >> >> config options as per Sean's comment.
> > >> >> - arch/riscv/lib/interrupts.c: Check for post and pre
> instructions
> > >> >> of the ebreak statement whether they are as per the RISCV
> > >> >> semihosting specification. Only then do a
> disable_semihosting
> > >> >> and epc += 4 and return.
> > >> >>
> > >> >> Compilation and test commands for SPL and S-mode configurations
> > >> >> =================================================================
> > >> >>
> > >> >> U-Boot S-mode on QEMU virt
> > >> >> ----------------------------
> > >> >> // Compilation of S-mode u-boot
> > >> >> ARCH=riscv
> > >> >> CROSS_COMPILE=riscv64-unknown-linux-gnu-
> > >> >> make qemu-riscv64_smode_defconfig
> > >> >> make
> > >> >> // Run riscv 64-bit u-boot with opensbi on qemu
> > >> >> qemu-system-riscv64 -M virt -m 256M -display none -serial stdio
> -bios\
> > >> >> opensbi/build/platform/generic/firmware/fw_jump.bin -kernel\
> > >> >> u-boot/u-boot.bin
>
> It turns out your instructions missed "-semihosting" in the QEMU command
> line.
>
> With that I can see U-Boot boots with the serial_semihosting driver.
>
> > >> >>
> > >> >> U-Boot SPL on QEMU virt
> > >> >> ------------------------
> > >> >> // Compilation of u-boot-spl
> > >> >> ARCH=riscv
> > >> >> CROSS_COMPILE=riscv64-unknown-linux-gnu-
> > >> >> make qemu-riscv64_spl_defconfig
> > >> >> make OPENSBI=opensbi/build/platform/generic/firmware/fw_dynamic.bin
> > >> >> // Run 64-bit u-boot-spl in qemu
> > >> >> qemu-system-riscv64 -M virt -m 256M -display none -serial stdio
> -bios\
> > >> >> u-boot/spl/u-boot-spl.bin -device\
> > >> >> loader,file=u-boot/u-boot.itb,addr=0x80200000
> > >> >>
> > >>
> > >> Do you have instructions on how to actually test semihosting? Does it
> > >> require a JTAG debugger? But I see you are using QEMU?
> > >>
> >
>
> Regards,
> Bin
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v5 3/3] board: qemu-riscv: enable semihosting
2022-12-03 4:14 ` Bin Meng
@ 2022-12-05 5:51 ` Kautuk Consul
2022-12-05 13:54 ` Bin Meng
2022-12-05 15:16 ` Sean Anderson
0 siblings, 2 replies; 29+ messages in thread
From: Kautuk Consul @ 2022-12-05 5:51 UTC (permalink / raw)
To: Bin Meng
Cc: Rayagonda Kokatanur, Sean Anderson, Rick Chen, Leo, Simon Glass,
Ilias Apalodimas, Alexandru Gagniuc, Philippe Reynes,
Heinrich Schuchardt, Rasmus Villemoes, Eugen Hristev,
Stefan Roese, Loic Poulain, Peng Fan, Michal Simek, u-boot
Hi,
On Sat, Dec 3, 2022 at 9:44 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Fri, Sep 23, 2022 at 3:03 PM Kautuk Consul <kconsul@ventanamicro.com> wrote:
> >
> > To enable semihosting we also need to enable the following
> > configs in defconfigs:
> > CONFIG_SEMIHOSTING
> > CONFIG_SPL_SEMIHOSTING
> > CONFIG_SEMIHOSTING_SERIAL
> > CONFIG_SERIAL_PROBE_ALL
> > CONFIG_SPL_FS_EXT4
> > CONFIG_SPL_FS_FAT
>
> Why should these _SPL_FS_xxx be required? If it's required by
> SEMIHOSTING, could the dependency be fixed there?
The build dependencies require that these options be there.
>
> >
> > Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
> > ---
> > configs/qemu-riscv32_defconfig | 4 ++++
> > configs/qemu-riscv32_smode_defconfig | 4 ++++
> > configs/qemu-riscv32_spl_defconfig | 7 +++++++
> > configs/qemu-riscv64_defconfig | 4 ++++
> > configs/qemu-riscv64_smode_defconfig | 4 ++++
> > configs/qemu-riscv64_spl_defconfig | 7 +++++++
> > 6 files changed, 30 insertions(+)
> >
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v5 3/3] board: qemu-riscv: enable semihosting
2022-12-05 5:51 ` Kautuk Consul
@ 2022-12-05 13:54 ` Bin Meng
2022-12-05 15:16 ` Sean Anderson
1 sibling, 0 replies; 29+ messages in thread
From: Bin Meng @ 2022-12-05 13:54 UTC (permalink / raw)
To: Kautuk Consul
Cc: Rayagonda Kokatanur, Sean Anderson, Rick Chen, Leo, Simon Glass,
Ilias Apalodimas, Alexandru Gagniuc, Philippe Reynes,
Heinrich Schuchardt, Rasmus Villemoes, Eugen Hristev,
Stefan Roese, Loic Poulain, Peng Fan, Michal Simek, u-boot
On Mon, Dec 5, 2022 at 1:51 PM Kautuk Consul <kconsul@ventanamicro.com> wrote:
>
> Hi,
>
> On Sat, Dec 3, 2022 at 9:44 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > On Fri, Sep 23, 2022 at 3:03 PM Kautuk Consul <kconsul@ventanamicro.com> wrote:
> > >
> > > To enable semihosting we also need to enable the following
> > > configs in defconfigs:
> > > CONFIG_SEMIHOSTING
> > > CONFIG_SPL_SEMIHOSTING
> > > CONFIG_SEMIHOSTING_SERIAL
> > > CONFIG_SERIAL_PROBE_ALL
> > > CONFIG_SPL_FS_EXT4
> > > CONFIG_SPL_FS_FAT
> >
> > Why should these _SPL_FS_xxx be required? If it's required by
> > SEMIHOSTING, could the dependency be fixed there?
>
> The build dependencies require that these options be there.
>
I think you need to fix the dependencies of CONFIG_SPL_SEMIHOSTING
Regards,
Bin
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v5 3/3] board: qemu-riscv: enable semihosting
2022-12-05 5:51 ` Kautuk Consul
2022-12-05 13:54 ` Bin Meng
@ 2022-12-05 15:16 ` Sean Anderson
2022-12-06 5:42 ` Kautuk Consul
1 sibling, 1 reply; 29+ messages in thread
From: Sean Anderson @ 2022-12-05 15:16 UTC (permalink / raw)
To: Kautuk Consul, Bin Meng
Cc: Rayagonda Kokatanur, Rick Chen, Leo, Simon Glass,
Ilias Apalodimas, Alexandru Gagniuc, Philippe Reynes,
Heinrich Schuchardt, Rasmus Villemoes, Eugen Hristev,
Stefan Roese, Loic Poulain, Peng Fan, Michal Simek, u-boot
On 12/5/22 00:51, Kautuk Consul wrote:
> Hi,
>
> On Sat, Dec 3, 2022 at 9:44 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>>
>> On Fri, Sep 23, 2022 at 3:03 PM Kautuk Consul <kconsul@ventanamicro.com> wrote:
>> >
>> > To enable semihosting we also need to enable the following
>> > configs in defconfigs:
>> > CONFIG_SEMIHOSTING
>> > CONFIG_SPL_SEMIHOSTING
>> > CONFIG_SEMIHOSTING_SERIAL
>> > CONFIG_SERIAL_PROBE_ALL
>> > CONFIG_SPL_FS_EXT4
>> > CONFIG_SPL_FS_FAT
>>
>> Why should these _SPL_FS_xxx be required? If it's required by
>> SEMIHOSTING, could the dependency be fixed there?
>
> The build dependencies require that these options be there.
What error do you get?
--Sean
>>
>> >
>> > Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
>> > ---
>> > configs/qemu-riscv32_defconfig | 4 ++++
>> > configs/qemu-riscv32_smode_defconfig | 4 ++++
>> > configs/qemu-riscv32_spl_defconfig | 7 +++++++
>> > configs/qemu-riscv64_defconfig | 4 ++++
>> > configs/qemu-riscv64_smode_defconfig | 4 ++++
>> > configs/qemu-riscv64_spl_defconfig | 7 +++++++
>> > 6 files changed, 30 insertions(+)
>> >
>>
>> Regards,
>> Bin
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v5 3/3] board: qemu-riscv: enable semihosting
2022-12-05 15:16 ` Sean Anderson
@ 2022-12-06 5:42 ` Kautuk Consul
2022-12-06 10:58 ` Leo Liang
2022-12-06 15:16 ` Sean Anderson
0 siblings, 2 replies; 29+ messages in thread
From: Kautuk Consul @ 2022-12-06 5:42 UTC (permalink / raw)
To: Sean Anderson
Cc: Bin Meng, Rayagonda Kokatanur, Rick Chen, Leo, Simon Glass,
Ilias Apalodimas, Alexandru Gagniuc, Philippe Reynes,
Heinrich Schuchardt, Rasmus Villemoes, Eugen Hristev,
Stefan Roese, Loic Poulain, Peng Fan, Michal Simek, u-boot
Hi,
On Mon, Dec 5, 2022 at 8:46 PM Sean Anderson <sean.anderson@seco.com> wrote:
>
> On 12/5/22 00:51, Kautuk Consul wrote:
> > Hi,
> >
> > On Sat, Dec 3, 2022 at 9:44 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> >>
> >> On Fri, Sep 23, 2022 at 3:03 PM Kautuk Consul <kconsul@ventanamicro.com> wrote:
> >> >
> >> > To enable semihosting we also need to enable the following
> >> > configs in defconfigs:
> >> > CONFIG_SEMIHOSTING
> >> > CONFIG_SPL_SEMIHOSTING
> >> > CONFIG_SEMIHOSTING_SERIAL
> >> > CONFIG_SERIAL_PROBE_ALL
> >> > CONFIG_SPL_FS_EXT4
> >> > CONFIG_SPL_FS_FAT
> >>
> >> Why should these _SPL_FS_xxx be required? If it's required by
> >> SEMIHOSTING, could the dependency be fixed there?
> >
> > The build dependencies require that these options be there.
>
> What error do you get?
If I disable both the _SPL_FS_* config options then I get the
following compilation error:
common/spl/spl_semihosting.c: In function 'spl_smh_load_image':
common/spl/spl_semihosting.c:27:32: error:
'CONFIG_SPL_FS_LOAD_PAYLOAD_NAME' undeclared (first use in this
function)
27 | const char *filename = CONFIG_SPL_FS_LOAD_PAYLOAD_NAME;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
common/spl/spl_semihosting.c:27:32: note: each undeclared identifier
is reported only once for each function it appears in
Bin/Sean: This error is not really related to the semihosting feature
but is related to COFIG_SPL in general.
Can you please accept this patch-set and then I'll try and find time
in the future maybe to rectify this build dependency
problem ?
>
> --Sean
>
> >>
> >> >
> >> > Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
> >> > ---
> >> > configs/qemu-riscv32_defconfig | 4 ++++
> >> > configs/qemu-riscv32_smode_defconfig | 4 ++++
> >> > configs/qemu-riscv32_spl_defconfig | 7 +++++++
> >> > configs/qemu-riscv64_defconfig | 4 ++++
> >> > configs/qemu-riscv64_smode_defconfig | 4 ++++
> >> > configs/qemu-riscv64_spl_defconfig | 7 +++++++
> >> > 6 files changed, 30 insertions(+)
> >> >
> >>
> >> Regards,
> >> Bin
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v5 3/3] board: qemu-riscv: enable semihosting
2022-12-06 5:42 ` Kautuk Consul
@ 2022-12-06 10:58 ` Leo Liang
2022-12-06 11:32 ` Kautuk Consul
2022-12-06 15:16 ` Sean Anderson
1 sibling, 1 reply; 29+ messages in thread
From: Leo Liang @ 2022-12-06 10:58 UTC (permalink / raw)
To: Kautuk Consul
Cc: Sean Anderson, Bin Meng, Rayagonda Kokatanur, Rick Chen,
Simon Glass, Ilias Apalodimas, Alexandru Gagniuc,
Philippe Reynes, Heinrich Schuchardt, Rasmus Villemoes,
Eugen Hristev, Stefan Roese, Loic Poulain, Peng Fan,
Michal Simek, u-boot
Hi Kautuk,
We have tested your patchset with QEMU 7.1.0.
It generally looks fine, but CI error seems to persist.
https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/14314
The error comes from CI testcase timed-out.
The reason for the time-out is not yet confirmed,
but we suspect it's because when executing under semihosting,
QEMU could not exit normally. (thru ctrl+x a)
There is a seemingly relevent patchset that sits on QEMU mailing list for some time.
https://lore.kernel.org/all/20220620190834.GA16887@ws2101.lin.mbt.kalray.eu/T/#m1bc32cc32511b6ac8adfaf67983dc2bccd4b9ec9
On the u-boot side, what do you think if we disable semihosting by default?
(i.e., not adding CONFIG_SEMIHOSTING_XXX in qemu's defconfig)
Best regards,
Leo
On Tue, Dec 06, 2022 at 11:12:41AM +0530, Kautuk Consul wrote:
> Hi,
>
> On Mon, Dec 5, 2022 at 8:46 PM Sean Anderson <sean.anderson@seco.com> wrote:
> >
> > On 12/5/22 00:51, Kautuk Consul wrote:
> > > Hi,
> > >
> > > On Sat, Dec 3, 2022 at 9:44 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> > >>
> > >> On Fri, Sep 23, 2022 at 3:03 PM Kautuk Consul <kconsul@ventanamicro.com> wrote:
> > >> >
> > >> > To enable semihosting we also need to enable the following
> > >> > configs in defconfigs:
> > >> > CONFIG_SEMIHOSTING
> > >> > CONFIG_SPL_SEMIHOSTING
> > >> > CONFIG_SEMIHOSTING_SERIAL
> > >> > CONFIG_SERIAL_PROBE_ALL
> > >> > CONFIG_SPL_FS_EXT4
> > >> > CONFIG_SPL_FS_FAT
> > >>
> > >> Why should these _SPL_FS_xxx be required? If it's required by
> > >> SEMIHOSTING, could the dependency be fixed there?
> > >
> > > The build dependencies require that these options be there.
> >
> > What error do you get?
>
> If I disable both the _SPL_FS_* config options then I get the
> following compilation error:
> common/spl/spl_semihosting.c: In function 'spl_smh_load_image':
> common/spl/spl_semihosting.c:27:32: error:
> 'CONFIG_SPL_FS_LOAD_PAYLOAD_NAME' undeclared (first use in this
> function)
> 27 | const char *filename = CONFIG_SPL_FS_LOAD_PAYLOAD_NAME;
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> common/spl/spl_semihosting.c:27:32: note: each undeclared identifier
> is reported only once for each function it appears in
>
> Bin/Sean: This error is not really related to the semihosting feature
> but is related to COFIG_SPL in general.
> Can you please accept this patch-set and then I'll try and find time
> in the future maybe to rectify this build dependency
> problem ?
>
> >
> > --Sean
> >
> > >>
> > >> >
> > >> > Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
> > >> > ---
> > >> > configs/qemu-riscv32_defconfig | 4 ++++
> > >> > configs/qemu-riscv32_smode_defconfig | 4 ++++
> > >> > configs/qemu-riscv32_spl_defconfig | 7 +++++++
> > >> > configs/qemu-riscv64_defconfig | 4 ++++
> > >> > configs/qemu-riscv64_smode_defconfig | 4 ++++
> > >> > configs/qemu-riscv64_spl_defconfig | 7 +++++++
> > >> > 6 files changed, 30 insertions(+)
> > >> >
> > >>
> > >> Regards,
> > >> Bin
> >
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v5 3/3] board: qemu-riscv: enable semihosting
2022-12-06 10:58 ` Leo Liang
@ 2022-12-06 11:32 ` Kautuk Consul
2022-12-07 7:01 ` Leo Liang
0 siblings, 1 reply; 29+ messages in thread
From: Kautuk Consul @ 2022-12-06 11:32 UTC (permalink / raw)
To: Leo Liang
Cc: Sean Anderson, Bin Meng, Rayagonda Kokatanur, Rick Chen,
Simon Glass, Ilias Apalodimas, Alexandru Gagniuc,
Philippe Reynes, Heinrich Schuchardt, Rasmus Villemoes,
Eugen Hristev, Stefan Roese, Loic Poulain, Peng Fan,
Michal Simek, u-boot
Hi Leo,
On Tue, Dec 6, 2022 at 4:29 PM Leo Liang <ycliang@andestech.com> wrote:
>
> Hi Kautuk,
>
> We have tested your patchset with QEMU 7.1.0.
> It generally looks fine, but CI error seems to persist.
> https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/14314
>
> The error comes from CI testcase timed-out.
> The reason for the time-out is not yet confirmed,
> but we suspect it's because when executing under semihosting,
> QEMU could not exit normally. (thru ctrl+x a)
>
> There is a seemingly relevent patchset that sits on QEMU mailing list for some time.
> https://lore.kernel.org/all/20220620190834.GA16887@ws2101.lin.mbt.kalray.eu/T/#m1bc32cc32511b6ac8adfaf67983dc2bccd4b9ec9
>
> On the u-boot side, what do you think if we disable semihosting by default?
> (i.e., not adding CONFIG_SEMIHOSTING_XXX in qemu's defconfig)
I think it is okay to disable semihosting by default. Then the user
will configure it when needed.
So then can you ACK the first 2 patches ? I think we can leave out the
3rd qemu config patch for now.
>
> Best regards,
> Leo
>
> On Tue, Dec 06, 2022 at 11:12:41AM +0530, Kautuk Consul wrote:
> > Hi,
> >
> > On Mon, Dec 5, 2022 at 8:46 PM Sean Anderson <sean.anderson@seco.com> wrote:
> > >
> > > On 12/5/22 00:51, Kautuk Consul wrote:
> > > > Hi,
> > > >
> > > > On Sat, Dec 3, 2022 at 9:44 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> > > >>
> > > >> On Fri, Sep 23, 2022 at 3:03 PM Kautuk Consul <kconsul@ventanamicro.com> wrote:
> > > >> >
> > > >> > To enable semihosting we also need to enable the following
> > > >> > configs in defconfigs:
> > > >> > CONFIG_SEMIHOSTING
> > > >> > CONFIG_SPL_SEMIHOSTING
> > > >> > CONFIG_SEMIHOSTING_SERIAL
> > > >> > CONFIG_SERIAL_PROBE_ALL
> > > >> > CONFIG_SPL_FS_EXT4
> > > >> > CONFIG_SPL_FS_FAT
> > > >>
> > > >> Why should these _SPL_FS_xxx be required? If it's required by
> > > >> SEMIHOSTING, could the dependency be fixed there?
> > > >
> > > > The build dependencies require that these options be there.
> > >
> > > What error do you get?
> >
> > If I disable both the _SPL_FS_* config options then I get the
> > following compilation error:
> > common/spl/spl_semihosting.c: In function 'spl_smh_load_image':
> > common/spl/spl_semihosting.c:27:32: error:
> > 'CONFIG_SPL_FS_LOAD_PAYLOAD_NAME' undeclared (first use in this
> > function)
> > 27 | const char *filename = CONFIG_SPL_FS_LOAD_PAYLOAD_NAME;
> > | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > common/spl/spl_semihosting.c:27:32: note: each undeclared identifier
> > is reported only once for each function it appears in
> >
> > Bin/Sean: This error is not really related to the semihosting feature
> > but is related to COFIG_SPL in general.
> > Can you please accept this patch-set and then I'll try and find time
> > in the future maybe to rectify this build dependency
> > problem ?
> >
> > >
> > > --Sean
> > >
> > > >>
> > > >> >
> > > >> > Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
> > > >> > ---
> > > >> > configs/qemu-riscv32_defconfig | 4 ++++
> > > >> > configs/qemu-riscv32_smode_defconfig | 4 ++++
> > > >> > configs/qemu-riscv32_spl_defconfig | 7 +++++++
> > > >> > configs/qemu-riscv64_defconfig | 4 ++++
> > > >> > configs/qemu-riscv64_smode_defconfig | 4 ++++
> > > >> > configs/qemu-riscv64_spl_defconfig | 7 +++++++
> > > >> > 6 files changed, 30 insertions(+)
> > > >> >
> > > >>
> > > >> Regards,
> > > >> Bin
> > >
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v5 3/3] board: qemu-riscv: enable semihosting
2022-12-06 5:42 ` Kautuk Consul
2022-12-06 10:58 ` Leo Liang
@ 2022-12-06 15:16 ` Sean Anderson
1 sibling, 0 replies; 29+ messages in thread
From: Sean Anderson @ 2022-12-06 15:16 UTC (permalink / raw)
To: Kautuk Consul
Cc: Bin Meng, Rayagonda Kokatanur, Rick Chen, Leo, Simon Glass,
Ilias Apalodimas, Alexandru Gagniuc, Philippe Reynes,
Heinrich Schuchardt, Rasmus Villemoes, Eugen Hristev,
Stefan Roese, Loic Poulain, Peng Fan, Michal Simek, u-boot
On 12/6/22 00:42, Kautuk Consul wrote:
> Hi,
>
> On Mon, Dec 5, 2022 at 8:46 PM Sean Anderson <sean.anderson@seco.com> wrote:
>>
>> On 12/5/22 00:51, Kautuk Consul wrote:
>> > Hi,
>> >
>> > On Sat, Dec 3, 2022 at 9:44 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>> >>
>> >> On Fri, Sep 23, 2022 at 3:03 PM Kautuk Consul <kconsul@ventanamicro.com> wrote:
>> >> >
>> >> > To enable semihosting we also need to enable the following
>> >> > configs in defconfigs:
>> >> > CONFIG_SEMIHOSTING
>> >> > CONFIG_SPL_SEMIHOSTING
>> >> > CONFIG_SEMIHOSTING_SERIAL
>> >> > CONFIG_SERIAL_PROBE_ALL
>> >> > CONFIG_SPL_FS_EXT4
>> >> > CONFIG_SPL_FS_FAT
>> >>
>> >> Why should these _SPL_FS_xxx be required? If it's required by
>> >> SEMIHOSTING, could the dependency be fixed there?
>> >
>> > The build dependencies require that these options be there.
>>
>> What error do you get?
>
> If I disable both the _SPL_FS_* config options then I get the
> following compilation error:
> common/spl/spl_semihosting.c: In function 'spl_smh_load_image':
> common/spl/spl_semihosting.c:27:32: error:
> 'CONFIG_SPL_FS_LOAD_PAYLOAD_NAME' undeclared (first use in this
> function)
> 27 | const char *filename = CONFIG_SPL_FS_LOAD_PAYLOAD_NAME;
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> common/spl/spl_semihosting.c:27:32: note: each undeclared identifier
> is reported only once for each function it appears in
>
> Bin/Sean: This error is not really related to the semihosting feature
> but is related to COFIG_SPL in general.
> Can you please accept this patch-set and then I'll try and find time
> in the future maybe to rectify this build dependency
> problem ?
config SPL_FS_LOAD_PAYLOAD_NAME
string "File to load for U-Boot from the filesystem"
depends on SPL_FS_EXT4 || SPL_FS_FAT || SPL_FS_SQUASHFS
default "tispl.bin" if SYS_K3_SPL_ATF
default "u-boot.itb" if SPL_LOAD_FIT
default "u-boot.img"
help
Filename to read to load U-Boot when reading from filesystem.
Add CONFIG_SPL_SEMIHOSTING to the depends.
--Sean
>>
>> --Sean
>>
>> >>
>> >> >
>> >> > Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
>> >> > ---
>> >> > configs/qemu-riscv32_defconfig | 4 ++++
>> >> > configs/qemu-riscv32_smode_defconfig | 4 ++++
>> >> > configs/qemu-riscv32_spl_defconfig | 7 +++++++
>> >> > configs/qemu-riscv64_defconfig | 4 ++++
>> >> > configs/qemu-riscv64_smode_defconfig | 4 ++++
>> >> > configs/qemu-riscv64_spl_defconfig | 7 +++++++
>> >> > 6 files changed, 30 insertions(+)
>> >> >
>> >>
>> >> Regards,
>> >> Bin
>>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v5 3/3] board: qemu-riscv: enable semihosting
2022-12-06 11:32 ` Kautuk Consul
@ 2022-12-07 7:01 ` Leo Liang
2022-12-07 11:47 ` Kautuk Consul
0 siblings, 1 reply; 29+ messages in thread
From: Leo Liang @ 2022-12-07 7:01 UTC (permalink / raw)
To: Kautuk Consul
Cc: Sean Anderson, Bin Meng, Rayagonda Kokatanur, Rick Chen,
Simon Glass, Ilias Apalodimas, Alexandru Gagniuc,
Philippe Reynes, Heinrich Schuchardt, Rasmus Villemoes,
Eugen Hristev, Stefan Roese, Loic Poulain, Peng Fan,
Michal Simek, u-boot, ycliang
Hi Kautuk,
On Tue, Dec 06, 2022 at 05:02:49PM +0530, Kautuk Consul wrote:
> Hi Leo,
>
> On Tue, Dec 6, 2022 at 4:29 PM Leo Liang <ycliang@andestech.com> wrote:
> >
> > Hi Kautuk,
> >
> > We have tested your patchset with QEMU 7.1.0.
> > It generally looks fine, but CI error seems to persist.
> > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/14314
> >
> > The error comes from CI testcase timed-out.
> > The reason for the time-out is not yet confirmed,
> > but we suspect it's because when executing under semihosting,
> > QEMU could not exit normally. (thru ctrl+x a)
> >
> > There is a seemingly relevent patchset that sits on QEMU mailing list for some time.
> > https://lore.kernel.org/all/20220620190834.GA16887@ws2101.lin.mbt.kalray.eu/T/#m1bc32cc32511b6ac8adfaf67983dc2bccd4b9ec9
> >
> > On the u-boot side, what do you think if we disable semihosting by default?
> > (i.e., not adding CONFIG_SEMIHOSTING_XXX in qemu's defconfig)
>
> I think it is okay to disable semihosting by default. Then the user
> will configure it when needed.
> So then can you ACK the first 2 patches ? I think we can leave out the
> 3rd qemu config patch for now.
>
No problem!
Additionally, could you rebase the patchset to current master,
add what Sean suggested, and then send again?
I think I could merge your patch as soon as you re-send it.
Best regards,
Leo
> >
> > Best regards,
> > Leo
> >
> > On Tue, Dec 06, 2022 at 11:12:41AM +0530, Kautuk Consul wrote:
> > > Hi,
> > >
> > > On Mon, Dec 5, 2022 at 8:46 PM Sean Anderson <sean.anderson@seco.com> wrote:
> > > >
> > > > On 12/5/22 00:51, Kautuk Consul wrote:
> > > > > Hi,
> > > > >
> > > > > On Sat, Dec 3, 2022 at 9:44 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> > > > >>
> > > > >> On Fri, Sep 23, 2022 at 3:03 PM Kautuk Consul <kconsul@ventanamicro.com> wrote:
> > > > >> >
> > > > >> > To enable semihosting we also need to enable the following
> > > > >> > configs in defconfigs:
> > > > >> > CONFIG_SEMIHOSTING
> > > > >> > CONFIG_SPL_SEMIHOSTING
> > > > >> > CONFIG_SEMIHOSTING_SERIAL
> > > > >> > CONFIG_SERIAL_PROBE_ALL
> > > > >> > CONFIG_SPL_FS_EXT4
> > > > >> > CONFIG_SPL_FS_FAT
> > > > >>
> > > > >> Why should these _SPL_FS_xxx be required? If it's required by
> > > > >> SEMIHOSTING, could the dependency be fixed there?
> > > > >
> > > > > The build dependencies require that these options be there.
> > > >
> > > > What error do you get?
> > >
> > > If I disable both the _SPL_FS_* config options then I get the
> > > following compilation error:
> > > common/spl/spl_semihosting.c: In function 'spl_smh_load_image':
> > > common/spl/spl_semihosting.c:27:32: error:
> > > 'CONFIG_SPL_FS_LOAD_PAYLOAD_NAME' undeclared (first use in this
> > > function)
> > > 27 | const char *filename = CONFIG_SPL_FS_LOAD_PAYLOAD_NAME;
> > > | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > > common/spl/spl_semihosting.c:27:32: note: each undeclared identifier
> > > is reported only once for each function it appears in
> > >
> > > Bin/Sean: This error is not really related to the semihosting feature
> > > but is related to COFIG_SPL in general.
> > > Can you please accept this patch-set and then I'll try and find time
> > > in the future maybe to rectify this build dependency
> > > problem ?
> > >
> > > >
> > > > --Sean
> > > >
> > > > >>
> > > > >> >
> > > > >> > Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
> > > > >> > ---
> > > > >> > configs/qemu-riscv32_defconfig | 4 ++++
> > > > >> > configs/qemu-riscv32_smode_defconfig | 4 ++++
> > > > >> > configs/qemu-riscv32_spl_defconfig | 7 +++++++
> > > > >> > configs/qemu-riscv64_defconfig | 4 ++++
> > > > >> > configs/qemu-riscv64_smode_defconfig | 4 ++++
> > > > >> > configs/qemu-riscv64_spl_defconfig | 7 +++++++
> > > > >> > 6 files changed, 30 insertions(+)
> > > > >> >
> > > > >>
> > > > >> Regards,
> > > > >> Bin
> > > >
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v5 3/3] board: qemu-riscv: enable semihosting
2022-12-07 7:01 ` Leo Liang
@ 2022-12-07 11:47 ` Kautuk Consul
0 siblings, 0 replies; 29+ messages in thread
From: Kautuk Consul @ 2022-12-07 11:47 UTC (permalink / raw)
To: Leo Liang
Cc: Sean Anderson, Bin Meng, Rayagonda Kokatanur, Rick Chen,
Simon Glass, Ilias Apalodimas, Alexandru Gagniuc,
Philippe Reynes, Heinrich Schuchardt, Rasmus Villemoes,
Eugen Hristev, Stefan Roese, Loic Poulain, Peng Fan,
Michal Simek, u-boot
Hi Leo,
Thanks! I have sent a v6 of this patchset wherein I have rebased the
patchset on the
latest master. I have removed the last patch with default config
options for qemu-riscv64
targets and have replaced it with a patch with Sean's suggestion for
adding to the
dependencies.
Thanks again.
On Wed, Dec 7, 2022 at 12:31 PM Leo Liang <ycliang@andestech.com> wrote:
>
> Hi Kautuk,
>
> On Tue, Dec 06, 2022 at 05:02:49PM +0530, Kautuk Consul wrote:
> > Hi Leo,
> >
> > On Tue, Dec 6, 2022 at 4:29 PM Leo Liang <ycliang@andestech.com> wrote:
> > >
> > > Hi Kautuk,
> > >
> > > We have tested your patchset with QEMU 7.1.0.
> > > It generally looks fine, but CI error seems to persist.
> > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/14314
> > >
> > > The error comes from CI testcase timed-out.
> > > The reason for the time-out is not yet confirmed,
> > > but we suspect it's because when executing under semihosting,
> > > QEMU could not exit normally. (thru ctrl+x a)
> > >
> > > There is a seemingly relevent patchset that sits on QEMU mailing list for some time.
> > > https://lore.kernel.org/all/20220620190834.GA16887@ws2101.lin.mbt.kalray.eu/T/#m1bc32cc32511b6ac8adfaf67983dc2bccd4b9ec9
> > >
> > > On the u-boot side, what do you think if we disable semihosting by default?
> > > (i.e., not adding CONFIG_SEMIHOSTING_XXX in qemu's defconfig)
> >
> > I think it is okay to disable semihosting by default. Then the user
> > will configure it when needed.
> > So then can you ACK the first 2 patches ? I think we can leave out the
> > 3rd qemu config patch for now.
> >
>
> No problem!
> Additionally, could you rebase the patchset to current master,
> add what Sean suggested, and then send again?
> I think I could merge your patch as soon as you re-send it.
>
> Best regards,
> Leo
>
> > >
> > > Best regards,
> > > Leo
> > >
> > > On Tue, Dec 06, 2022 at 11:12:41AM +0530, Kautuk Consul wrote:
> > > > Hi,
> > > >
> > > > On Mon, Dec 5, 2022 at 8:46 PM Sean Anderson <sean.anderson@seco.com> wrote:
> > > > >
> > > > > On 12/5/22 00:51, Kautuk Consul wrote:
> > > > > > Hi,
> > > > > >
> > > > > > On Sat, Dec 3, 2022 at 9:44 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> > > > > >>
> > > > > >> On Fri, Sep 23, 2022 at 3:03 PM Kautuk Consul <kconsul@ventanamicro.com> wrote:
> > > > > >> >
> > > > > >> > To enable semihosting we also need to enable the following
> > > > > >> > configs in defconfigs:
> > > > > >> > CONFIG_SEMIHOSTING
> > > > > >> > CONFIG_SPL_SEMIHOSTING
> > > > > >> > CONFIG_SEMIHOSTING_SERIAL
> > > > > >> > CONFIG_SERIAL_PROBE_ALL
> > > > > >> > CONFIG_SPL_FS_EXT4
> > > > > >> > CONFIG_SPL_FS_FAT
> > > > > >>
> > > > > >> Why should these _SPL_FS_xxx be required? If it's required by
> > > > > >> SEMIHOSTING, could the dependency be fixed there?
> > > > > >
> > > > > > The build dependencies require that these options be there.
> > > > >
> > > > > What error do you get?
> > > >
> > > > If I disable both the _SPL_FS_* config options then I get the
> > > > following compilation error:
> > > > common/spl/spl_semihosting.c: In function 'spl_smh_load_image':
> > > > common/spl/spl_semihosting.c:27:32: error:
> > > > 'CONFIG_SPL_FS_LOAD_PAYLOAD_NAME' undeclared (first use in this
> > > > function)
> > > > 27 | const char *filename = CONFIG_SPL_FS_LOAD_PAYLOAD_NAME;
> > > > | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > > > common/spl/spl_semihosting.c:27:32: note: each undeclared identifier
> > > > is reported only once for each function it appears in
> > > >
> > > > Bin/Sean: This error is not really related to the semihosting feature
> > > > but is related to COFIG_SPL in general.
> > > > Can you please accept this patch-set and then I'll try and find time
> > > > in the future maybe to rectify this build dependency
> > > > problem ?
> > > >
> > > > >
> > > > > --Sean
> > > > >
> > > > > >>
> > > > > >> >
> > > > > >> > Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
> > > > > >> > ---
> > > > > >> > configs/qemu-riscv32_defconfig | 4 ++++
> > > > > >> > configs/qemu-riscv32_smode_defconfig | 4 ++++
> > > > > >> > configs/qemu-riscv32_spl_defconfig | 7 +++++++
> > > > > >> > configs/qemu-riscv64_defconfig | 4 ++++
> > > > > >> > configs/qemu-riscv64_smode_defconfig | 4 ++++
> > > > > >> > configs/qemu-riscv64_spl_defconfig | 7 +++++++
> > > > > >> > 6 files changed, 30 insertions(+)
> > > > > >> >
> > > > > >>
> > > > > >> Regards,
> > > > > >> Bin
> > > > >
^ permalink raw reply [flat|nested] 29+ messages in thread
end of thread, other threads:[~2022-12-07 11:47 UTC | newest]
Thread overview: 29+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-23 7:03 [PATCH v5 0/3] Add riscv semihosting support in u-boot Kautuk Consul
2022-09-23 7:03 ` [PATCH v5 1/3] lib: Add common semihosting library Kautuk Consul
2022-10-10 15:39 ` Sean Anderson
2022-09-23 7:03 ` [PATCH v5 2/3] arch/riscv: add semihosting support for RISC-V Kautuk Consul
2022-10-10 15:43 ` Sean Anderson
[not found] ` <HK0PR03MB2994013C655E85AF1F3D2CFBC1229@HK0PR03MB2994.apcprd03.prod.outlook.com>
2022-10-12 1:40 ` Rick Chen
2022-09-23 7:03 ` [PATCH v5 3/3] board: qemu-riscv: enable semihosting Kautuk Consul
2022-10-05 6:17 ` Leo Liang
2022-10-06 5:13 ` Kautuk Consul
[not found] ` <HK0PR03MB29949257906C387D549119EBC1229@HK0PR03MB2994.apcprd03.prod.outlook.com>
2022-10-12 1:33 ` Rick Chen
2022-12-03 4:14 ` Bin Meng
2022-12-05 5:51 ` Kautuk Consul
2022-12-05 13:54 ` Bin Meng
2022-12-05 15:16 ` Sean Anderson
2022-12-06 5:42 ` Kautuk Consul
2022-12-06 10:58 ` Leo Liang
2022-12-06 11:32 ` Kautuk Consul
2022-12-07 7:01 ` Leo Liang
2022-12-07 11:47 ` Kautuk Consul
2022-12-06 15:16 ` Sean Anderson
2022-11-29 6:29 ` [PATCH v5 0/3] Add riscv semihosting support in u-boot Kautuk Consul
2022-11-29 6:36 ` Bin Meng
2022-11-29 6:57 ` Kautuk Consul
2022-12-02 8:46 ` Leo Liang
2022-12-02 9:52 ` Kautuk Consul
2022-12-02 12:01 ` Leo Liang
2022-12-03 4:28 ` Bin Meng
2022-12-03 6:01 ` Bin Meng
2022-12-05 5:50 ` Kautuk Consul
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