[PATCH i-g-t] i915/gem_workarounds: Verify regs directly

[PATCH i-g-t] i915/gem_workarounds: Verify regs directly

[Chris Wilson]

---
 tests/i915/gem_workarounds.c | 45 +++++++++++++++++++++++++++++-------
 1 file changed, 37 insertions(+), 8 deletions(-)

diff --git a/tests/i915/gem_workarounds.c b/tests/i915/gem_workarounds.c
index 44e3dce8a..bf8b4f630 100644
--- a/tests/i915/gem_workarounds.c
+++ b/tests/i915/gem_workarounds.c
@@ -82,6 +82,7 @@ static bool write_only(const uint32_t addr)
 
 #define MI_STORE_REGISTER_MEM (0x24 << 23)
 
+#if 0
 static int workaround_fail_count(int fd, uint32_t ctx)
 {
 	struct drm_i915_gem_exec_object2 obj[2];
@@ -162,17 +163,45 @@ static int workaround_fail_count(int fd, uint32_t ctx)
 
 	return fail_count;
 }
-
-static int reopen(int fd)
+#else
+static int workaround_fail_count(int i915, uint32_t ctx)
 {
-	char path[256];
+	igt_spin_t *spin;
+	int fail = 0;
+
+	intel_mmio_use_pci_bar(intel_get_pci_device());
+
+	spin = igt_spin_new(i915, .ctx = ctx, .flags = IGT_SPIN_POLL_RUN);
+	igt_spin_busywait_until_started(spin);
+
+	for (int i = 0; i < num_wa_regs; i++) {
+		uint32_t value =
+			*(uint32_t *)(igt_global_mmio + wa_regs[i].addr);
+		const bool ok =
+			(wa_regs[i].value & wa_regs[i].mask) ==
+			(value & wa_regs[i].mask);
+		char buf[80];
+
+		snprintf(buf, sizeof(buf),
+			 "0x%05X\t0x%08X\t0x%08X\t0x%08X",
+			 wa_regs[i].addr, wa_regs[i].value, wa_regs[i].mask,
+			 value);
+
+		if (ok) {
+			igt_debug("%s\tOK\n", buf);
+		} else if (write_only(wa_regs[i].addr)) {
+			igt_debug("%s\tIGNORED (w/o)\n", buf);
+		} else {
+			igt_warn("%s\tFAIL\n", buf);
+			fail++;
+		}
+	}
 
-	snprintf(path, sizeof(path), "/proc/self/fd/%d", fd);
-	fd = open(path, O_RDWR);
-	igt_assert_lte(0, fd);
+	igt_spin_free(i915, spin);
 
-	return fd;
+	return fail;
 }
+#endif
 
 #define CONTEXT 0x1
 #define FD 0x2
@@ -181,7 +210,7 @@ static void check_workarounds(int fd, enum operation op, unsigned int flags)
 	uint32_t ctx = 0;
 
 	if (flags & FD)
-		fd = reopen(fd);
+		fd = gem_reopen_driver(fd);
 
 	if (flags & CONTEXT) {
 		gem_require_contexts(fd);
-- 
2.20.1

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[igt-dev] [PATCH i-g-t] i915/gem_workarounds: Verify regs directly

[Chris Wilson]

---
 tests/i915/gem_workarounds.c | 45 +++++++++++++++++++++++++++++-------
 1 file changed, 37 insertions(+), 8 deletions(-)

diff --git a/tests/i915/gem_workarounds.c b/tests/i915/gem_workarounds.c
index 44e3dce8a..bf8b4f630 100644
--- a/tests/i915/gem_workarounds.c
+++ b/tests/i915/gem_workarounds.c
@@ -82,6 +82,7 @@ static bool write_only(const uint32_t addr)
 
 #define MI_STORE_REGISTER_MEM (0x24 << 23)
 
+#if 0
 static int workaround_fail_count(int fd, uint32_t ctx)
 {
 	struct drm_i915_gem_exec_object2 obj[2];
@@ -162,17 +163,45 @@ static int workaround_fail_count(int fd, uint32_t ctx)
 
 	return fail_count;
 }
-
-static int reopen(int fd)
+#else
+static int workaround_fail_count(int i915, uint32_t ctx)
 {
-	char path[256];
+	igt_spin_t *spin;
+	int fail = 0;
+
+	intel_mmio_use_pci_bar(intel_get_pci_device());
+
+	spin = igt_spin_new(i915, .ctx = ctx, .flags = IGT_SPIN_POLL_RUN);
+	igt_spin_busywait_until_started(spin);
+
+	for (int i = 0; i < num_wa_regs; i++) {
+		uint32_t value =
+			*(uint32_t *)(igt_global_mmio + wa_regs[i].addr);
+		const bool ok =
+			(wa_regs[i].value & wa_regs[i].mask) ==
+			(value & wa_regs[i].mask);
+		char buf[80];
+
+		snprintf(buf, sizeof(buf),
+			 "0x%05X\t0x%08X\t0x%08X\t0x%08X",
+			 wa_regs[i].addr, wa_regs[i].value, wa_regs[i].mask,
+			 value);
+
+		if (ok) {
+			igt_debug("%s\tOK\n", buf);
+		} else if (write_only(wa_regs[i].addr)) {
+			igt_debug("%s\tIGNORED (w/o)\n", buf);
+		} else {
+			igt_warn("%s\tFAIL\n", buf);
+			fail++;
+		}
+	}
 
-	snprintf(path, sizeof(path), "/proc/self/fd/%d", fd);
-	fd = open(path, O_RDWR);
-	igt_assert_lte(0, fd);
+	igt_spin_free(i915, spin);
 
-	return fd;
+	return fail;
 }
+#endif
 
 #define CONTEXT 0x1
 #define FD 0x2
@@ -181,7 +210,7 @@ static void check_workarounds(int fd, enum operation op, unsigned int flags)
 	uint32_t ctx = 0;
 
 	if (flags & FD)
-		fd = reopen(fd);
+		fd = gem_reopen_driver(fd);
 
 	if (flags & CONTEXT) {
 		gem_require_contexts(fd);
-- 
2.20.1

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[igt-dev] ✓ Fi.CI.BAT: success for i915/gem_workarounds: Verify regs directly

[Patchwork]

== Series Details ==

Series: i915/gem_workarounds: Verify regs directly
URL   : https://patchwork.freedesktop.org/series/61140/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6141 -> IGTPW_3058
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/61140/revisions/1/mbox/

Known issues
------------

  Here are the changes found in IGTPW_3058 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_auth@basic-auth:
    - fi-icl-u3:          [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/fi-icl-u3/igt@core_auth@basic-auth.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/fi-icl-u3/igt@core_auth@basic-auth.html

  * igt@gem_workarounds@basic-read:
    - fi-apl-guc:         [PASS][3] -> [FAIL][4] ([fdo#110544])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/fi-apl-guc/igt@gem_workarounds@basic-read.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/fi-apl-guc/igt@gem_workarounds@basic-read.html

  * igt@i915_module_load@reload-with-fault-injection:
    - fi-icl-u3:          [PASS][5] -> [DMESG-WARN][6] ([fdo#110718])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/fi-icl-u3/igt@i915_module_load@reload-with-fault-injection.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/fi-icl-u3/igt@i915_module_load@reload-with-fault-injection.html

  
#### Possible fixes ####

  * igt@gem_mmap_gtt@basic:
    - fi-icl-u3:          [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/fi-icl-u3/igt@gem_mmap_gtt@basic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/fi-icl-u3/igt@gem_mmap_gtt@basic.html

  * igt@gem_workarounds@basic-read:
    - fi-cml-u2:          [FAIL][9] ([fdo#110544]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/fi-cml-u2/igt@gem_workarounds@basic-read.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/fi-cml-u2/igt@gem_workarounds@basic-read.html
    - fi-cml-u:           [FAIL][11] ([fdo#110544]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/fi-cml-u/igt@gem_workarounds@basic-read.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/fi-cml-u/igt@gem_workarounds@basic-read.html

  * igt@i915_pm_rpm@basic-rte:
    - fi-skl-6600u:       [INCOMPLETE][13] ([fdo#107807]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/fi-skl-6600u/igt@i915_pm_rpm@basic-rte.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/fi-skl-6600u/igt@i915_pm_rpm@basic-rte.html

  * igt@kms_addfb_basic@bad-pitch-65536:
    - {fi-icl-dsi}:       [INCOMPLETE][15] ([fdo#107713]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/fi-icl-dsi/igt@kms_addfb_basic@bad-pitch-65536.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/fi-icl-dsi/igt@kms_addfb_basic@bad-pitch-65536.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#110544]: https://bugs.freedesktop.org/show_bug.cgi?id=110544
  [fdo#110718]: https://bugs.freedesktop.org/show_bug.cgi?id=110718


Participating hosts (53 -> 46)
------------------------------

  Missing    (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * IGT: IGT_5015 -> IGTPW_3058

  CI_DRM_6141: e94845147cc0346c3a9114d5359b188008daff9d @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3058: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/
  IGT_5015: cdd6b0a7630762cec14596b9863f418b48c32f46 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/
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[igt-dev] ✗ Fi.CI.IGT: failure for i915/gem_workarounds: Verify regs directly

[Patchwork]

== Series Details ==

Series: i915/gem_workarounds: Verify regs directly
URL   : https://patchwork.freedesktop.org/series/61140/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6141_full -> IGTPW_3058_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_3058_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_3058_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/61140/revisions/1/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_3058_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_workarounds@basic-read:
    - shard-iclb:         NOTRUN -> [FAIL][1] +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/shard-iclb1/igt@gem_workarounds@basic-read.html

  
Known issues
------------

  Here are the changes found in IGTPW_3058_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ppgtt@blt-vs-render-ctxn:
    - shard-snb:          [PASS][2] -> [INCOMPLETE][3] ([fdo#105411])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/shard-snb2/igt@gem_ppgtt@blt-vs-render-ctxn.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/shard-snb1/igt@gem_ppgtt@blt-vs-render-ctxn.html

  * igt@gem_workarounds@reset-fd:
    - shard-apl:          [PASS][4] -> [FAIL][5] ([fdo#110544]) +6 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/shard-apl6/igt@gem_workarounds@reset-fd.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/shard-apl3/igt@gem_workarounds@reset-fd.html

  * igt@kms_busy@extended-modeset-hang-newfb-render-a:
    - shard-hsw:          [PASS][6] -> [INCOMPLETE][7] ([fdo#103540])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/shard-hsw4/igt@kms_busy@extended-modeset-hang-newfb-render-a.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/shard-hsw5/igt@kms_busy@extended-modeset-hang-newfb-render-a.html

  * igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack:
    - shard-glk:          [PASS][8] -> [INCOMPLETE][9] ([fdo#103359] / [k.org#198133])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/shard-glk4/igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/shard-glk8/igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
    - shard-iclb:         [PASS][10] -> [FAIL][11] ([fdo#103167]) +5 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         [PASS][12] -> [SKIP][13] ([fdo#109642])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/shard-iclb2/igt@kms_psr2_su@page_flip.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/shard-iclb1/igt@kms_psr2_su@page_flip.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [PASS][14] -> [SKIP][15] ([fdo#109441]) +2 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/shard-iclb5/igt@kms_psr@psr2_sprite_plane_move.html

  * igt@kms_setmode@basic:
    - shard-hsw:          [PASS][16] -> [FAIL][17] ([fdo#99912])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/shard-hsw1/igt@kms_setmode@basic.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/shard-hsw7/igt@kms_setmode@basic.html

  * igt@kms_universal_plane@universal-plane-pipe-a-functional:
    - shard-snb:          [PASS][18] -> [SKIP][19] ([fdo#109271])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/shard-snb5/igt@kms_universal_plane@universal-plane-pipe-a-functional.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/shard-snb1/igt@kms_universal_plane@universal-plane-pipe-a-functional.html

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-apl:          [PASS][20] -> [DMESG-WARN][21] ([fdo#108566]) +6 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/shard-apl1/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/shard-apl6/igt@kms_vblank@pipe-c-ts-continuation-suspend.html

  
#### Possible fixes ####

  * igt@gem_exec_schedule@preemptive-hang-render:
    - shard-apl:          [INCOMPLETE][22] ([fdo#103927]) -> [PASS][23]
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/shard-apl6/igt@gem_exec_schedule@preemptive-hang-render.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/shard-apl6/igt@gem_exec_schedule@preemptive-hang-render.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-apl:          [DMESG-WARN][24] ([fdo#108566]) -> [PASS][25] +4 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/shard-apl3/igt@i915_suspend@fence-restore-tiled2untiled.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/shard-apl7/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_cursor_crc@pipe-b-cursor-256x85-sliding:
    - shard-apl:          [FAIL][26] ([fdo#103232]) -> [PASS][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/shard-apl8/igt@kms_cursor_crc@pipe-b-cursor-256x85-sliding.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/shard-apl3/igt@kms_cursor_crc@pipe-b-cursor-256x85-sliding.html
    - shard-kbl:          [FAIL][28] ([fdo#103232]) -> [PASS][29]
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/shard-kbl1/igt@kms_cursor_crc@pipe-b-cursor-256x85-sliding.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/shard-kbl6/igt@kms_cursor_crc@pipe-b-cursor-256x85-sliding.html

  * igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
    - shard-glk:          [FAIL][30] ([fdo#106509] / [fdo#107409]) -> [PASS][31]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/shard-glk8/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/shard-glk4/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-hsw:          [SKIP][32] ([fdo#109271]) -> [PASS][33] +16 similar issues
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/shard-hsw1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/shard-hsw7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-glk:          [FAIL][34] ([fdo#103060]) -> [PASS][35]
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/shard-glk1/igt@kms_flip@2x-modeset-vs-vblank-race.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/shard-glk5/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt:
    - shard-iclb:         [FAIL][36] ([fdo#103167]) -> [PASS][37] +7 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
    - shard-glk:          [INCOMPLETE][38] ([fdo#103359] / [k.org#198133]) -> [PASS][39]
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/shard-glk1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/shard-glk4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-iclb:         [FAIL][40] ([fdo#103166]) -> [PASS][41]
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/shard-iclb8/igt@kms_plane_lowres@pipe-a-tiling-x.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-x.html

  * igt@kms_psr@psr2_cursor_blt:
    - shard-iclb:         [SKIP][42] ([fdo#109441]) -> [PASS][43]
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/shard-iclb5/igt@kms_psr@psr2_cursor_blt.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html

  
#### Warnings ####

  * igt@gem_workarounds@suspend-resume:
    - shard-apl:          [DMESG-WARN][44] ([fdo#108566]) -> [FAIL][45] ([fdo#110544]) +1 similar issue
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/shard-apl6/igt@gem_workarounds@suspend-resume.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/shard-apl6/igt@gem_workarounds@suspend-resume.html

  * igt@prime_vgem@wait-bsd1:
    - shard-snb:          [FAIL][46] -> [INCOMPLETE][47] ([fdo#105411])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6141/shard-snb6/igt@prime_vgem@wait-bsd1.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/shard-snb5/igt@prime_vgem@wait-bsd1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#106509]: https://bugs.freedesktop.org/show_bug.cgi?id=106509
  [fdo#107409]: https://bugs.freedesktop.org/show_bug.cgi?id=107409
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110544]: https://bugs.freedesktop.org/show_bug.cgi?id=110544
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (10 -> 6)
------------------------------

  Missing    (4): pig-skl-6260u shard-skl pig-hsw-4770r pig-glk-j5005 


Build changes
-------------

  * IGT: IGT_5015 -> IGTPW_3058
  * Piglit: piglit_4509 -> None

  CI_DRM_6141: e94845147cc0346c3a9114d5359b188008daff9d @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3058: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/
  IGT_5015: cdd6b0a7630762cec14596b9863f418b48c32f46 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3058/
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Re: [igt-dev] [PATCH i-g-t] i915/gem_workarounds: Verify regs directly

[Matthew Auld]

On Sat, 25 May 2019 at 08:05, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>
> ---

Reviewed-by: Matthew Auld <matthew.auld@intel.com>

>  tests/i915/gem_workarounds.c | 45 +++++++++++++++++++++++++++++-------
>  1 file changed, 37 insertions(+), 8 deletions(-)
>
> diff --git a/tests/i915/gem_workarounds.c b/tests/i915/gem_workarounds.c
> index 44e3dce8a..bf8b4f630 100644
> --- a/tests/i915/gem_workarounds.c
> +++ b/tests/i915/gem_workarounds.c
> @@ -82,6 +82,7 @@ static bool write_only(const uint32_t addr)
>
>  #define MI_STORE_REGISTER_MEM (0x24 << 23)
>
> +#if 0
>  static int workaround_fail_count(int fd, uint32_t ctx)
>  {
>         struct drm_i915_gem_exec_object2 obj[2];
> @@ -162,17 +163,45 @@ static int workaround_fail_count(int fd, uint32_t ctx)
>
>         return fail_count;
>  }
> -
> -static int reopen(int fd)
> +#else
> +static int workaround_fail_count(int i915, uint32_t ctx)
>  {
> -       char path[256];
> +       igt_spin_t *spin;
> +       int fail = 0;
> +
> +       intel_mmio_use_pci_bar(intel_get_pci_device());
> +
> +       spin = igt_spin_new(i915, .ctx = ctx, .flags = IGT_SPIN_POLL_RUN);
> +       igt_spin_busywait_until_started(spin);
> +
> +       for (int i = 0; i < num_wa_regs; i++) {
> +               uint32_t value =
> +                       *(uint32_t *)(igt_global_mmio + wa_regs[i].addr);
> +               const bool ok =
> +                       (wa_regs[i].value & wa_regs[i].mask) ==
> +                       (value & wa_regs[i].mask);
> +               char buf[80];
> +
> +               snprintf(buf, sizeof(buf),
> +                        "0x%05X\t0x%08X\t0x%08X\t0x%08X",
> +                        wa_regs[i].addr, wa_regs[i].value, wa_regs[i].mask,
> +                        value);
> +
> +               if (ok) {
> +                       igt_debug("%s\tOK\n", buf);
> +               } else if (write_only(wa_regs[i].addr)) {
> +                       igt_debug("%s\tIGNORED (w/o)\n", buf);
> +               } else {
> +                       igt_warn("%s\tFAIL\n", buf);
> +                       fail++;
> +               }
> +       }
>
> -       snprintf(path, sizeof(path), "/proc/self/fd/%d", fd);
> -       fd = open(path, O_RDWR);
> -       igt_assert_lte(0, fd);
> +       igt_spin_free(i915, spin);
>
> -       return fd;
> +       return fail;
>  }
> +#endif
>
>  #define CONTEXT 0x1
>  #define FD 0x2
> @@ -181,7 +210,7 @@ static void check_workarounds(int fd, enum operation op, unsigned int flags)
>         uint32_t ctx = 0;
>
>         if (flags & FD)
> -               fd = reopen(fd);
> +               fd = gem_reopen_driver(fd);
>
>         if (flags & CONTEXT) {
>                 gem_require_contexts(fd);
> --
> 2.20.1
>
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [igt-dev] [PATCH i-g-t] i915/gem_workarounds: Verify regs directly

[Matthew Auld]

On Sat, 25 May 2019 at 08:05, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>
> ---

Reviewed-by: Matthew Auld <matthew.auld@intel.com>

>  tests/i915/gem_workarounds.c | 45 +++++++++++++++++++++++++++++-------
>  1 file changed, 37 insertions(+), 8 deletions(-)
>
> diff --git a/tests/i915/gem_workarounds.c b/tests/i915/gem_workarounds.c
> index 44e3dce8a..bf8b4f630 100644
> --- a/tests/i915/gem_workarounds.c
> +++ b/tests/i915/gem_workarounds.c
> @@ -82,6 +82,7 @@ static bool write_only(const uint32_t addr)
>
>  #define MI_STORE_REGISTER_MEM (0x24 << 23)
>
> +#if 0
>  static int workaround_fail_count(int fd, uint32_t ctx)
>  {
>         struct drm_i915_gem_exec_object2 obj[2];
> @@ -162,17 +163,45 @@ static int workaround_fail_count(int fd, uint32_t ctx)
>
>         return fail_count;
>  }
> -
> -static int reopen(int fd)
> +#else
> +static int workaround_fail_count(int i915, uint32_t ctx)
>  {
> -       char path[256];
> +       igt_spin_t *spin;
> +       int fail = 0;
> +
> +       intel_mmio_use_pci_bar(intel_get_pci_device());
> +
> +       spin = igt_spin_new(i915, .ctx = ctx, .flags = IGT_SPIN_POLL_RUN);
> +       igt_spin_busywait_until_started(spin);
> +
> +       for (int i = 0; i < num_wa_regs; i++) {
> +               uint32_t value =
> +                       *(uint32_t *)(igt_global_mmio + wa_regs[i].addr);
> +               const bool ok =
> +                       (wa_regs[i].value & wa_regs[i].mask) ==
> +                       (value & wa_regs[i].mask);
> +               char buf[80];
> +
> +               snprintf(buf, sizeof(buf),
> +                        "0x%05X\t0x%08X\t0x%08X\t0x%08X",
> +                        wa_regs[i].addr, wa_regs[i].value, wa_regs[i].mask,
> +                        value);
> +
> +               if (ok) {
> +                       igt_debug("%s\tOK\n", buf);
> +               } else if (write_only(wa_regs[i].addr)) {
> +                       igt_debug("%s\tIGNORED (w/o)\n", buf);
> +               } else {
> +                       igt_warn("%s\tFAIL\n", buf);
> +                       fail++;
> +               }
> +       }
>
> -       snprintf(path, sizeof(path), "/proc/self/fd/%d", fd);
> -       fd = open(path, O_RDWR);
> -       igt_assert_lte(0, fd);
> +       igt_spin_free(i915, spin);
>
> -       return fd;
> +       return fail;
>  }
> +#endif
>
>  #define CONTEXT 0x1
>  #define FD 0x2
> @@ -181,7 +210,7 @@ static void check_workarounds(int fd, enum operation op, unsigned int flags)
>         uint32_t ctx = 0;
>
>         if (flags & FD)
> -               fd = reopen(fd);
> +               fd = gem_reopen_driver(fd);
>
>         if (flags & CONTEXT) {
>                 gem_require_contexts(fd);
> --
> 2.20.1
>
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [igt-dev] [PATCH i-g-t] i915/gem_workarounds: Verify regs directly

[Chris Wilson]

Quoting Mika Kuoppala (2019-05-29 11:15:46)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
> 
> > It seems like the HW validator is getting better at preventing our
> > snooping of system registers from non-privileged batches! If we can't
> > use SRM, let's probe the register directly through mmio, making sure we
> > have the context spinning on the GPU first.
> >
> > v2: Hold forcewake just in case the spinning batch isn't enough to
> > justify our register access.
> >
> 
> If I recall correctly, either of them separately didn't
> work. And there was delay after grabbing the fw before
> the register contents appeared. Don't remember the gen tho.

That would be a kernel bug / HW bug. Either we fail in our ack sequence
(maybe let the read overtake the fw ack or something equally impossible),
or the HW fails in its.

If you can think of a way of spotting it, add it to
selftests/intel_uncore -- it's exactly the type of test we need in bring
up, verifying our mmio is accurate.

> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110544
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Matthew Auld <matthew.william.auld@gmail.com>
> > ---
> >  tests/i915/gem_workarounds.c | 88 +++++++-----------------------------
> >  1 file changed, 17 insertions(+), 71 deletions(-)
> >
> > diff --git a/tests/i915/gem_workarounds.c b/tests/i915/gem_workarounds.c
> > index 44e3dce8a..2767b04d7 100644
> > --- a/tests/i915/gem_workarounds.c
> > +++ b/tests/i915/gem_workarounds.c
> > @@ -80,70 +80,27 @@ static bool write_only(const uint32_t addr)
> >       return false;
> >  }
> >  
> > -#define MI_STORE_REGISTER_MEM (0x24 << 23)
> > -
> > -static int workaround_fail_count(int fd, uint32_t ctx)
> > +static int workaround_fail_count(int i915, uint32_t ctx)
> >  {
> > -     struct drm_i915_gem_exec_object2 obj[2];
> > -     struct drm_i915_gem_relocation_entry *reloc;
> > -     struct drm_i915_gem_execbuffer2 execbuf;
> > -     uint32_t result_sz, batch_sz;
> > -     uint32_t *base, *out;
> > -     int fail_count = 0;
> > -
> > -     reloc = calloc(num_wa_regs, sizeof(*reloc));
> > -     igt_assert(reloc);
> > -
> > -     result_sz = 4 * num_wa_regs;
> > -     result_sz = PAGE_ALIGN(result_sz);
> > -
> > -     batch_sz = 16 * num_wa_regs + 4;
> > -     batch_sz = PAGE_ALIGN(batch_sz);
> > -
> > -     memset(obj, 0, sizeof(obj));
> > -     obj[0].handle = gem_create(fd, result_sz);
> > -     gem_set_caching(fd, obj[0].handle, I915_CACHING_CACHED);
> > -     obj[1].handle = gem_create(fd, batch_sz);
> > -     obj[1].relocs_ptr = to_user_pointer(reloc);
> > -     obj[1].relocation_count = num_wa_regs;
> > -
> > -     out = base = gem_mmap__cpu(fd, obj[1].handle, 0, batch_sz, PROT_WRITE);
> > -     for (int i = 0; i < num_wa_regs; i++) {
> > -             *out++ = MI_STORE_REGISTER_MEM | ((gen >= 8 ? 4 : 2) - 2);
> > -             *out++ = wa_regs[i].addr;
> > -             reloc[i].target_handle = obj[0].handle;
> > -             reloc[i].offset = (out - base) * sizeof(*out);
> > -             reloc[i].delta = i * sizeof(uint32_t);
> > -             reloc[i].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
> > -             reloc[i].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
> > -             *out++ = reloc[i].delta;
> > -             if (gen >= 8)
> > -                     *out++ = 0;
> > -     }
> > -     *out++ = MI_BATCH_BUFFER_END;
> > -     munmap(base, batch_sz);
> > +     igt_spin_t *spin;
> > +     int fw, fail = 0;
> >  
> > -     memset(&execbuf, 0, sizeof(execbuf));
> > -     execbuf.buffers_ptr = to_user_pointer(obj);
> > -     execbuf.buffer_count = 2;
> > -     execbuf.rsvd1 = ctx;
> > -     gem_execbuf(fd, &execbuf);
> > +     spin = igt_spin_new(i915, .ctx = ctx, .flags = IGT_SPIN_POLL_RUN);
> > +     igt_spin_busywait_until_started(spin);
> >  
> > -     gem_set_domain(fd, obj[0].handle, I915_GEM_DOMAIN_CPU, 0);
> > -
> > -     igt_debug("Address\tval\t\tmask\t\tread\t\tresult\n");
> > -
> > -     out = gem_mmap__cpu(fd, obj[0].handle, 0, result_sz, PROT_READ);
> > +     fw = igt_open_forcewake_handle(i915);
> 
> assert that it went fine?

Do we always expect the debugfs to be present? Do we strictly need it?
igt_debug if it isn't present and correlate that to a fail.
 
> Perhaps both will now do the trick. But if it fails
> get the forcewake before spinner so you get more delay.

Nah, I vote that in that case forcewake is broken and needs a kernel fix,
as we don't have any such delay when using I915_READ().
-Chris
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Re: [igt-dev] [PATCH i-g-t] i915/gem_workarounds: Verify regs directly

[Chris Wilson]

Quoting Mika Kuoppala (2019-05-29 11:15:46)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
> 
> > It seems like the HW validator is getting better at preventing our
> > snooping of system registers from non-privileged batches! If we can't
> > use SRM, let's probe the register directly through mmio, making sure we
> > have the context spinning on the GPU first.
> >
> > v2: Hold forcewake just in case the spinning batch isn't enough to
> > justify our register access.
> >
> 
> If I recall correctly, either of them separately didn't
> work. And there was delay after grabbing the fw before
> the register contents appeared. Don't remember the gen tho.

That would be a kernel bug / HW bug. Either we fail in our ack sequence
(maybe let the read overtake the fw ack or something equally impossible),
or the HW fails in its.

If you can think of a way of spotting it, add it to
selftests/intel_uncore -- it's exactly the type of test we need in bring
up, verifying our mmio is accurate.

> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110544
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Matthew Auld <matthew.william.auld@gmail.com>
> > ---
> >  tests/i915/gem_workarounds.c | 88 +++++++-----------------------------
> >  1 file changed, 17 insertions(+), 71 deletions(-)
> >
> > diff --git a/tests/i915/gem_workarounds.c b/tests/i915/gem_workarounds.c
> > index 44e3dce8a..2767b04d7 100644
> > --- a/tests/i915/gem_workarounds.c
> > +++ b/tests/i915/gem_workarounds.c
> > @@ -80,70 +80,27 @@ static bool write_only(const uint32_t addr)
> >       return false;
> >  }
> >  
> > -#define MI_STORE_REGISTER_MEM (0x24 << 23)
> > -
> > -static int workaround_fail_count(int fd, uint32_t ctx)
> > +static int workaround_fail_count(int i915, uint32_t ctx)
> >  {
> > -     struct drm_i915_gem_exec_object2 obj[2];
> > -     struct drm_i915_gem_relocation_entry *reloc;
> > -     struct drm_i915_gem_execbuffer2 execbuf;
> > -     uint32_t result_sz, batch_sz;
> > -     uint32_t *base, *out;
> > -     int fail_count = 0;
> > -
> > -     reloc = calloc(num_wa_regs, sizeof(*reloc));
> > -     igt_assert(reloc);
> > -
> > -     result_sz = 4 * num_wa_regs;
> > -     result_sz = PAGE_ALIGN(result_sz);
> > -
> > -     batch_sz = 16 * num_wa_regs + 4;
> > -     batch_sz = PAGE_ALIGN(batch_sz);
> > -
> > -     memset(obj, 0, sizeof(obj));
> > -     obj[0].handle = gem_create(fd, result_sz);
> > -     gem_set_caching(fd, obj[0].handle, I915_CACHING_CACHED);
> > -     obj[1].handle = gem_create(fd, batch_sz);
> > -     obj[1].relocs_ptr = to_user_pointer(reloc);
> > -     obj[1].relocation_count = num_wa_regs;
> > -
> > -     out = base = gem_mmap__cpu(fd, obj[1].handle, 0, batch_sz, PROT_WRITE);
> > -     for (int i = 0; i < num_wa_regs; i++) {
> > -             *out++ = MI_STORE_REGISTER_MEM | ((gen >= 8 ? 4 : 2) - 2);
> > -             *out++ = wa_regs[i].addr;
> > -             reloc[i].target_handle = obj[0].handle;
> > -             reloc[i].offset = (out - base) * sizeof(*out);
> > -             reloc[i].delta = i * sizeof(uint32_t);
> > -             reloc[i].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
> > -             reloc[i].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
> > -             *out++ = reloc[i].delta;
> > -             if (gen >= 8)
> > -                     *out++ = 0;
> > -     }
> > -     *out++ = MI_BATCH_BUFFER_END;
> > -     munmap(base, batch_sz);
> > +     igt_spin_t *spin;
> > +     int fw, fail = 0;
> >  
> > -     memset(&execbuf, 0, sizeof(execbuf));
> > -     execbuf.buffers_ptr = to_user_pointer(obj);
> > -     execbuf.buffer_count = 2;
> > -     execbuf.rsvd1 = ctx;
> > -     gem_execbuf(fd, &execbuf);
> > +     spin = igt_spin_new(i915, .ctx = ctx, .flags = IGT_SPIN_POLL_RUN);
> > +     igt_spin_busywait_until_started(spin);
> >  
> > -     gem_set_domain(fd, obj[0].handle, I915_GEM_DOMAIN_CPU, 0);
> > -
> > -     igt_debug("Address\tval\t\tmask\t\tread\t\tresult\n");
> > -
> > -     out = gem_mmap__cpu(fd, obj[0].handle, 0, result_sz, PROT_READ);
> > +     fw = igt_open_forcewake_handle(i915);
> 
> assert that it went fine?

Do we always expect the debugfs to be present? Do we strictly need it?
igt_debug if it isn't present and correlate that to a fail.
 
> Perhaps both will now do the trick. But if it fails
> get the forcewake before spinner so you get more delay.

Nah, I vote that in that case forcewake is broken and needs a kernel fix,
as we don't have any such delay when using I915_READ().
-Chris
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Re: [igt-dev] [PATCH i-g-t] i915/gem_workarounds: Verify regs directly

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> It seems like the HW validator is getting better at preventing our
> snooping of system registers from non-privileged batches! If we can't
> use SRM, let's probe the register directly through mmio, making sure we
> have the context spinning on the GPU first.
>
> v2: Hold forcewake just in case the spinning batch isn't enough to
> justify our register access.
>

If I recall correctly, either of them separately didn't
work. And there was delay after grabbing the fw before
the register contents appeared. Don't remember the gen tho.

> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110544
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Matthew Auld <matthew.william.auld@gmail.com>
> ---
>  tests/i915/gem_workarounds.c | 88 +++++++-----------------------------
>  1 file changed, 17 insertions(+), 71 deletions(-)
>
> diff --git a/tests/i915/gem_workarounds.c b/tests/i915/gem_workarounds.c
> index 44e3dce8a..2767b04d7 100644
> --- a/tests/i915/gem_workarounds.c
> +++ b/tests/i915/gem_workarounds.c
> @@ -80,70 +80,27 @@ static bool write_only(const uint32_t addr)
>  	return false;
>  }
>  
> -#define MI_STORE_REGISTER_MEM (0x24 << 23)
> -
> -static int workaround_fail_count(int fd, uint32_t ctx)
> +static int workaround_fail_count(int i915, uint32_t ctx)
>  {
> -	struct drm_i915_gem_exec_object2 obj[2];
> -	struct drm_i915_gem_relocation_entry *reloc;
> -	struct drm_i915_gem_execbuffer2 execbuf;
> -	uint32_t result_sz, batch_sz;
> -	uint32_t *base, *out;
> -	int fail_count = 0;
> -
> -	reloc = calloc(num_wa_regs, sizeof(*reloc));
> -	igt_assert(reloc);
> -
> -	result_sz = 4 * num_wa_regs;
> -	result_sz = PAGE_ALIGN(result_sz);
> -
> -	batch_sz = 16 * num_wa_regs + 4;
> -	batch_sz = PAGE_ALIGN(batch_sz);
> -
> -	memset(obj, 0, sizeof(obj));
> -	obj[0].handle = gem_create(fd, result_sz);
> -	gem_set_caching(fd, obj[0].handle, I915_CACHING_CACHED);
> -	obj[1].handle = gem_create(fd, batch_sz);
> -	obj[1].relocs_ptr = to_user_pointer(reloc);
> -	obj[1].relocation_count = num_wa_regs;
> -
> -	out = base = gem_mmap__cpu(fd, obj[1].handle, 0, batch_sz, PROT_WRITE);
> -	for (int i = 0; i < num_wa_regs; i++) {
> -		*out++ = MI_STORE_REGISTER_MEM | ((gen >= 8 ? 4 : 2) - 2);
> -		*out++ = wa_regs[i].addr;
> -		reloc[i].target_handle = obj[0].handle;
> -		reloc[i].offset = (out - base) * sizeof(*out);
> -		reloc[i].delta = i * sizeof(uint32_t);
> -		reloc[i].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
> -		reloc[i].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
> -		*out++ = reloc[i].delta;
> -		if (gen >= 8)
> -			*out++ = 0;
> -	}
> -	*out++ = MI_BATCH_BUFFER_END;
> -	munmap(base, batch_sz);
> +	igt_spin_t *spin;
> +	int fw, fail = 0;
>  
> -	memset(&execbuf, 0, sizeof(execbuf));
> -	execbuf.buffers_ptr = to_user_pointer(obj);
> -	execbuf.buffer_count = 2;
> -	execbuf.rsvd1 = ctx;
> -	gem_execbuf(fd, &execbuf);
> +	spin = igt_spin_new(i915, .ctx = ctx, .flags = IGT_SPIN_POLL_RUN);
> +	igt_spin_busywait_until_started(spin);
>  
> -	gem_set_domain(fd, obj[0].handle, I915_GEM_DOMAIN_CPU, 0);
> -
> -	igt_debug("Address\tval\t\tmask\t\tread\t\tresult\n");
> -
> -	out = gem_mmap__cpu(fd, obj[0].handle, 0, result_sz, PROT_READ);
> +	fw = igt_open_forcewake_handle(i915);

assert that it went fine?

Perhaps both will now do the trick. But if it fails
get the forcewake before spinner so you get more delay.

>  	for (int i = 0; i < num_wa_regs; i++) {
> +		uint32_t value =
> +			*(uint32_t *)(igt_global_mmio + wa_regs[i].addr);

const might have been warranted.

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

>  		const bool ok =
>  			(wa_regs[i].value & wa_regs[i].mask) ==
> -			(out[i] & wa_regs[i].mask);
> +			(value & wa_regs[i].mask);
>  		char buf[80];
>  
>  		snprintf(buf, sizeof(buf),
>  			 "0x%05X\t0x%08X\t0x%08X\t0x%08X",
>  			 wa_regs[i].addr, wa_regs[i].value, wa_regs[i].mask,
> -			 out[i]);
> +			 value);
>  
>  		if (ok) {
>  			igt_debug("%s\tOK\n", buf);
> @@ -151,27 +108,14 @@ static int workaround_fail_count(int fd, uint32_t ctx)
>  			igt_debug("%s\tIGNORED (w/o)\n", buf);
>  		} else {
>  			igt_warn("%s\tFAIL\n", buf);
> -			fail_count++;
> +			fail++;
>  		}
>  	}
> -	munmap(out, result_sz);
> +	close(fw);
>  
> -	gem_close(fd, obj[1].handle);
> -	gem_close(fd, obj[0].handle);
> -	free(reloc);
> +	igt_spin_free(i915, spin);
>  
> -	return fail_count;
> -}
> -
> -static int reopen(int fd)
> -{
> -	char path[256];
> -
> -	snprintf(path, sizeof(path), "/proc/self/fd/%d", fd);
> -	fd = open(path, O_RDWR);
> -	igt_assert_lte(0, fd);
> -
> -	return fd;
> +	return fail;
>  }
>  
>  #define CONTEXT 0x1
> @@ -181,7 +125,7 @@ static void check_workarounds(int fd, enum operation op, unsigned int flags)
>  	uint32_t ctx = 0;
>  
>  	if (flags & FD)
> -		fd = reopen(fd);
> +		fd = gem_reopen_driver(fd);
>  
>  	if (flags & CONTEXT) {
>  		gem_require_contexts(fd);
> @@ -252,6 +196,8 @@ igt_main
>  		device = drm_open_driver(DRIVER_INTEL);
>  		igt_require_gem(device);
>  
> +		intel_mmio_use_pci_bar(intel_get_pci_device());
> +
>  		gen = intel_gen(intel_get_drm_devid(device));
>  
>  		fd = igt_debugfs_open(device, "i915_wa_registers", O_RDONLY);
> -- 
> 2.20.1
>
> _______________________________________________
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> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [igt-dev] [PATCH i-g-t] i915/gem_workarounds: Verify regs directly

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> It seems like the HW validator is getting better at preventing our
> snooping of system registers from non-privileged batches! If we can't
> use SRM, let's probe the register directly through mmio, making sure we
> have the context spinning on the GPU first.
>
> v2: Hold forcewake just in case the spinning batch isn't enough to
> justify our register access.
>

If I recall correctly, either of them separately didn't
work. And there was delay after grabbing the fw before
the register contents appeared. Don't remember the gen tho.

> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110544
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Matthew Auld <matthew.william.auld@gmail.com>
> ---
>  tests/i915/gem_workarounds.c | 88 +++++++-----------------------------
>  1 file changed, 17 insertions(+), 71 deletions(-)
>
> diff --git a/tests/i915/gem_workarounds.c b/tests/i915/gem_workarounds.c
> index 44e3dce8a..2767b04d7 100644
> --- a/tests/i915/gem_workarounds.c
> +++ b/tests/i915/gem_workarounds.c
> @@ -80,70 +80,27 @@ static bool write_only(const uint32_t addr)
>  	return false;
>  }
>  
> -#define MI_STORE_REGISTER_MEM (0x24 << 23)
> -
> -static int workaround_fail_count(int fd, uint32_t ctx)
> +static int workaround_fail_count(int i915, uint32_t ctx)
>  {
> -	struct drm_i915_gem_exec_object2 obj[2];
> -	struct drm_i915_gem_relocation_entry *reloc;
> -	struct drm_i915_gem_execbuffer2 execbuf;
> -	uint32_t result_sz, batch_sz;
> -	uint32_t *base, *out;
> -	int fail_count = 0;
> -
> -	reloc = calloc(num_wa_regs, sizeof(*reloc));
> -	igt_assert(reloc);
> -
> -	result_sz = 4 * num_wa_regs;
> -	result_sz = PAGE_ALIGN(result_sz);
> -
> -	batch_sz = 16 * num_wa_regs + 4;
> -	batch_sz = PAGE_ALIGN(batch_sz);
> -
> -	memset(obj, 0, sizeof(obj));
> -	obj[0].handle = gem_create(fd, result_sz);
> -	gem_set_caching(fd, obj[0].handle, I915_CACHING_CACHED);
> -	obj[1].handle = gem_create(fd, batch_sz);
> -	obj[1].relocs_ptr = to_user_pointer(reloc);
> -	obj[1].relocation_count = num_wa_regs;
> -
> -	out = base = gem_mmap__cpu(fd, obj[1].handle, 0, batch_sz, PROT_WRITE);
> -	for (int i = 0; i < num_wa_regs; i++) {
> -		*out++ = MI_STORE_REGISTER_MEM | ((gen >= 8 ? 4 : 2) - 2);
> -		*out++ = wa_regs[i].addr;
> -		reloc[i].target_handle = obj[0].handle;
> -		reloc[i].offset = (out - base) * sizeof(*out);
> -		reloc[i].delta = i * sizeof(uint32_t);
> -		reloc[i].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
> -		reloc[i].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
> -		*out++ = reloc[i].delta;
> -		if (gen >= 8)
> -			*out++ = 0;
> -	}
> -	*out++ = MI_BATCH_BUFFER_END;
> -	munmap(base, batch_sz);
> +	igt_spin_t *spin;
> +	int fw, fail = 0;
>  
> -	memset(&execbuf, 0, sizeof(execbuf));
> -	execbuf.buffers_ptr = to_user_pointer(obj);
> -	execbuf.buffer_count = 2;
> -	execbuf.rsvd1 = ctx;
> -	gem_execbuf(fd, &execbuf);
> +	spin = igt_spin_new(i915, .ctx = ctx, .flags = IGT_SPIN_POLL_RUN);
> +	igt_spin_busywait_until_started(spin);
>  
> -	gem_set_domain(fd, obj[0].handle, I915_GEM_DOMAIN_CPU, 0);
> -
> -	igt_debug("Address\tval\t\tmask\t\tread\t\tresult\n");
> -
> -	out = gem_mmap__cpu(fd, obj[0].handle, 0, result_sz, PROT_READ);
> +	fw = igt_open_forcewake_handle(i915);

assert that it went fine?

Perhaps both will now do the trick. But if it fails
get the forcewake before spinner so you get more delay.

>  	for (int i = 0; i < num_wa_regs; i++) {
> +		uint32_t value =
> +			*(uint32_t *)(igt_global_mmio + wa_regs[i].addr);

const might have been warranted.

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

>  		const bool ok =
>  			(wa_regs[i].value & wa_regs[i].mask) ==
> -			(out[i] & wa_regs[i].mask);
> +			(value & wa_regs[i].mask);
>  		char buf[80];
>  
>  		snprintf(buf, sizeof(buf),
>  			 "0x%05X\t0x%08X\t0x%08X\t0x%08X",
>  			 wa_regs[i].addr, wa_regs[i].value, wa_regs[i].mask,
> -			 out[i]);
> +			 value);
>  
>  		if (ok) {
>  			igt_debug("%s\tOK\n", buf);
> @@ -151,27 +108,14 @@ static int workaround_fail_count(int fd, uint32_t ctx)
>  			igt_debug("%s\tIGNORED (w/o)\n", buf);
>  		} else {
>  			igt_warn("%s\tFAIL\n", buf);
> -			fail_count++;
> +			fail++;
>  		}
>  	}
> -	munmap(out, result_sz);
> +	close(fw);
>  
> -	gem_close(fd, obj[1].handle);
> -	gem_close(fd, obj[0].handle);
> -	free(reloc);
> +	igt_spin_free(i915, spin);
>  
> -	return fail_count;
> -}
> -
> -static int reopen(int fd)
> -{
> -	char path[256];
> -
> -	snprintf(path, sizeof(path), "/proc/self/fd/%d", fd);
> -	fd = open(path, O_RDWR);
> -	igt_assert_lte(0, fd);
> -
> -	return fd;
> +	return fail;
>  }
>  
>  #define CONTEXT 0x1
> @@ -181,7 +125,7 @@ static void check_workarounds(int fd, enum operation op, unsigned int flags)
>  	uint32_t ctx = 0;
>  
>  	if (flags & FD)
> -		fd = reopen(fd);
> +		fd = gem_reopen_driver(fd);
>  
>  	if (flags & CONTEXT) {
>  		gem_require_contexts(fd);
> @@ -252,6 +196,8 @@ igt_main
>  		device = drm_open_driver(DRIVER_INTEL);
>  		igt_require_gem(device);
>  
> +		intel_mmio_use_pci_bar(intel_get_pci_device());
> +
>  		gen = intel_gen(intel_get_drm_devid(device));
>  
>  		fd = igt_debugfs_open(device, "i915_wa_registers", O_RDONLY);
> -- 
> 2.20.1
>
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> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
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[igt-dev] [PATCH i-g-t] i915/gem_workarounds: Verify regs directly

[Chris Wilson]

It seems like the HW validator is getting better at preventing our
snooping of system registers from non-privileged batches! If we can't
use SRM, let's probe the register directly through mmio, making sure we
have the context spinning on the GPU first.

v2: Hold forcewake just in case the spinning batch isn't enough to
justify our register access.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110544
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matthew Auld <matthew.william.auld@gmail.com>
---
 tests/i915/gem_workarounds.c | 88 +++++++-----------------------------
 1 file changed, 17 insertions(+), 71 deletions(-)

diff --git a/tests/i915/gem_workarounds.c b/tests/i915/gem_workarounds.c
index 44e3dce8a..2767b04d7 100644
--- a/tests/i915/gem_workarounds.c
+++ b/tests/i915/gem_workarounds.c
@@ -80,70 +80,27 @@ static bool write_only(const uint32_t addr)
 	return false;
 }
 
-#define MI_STORE_REGISTER_MEM (0x24 << 23)
-
-static int workaround_fail_count(int fd, uint32_t ctx)
+static int workaround_fail_count(int i915, uint32_t ctx)
 {
-	struct drm_i915_gem_exec_object2 obj[2];
-	struct drm_i915_gem_relocation_entry *reloc;
-	struct drm_i915_gem_execbuffer2 execbuf;
-	uint32_t result_sz, batch_sz;
-	uint32_t *base, *out;
-	int fail_count = 0;
-
-	reloc = calloc(num_wa_regs, sizeof(*reloc));
-	igt_assert(reloc);
-
-	result_sz = 4 * num_wa_regs;
-	result_sz = PAGE_ALIGN(result_sz);
-
-	batch_sz = 16 * num_wa_regs + 4;
-	batch_sz = PAGE_ALIGN(batch_sz);
-
-	memset(obj, 0, sizeof(obj));
-	obj[0].handle = gem_create(fd, result_sz);
-	gem_set_caching(fd, obj[0].handle, I915_CACHING_CACHED);
-	obj[1].handle = gem_create(fd, batch_sz);
-	obj[1].relocs_ptr = to_user_pointer(reloc);
-	obj[1].relocation_count = num_wa_regs;
-
-	out = base = gem_mmap__cpu(fd, obj[1].handle, 0, batch_sz, PROT_WRITE);
-	for (int i = 0; i < num_wa_regs; i++) {
-		*out++ = MI_STORE_REGISTER_MEM | ((gen >= 8 ? 4 : 2) - 2);
-		*out++ = wa_regs[i].addr;
-		reloc[i].target_handle = obj[0].handle;
-		reloc[i].offset = (out - base) * sizeof(*out);
-		reloc[i].delta = i * sizeof(uint32_t);
-		reloc[i].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
-		reloc[i].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
-		*out++ = reloc[i].delta;
-		if (gen >= 8)
-			*out++ = 0;
-	}
-	*out++ = MI_BATCH_BUFFER_END;
-	munmap(base, batch_sz);
+	igt_spin_t *spin;
+	int fw, fail = 0;
 
-	memset(&execbuf, 0, sizeof(execbuf));
-	execbuf.buffers_ptr = to_user_pointer(obj);
-	execbuf.buffer_count = 2;
-	execbuf.rsvd1 = ctx;
-	gem_execbuf(fd, &execbuf);
+	spin = igt_spin_new(i915, .ctx = ctx, .flags = IGT_SPIN_POLL_RUN);
+	igt_spin_busywait_until_started(spin);
 
-	gem_set_domain(fd, obj[0].handle, I915_GEM_DOMAIN_CPU, 0);
-
-	igt_debug("Address\tval\t\tmask\t\tread\t\tresult\n");
-
-	out = gem_mmap__cpu(fd, obj[0].handle, 0, result_sz, PROT_READ);
+	fw = igt_open_forcewake_handle(i915);
 	for (int i = 0; i < num_wa_regs; i++) {
+		uint32_t value =
+			*(uint32_t *)(igt_global_mmio + wa_regs[i].addr);
 		const bool ok =
 			(wa_regs[i].value & wa_regs[i].mask) ==
-			(out[i] & wa_regs[i].mask);
+			(value & wa_regs[i].mask);
 		char buf[80];
 
 		snprintf(buf, sizeof(buf),
 			 "0x%05X\t0x%08X\t0x%08X\t0x%08X",
 			 wa_regs[i].addr, wa_regs[i].value, wa_regs[i].mask,
-			 out[i]);
+			 value);
 
 		if (ok) {
 			igt_debug("%s\tOK\n", buf);
@@ -151,27 +108,14 @@ static int workaround_fail_count(int fd, uint32_t ctx)
 			igt_debug("%s\tIGNORED (w/o)\n", buf);
 		} else {
 			igt_warn("%s\tFAIL\n", buf);
-			fail_count++;
+			fail++;
 		}
 	}
-	munmap(out, result_sz);
+	close(fw);
 
-	gem_close(fd, obj[1].handle);
-	gem_close(fd, obj[0].handle);
-	free(reloc);
+	igt_spin_free(i915, spin);
 
-	return fail_count;
-}
-
-static int reopen(int fd)
-{
-	char path[256];
-
-	snprintf(path, sizeof(path), "/proc/self/fd/%d", fd);
-	fd = open(path, O_RDWR);
-	igt_assert_lte(0, fd);
-
-	return fd;
+	return fail;
 }
 
 #define CONTEXT 0x1
@@ -181,7 +125,7 @@ static void check_workarounds(int fd, enum operation op, unsigned int flags)
 	uint32_t ctx = 0;
 
 	if (flags & FD)
-		fd = reopen(fd);
+		fd = gem_reopen_driver(fd);
 
 	if (flags & CONTEXT) {
 		gem_require_contexts(fd);
@@ -252,6 +196,8 @@ igt_main
 		device = drm_open_driver(DRIVER_INTEL);
 		igt_require_gem(device);
 
+		intel_mmio_use_pci_bar(intel_get_pci_device());
+
 		gen = intel_gen(intel_get_drm_devid(device));
 
 		fd = igt_debugfs_open(device, "i915_wa_registers", O_RDONLY);
-- 
2.20.1

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