* [PATCH] drm/i915/gem: Limit the blitter sizes to ensure low preemption latency
@ 2019-10-25 21:05 ` Chris Wilson
0 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2019-10-25 21:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Matthew Auld
Currently we insert a arbitration point every 128MiB during a blitter
copy. At 8GiB/s, this is around 30ms. This is a little on the large side
if we need to inject a high priority work, so reduced it down to 8MiB or
roughly 1ms.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matthew Auld <matthew.auld@intel.com>
---
Ok, I need to do a selftest to ensure we are exceeding the estimated
blitter throughtput, and I would also like a test to measure the
preemption latency directly. Remind me!
---
drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
index 516e61e99212..7e25f05939bc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
@@ -17,7 +17,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce,
u32 value)
{
struct drm_i915_private *i915 = ce->vm->i915;
- const u32 block_size = S16_MAX * PAGE_SIZE;
+ const u32 block_size = SZ_8M; /* ~1ms at 8GiB/s preemption delay */
struct intel_engine_pool_node *pool;
struct i915_vma *batch;
u64 offset;
--
2.24.0.rc1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/gem: Limit the blitter sizes to ensure low preemption latency
@ 2019-10-25 21:05 ` Chris Wilson
0 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2019-10-25 21:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Matthew Auld
Currently we insert a arbitration point every 128MiB during a blitter
copy. At 8GiB/s, this is around 30ms. This is a little on the large side
if we need to inject a high priority work, so reduced it down to 8MiB or
roughly 1ms.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matthew Auld <matthew.auld@intel.com>
---
Ok, I need to do a selftest to ensure we are exceeding the estimated
blitter throughtput, and I would also like a test to measure the
preemption latency directly. Remind me!
---
drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
index 516e61e99212..7e25f05939bc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
@@ -17,7 +17,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce,
u32 value)
{
struct drm_i915_private *i915 = ce->vm->i915;
- const u32 block_size = S16_MAX * PAGE_SIZE;
+ const u32 block_size = SZ_8M; /* ~1ms at 8GiB/s preemption delay */
struct intel_engine_pool_node *pool;
struct i915_vma *batch;
u64 offset;
--
2.24.0.rc1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/gem: Limit the blitter sizes to ensure low preemption latency
@ 2019-10-26 1:24 ` Patchwork
0 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2019-10-26 1:24 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gem: Limit the blitter sizes to ensure low preemption latency
URL : https://patchwork.freedesktop.org/series/68584/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7191 -> Patchwork_14992
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14992 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14992, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14992/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14992:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_blt:
- fi-kbl-8809g: [PASS][1] -> [TIMEOUT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-kbl-8809g/igt@i915_selftest@live_blt.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14992/fi-kbl-8809g/igt@i915_selftest@live_blt.html
- fi-cml-u2: [PASS][3] -> [TIMEOUT][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-cml-u2/igt@i915_selftest@live_blt.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14992/fi-cml-u2/igt@i915_selftest@live_blt.html
- fi-cfl-guc: [PASS][5] -> [TIMEOUT][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-cfl-guc/igt@i915_selftest@live_blt.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14992/fi-cfl-guc/igt@i915_selftest@live_blt.html
* igt@runner@aborted:
- fi-kbl-8809g: NOTRUN -> [FAIL][7]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14992/fi-kbl-8809g/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_14992 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_basic@create-close:
- fi-icl-u3: [PASS][8] -> [DMESG-WARN][9] ([fdo#107724])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-icl-u3/igt@gem_basic@create-close.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14992/fi-icl-u3/igt@gem_basic@create-close.html
* igt@kms_chamelium@dp-edid-read:
- fi-kbl-7500u: [PASS][10] -> [WARN][11] ([fdo#109483])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-kbl-7500u/igt@kms_chamelium@dp-edid-read.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14992/fi-kbl-7500u/igt@kms_chamelium@dp-edid-read.html
#### Possible fixes ####
* igt@gem_close_race@basic-process:
- fi-icl-u3: [INCOMPLETE][12] ([fdo#107713]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-icl-u3/igt@gem_close_race@basic-process.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14992/fi-icl-u3/igt@gem_close_race@basic-process.html
* igt@gem_ctx_switch@rcs0:
- fi-icl-u2: [INCOMPLETE][14] ([fdo#107713]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-icl-u2/igt@gem_ctx_switch@rcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14992/fi-icl-u2/igt@gem_ctx_switch@rcs0.html
* igt@i915_selftest@live_gem_contexts:
- fi-bsw-kefka: [INCOMPLETE][16] -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14992/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111831]: https://bugs.freedesktop.org/show_bug.cgi?id=111831
Participating hosts (50 -> 43)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7191 -> Patchwork_14992
CI-20190529: 20190529
CI_DRM_7191: 59c58784011dbec9a742d33b3d8d673393b95112 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5242: 15c11e2df77f769b5fa9ca5b40a94f266370a479 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14992: d0f0b1e945ecb620782e8dabda87f4dca839060d @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d0f0b1e945ec drm/i915/gem: Limit the blitter sizes to ensure low preemption latency
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14992/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gem: Limit the blitter sizes to ensure low preemption latency
@ 2019-10-26 1:24 ` Patchwork
0 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2019-10-26 1:24 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gem: Limit the blitter sizes to ensure low preemption latency
URL : https://patchwork.freedesktop.org/series/68584/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7191 -> Patchwork_14992
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14992 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14992, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14992/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14992:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_blt:
- fi-kbl-8809g: [PASS][1] -> [TIMEOUT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-kbl-8809g/igt@i915_selftest@live_blt.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14992/fi-kbl-8809g/igt@i915_selftest@live_blt.html
- fi-cml-u2: [PASS][3] -> [TIMEOUT][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-cml-u2/igt@i915_selftest@live_blt.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14992/fi-cml-u2/igt@i915_selftest@live_blt.html
- fi-cfl-guc: [PASS][5] -> [TIMEOUT][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-cfl-guc/igt@i915_selftest@live_blt.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14992/fi-cfl-guc/igt@i915_selftest@live_blt.html
* igt@runner@aborted:
- fi-kbl-8809g: NOTRUN -> [FAIL][7]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14992/fi-kbl-8809g/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_14992 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_basic@create-close:
- fi-icl-u3: [PASS][8] -> [DMESG-WARN][9] ([fdo#107724])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-icl-u3/igt@gem_basic@create-close.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14992/fi-icl-u3/igt@gem_basic@create-close.html
* igt@kms_chamelium@dp-edid-read:
- fi-kbl-7500u: [PASS][10] -> [WARN][11] ([fdo#109483])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-kbl-7500u/igt@kms_chamelium@dp-edid-read.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14992/fi-kbl-7500u/igt@kms_chamelium@dp-edid-read.html
#### Possible fixes ####
* igt@gem_close_race@basic-process:
- fi-icl-u3: [INCOMPLETE][12] ([fdo#107713]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-icl-u3/igt@gem_close_race@basic-process.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14992/fi-icl-u3/igt@gem_close_race@basic-process.html
* igt@gem_ctx_switch@rcs0:
- fi-icl-u2: [INCOMPLETE][14] ([fdo#107713]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-icl-u2/igt@gem_ctx_switch@rcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14992/fi-icl-u2/igt@gem_ctx_switch@rcs0.html
* igt@i915_selftest@live_gem_contexts:
- fi-bsw-kefka: [INCOMPLETE][16] -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7191/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14992/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111831]: https://bugs.freedesktop.org/show_bug.cgi?id=111831
Participating hosts (50 -> 43)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7191 -> Patchwork_14992
CI-20190529: 20190529
CI_DRM_7191: 59c58784011dbec9a742d33b3d8d673393b95112 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5242: 15c11e2df77f769b5fa9ca5b40a94f266370a479 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14992: d0f0b1e945ecb620782e8dabda87f4dca839060d @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d0f0b1e945ec drm/i915/gem: Limit the blitter sizes to ensure low preemption latency
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14992/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915/gem: Limit the blitter sizes to ensure low preemption latency
@ 2019-10-28 16:43 ` Matthew Auld
0 siblings, 0 replies; 6+ messages in thread
From: Matthew Auld @ 2019-10-28 16:43 UTC (permalink / raw)
To: Chris Wilson; +Cc: Intel Graphics Development, Matthew Auld
On Fri, 25 Oct 2019 at 22:06, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>
> Currently we insert a arbitration point every 128MiB during a blitter
> copy. At 8GiB/s, this is around 30ms. This is a little on the large side
> if we need to inject a high priority work, so reduced it down to 8MiB or
> roughly 1ms.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Matthew Auld <matthew.auld@intel.com>
> ---
> Ok, I need to do a selftest to ensure we are exceeding the estimated
> blitter throughtput, and I would also like a test to measure the
> preemption latency directly. Remind me!
> ---
> drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> index 516e61e99212..7e25f05939bc 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> @@ -17,7 +17,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce,
> u32 value)
> {
> struct drm_i915_private *i915 = ce->vm->i915;
> - const u32 block_size = S16_MAX * PAGE_SIZE;
> + const u32 block_size = SZ_8M; /* ~1ms at 8GiB/s preemption delay */
Also update the copy?
Not sure if this will need more tuning.
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gem: Limit the blitter sizes to ensure low preemption latency
@ 2019-10-28 16:43 ` Matthew Auld
0 siblings, 0 replies; 6+ messages in thread
From: Matthew Auld @ 2019-10-28 16:43 UTC (permalink / raw)
To: Chris Wilson; +Cc: Intel Graphics Development, Matthew Auld
On Fri, 25 Oct 2019 at 22:06, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>
> Currently we insert a arbitration point every 128MiB during a blitter
> copy. At 8GiB/s, this is around 30ms. This is a little on the large side
> if we need to inject a high priority work, so reduced it down to 8MiB or
> roughly 1ms.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Matthew Auld <matthew.auld@intel.com>
> ---
> Ok, I need to do a selftest to ensure we are exceeding the estimated
> blitter throughtput, and I would also like a test to measure the
> preemption latency directly. Remind me!
> ---
> drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> index 516e61e99212..7e25f05939bc 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> @@ -17,7 +17,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce,
> u32 value)
> {
> struct drm_i915_private *i915 = ce->vm->i915;
> - const u32 block_size = S16_MAX * PAGE_SIZE;
> + const u32 block_size = SZ_8M; /* ~1ms at 8GiB/s preemption delay */
Also update the copy?
Not sure if this will need more tuning.
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-10-28 16:44 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-25 21:05 [PATCH] drm/i915/gem: Limit the blitter sizes to ensure low preemption latency Chris Wilson
2019-10-25 21:05 ` [Intel-gfx] " Chris Wilson
2019-10-26 1:24 ` ✗ Fi.CI.BAT: failure for " Patchwork
2019-10-26 1:24 ` [Intel-gfx] " Patchwork
2019-10-28 16:43 ` [PATCH] " Matthew Auld
2019-10-28 16:43 ` [Intel-gfx] " Matthew Auld
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