From: Vitaly Wool <vitaly.wool@konsulko.com> To: Alexandre Ghiti <alex@ghiti.fr> Cc: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, linux-riscv <linux-riscv@lists.infradead.org>, LKML <linux-kernel@vger.kernel.org> Subject: Re: [PATCH] riscv: Disallow to build XIP_KERNEL with SOC_SIFIVE Date: Thu, 29 Apr 2021 11:11:55 +0200 [thread overview] Message-ID: <CAM4kBBK=yQ=jXYw85Ti7Y3EyGd11aOYt7QnD4+fFFkDhvrwcxA@mail.gmail.com> (raw) In-Reply-To: <20210429084541.28083-1-alex@ghiti.fr> On Thu, Apr 29, 2021 at 10:47 AM Alexandre Ghiti <alex@ghiti.fr> wrote: > > RISCV_ERRATA_ALTERNATIVE patches text at runtime which is not possible when > the kernel is executed from the flash in XIP mode, and as the SIFIVE > errata must be fixed somehow, disallow to build a XIP kernel that > supports SIFIVE socs. Could you please hold off this patch for a bit? I will try to come up with an alternative solution. It should be possible to define a special section within the RW area and place the functions that need such patching there. Not that I like that much but at least we'll keep the ability to use XIP on SiFive. Best regards, Vitaly > Signed-off-by: Alexandre Ghiti <alex@ghiti.fr> > --- > arch/riscv/Kconfig.erratas | 2 +- > arch/riscv/Kconfig.socs | 1 + > 2 files changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas > index d5d03ae8d685..9537dbd67357 100644 > --- a/arch/riscv/Kconfig.erratas > +++ b/arch/riscv/Kconfig.erratas > @@ -2,7 +2,7 @@ menu "CPU errata selection" > > config RISCV_ERRATA_ALTERNATIVE > bool "RISC-V alternative scheme" > - default y > + default y if !XIP_KERNEL > help > This Kconfig allows the kernel to automatically patch the > errata required by the execution platform at run time. The > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > index 00c2b205654c..9cb38bc9d7cd 100644 > --- a/arch/riscv/Kconfig.socs > +++ b/arch/riscv/Kconfig.socs > @@ -9,6 +9,7 @@ config SOC_MICROCHIP_POLARFIRE > > config SOC_SIFIVE > bool "SiFive SoCs" > + depends on !XIP_KERNEL > select SERIAL_SIFIVE if TTY > select SERIAL_SIFIVE_CONSOLE if TTY > select CLK_SIFIVE > -- > 2.20.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Vitaly Wool <vitaly.wool@konsulko.com> To: Alexandre Ghiti <alex@ghiti.fr> Cc: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, linux-riscv <linux-riscv@lists.infradead.org>, LKML <linux-kernel@vger.kernel.org> Subject: Re: [PATCH] riscv: Disallow to build XIP_KERNEL with SOC_SIFIVE Date: Thu, 29 Apr 2021 11:11:55 +0200 [thread overview] Message-ID: <CAM4kBBK=yQ=jXYw85Ti7Y3EyGd11aOYt7QnD4+fFFkDhvrwcxA@mail.gmail.com> (raw) In-Reply-To: <20210429084541.28083-1-alex@ghiti.fr> On Thu, Apr 29, 2021 at 10:47 AM Alexandre Ghiti <alex@ghiti.fr> wrote: > > RISCV_ERRATA_ALTERNATIVE patches text at runtime which is not possible when > the kernel is executed from the flash in XIP mode, and as the SIFIVE > errata must be fixed somehow, disallow to build a XIP kernel that > supports SIFIVE socs. Could you please hold off this patch for a bit? I will try to come up with an alternative solution. It should be possible to define a special section within the RW area and place the functions that need such patching there. Not that I like that much but at least we'll keep the ability to use XIP on SiFive. Best regards, Vitaly > Signed-off-by: Alexandre Ghiti <alex@ghiti.fr> > --- > arch/riscv/Kconfig.erratas | 2 +- > arch/riscv/Kconfig.socs | 1 + > 2 files changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas > index d5d03ae8d685..9537dbd67357 100644 > --- a/arch/riscv/Kconfig.erratas > +++ b/arch/riscv/Kconfig.erratas > @@ -2,7 +2,7 @@ menu "CPU errata selection" > > config RISCV_ERRATA_ALTERNATIVE > bool "RISC-V alternative scheme" > - default y > + default y if !XIP_KERNEL > help > This Kconfig allows the kernel to automatically patch the > errata required by the execution platform at run time. The > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > index 00c2b205654c..9cb38bc9d7cd 100644 > --- a/arch/riscv/Kconfig.socs > +++ b/arch/riscv/Kconfig.socs > @@ -9,6 +9,7 @@ config SOC_MICROCHIP_POLARFIRE > > config SOC_SIFIVE > bool "SiFive SoCs" > + depends on !XIP_KERNEL > select SERIAL_SIFIVE if TTY > select SERIAL_SIFIVE_CONSOLE if TTY > select CLK_SIFIVE > -- > 2.20.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-04-29 9:12 UTC|newest] Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-04-29 8:45 [PATCH] riscv: Disallow to build XIP_KERNEL with SOC_SIFIVE Alexandre Ghiti 2021-04-29 8:45 ` Alexandre Ghiti 2021-04-29 9:04 ` Anup Patel 2021-04-29 9:04 ` Anup Patel 2021-04-29 12:17 ` Alex Ghiti 2021-04-29 12:17 ` Alex Ghiti 2021-04-29 9:11 ` Vitaly Wool [this message] 2021-04-29 9:11 ` Vitaly Wool 2021-04-29 12:13 ` Alex Ghiti 2021-04-29 12:13 ` Alex Ghiti 2021-04-30 8:09 ` Alex Ghiti 2021-04-30 8:09 ` Alex Ghiti 2021-04-30 19:47 ` Palmer Dabbelt 2021-04-30 19:47 ` Palmer Dabbelt
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