* Re: [PATCH v6] ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420
@ 2014-07-04 18:30 Nicolas Pitre
2014-07-04 19:02 ` Abhilash Kesavan
0 siblings, 1 reply; 11+ messages in thread
From: Nicolas Pitre @ 2014-07-04 18:30 UTC (permalink / raw)
To: Abhilash Kesavan, Abhilash Kesavan
Cc: linux-samsung-soc, linux-arm-kernel, kgene.kim,
Lorenzo Pieralisi, Andrew Bresticker, Douglas Anderson
On Fri, 4 Jul 2014, Abhilash Kesavan wrote:
> On Fri, Jul 4, 2014 at 9:43 AM, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
> > Another suggestion which might possibly be better: why not looking for
> > the SYS_PWR_CFG bit in exynos_cpu_power_down() directly? After all,
> > exynos_cpu_power_down() is semantically supposed to do what its name
> > suggest and could simply do nothing if the proper conditions are already
> > in place.
> I have implemented this and it works fine. Patch coming up.
On Fri, 4 Jul 2014, Abhilash Kesavan wrote:
> Use the MCPM layer to handle core suspend/resume on Exynos5420.
> Also, restore the entry address setup code post-resume.
>
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
> Changes in v2:
> - Made use of the MCPM suspend/powered_up call-backs
> Changes in v3:
> - Used the residency value to indicate the entered state
> Changes in v4:
> - Checked if MCPM has been enabled to prevent build error
> Changes in v5:
> - Removed the MCPM flags and just used a local flag to
> indicate that we are suspending.
> Changes in v6:
> - Read the SYS_PWR_REG value to decide if we are suspending
> the system.
> - Restore the SYS_PWR_REG value post-resume.
> - Modified the comments to reflect the first change.
[...]
> @@ -150,7 +153,15 @@ static void exynos_power_down(void)
> BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
> cpu_use_count[cpu][cluster]--;
> if (cpu_use_count[cpu][cluster] == 0) {
> - exynos_cpu_power_down(cpunr);
> + /*
> + * Bypass power down for CPU0 during suspend. Check for
> + * the SYS_PWR_REG value to decide if we are suspending
> + * the system.
> + */
> + temp = __raw_readl(pmu_base_addr +
> + EXYNOS5_ARM_CORE0_SYS_PWR_REG);
> + if ((cpu != 0) || ((temp & S5P_CORE_LOCAL_PWR_EN) != 0))
> + exynos_cpu_power_down(cpunr);
Nah... We're going in circles, aren't we?
What I suggested above is:
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 67d383de61..0a48421860 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -110,6 +110,16 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
*/
void exynos_cpu_power_down(int cpu)
{
+ if (soc_is_exynos5250() && cpu == 0) {
+ /*
+ * Bypass power down for CPU0 during suspend. Check for
+ * the SYS_PWR_REG value to decide if we are suspending
+ * the system.
+ */
+ int val = __raw_readl(pmu_base_addr +EXYNOS5_ARM_CORE0_SYS_PWR_REG);
+ if (!(val & S5P_CORE_LOCAL_PWR_EN))
+ return;
+ }
__raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
}
Nicolas
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v6] ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420
2014-07-04 18:30 [PATCH v6] ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420 Nicolas Pitre
@ 2014-07-04 19:02 ` Abhilash Kesavan
0 siblings, 0 replies; 11+ messages in thread
From: Abhilash Kesavan @ 2014-07-04 19:02 UTC (permalink / raw)
To: Nicolas Pitre
Cc: linux-samsung-soc, linux-arm-kernel, Kukjin Kim,
Lorenzo Pieralisi, Andrew Bresticker, Douglas Anderson
Hi Nicolas,
On Sat, Jul 5, 2014 at 12:00 AM, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
> On Fri, 4 Jul 2014, Abhilash Kesavan wrote:
>
>> On Fri, Jul 4, 2014 at 9:43 AM, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
>> > Another suggestion which might possibly be better: why not looking for
>> > the SYS_PWR_CFG bit in exynos_cpu_power_down() directly? After all,
>> > exynos_cpu_power_down() is semantically supposed to do what its name
>> > suggest and could simply do nothing if the proper conditions are already
>> > in place.
>> I have implemented this and it works fine. Patch coming up.
>
> On Fri, 4 Jul 2014, Abhilash Kesavan wrote:
>
>> Use the MCPM layer to handle core suspend/resume on Exynos5420.
>> Also, restore the entry address setup code post-resume.
>>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> ---
>> Changes in v2:
>> - Made use of the MCPM suspend/powered_up call-backs
>> Changes in v3:
>> - Used the residency value to indicate the entered state
>> Changes in v4:
>> - Checked if MCPM has been enabled to prevent build error
>> Changes in v5:
>> - Removed the MCPM flags and just used a local flag to
>> indicate that we are suspending.
>> Changes in v6:
>> - Read the SYS_PWR_REG value to decide if we are suspending
>> the system.
>> - Restore the SYS_PWR_REG value post-resume.
>> - Modified the comments to reflect the first change.
>
> [...]
>
>> @@ -150,7 +153,15 @@ static void exynos_power_down(void)
>> BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
>> cpu_use_count[cpu][cluster]--;
>> if (cpu_use_count[cpu][cluster] == 0) {
>> - exynos_cpu_power_down(cpunr);
>> + /*
>> + * Bypass power down for CPU0 during suspend. Check for
>> + * the SYS_PWR_REG value to decide if we are suspending
>> + * the system.
>> + */
>> + temp = __raw_readl(pmu_base_addr +
>> + EXYNOS5_ARM_CORE0_SYS_PWR_REG);
>> + if ((cpu != 0) || ((temp & S5P_CORE_LOCAL_PWR_EN) != 0))
>> + exynos_cpu_power_down(cpunr);
>
> Nah... We're going in circles, aren't we?
>
> What I suggested above is:
>
> diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
> index 67d383de61..0a48421860 100644
> --- a/arch/arm/mach-exynos/pm.c
> +++ b/arch/arm/mach-exynos/pm.c
> @@ -110,6 +110,16 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
> */
> void exynos_cpu_power_down(int cpu)
> {
> + if (soc_is_exynos5250() && cpu == 0) {
> + /*
> + * Bypass power down for CPU0 during suspend. Check for
> + * the SYS_PWR_REG value to decide if we are suspending
> + * the system.
> + */
> + int val = __raw_readl(pmu_base_addr +EXYNOS5_ARM_CORE0_SYS_PWR_REG);
> + if (!(val & S5P_CORE_LOCAL_PWR_EN))
> + return;
> + }
> __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
> }
Ah, I get it, much nicer indeed. Will change.
>
>
> Nicolas
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v6] ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420
@ 2014-07-04 19:02 ` Abhilash Kesavan
0 siblings, 0 replies; 11+ messages in thread
From: Abhilash Kesavan @ 2014-07-04 19:02 UTC (permalink / raw)
To: linux-arm-kernel
Hi Nicolas,
On Sat, Jul 5, 2014 at 12:00 AM, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
> On Fri, 4 Jul 2014, Abhilash Kesavan wrote:
>
>> On Fri, Jul 4, 2014 at 9:43 AM, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
>> > Another suggestion which might possibly be better: why not looking for
>> > the SYS_PWR_CFG bit in exynos_cpu_power_down() directly? After all,
>> > exynos_cpu_power_down() is semantically supposed to do what its name
>> > suggest and could simply do nothing if the proper conditions are already
>> > in place.
>> I have implemented this and it works fine. Patch coming up.
>
> On Fri, 4 Jul 2014, Abhilash Kesavan wrote:
>
>> Use the MCPM layer to handle core suspend/resume on Exynos5420.
>> Also, restore the entry address setup code post-resume.
>>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> ---
>> Changes in v2:
>> - Made use of the MCPM suspend/powered_up call-backs
>> Changes in v3:
>> - Used the residency value to indicate the entered state
>> Changes in v4:
>> - Checked if MCPM has been enabled to prevent build error
>> Changes in v5:
>> - Removed the MCPM flags and just used a local flag to
>> indicate that we are suspending.
>> Changes in v6:
>> - Read the SYS_PWR_REG value to decide if we are suspending
>> the system.
>> - Restore the SYS_PWR_REG value post-resume.
>> - Modified the comments to reflect the first change.
>
> [...]
>
>> @@ -150,7 +153,15 @@ static void exynos_power_down(void)
>> BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
>> cpu_use_count[cpu][cluster]--;
>> if (cpu_use_count[cpu][cluster] == 0) {
>> - exynos_cpu_power_down(cpunr);
>> + /*
>> + * Bypass power down for CPU0 during suspend. Check for
>> + * the SYS_PWR_REG value to decide if we are suspending
>> + * the system.
>> + */
>> + temp = __raw_readl(pmu_base_addr +
>> + EXYNOS5_ARM_CORE0_SYS_PWR_REG);
>> + if ((cpu != 0) || ((temp & S5P_CORE_LOCAL_PWR_EN) != 0))
>> + exynos_cpu_power_down(cpunr);
>
> Nah... We're going in circles, aren't we?
>
> What I suggested above is:
>
> diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
> index 67d383de61..0a48421860 100644
> --- a/arch/arm/mach-exynos/pm.c
> +++ b/arch/arm/mach-exynos/pm.c
> @@ -110,6 +110,16 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
> */
> void exynos_cpu_power_down(int cpu)
> {
> + if (soc_is_exynos5250() && cpu == 0) {
> + /*
> + * Bypass power down for CPU0 during suspend. Check for
> + * the SYS_PWR_REG value to decide if we are suspending
> + * the system.
> + */
> + int val = __raw_readl(pmu_base_addr +EXYNOS5_ARM_CORE0_SYS_PWR_REG);
> + if (!(val & S5P_CORE_LOCAL_PWR_EN))
> + return;
> + }
> __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
> }
Ah, I get it, much nicer indeed. Will change.
>
>
> Nicolas
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v6] ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420
2014-07-04 19:02 ` Abhilash Kesavan
@ 2014-07-04 19:49 ` Abhilash Kesavan
-1 siblings, 0 replies; 11+ messages in thread
From: Abhilash Kesavan @ 2014-07-04 19:49 UTC (permalink / raw)
To: Nicolas Pitre
Cc: linux-samsung-soc, linux-arm-kernel, Kukjin Kim,
Lorenzo Pieralisi, Andrew Bresticker, Douglas Anderson
Hi Nicolas,
On Sat, Jul 5, 2014 at 12:32 AM, Abhilash Kesavan
<kesavan.abhilash@gmail.com> wrote:
> Hi Nicolas,
>
> On Sat, Jul 5, 2014 at 12:00 AM, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
>> On Fri, 4 Jul 2014, Abhilash Kesavan wrote:
>>
>>> On Fri, Jul 4, 2014 at 9:43 AM, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
>>> > Another suggestion which might possibly be better: why not looking for
>>> > the SYS_PWR_CFG bit in exynos_cpu_power_down() directly? After all,
>>> > exynos_cpu_power_down() is semantically supposed to do what its name
>>> > suggest and could simply do nothing if the proper conditions are already
>>> > in place.
>>> I have implemented this and it works fine. Patch coming up.
>>
>> On Fri, 4 Jul 2014, Abhilash Kesavan wrote:
>>
>>> Use the MCPM layer to handle core suspend/resume on Exynos5420.
>>> Also, restore the entry address setup code post-resume.
>>>
>>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>>> ---
>>> Changes in v2:
>>> - Made use of the MCPM suspend/powered_up call-backs
>>> Changes in v3:
>>> - Used the residency value to indicate the entered state
>>> Changes in v4:
>>> - Checked if MCPM has been enabled to prevent build error
>>> Changes in v5:
>>> - Removed the MCPM flags and just used a local flag to
>>> indicate that we are suspending.
>>> Changes in v6:
>>> - Read the SYS_PWR_REG value to decide if we are suspending
>>> the system.
>>> - Restore the SYS_PWR_REG value post-resume.
>>> - Modified the comments to reflect the first change.
>>
>> [...]
>>
>>> @@ -150,7 +153,15 @@ static void exynos_power_down(void)
>>> BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
>>> cpu_use_count[cpu][cluster]--;
>>> if (cpu_use_count[cpu][cluster] == 0) {
>>> - exynos_cpu_power_down(cpunr);
>>> + /*
>>> + * Bypass power down for CPU0 during suspend. Check for
>>> + * the SYS_PWR_REG value to decide if we are suspending
>>> + * the system.
>>> + */
>>> + temp = __raw_readl(pmu_base_addr +
>>> + EXYNOS5_ARM_CORE0_SYS_PWR_REG);
>>> + if ((cpu != 0) || ((temp & S5P_CORE_LOCAL_PWR_EN) != 0))
>>> + exynos_cpu_power_down(cpunr);
>>
>> Nah... We're going in circles, aren't we?
>>
>> What I suggested above is:
>>
>> diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
>> index 67d383de61..0a48421860 100644
>> --- a/arch/arm/mach-exynos/pm.c
>> +++ b/arch/arm/mach-exynos/pm.c
>> @@ -110,6 +110,16 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
>> */
>> void exynos_cpu_power_down(int cpu)
>> {
>> + if (soc_is_exynos5250() && cpu == 0) {
>> + /*
>> + * Bypass power down for CPU0 during suspend. Check for
>> + * the SYS_PWR_REG value to decide if we are suspending
>> + * the system.
>> + */
>> + int val = __raw_readl(pmu_base_addr +EXYNOS5_ARM_CORE0_SYS_PWR_REG);
>> + if (!(val & S5P_CORE_LOCAL_PWR_EN))
>> + return;
>> + }
>> __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
>> }
> Ah, I get it, much nicer indeed. Will change.
On a different note, I have been using the cpuidle patchset
(https://patchwork.kernel.org/patch/4357421/) as base for S2R support
and had a question. Rather than making the driver depend on
ARCH_EXYNOS should it depend on EXYNOS5420_MCPM which in turn depends
on MCPM (like TC2) or should we just be making the bL cpuidle driver
depend on MCPM ?
Regards,
Abhilash
>>
>>
>> Nicolas
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v6] ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420
@ 2014-07-04 19:49 ` Abhilash Kesavan
0 siblings, 0 replies; 11+ messages in thread
From: Abhilash Kesavan @ 2014-07-04 19:49 UTC (permalink / raw)
To: linux-arm-kernel
Hi Nicolas,
On Sat, Jul 5, 2014 at 12:32 AM, Abhilash Kesavan
<kesavan.abhilash@gmail.com> wrote:
> Hi Nicolas,
>
> On Sat, Jul 5, 2014 at 12:00 AM, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
>> On Fri, 4 Jul 2014, Abhilash Kesavan wrote:
>>
>>> On Fri, Jul 4, 2014 at 9:43 AM, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
>>> > Another suggestion which might possibly be better: why not looking for
>>> > the SYS_PWR_CFG bit in exynos_cpu_power_down() directly? After all,
>>> > exynos_cpu_power_down() is semantically supposed to do what its name
>>> > suggest and could simply do nothing if the proper conditions are already
>>> > in place.
>>> I have implemented this and it works fine. Patch coming up.
>>
>> On Fri, 4 Jul 2014, Abhilash Kesavan wrote:
>>
>>> Use the MCPM layer to handle core suspend/resume on Exynos5420.
>>> Also, restore the entry address setup code post-resume.
>>>
>>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>>> ---
>>> Changes in v2:
>>> - Made use of the MCPM suspend/powered_up call-backs
>>> Changes in v3:
>>> - Used the residency value to indicate the entered state
>>> Changes in v4:
>>> - Checked if MCPM has been enabled to prevent build error
>>> Changes in v5:
>>> - Removed the MCPM flags and just used a local flag to
>>> indicate that we are suspending.
>>> Changes in v6:
>>> - Read the SYS_PWR_REG value to decide if we are suspending
>>> the system.
>>> - Restore the SYS_PWR_REG value post-resume.
>>> - Modified the comments to reflect the first change.
>>
>> [...]
>>
>>> @@ -150,7 +153,15 @@ static void exynos_power_down(void)
>>> BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
>>> cpu_use_count[cpu][cluster]--;
>>> if (cpu_use_count[cpu][cluster] == 0) {
>>> - exynos_cpu_power_down(cpunr);
>>> + /*
>>> + * Bypass power down for CPU0 during suspend. Check for
>>> + * the SYS_PWR_REG value to decide if we are suspending
>>> + * the system.
>>> + */
>>> + temp = __raw_readl(pmu_base_addr +
>>> + EXYNOS5_ARM_CORE0_SYS_PWR_REG);
>>> + if ((cpu != 0) || ((temp & S5P_CORE_LOCAL_PWR_EN) != 0))
>>> + exynos_cpu_power_down(cpunr);
>>
>> Nah... We're going in circles, aren't we?
>>
>> What I suggested above is:
>>
>> diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
>> index 67d383de61..0a48421860 100644
>> --- a/arch/arm/mach-exynos/pm.c
>> +++ b/arch/arm/mach-exynos/pm.c
>> @@ -110,6 +110,16 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
>> */
>> void exynos_cpu_power_down(int cpu)
>> {
>> + if (soc_is_exynos5250() && cpu == 0) {
>> + /*
>> + * Bypass power down for CPU0 during suspend. Check for
>> + * the SYS_PWR_REG value to decide if we are suspending
>> + * the system.
>> + */
>> + int val = __raw_readl(pmu_base_addr +EXYNOS5_ARM_CORE0_SYS_PWR_REG);
>> + if (!(val & S5P_CORE_LOCAL_PWR_EN))
>> + return;
>> + }
>> __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
>> }
> Ah, I get it, much nicer indeed. Will change.
On a different note, I have been using the cpuidle patchset
(https://patchwork.kernel.org/patch/4357421/) as base for S2R support
and had a question. Rather than making the driver depend on
ARCH_EXYNOS should it depend on EXYNOS5420_MCPM which in turn depends
on MCPM (like TC2) or should we just be making the bL cpuidle driver
depend on MCPM ?
Regards,
Abhilash
>>
>>
>> Nicolas
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v6] ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420
2014-07-04 19:49 ` Abhilash Kesavan
@ 2014-07-04 21:03 ` Nicolas Pitre
-1 siblings, 0 replies; 11+ messages in thread
From: Nicolas Pitre @ 2014-07-04 21:03 UTC (permalink / raw)
To: Abhilash Kesavan
Cc: linux-samsung-soc, linux-arm-kernel, Kukjin Kim,
Lorenzo Pieralisi, Andrew Bresticker, Douglas Anderson
On Sat, 5 Jul 2014, Abhilash Kesavan wrote:
> On a different note, I have been using the cpuidle patchset
> (https://patchwork.kernel.org/patch/4357421/) as base for S2R support
> and had a question. Rather than making the driver depend on
> ARCH_EXYNOS should it depend on EXYNOS5420_MCPM which in turn depends
> on MCPM (like TC2) or should we just be making the bL cpuidle driver
> depend on MCPM ?
Probably making it depend on MCPM directly is the best approach.
Nicolas
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v6] ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420
@ 2014-07-04 21:03 ` Nicolas Pitre
0 siblings, 0 replies; 11+ messages in thread
From: Nicolas Pitre @ 2014-07-04 21:03 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, 5 Jul 2014, Abhilash Kesavan wrote:
> On a different note, I have been using the cpuidle patchset
> (https://patchwork.kernel.org/patch/4357421/) as base for S2R support
> and had a question. Rather than making the driver depend on
> ARCH_EXYNOS should it depend on EXYNOS5420_MCPM which in turn depends
> on MCPM (like TC2) or should we just be making the bL cpuidle driver
> depend on MCPM ?
Probably making it depend on MCPM directly is the best approach.
Nicolas
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v6] ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420
2014-07-04 21:03 ` Nicolas Pitre
@ 2014-07-04 21:22 ` Abhilash Kesavan
-1 siblings, 0 replies; 11+ messages in thread
From: Abhilash Kesavan @ 2014-07-04 21:22 UTC (permalink / raw)
To: Nicolas Pitre
Cc: linux-samsung-soc, linux-arm-kernel, Kukjin Kim,
Lorenzo Pieralisi, Andrew Bresticker, Douglas Anderson
Hi Nicolas,
On Sat, Jul 5, 2014 at 2:33 AM, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
> On Sat, 5 Jul 2014, Abhilash Kesavan wrote:
>
>> On a different note, I have been using the cpuidle patchset
>> (https://patchwork.kernel.org/patch/4357421/) as base for S2R support
>> and had a question. Rather than making the driver depend on
>> ARCH_EXYNOS should it depend on EXYNOS5420_MCPM which in turn depends
>> on MCPM (like TC2) or should we just be making the bL cpuidle driver
>> depend on MCPM ?
>
> Probably making it depend on MCPM directly is the best approach.
I'll discuss this with Chander and one of us will post a patch for it.
Regards,
Abhilash
>
>
> Nicolas
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v6] ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420
@ 2014-07-04 21:22 ` Abhilash Kesavan
0 siblings, 0 replies; 11+ messages in thread
From: Abhilash Kesavan @ 2014-07-04 21:22 UTC (permalink / raw)
To: linux-arm-kernel
Hi Nicolas,
On Sat, Jul 5, 2014 at 2:33 AM, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
> On Sat, 5 Jul 2014, Abhilash Kesavan wrote:
>
>> On a different note, I have been using the cpuidle patchset
>> (https://patchwork.kernel.org/patch/4357421/) as base for S2R support
>> and had a question. Rather than making the driver depend on
>> ARCH_EXYNOS should it depend on EXYNOS5420_MCPM which in turn depends
>> on MCPM (like TC2) or should we just be making the bL cpuidle driver
>> depend on MCPM ?
>
> Probably making it depend on MCPM directly is the best approach.
I'll discuss this with Chander and one of us will post a patch for it.
Regards,
Abhilash
>
>
> Nicolas
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v5] ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420
@ 2014-07-03 14:46 Abhilash Kesavan
2014-07-04 17:47 ` Abhilash Kesavan
0 siblings, 1 reply; 11+ messages in thread
From: Abhilash Kesavan @ 2014-07-03 14:46 UTC (permalink / raw)
To: linux-samsung-soc, linux-arm-kernel, kgene.kim, nicolas.pitre,
lorenzo.pieralisi
Cc: abrestic, dianders, kesavan.abhilash
Use the MCPM layer to handle core suspend/resume on Exynos5420.
Also, restore the entry address setup code post-resume.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
Changes in v2:
- Made use of the MCPM suspend/powered_up call-backs
Changes in v3:
- Used the residency value to indicate the entered state
Changes in v4:
- Checked if MCPM has been enabled to prevent build error
Changes in v5:
- Removed the MCPM flags and just used a local flag to
indicate that we are suspending.
This has been tested both on an SMDK5420 and Peach Pit Chromebook on
3.16-rc3/next-20140702.
Here are the dependencies (some of these patches did not apply cleanly):
1) Cleanup patches for mach-exynos
http://comments.gmane.org/gmane.linux.kernel.samsung-soc/33772
2) PMU cleanup and refactoring for using DT
https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg671625.html
3) Exynos5420 PMU/S2R Series
http://comments.gmane.org/gmane.linux.kernel.samsung-soc/33898
4) MCPM boot CPU CCI enablement patches
www.spinics.net/lists/linux-samsung-soc/msg32923.html
5) Exynos5420 CPUIdle Series which populates MCPM suspend/powered_up
call-backs.
www.gossamer-threads.com/lists/linux/kernel/1945347
https://patchwork.kernel.org/patch/4357461/
6) Exynos5420 MCPM cluster power down support
http://www.spinics.net/lists/arm-kernel/msg339988.html
7) TPM reset mask patch
http://www.spinics.net/lists/arm-kernel/msg341884.html
arch/arm/mach-exynos/mcpm-exynos.c | 50 +++++++++++++++++++++++++++-----------
arch/arm/mach-exynos/pm.c | 37 +++++++++++++++++++++++++---
arch/arm/mach-exynos/regs-pmu.h | 1 +
3 files changed, 71 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
index 2dd51cc..60f84c9 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -15,6 +15,7 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
#include <asm/cputype.h>
#include <asm/cp15.h>
@@ -30,6 +31,8 @@
#define EXYNOS5420_USE_ARM_CORE_DOWN_STATE BIT(29)
#define EXYNOS5420_USE_L2_COMMON_UP_STATE BIT(30)
+static void __iomem *ns_sram_base_addr;
+
/*
* The common v7_exit_coherency_flush API could not be used because of the
* Erratum 799270 workaround. This macro is the same as the common one (in
@@ -129,7 +132,7 @@ static int exynos_power_up(unsigned int cpu, unsigned int cluster)
* and can only be executed on processors like A15 and A7 that hit the cache
* with the C bit clear in the SCTLR register.
*/
-static void exynos_power_down(void)
+static void exynos_mcpm_power_down(u64 residency)
{
unsigned int mpidr, cpu, cluster;
bool last_man = false, skip_wfi = false;
@@ -150,7 +153,12 @@ static void exynos_power_down(void)
BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
cpu_use_count[cpu][cluster]--;
if (cpu_use_count[cpu][cluster] == 0) {
- exynos_cpu_power_down(cpunr);
+ /*
+ * Bypass power down for CPU0 during suspend. This is being
+ * taken care by the SYS_PWR_CFG bit in CORE0_SYS_PWR_REG.
+ */
+ if ((cpunr != 0) || (residency != S5P_CHECK_SLEEP))
+ exynos_cpu_power_down(cpunr);
if (exynos_cluster_unused(cluster)) {
exynos_cluster_power_down(cluster);
@@ -209,6 +217,11 @@ static void exynos_power_down(void)
/* Not dead at this point? Let our caller cope. */
}
+static void exynos_power_down(void)
+{
+ exynos_mcpm_power_down(0);
+}
+
static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
{
unsigned int tries = 100;
@@ -250,11 +263,11 @@ static void exynos_suspend(u64 residency)
{
unsigned int mpidr, cpunr;
- exynos_power_down();
+ exynos_mcpm_power_down(residency);
/*
* Execution reaches here only if cpu did not power down.
- * Hence roll back the changes done in exynos_power_down function.
+ * Hence roll back the changes done in exynos_mcpm_power_down function.
*
* CAUTION: "This function requires the stack data to be visible through
* power down and can only be executed on processors like A15 and A7
@@ -319,10 +332,26 @@ static const struct of_device_id exynos_dt_mcpm_match[] = {
{},
};
+static void exynos_mcpm_setup_entry_point(void)
+{
+ /*
+ * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
+ * as part of secondary_cpu_start(). Let's redirect it to the
+ * mcpm_entry_point(). This is done during both secondary boot-up as
+ * well as system resume.
+ */
+ __raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */
+ __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */
+ __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8);
+}
+
+static struct syscore_ops exynos_mcpm_syscore_ops = {
+ .resume = exynos_mcpm_setup_entry_point,
+};
+
static int __init exynos_mcpm_init(void)
{
struct device_node *node;
- void __iomem *ns_sram_base_addr;
unsigned int value, i;
int ret;
@@ -389,16 +418,9 @@ static int __init exynos_mcpm_init(void)
__raw_writel(value, pmu_base_addr + EXYNOS_COMMON_OPTION(i));
}
- /*
- * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
- * as part of secondary_cpu_start(). Let's redirect it to the
- * mcpm_entry_point().
- */
- __raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */
- __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */
- __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8);
+ exynos_mcpm_setup_entry_point();
- iounmap(ns_sram_base_addr);
+ register_syscore_ops(&exynos_mcpm_syscore_ops);
return ret;
}
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 69cf678..278f204 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -24,6 +24,7 @@
#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
+#include <asm/mcpm.h>
#include <asm/smp_scu.h>
#include <asm/suspend.h>
@@ -191,7 +192,6 @@ int exynos_cluster_power_state(int cluster)
pmu_base_addr + S5P_INFORM1))
#define S5P_CHECK_AFTR 0xFCBA0D10
-#define S5P_CHECK_SLEEP 0x00000BAD
/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
static void exynos_set_wakeupmask(long mask)
@@ -318,7 +318,10 @@ static void exynos_pm_prepare(void)
/* ensure at least INFORM0 has the resume address */
- pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
+ if (soc_is_exynos5420() && IS_ENABLED(CONFIG_MCPM))
+ pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0);
+ else
+ pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
if (soc_is_exynos5420()) {
tmp = __raw_readl(pmu_base_addr + EXYNOS5_ARM_L2_OPTION);
@@ -490,6 +493,27 @@ static struct syscore_ops exynos_pm_syscore_ops = {
.resume = exynos_pm_resume,
};
+static int notrace exynos_mcpm_cpu_suspend(unsigned long arg)
+{
+ /* MCPM works with HW CPU identifiers */
+ unsigned int mpidr = read_cpuid_mpidr();
+ unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+ unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+
+ __raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
+
+ mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
+
+ /*
+ * Pass S5P_CHECK_SLEEP flag to the MCPM back-end to indicate that
+ * we are suspending the system and need to skip CPU0 power down.
+ */
+ mcpm_cpu_suspend(S5P_CHECK_SLEEP);
+
+ /* return value != 0 means failure */
+ return 1;
+}
+
/*
* Suspend Ops
*/
@@ -517,10 +541,17 @@ static int exynos_suspend_enter(suspend_state_t state)
flush_cache_all();
s3c_pm_check_store();
- ret = cpu_suspend(0, exynos_cpu_suspend);
+ /* Use the MCPM layer to suspend 5420 which is a multi-cluster SoC */
+ if (soc_is_exynos5420() && IS_ENABLED(CONFIG_MCPM))
+ ret = cpu_suspend(0, exynos_mcpm_cpu_suspend);
+ else
+ ret = cpu_suspend(0, exynos_cpu_suspend);
if (ret)
return ret;
+ if (soc_is_exynos5420() && IS_ENABLED(CONFIG_MCPM))
+ mcpm_cpu_powered_up();
+
s3c_pm_restore_uarts();
S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 3cf0454..e8c75db 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -152,6 +152,7 @@
#define S5P_PAD_RET_EBIB_OPTION 0x31A8
#define S5P_CORE_LOCAL_PWR_EN 0x3
+#define S5P_CHECK_SLEEP 0x00000BAD
/* Only for EXYNOS4210 */
#define S5P_CMU_CLKSTOP_LCD1_LOWPWR 0x1154
--
2.0.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v6] ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420
2014-07-03 14:46 [PATCH v5] " Abhilash Kesavan
@ 2014-07-04 17:47 ` Abhilash Kesavan
0 siblings, 0 replies; 11+ messages in thread
From: Abhilash Kesavan @ 2014-07-04 17:47 UTC (permalink / raw)
To: linux-samsung-soc, linux-arm-kernel, kgene.kim, nicolas.pitre,
lorenzo.pieralisi
Cc: abrestic, dianders, kesavan.abhilash
Use the MCPM layer to handle core suspend/resume on Exynos5420.
Also, restore the entry address setup code post-resume.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
Changes in v2:
- Made use of the MCPM suspend/powered_up call-backs
Changes in v3:
- Used the residency value to indicate the entered state
Changes in v4:
- Checked if MCPM has been enabled to prevent build error
Changes in v5:
- Removed the MCPM flags and just used a local flag to
indicate that we are suspending.
Changes in v6:
- Read the SYS_PWR_REG value to decide if we are suspending
the system.
- Restore the SYS_PWR_REG value post-resume.
- Modified the comments to reflect the first change.
This has been tested both on an SMDK5420 and Peach Pit Chromebook on
next-20140704. Nicolas' boot cluster CCI enablement patches are in
linux-next now.
Here are the dependencies (some of these patches did not apply cleanly):
1) Cleanup patches for mach-exynos
http://comments.gmane.org/gmane.linux.kernel.samsung-soc/33772
2) PMU cleanup and refactoring for using DT
https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg671625.html
3) Exynos5420 PMU/S2R Series
http://comments.gmane.org/gmane.linux.kernel.samsung-soc/33898
4) Exynos5420 CPUIdle Series which populates MCPM suspend/powered_up
call-backs.
www.gossamer-threads.com/lists/linux/kernel/1945347
https://patchwork.kernel.org/patch/4357461/
5) Exynos5420 MCPM cluster power down support
http://www.spinics.net/lists/arm-kernel/msg339988.html
6) TPM reset mask patch
http://www.spinics.net/lists/arm-kernel/msg341884.html
arch/arm/mach-exynos/mcpm-exynos.c | 55 ++++++++++++++++++++++++++----------
arch/arm/mach-exynos/pm.c | 42 +++++++++++++++++++++++++--
2 files changed, 80 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
index 2dd51cc..26670e7 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -15,6 +15,7 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
#include <asm/cputype.h>
#include <asm/cp15.h>
@@ -30,6 +31,8 @@
#define EXYNOS5420_USE_ARM_CORE_DOWN_STATE BIT(29)
#define EXYNOS5420_USE_L2_COMMON_UP_STATE BIT(30)
+static void __iomem *ns_sram_base_addr;
+
/*
* The common v7_exit_coherency_flush API could not be used because of the
* Erratum 799270 workaround. This macro is the same as the common one (in
@@ -129,11 +132,11 @@ static int exynos_power_up(unsigned int cpu, unsigned int cluster)
* and can only be executed on processors like A15 and A7 that hit the cache
* with the C bit clear in the SCTLR register.
*/
-static void exynos_power_down(void)
+static void exynos_mcpm_power_down(u64 residency)
{
unsigned int mpidr, cpu, cluster;
bool last_man = false, skip_wfi = false;
- unsigned int cpunr;
+ unsigned int cpunr, temp;
mpidr = read_cpuid_mpidr();
cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
@@ -150,7 +153,15 @@ static void exynos_power_down(void)
BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
cpu_use_count[cpu][cluster]--;
if (cpu_use_count[cpu][cluster] == 0) {
- exynos_cpu_power_down(cpunr);
+ /*
+ * Bypass power down for CPU0 during suspend. Check for
+ * the SYS_PWR_REG value to decide if we are suspending
+ * the system.
+ */
+ temp = __raw_readl(pmu_base_addr +
+ EXYNOS5_ARM_CORE0_SYS_PWR_REG);
+ if ((cpu != 0) || ((temp & S5P_CORE_LOCAL_PWR_EN) != 0))
+ exynos_cpu_power_down(cpunr);
if (exynos_cluster_unused(cluster)) {
exynos_cluster_power_down(cluster);
@@ -209,6 +220,11 @@ static void exynos_power_down(void)
/* Not dead at this point? Let our caller cope. */
}
+static void exynos_power_down(void)
+{
+ exynos_mcpm_power_down(0);
+}
+
static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
{
unsigned int tries = 100;
@@ -250,11 +266,11 @@ static void exynos_suspend(u64 residency)
{
unsigned int mpidr, cpunr;
- exynos_power_down();
+ exynos_mcpm_power_down(residency);
/*
* Execution reaches here only if cpu did not power down.
- * Hence roll back the changes done in exynos_power_down function.
+ * Hence roll back the changes done in exynos_mcpm_power_down function.
*
* CAUTION: "This function requires the stack data to be visible through
* power down and can only be executed on processors like A15 and A7
@@ -319,10 +335,26 @@ static const struct of_device_id exynos_dt_mcpm_match[] = {
{},
};
+static void exynos_mcpm_setup_entry_point(void)
+{
+ /*
+ * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
+ * as part of secondary_cpu_start(). Let's redirect it to the
+ * mcpm_entry_point(). This is done during both secondary boot-up as
+ * well as system resume.
+ */
+ __raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */
+ __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */
+ __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8);
+}
+
+static struct syscore_ops exynos_mcpm_syscore_ops = {
+ .resume = exynos_mcpm_setup_entry_point,
+};
+
static int __init exynos_mcpm_init(void)
{
struct device_node *node;
- void __iomem *ns_sram_base_addr;
unsigned int value, i;
int ret;
@@ -389,16 +421,9 @@ static int __init exynos_mcpm_init(void)
__raw_writel(value, pmu_base_addr + EXYNOS_COMMON_OPTION(i));
}
- /*
- * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
- * as part of secondary_cpu_start(). Let's redirect it to the
- * mcpm_entry_point().
- */
- __raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */
- __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */
- __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8);
+ exynos_mcpm_setup_entry_point();
- iounmap(ns_sram_base_addr);
+ register_syscore_ops(&exynos_mcpm_syscore_ops);
return ret;
}
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 69cf678..d2751f4 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -24,6 +24,7 @@
#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
+#include <asm/mcpm.h>
#include <asm/smp_scu.h>
#include <asm/suspend.h>
@@ -318,7 +319,10 @@ static void exynos_pm_prepare(void)
/* ensure at least INFORM0 has the resume address */
- pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
+ if (soc_is_exynos5420() && IS_ENABLED(CONFIG_MCPM))
+ pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0);
+ else
+ pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
if (soc_is_exynos5420()) {
tmp = __raw_readl(pmu_base_addr + EXYNOS5_ARM_L2_OPTION);
@@ -408,6 +412,11 @@ static void exynos_pm_resume(void)
unsigned int tmp;
if (soc_is_exynos5420()) {
+ /* Restore the CPU0 low power state register */
+ pmu_raw_writel(
+ __raw_readl(pmu_base_addr + EXYNOS5_ARM_CORE0_SYS_PWR_REG) |
+ S5P_CORE_LOCAL_PWR_EN, EXYNOS5_ARM_CORE0_SYS_PWR_REG);
+
/* Restore the sysram cpu state register */
__raw_writel(exynos5420_cpu_state,
sysram_base_addr + EXYNOS5420_CPU_STATE);
@@ -490,6 +499,28 @@ static struct syscore_ops exynos_pm_syscore_ops = {
.resume = exynos_pm_resume,
};
+static int notrace exynos_mcpm_cpu_suspend(unsigned long arg)
+{
+ /* MCPM works with HW CPU identifiers */
+ unsigned int mpidr = read_cpuid_mpidr();
+ unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+ unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+
+ __raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
+
+ mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
+
+ /*
+ * Residency value passed to mcpm_cpu_suspend back-end
+ * has to be given clear semantics. Set to 0 as a
+ * temporary value.
+ */
+ mcpm_cpu_suspend(0);
+
+ /* return value != 0 means failure */
+ return 1;
+}
+
/*
* Suspend Ops
*/
@@ -517,10 +548,17 @@ static int exynos_suspend_enter(suspend_state_t state)
flush_cache_all();
s3c_pm_check_store();
- ret = cpu_suspend(0, exynos_cpu_suspend);
+ /* Use the MCPM layer to suspend 5420 which is a multi-cluster SoC */
+ if (soc_is_exynos5420() && IS_ENABLED(CONFIG_MCPM))
+ ret = cpu_suspend(0, exynos_mcpm_cpu_suspend);
+ else
+ ret = cpu_suspend(0, exynos_cpu_suspend);
if (ret)
return ret;
+ if (soc_is_exynos5420() && IS_ENABLED(CONFIG_MCPM))
+ mcpm_cpu_powered_up();
+
s3c_pm_restore_uarts();
S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v6] ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420
@ 2014-07-04 17:47 ` Abhilash Kesavan
0 siblings, 0 replies; 11+ messages in thread
From: Abhilash Kesavan @ 2014-07-04 17:47 UTC (permalink / raw)
To: linux-arm-kernel
Use the MCPM layer to handle core suspend/resume on Exynos5420.
Also, restore the entry address setup code post-resume.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
Changes in v2:
- Made use of the MCPM suspend/powered_up call-backs
Changes in v3:
- Used the residency value to indicate the entered state
Changes in v4:
- Checked if MCPM has been enabled to prevent build error
Changes in v5:
- Removed the MCPM flags and just used a local flag to
indicate that we are suspending.
Changes in v6:
- Read the SYS_PWR_REG value to decide if we are suspending
the system.
- Restore the SYS_PWR_REG value post-resume.
- Modified the comments to reflect the first change.
This has been tested both on an SMDK5420 and Peach Pit Chromebook on
next-20140704. Nicolas' boot cluster CCI enablement patches are in
linux-next now.
Here are the dependencies (some of these patches did not apply cleanly):
1) Cleanup patches for mach-exynos
http://comments.gmane.org/gmane.linux.kernel.samsung-soc/33772
2) PMU cleanup and refactoring for using DT
https://www.mail-archive.com/linux-kernel at vger.kernel.org/msg671625.html
3) Exynos5420 PMU/S2R Series
http://comments.gmane.org/gmane.linux.kernel.samsung-soc/33898
4) Exynos5420 CPUIdle Series which populates MCPM suspend/powered_up
call-backs.
www.gossamer-threads.com/lists/linux/kernel/1945347
https://patchwork.kernel.org/patch/4357461/
5) Exynos5420 MCPM cluster power down support
http://www.spinics.net/lists/arm-kernel/msg339988.html
6) TPM reset mask patch
http://www.spinics.net/lists/arm-kernel/msg341884.html
arch/arm/mach-exynos/mcpm-exynos.c | 55 ++++++++++++++++++++++++++----------
arch/arm/mach-exynos/pm.c | 42 +++++++++++++++++++++++++--
2 files changed, 80 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
index 2dd51cc..26670e7 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -15,6 +15,7 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
#include <asm/cputype.h>
#include <asm/cp15.h>
@@ -30,6 +31,8 @@
#define EXYNOS5420_USE_ARM_CORE_DOWN_STATE BIT(29)
#define EXYNOS5420_USE_L2_COMMON_UP_STATE BIT(30)
+static void __iomem *ns_sram_base_addr;
+
/*
* The common v7_exit_coherency_flush API could not be used because of the
* Erratum 799270 workaround. This macro is the same as the common one (in
@@ -129,11 +132,11 @@ static int exynos_power_up(unsigned int cpu, unsigned int cluster)
* and can only be executed on processors like A15 and A7 that hit the cache
* with the C bit clear in the SCTLR register.
*/
-static void exynos_power_down(void)
+static void exynos_mcpm_power_down(u64 residency)
{
unsigned int mpidr, cpu, cluster;
bool last_man = false, skip_wfi = false;
- unsigned int cpunr;
+ unsigned int cpunr, temp;
mpidr = read_cpuid_mpidr();
cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
@@ -150,7 +153,15 @@ static void exynos_power_down(void)
BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
cpu_use_count[cpu][cluster]--;
if (cpu_use_count[cpu][cluster] == 0) {
- exynos_cpu_power_down(cpunr);
+ /*
+ * Bypass power down for CPU0 during suspend. Check for
+ * the SYS_PWR_REG value to decide if we are suspending
+ * the system.
+ */
+ temp = __raw_readl(pmu_base_addr +
+ EXYNOS5_ARM_CORE0_SYS_PWR_REG);
+ if ((cpu != 0) || ((temp & S5P_CORE_LOCAL_PWR_EN) != 0))
+ exynos_cpu_power_down(cpunr);
if (exynos_cluster_unused(cluster)) {
exynos_cluster_power_down(cluster);
@@ -209,6 +220,11 @@ static void exynos_power_down(void)
/* Not dead at this point? Let our caller cope. */
}
+static void exynos_power_down(void)
+{
+ exynos_mcpm_power_down(0);
+}
+
static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
{
unsigned int tries = 100;
@@ -250,11 +266,11 @@ static void exynos_suspend(u64 residency)
{
unsigned int mpidr, cpunr;
- exynos_power_down();
+ exynos_mcpm_power_down(residency);
/*
* Execution reaches here only if cpu did not power down.
- * Hence roll back the changes done in exynos_power_down function.
+ * Hence roll back the changes done in exynos_mcpm_power_down function.
*
* CAUTION: "This function requires the stack data to be visible through
* power down and can only be executed on processors like A15 and A7
@@ -319,10 +335,26 @@ static const struct of_device_id exynos_dt_mcpm_match[] = {
{},
};
+static void exynos_mcpm_setup_entry_point(void)
+{
+ /*
+ * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
+ * as part of secondary_cpu_start(). Let's redirect it to the
+ * mcpm_entry_point(). This is done during both secondary boot-up as
+ * well as system resume.
+ */
+ __raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */
+ __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */
+ __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8);
+}
+
+static struct syscore_ops exynos_mcpm_syscore_ops = {
+ .resume = exynos_mcpm_setup_entry_point,
+};
+
static int __init exynos_mcpm_init(void)
{
struct device_node *node;
- void __iomem *ns_sram_base_addr;
unsigned int value, i;
int ret;
@@ -389,16 +421,9 @@ static int __init exynos_mcpm_init(void)
__raw_writel(value, pmu_base_addr + EXYNOS_COMMON_OPTION(i));
}
- /*
- * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
- * as part of secondary_cpu_start(). Let's redirect it to the
- * mcpm_entry_point().
- */
- __raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */
- __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */
- __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8);
+ exynos_mcpm_setup_entry_point();
- iounmap(ns_sram_base_addr);
+ register_syscore_ops(&exynos_mcpm_syscore_ops);
return ret;
}
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 69cf678..d2751f4 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -24,6 +24,7 @@
#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
+#include <asm/mcpm.h>
#include <asm/smp_scu.h>
#include <asm/suspend.h>
@@ -318,7 +319,10 @@ static void exynos_pm_prepare(void)
/* ensure at least INFORM0 has the resume address */
- pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
+ if (soc_is_exynos5420() && IS_ENABLED(CONFIG_MCPM))
+ pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0);
+ else
+ pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
if (soc_is_exynos5420()) {
tmp = __raw_readl(pmu_base_addr + EXYNOS5_ARM_L2_OPTION);
@@ -408,6 +412,11 @@ static void exynos_pm_resume(void)
unsigned int tmp;
if (soc_is_exynos5420()) {
+ /* Restore the CPU0 low power state register */
+ pmu_raw_writel(
+ __raw_readl(pmu_base_addr + EXYNOS5_ARM_CORE0_SYS_PWR_REG) |
+ S5P_CORE_LOCAL_PWR_EN, EXYNOS5_ARM_CORE0_SYS_PWR_REG);
+
/* Restore the sysram cpu state register */
__raw_writel(exynos5420_cpu_state,
sysram_base_addr + EXYNOS5420_CPU_STATE);
@@ -490,6 +499,28 @@ static struct syscore_ops exynos_pm_syscore_ops = {
.resume = exynos_pm_resume,
};
+static int notrace exynos_mcpm_cpu_suspend(unsigned long arg)
+{
+ /* MCPM works with HW CPU identifiers */
+ unsigned int mpidr = read_cpuid_mpidr();
+ unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+ unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+
+ __raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
+
+ mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
+
+ /*
+ * Residency value passed to mcpm_cpu_suspend back-end
+ * has to be given clear semantics. Set to 0 as a
+ * temporary value.
+ */
+ mcpm_cpu_suspend(0);
+
+ /* return value != 0 means failure */
+ return 1;
+}
+
/*
* Suspend Ops
*/
@@ -517,10 +548,17 @@ static int exynos_suspend_enter(suspend_state_t state)
flush_cache_all();
s3c_pm_check_store();
- ret = cpu_suspend(0, exynos_cpu_suspend);
+ /* Use the MCPM layer to suspend 5420 which is a multi-cluster SoC */
+ if (soc_is_exynos5420() && IS_ENABLED(CONFIG_MCPM))
+ ret = cpu_suspend(0, exynos_mcpm_cpu_suspend);
+ else
+ ret = cpu_suspend(0, exynos_cpu_suspend);
if (ret)
return ret;
+ if (soc_is_exynos5420() && IS_ENABLED(CONFIG_MCPM))
+ mcpm_cpu_powered_up();
+
s3c_pm_restore_uarts();
S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2014-07-04 21:22 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-07-04 18:30 [PATCH v6] ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420 Nicolas Pitre
2014-07-04 19:02 ` Abhilash Kesavan
2014-07-04 19:02 ` Abhilash Kesavan
2014-07-04 19:49 ` Abhilash Kesavan
2014-07-04 19:49 ` Abhilash Kesavan
2014-07-04 21:03 ` Nicolas Pitre
2014-07-04 21:03 ` Nicolas Pitre
2014-07-04 21:22 ` Abhilash Kesavan
2014-07-04 21:22 ` Abhilash Kesavan
-- strict thread matches above, loose matches on Subject: below --
2014-07-03 14:46 [PATCH v5] " Abhilash Kesavan
2014-07-04 17:47 ` [PATCH v6] " Abhilash Kesavan
2014-07-04 17:47 ` Abhilash Kesavan
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