* [PATCH 0/5] S5P64X0 PM Support
@ 2011-08-12 10:26 ` Abhilash Kesavan
0 siblings, 0 replies; 40+ messages in thread
From: Abhilash Kesavan @ 2011-08-12 10:26 UTC (permalink / raw)
To: linux-arm-kernel
The patchset adds Power Mangement support for S5P64X0. The first
four patches lay the groundwork for adding PM support, while the
final patch adds the SoC specific PM code.
Tested using external interrupts as wake-up sources on SMDK6440
and SMDK6450.
Abhilash Kesavan (5):
ARM: S5P: Make the common S5P PM code conditionally compile
ARM: SAMSUNG: Make the sleep code common for S3C64XX and newer SoCs
ARM: S5P64X0: Add pm save/restore functions for GPIO banks
ARM: S5P64X0: Fix incorrect serial clock name
ARM: S5P64X0: Add Power Management support
arch/arm/Kconfig | 2 +-
arch/arm/mach-exynos4/Kconfig | 2 +
arch/arm/mach-exynos4/Makefile | 2 +-
arch/arm/mach-exynos4/sleep.S | 54 ------
arch/arm/mach-s3c64xx/Kconfig | 1 +
arch/arm/mach-s3c64xx/Makefile | 1 -
arch/arm/mach-s3c64xx/sleep.S | 72 --------
arch/arm/mach-s5p64x0/Kconfig | 4 +
arch/arm/mach-s5p64x0/Makefile | 1 +
arch/arm/mach-s5p64x0/clock-s5p6440.c | 2 +-
arch/arm/mach-s5p64x0/clock-s5p6450.c | 2 +-
arch/arm/mach-s5p64x0/gpiolib.c | 1 +
arch/arm/mach-s5p64x0/include/mach/map.h | 1 +
arch/arm/mach-s5p64x0/include/mach/pm-core.h | 117 +++++++++++++
arch/arm/mach-s5p64x0/include/mach/regs-clock.h | 33 ++++
arch/arm/mach-s5p64x0/include/mach/regs-gpio.h | 19 ++
arch/arm/mach-s5p64x0/init.c | 2 +-
arch/arm/mach-s5p64x0/irq-eint.c | 2 +
arch/arm/mach-s5p64x0/irq-pm.c | 92 ++++++++++
arch/arm/mach-s5p64x0/pm.c | 204 +++++++++++++++++++++++
arch/arm/mach-s5pv210/Kconfig | 2 +
arch/arm/mach-s5pv210/Makefile | 2 +-
arch/arm/mach-s5pv210/sleep.S | 52 ------
arch/arm/plat-s5p/Kconfig | 6 +
arch/arm/plat-s5p/Makefile | 3 +-
arch/arm/plat-samsung/Kconfig | 7 +
arch/arm/plat-samsung/Makefile | 1 +
arch/arm/plat-samsung/sleep.S | 80 +++++++++
drivers/gpio/gpio-plat-samsung.c | 4 +-
29 files changed, 583 insertions(+), 188 deletions(-)
delete mode 100644 arch/arm/mach-exynos4/sleep.S
delete mode 100644 arch/arm/mach-s3c64xx/sleep.S
create mode 100644 arch/arm/mach-s5p64x0/include/mach/pm-core.h
create mode 100644 arch/arm/mach-s5p64x0/irq-pm.c
create mode 100644 arch/arm/mach-s5p64x0/pm.c
delete mode 100644 arch/arm/mach-s5pv210/sleep.S
create mode 100644 arch/arm/plat-samsung/sleep.S
--
1.7.4.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 1/5] ARM: S5P: Make the common S5P PM code conditionally compile
2011-08-12 10:26 ` Abhilash Kesavan
@ 2011-08-12 10:26 ` Abhilash Kesavan
-1 siblings, 0 replies; 40+ messages in thread
From: Abhilash Kesavan @ 2011-08-12 10:26 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc, kgene.kim
Pave the way for adding PM support on S5P64X0, which is more similar
to the S3C64XX series than the S5P series. Hence, the common pm code
(containing dummy functions) should not be used for S5P64X0.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
arch/arm/mach-exynos4/Kconfig | 1 +
arch/arm/mach-s5pv210/Kconfig | 1 +
arch/arm/plat-s5p/Kconfig | 6 ++++++
arch/arm/plat-s5p/Makefile | 3 +--
4 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index 0c77ab9..77362c2 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -12,6 +12,7 @@ if ARCH_EXYNOS4
config CPU_EXYNOS4210
bool
select S3C_PL330_DMA
+ select S5P_PM if PM
help
Enable EXYNOS4210 CPU support
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index aaeb44a..b31e866 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -14,6 +14,7 @@ config CPU_S5PV210
select S3C_PL330_DMA
select S5P_EXT_INT
select S5P_HRT
+ select S5P_PM if PM
help
Enable S5PV210 CPU support
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 9843c95..3ca5341 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -43,6 +43,12 @@ config S5P_HRT
help
Use the High Resolution timer support
+config S5P_PM
+ bool
+ help
+ Common code for power management support on S5P and newer SoCs
+ Note: Do not select this for S5P6440 and S5P6450.
+
comment "System MMU"
config S5P_SYSTEM_MMU
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 4b53e04..735c270 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -20,8 +20,7 @@ obj-y += irq.o
obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o
obj-$(CONFIG_S5P_GPIO_INT) += irq-gpioint.o
obj-$(CONFIG_S5P_SYSTEM_MMU) += sysmmu.o
-obj-$(CONFIG_PM) += pm.o
-obj-$(CONFIG_PM) += irq-pm.o
+obj-$(CONFIG_S5P_PM) += pm.o irq-pm.o
obj-$(CONFIG_S5P_HRT) += s5p-time.o
# devices
--
1.7.4.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 1/5] ARM: S5P: Make the common S5P PM code conditionally compile
@ 2011-08-12 10:26 ` Abhilash Kesavan
0 siblings, 0 replies; 40+ messages in thread
From: Abhilash Kesavan @ 2011-08-12 10:26 UTC (permalink / raw)
To: linux-arm-kernel
Pave the way for adding PM support on S5P64X0, which is more similar
to the S3C64XX series than the S5P series. Hence, the common pm code
(containing dummy functions) should not be used for S5P64X0.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
arch/arm/mach-exynos4/Kconfig | 1 +
arch/arm/mach-s5pv210/Kconfig | 1 +
arch/arm/plat-s5p/Kconfig | 6 ++++++
arch/arm/plat-s5p/Makefile | 3 +--
4 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index 0c77ab9..77362c2 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -12,6 +12,7 @@ if ARCH_EXYNOS4
config CPU_EXYNOS4210
bool
select S3C_PL330_DMA
+ select S5P_PM if PM
help
Enable EXYNOS4210 CPU support
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index aaeb44a..b31e866 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -14,6 +14,7 @@ config CPU_S5PV210
select S3C_PL330_DMA
select S5P_EXT_INT
select S5P_HRT
+ select S5P_PM if PM
help
Enable S5PV210 CPU support
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 9843c95..3ca5341 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -43,6 +43,12 @@ config S5P_HRT
help
Use the High Resolution timer support
+config S5P_PM
+ bool
+ help
+ Common code for power management support on S5P and newer SoCs
+ Note: Do not select this for S5P6440 and S5P6450.
+
comment "System MMU"
config S5P_SYSTEM_MMU
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 4b53e04..735c270 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -20,8 +20,7 @@ obj-y += irq.o
obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o
obj-$(CONFIG_S5P_GPIO_INT) += irq-gpioint.o
obj-$(CONFIG_S5P_SYSTEM_MMU) += sysmmu.o
-obj-$(CONFIG_PM) += pm.o
-obj-$(CONFIG_PM) += irq-pm.o
+obj-$(CONFIG_S5P_PM) += pm.o irq-pm.o
obj-$(CONFIG_S5P_HRT) += s5p-time.o
# devices
--
1.7.4.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 2/5] ARM: SAMSUNG: Make the sleep code common for S3C64XX and newer SoCs
2011-08-12 10:26 ` Abhilash Kesavan
@ 2011-08-12 10:26 ` Abhilash Kesavan
-1 siblings, 0 replies; 40+ messages in thread
From: Abhilash Kesavan @ 2011-08-12 10:26 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc, kgene.kim
The sleep code for S5PV210 and EXYNOS4 is identical; moreover it is quite similar
to that for S3C64XX except for some SoC specific debug logic. S5P64X0 and S5PC100,
for which support will be added soon, can also use the same procedure. Create a
common sleep code in the plat-samsung directory so that it can be re-used.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
arch/arm/mach-exynos4/Kconfig | 1 +
arch/arm/mach-exynos4/Makefile | 2 +-
arch/arm/mach-exynos4/sleep.S | 54 ---------------------------
arch/arm/mach-s3c64xx/Kconfig | 1 +
arch/arm/mach-s3c64xx/Makefile | 1 -
arch/arm/mach-s3c64xx/sleep.S | 72 ------------------------------------
arch/arm/mach-s5pv210/Kconfig | 1 +
arch/arm/mach-s5pv210/Makefile | 2 +-
arch/arm/mach-s5pv210/sleep.S | 52 --------------------------
arch/arm/plat-samsung/Kconfig | 7 +++
arch/arm/plat-samsung/Makefile | 1 +
arch/arm/plat-samsung/sleep.S | 80 ++++++++++++++++++++++++++++++++++++++++
12 files changed, 93 insertions(+), 181 deletions(-)
delete mode 100644 arch/arm/mach-exynos4/sleep.S
delete mode 100644 arch/arm/mach-s3c64xx/sleep.S
delete mode 100644 arch/arm/mach-s5pv210/sleep.S
create mode 100644 arch/arm/plat-samsung/sleep.S
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index 77362c2..6c39ac4 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -13,6 +13,7 @@ config CPU_EXYNOS4210
bool
select S3C_PL330_DMA
select S5P_PM if PM
+ select SAMSUNG_SLEEP if PM
help
Enable EXYNOS4210 CPU support
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index b7fe1d7..e172b4b 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -14,7 +14,7 @@ obj- :=
obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o
obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o pmu.o
-obj-$(CONFIG_PM) += pm.o sleep.o
+obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/mach-exynos4/sleep.S
deleted file mode 100644
index 0984078..0000000
--- a/arch/arm/mach-exynos4/sleep.S
+++ /dev/null
@@ -1,54 +0,0 @@
-/* linux/arch/arm/mach-exynos4/sleep.S
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS4210 power Manager (Suspend-To-RAM) support
- * Based on S3C2410 sleep code by:
- * Ben Dooks, (c) 2004 Simtec Electronics
- *
- * Based on PXA/SA1100 sleep code by:
- * Nicolas Pitre, (c) 2002 Monta Vista Software Inc
- * Cliff Brake, (c) 2001
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-*/
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <asm/memory.h>
-
- .text
-
- /*
- * sleep magic, to allow the bootloader to check for an valid
- * image to resume to. Must be the first word before the
- * s3c_cpu_resume entry.
- */
-
- .word 0x2bedf00d
-
- /*
- * s3c_cpu_resume
- *
- * resume code entry for bootloader to call
- *
- * we must put this code here in the data segment as we have no
- * other way of restoring the stack pointer after sleep, and we
- * must not write to the code segment (code is read-only)
- */
-
-ENTRY(s3c_cpu_resume)
- b cpu_resume
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index f057b6a..764cca3 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -8,6 +8,7 @@ config PLAT_S3C64XX
bool
depends on ARCH_S3C64XX
select SAMSUNG_WAKEMASK
+ select SAMSUNG_SLEEP if PM
default y
help
Base platform code for any Samsung S3C64XX device
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 61b4034..c83b7d7 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -40,7 +40,6 @@ obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
# PM
obj-$(CONFIG_PM) += pm.o
-obj-$(CONFIG_PM) += sleep.o
obj-$(CONFIG_PM) += irq-pm.o
# Machine support
diff --git a/arch/arm/mach-s3c64xx/sleep.S b/arch/arm/mach-s3c64xx/sleep.S
deleted file mode 100644
index 34313f9..0000000
--- a/arch/arm/mach-s3c64xx/sleep.S
+++ /dev/null
@@ -1,72 +0,0 @@
-/* linux/arch/arm/plat-s3c64xx/sleep.S
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- * http://armlinux.simtec.co.uk/
- *
- * S3C64XX CPU sleep code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <mach/map.h>
-
-#undef S3C64XX_VA_GPIO
-#define S3C64XX_VA_GPIO (0x0)
-
-#include <mach/regs-gpio.h>
-
-#define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT))
-
- .text
-
- /* Sleep magic, the word before the resume entry point so that the
- * bootloader can check for a resumeable image. */
-
- .word 0x2bedf00d
-
- /* s3c_cpu_reusme
- *
- * This is the entry point, stored by whatever method the bootloader
- * requires to get the kernel runnign again. This code expects to be
- * entered with no caches live and the MMU disabled. It will then
- * restore the MMU and other basic CP registers saved and restart
- * the kernel C code to finish the resume code.
- */
-
-ENTRY(s3c_cpu_resume)
- msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
- ldr r2, =LL_UART /* for debug */
-
-#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
-
-#define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00)
-#define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04)
-
-#define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
-#define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
-
- /* Initialise the GPIO state if we are debugging via the SMDK LEDs,
- * as the uboot version supplied resets these to inputs during the
- * resume checks.
- */
-
- ldr r3, =S3C64XX_PA_GPIO
- ldr r0, [ r3, #S3C64XX_GPNCON ]
- bic r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \
- S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15))
- orr r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \
- S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15))
- str r0, [ r3, #S3C64XX_GPNCON ]
-
- ldr r0, [ r3, #S3C64XX_GPNDAT ]
- bic r0, r0, #0xf << 12 @ GPN12..15
- orr r0, r0, #1 << 15 @ GPN15
- str r0, [ r3, #S3C64XX_GPNDAT ]
-#endif
- b cpu_resume
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index b31e866..008eb67 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -15,6 +15,7 @@ config CPU_S5PV210
select S5P_EXT_INT
select S5P_HRT
select S5P_PM if PM
+ select SAMSUNG_SLEEP if PM
help
Enable S5PV210 CPU support
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index ef7e466..009fbe5 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -14,7 +14,7 @@ obj- :=
obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o
obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o
-obj-$(CONFIG_PM) += pm.o sleep.o
+obj-$(CONFIG_PM) += pm.o
# machine support
diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S
deleted file mode 100644
index e3452cc..0000000
--- a/arch/arm/mach-s5pv210/sleep.S
+++ /dev/null
@@ -1,52 +0,0 @@
-/* linux/arch/arm/plat-s5p/sleep.S
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * S5PV210 power Manager (Suspend-To-RAM) support
- * Based on S3C2410 sleep code by:
- * Ben Dooks, (c) 2004 Simtec Electronics
- *
- * Based on PXA/SA1100 sleep code by:
- * Nicolas Pitre, (c) 2002 Monta Vista Software Inc
- * Cliff Brake, (c) 2001
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-*/
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <asm/memory.h>
-
- .text
-
- /* sleep magic, to allow the bootloader to check for an valid
- * image to resume to. Must be the first word before the
- * s3c_cpu_resume entry.
- */
-
- .word 0x2bedf00d
-
- /* s3c_cpu_resume
- *
- * resume code entry for bootloader to call
- *
- * we must put this code here in the data segment as we have no
- * other way of restoring the stack pointer after sleep, and we
- * must not write to the code segment (code is read-only)
- */
-
-ENTRY(s3c_cpu_resume)
- b cpu_resume
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index b3e1065..aae6d55 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -359,6 +359,13 @@ config SAMSUNG_WAKEMASK
and above. This code allows a set of interrupt to wakeup-mask
mappings. See <plat/wakeup-mask.h>
+config SAMSUNG_SLEEP
+ bool
+ help
+ Internal configuration to enable the common Samsung sleep code.
+ Can be selected by S3C64XX and newer SoCs having similar sleep
+ procedure.
+
comment "Power Domain"
config SAMSUNG_PD
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 853764b..4cb4fcb 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -74,6 +74,7 @@ obj-$(CONFIG_PM) += pm-gpio.o
obj-$(CONFIG_SAMSUNG_PM_CHECK) += pm-check.o
obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o
+obj-$(CONFIG_SAMSUNG_SLEEP) += sleep.o
# PD support
diff --git a/arch/arm/plat-samsung/sleep.S b/arch/arm/plat-samsung/sleep.S
new file mode 100644
index 0000000..02777c5
--- /dev/null
+++ b/arch/arm/plat-samsung/sleep.S
@@ -0,0 +1,80 @@
+/* linux/arch/arm/plat-samsung/sleep.S
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Common Samsung sleep code for S3C64XX and newer SoCs
+ * Based on S3C64XX sleep code by:
+ * Ben Dooks, (c) 2008 Simtec Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+*/
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#if defined(CONFIG_S3C_PM_DEBUG_LED_SMDK)
+#include <mach/map.h>
+#include <mach/regs-gpio.h>
+#endif
+ .text
+
+ /*
+ * sleep magic, to allow the bootloader to check for an valid
+ * image to resume to. Must be the first word before the
+ * s3c_cpu_resume entry.
+ */
+
+ .word 0x2bedf00d
+
+ /*
+ * s3c_cpu_resume
+ *
+ * resume code entry for bootloader to call
+ *
+ * we must put this code here in the data segment as we have no
+ * other way of restoring the stack pointer after sleep, and we
+ * must not write to the code segment (code is read-only)
+ */
+
+ENTRY(s3c_cpu_resume)
+#if defined(CONFIG_S3C_PM_DEBUG_LED_SMDK)
+
+#undef S3C64XX_VA_GPIO
+#define S3C64XX_VA_GPIO (0x0)
+#define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00)
+#define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04)
+
+#define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
+#define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
+
+ /* Initialise the GPIO state if we are debugging via the SMDK LEDs,
+ * as the uboot version supplied resets these to inputs during the
+ * resume checks.
+ */
+
+ ldr r3, =S3C64XX_PA_GPIO
+ ldr r0, [ r3, #S3C64XX_GPNCON ]
+ bic r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \
+ S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15))
+ orr r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \
+ S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15))
+ str r0, [ r3, #S3C64XX_GPNCON ]
+
+ ldr r0, [ r3, #S3C64XX_GPNDAT ]
+ bic r0, r0, #0xf << 12 @ GPN12..15
+ orr r0, r0, #1 << 15 @ GPN15
+ str r0, [ r3, #S3C64XX_GPNDAT ]
+#endif
+ b cpu_resume
--
1.7.4.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 2/5] ARM: SAMSUNG: Make the sleep code common for S3C64XX and newer SoCs
@ 2011-08-12 10:26 ` Abhilash Kesavan
0 siblings, 0 replies; 40+ messages in thread
From: Abhilash Kesavan @ 2011-08-12 10:26 UTC (permalink / raw)
To: linux-arm-kernel
The sleep code for S5PV210 and EXYNOS4 is identical; moreover it is quite similar
to that for S3C64XX except for some SoC specific debug logic. S5P64X0 and S5PC100,
for which support will be added soon, can also use the same procedure. Create a
common sleep code in the plat-samsung directory so that it can be re-used.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
arch/arm/mach-exynos4/Kconfig | 1 +
arch/arm/mach-exynos4/Makefile | 2 +-
arch/arm/mach-exynos4/sleep.S | 54 ---------------------------
arch/arm/mach-s3c64xx/Kconfig | 1 +
arch/arm/mach-s3c64xx/Makefile | 1 -
arch/arm/mach-s3c64xx/sleep.S | 72 ------------------------------------
arch/arm/mach-s5pv210/Kconfig | 1 +
arch/arm/mach-s5pv210/Makefile | 2 +-
arch/arm/mach-s5pv210/sleep.S | 52 --------------------------
arch/arm/plat-samsung/Kconfig | 7 +++
arch/arm/plat-samsung/Makefile | 1 +
arch/arm/plat-samsung/sleep.S | 80 ++++++++++++++++++++++++++++++++++++++++
12 files changed, 93 insertions(+), 181 deletions(-)
delete mode 100644 arch/arm/mach-exynos4/sleep.S
delete mode 100644 arch/arm/mach-s3c64xx/sleep.S
delete mode 100644 arch/arm/mach-s5pv210/sleep.S
create mode 100644 arch/arm/plat-samsung/sleep.S
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index 77362c2..6c39ac4 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -13,6 +13,7 @@ config CPU_EXYNOS4210
bool
select S3C_PL330_DMA
select S5P_PM if PM
+ select SAMSUNG_SLEEP if PM
help
Enable EXYNOS4210 CPU support
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index b7fe1d7..e172b4b 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -14,7 +14,7 @@ obj- :=
obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o
obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o pmu.o
-obj-$(CONFIG_PM) += pm.o sleep.o
+obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/mach-exynos4/sleep.S
deleted file mode 100644
index 0984078..0000000
--- a/arch/arm/mach-exynos4/sleep.S
+++ /dev/null
@@ -1,54 +0,0 @@
-/* linux/arch/arm/mach-exynos4/sleep.S
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS4210 power Manager (Suspend-To-RAM) support
- * Based on S3C2410 sleep code by:
- * Ben Dooks, (c) 2004 Simtec Electronics
- *
- * Based on PXA/SA1100 sleep code by:
- * Nicolas Pitre, (c) 2002 Monta Vista Software Inc
- * Cliff Brake, (c) 2001
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-*/
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <asm/memory.h>
-
- .text
-
- /*
- * sleep magic, to allow the bootloader to check for an valid
- * image to resume to. Must be the first word before the
- * s3c_cpu_resume entry.
- */
-
- .word 0x2bedf00d
-
- /*
- * s3c_cpu_resume
- *
- * resume code entry for bootloader to call
- *
- * we must put this code here in the data segment as we have no
- * other way of restoring the stack pointer after sleep, and we
- * must not write to the code segment (code is read-only)
- */
-
-ENTRY(s3c_cpu_resume)
- b cpu_resume
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index f057b6a..764cca3 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -8,6 +8,7 @@ config PLAT_S3C64XX
bool
depends on ARCH_S3C64XX
select SAMSUNG_WAKEMASK
+ select SAMSUNG_SLEEP if PM
default y
help
Base platform code for any Samsung S3C64XX device
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 61b4034..c83b7d7 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -40,7 +40,6 @@ obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
# PM
obj-$(CONFIG_PM) += pm.o
-obj-$(CONFIG_PM) += sleep.o
obj-$(CONFIG_PM) += irq-pm.o
# Machine support
diff --git a/arch/arm/mach-s3c64xx/sleep.S b/arch/arm/mach-s3c64xx/sleep.S
deleted file mode 100644
index 34313f9..0000000
--- a/arch/arm/mach-s3c64xx/sleep.S
+++ /dev/null
@@ -1,72 +0,0 @@
-/* linux/arch/arm/plat-s3c64xx/sleep.S
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- * http://armlinux.simtec.co.uk/
- *
- * S3C64XX CPU sleep code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <mach/map.h>
-
-#undef S3C64XX_VA_GPIO
-#define S3C64XX_VA_GPIO (0x0)
-
-#include <mach/regs-gpio.h>
-
-#define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT))
-
- .text
-
- /* Sleep magic, the word before the resume entry point so that the
- * bootloader can check for a resumeable image. */
-
- .word 0x2bedf00d
-
- /* s3c_cpu_reusme
- *
- * This is the entry point, stored by whatever method the bootloader
- * requires to get the kernel runnign again. This code expects to be
- * entered with no caches live and the MMU disabled. It will then
- * restore the MMU and other basic CP registers saved and restart
- * the kernel C code to finish the resume code.
- */
-
-ENTRY(s3c_cpu_resume)
- msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
- ldr r2, =LL_UART /* for debug */
-
-#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
-
-#define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00)
-#define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04)
-
-#define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
-#define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
-
- /* Initialise the GPIO state if we are debugging via the SMDK LEDs,
- * as the uboot version supplied resets these to inputs during the
- * resume checks.
- */
-
- ldr r3, =S3C64XX_PA_GPIO
- ldr r0, [ r3, #S3C64XX_GPNCON ]
- bic r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \
- S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15))
- orr r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \
- S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15))
- str r0, [ r3, #S3C64XX_GPNCON ]
-
- ldr r0, [ r3, #S3C64XX_GPNDAT ]
- bic r0, r0, #0xf << 12 @ GPN12..15
- orr r0, r0, #1 << 15 @ GPN15
- str r0, [ r3, #S3C64XX_GPNDAT ]
-#endif
- b cpu_resume
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index b31e866..008eb67 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -15,6 +15,7 @@ config CPU_S5PV210
select S5P_EXT_INT
select S5P_HRT
select S5P_PM if PM
+ select SAMSUNG_SLEEP if PM
help
Enable S5PV210 CPU support
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index ef7e466..009fbe5 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -14,7 +14,7 @@ obj- :=
obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o
obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o
-obj-$(CONFIG_PM) += pm.o sleep.o
+obj-$(CONFIG_PM) += pm.o
# machine support
diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S
deleted file mode 100644
index e3452cc..0000000
--- a/arch/arm/mach-s5pv210/sleep.S
+++ /dev/null
@@ -1,52 +0,0 @@
-/* linux/arch/arm/plat-s5p/sleep.S
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * S5PV210 power Manager (Suspend-To-RAM) support
- * Based on S3C2410 sleep code by:
- * Ben Dooks, (c) 2004 Simtec Electronics
- *
- * Based on PXA/SA1100 sleep code by:
- * Nicolas Pitre, (c) 2002 Monta Vista Software Inc
- * Cliff Brake, (c) 2001
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-*/
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <asm/memory.h>
-
- .text
-
- /* sleep magic, to allow the bootloader to check for an valid
- * image to resume to. Must be the first word before the
- * s3c_cpu_resume entry.
- */
-
- .word 0x2bedf00d
-
- /* s3c_cpu_resume
- *
- * resume code entry for bootloader to call
- *
- * we must put this code here in the data segment as we have no
- * other way of restoring the stack pointer after sleep, and we
- * must not write to the code segment (code is read-only)
- */
-
-ENTRY(s3c_cpu_resume)
- b cpu_resume
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index b3e1065..aae6d55 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -359,6 +359,13 @@ config SAMSUNG_WAKEMASK
and above. This code allows a set of interrupt to wakeup-mask
mappings. See <plat/wakeup-mask.h>
+config SAMSUNG_SLEEP
+ bool
+ help
+ Internal configuration to enable the common Samsung sleep code.
+ Can be selected by S3C64XX and newer SoCs having similar sleep
+ procedure.
+
comment "Power Domain"
config SAMSUNG_PD
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 853764b..4cb4fcb 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -74,6 +74,7 @@ obj-$(CONFIG_PM) += pm-gpio.o
obj-$(CONFIG_SAMSUNG_PM_CHECK) += pm-check.o
obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o
+obj-$(CONFIG_SAMSUNG_SLEEP) += sleep.o
# PD support
diff --git a/arch/arm/plat-samsung/sleep.S b/arch/arm/plat-samsung/sleep.S
new file mode 100644
index 0000000..02777c5
--- /dev/null
+++ b/arch/arm/plat-samsung/sleep.S
@@ -0,0 +1,80 @@
+/* linux/arch/arm/plat-samsung/sleep.S
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Common Samsung sleep code for S3C64XX and newer SoCs
+ * Based on S3C64XX sleep code by:
+ * Ben Dooks, (c) 2008 Simtec Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+*/
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#if defined(CONFIG_S3C_PM_DEBUG_LED_SMDK)
+#include <mach/map.h>
+#include <mach/regs-gpio.h>
+#endif
+ .text
+
+ /*
+ * sleep magic, to allow the bootloader to check for an valid
+ * image to resume to. Must be the first word before the
+ * s3c_cpu_resume entry.
+ */
+
+ .word 0x2bedf00d
+
+ /*
+ * s3c_cpu_resume
+ *
+ * resume code entry for bootloader to call
+ *
+ * we must put this code here in the data segment as we have no
+ * other way of restoring the stack pointer after sleep, and we
+ * must not write to the code segment (code is read-only)
+ */
+
+ENTRY(s3c_cpu_resume)
+#if defined(CONFIG_S3C_PM_DEBUG_LED_SMDK)
+
+#undef S3C64XX_VA_GPIO
+#define S3C64XX_VA_GPIO (0x0)
+#define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00)
+#define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04)
+
+#define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
+#define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
+
+ /* Initialise the GPIO state if we are debugging via the SMDK LEDs,
+ * as the uboot version supplied resets these to inputs during the
+ * resume checks.
+ */
+
+ ldr r3, =S3C64XX_PA_GPIO
+ ldr r0, [ r3, #S3C64XX_GPNCON ]
+ bic r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \
+ S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15))
+ orr r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \
+ S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15))
+ str r0, [ r3, #S3C64XX_GPNCON ]
+
+ ldr r0, [ r3, #S3C64XX_GPNDAT ]
+ bic r0, r0, #0xf << 12 @ GPN12..15
+ orr r0, r0, #1 << 15 @ GPN15
+ str r0, [ r3, #S3C64XX_GPNDAT ]
+#endif
+ b cpu_resume
--
1.7.4.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* RE: [PATCH 2/5] ARM: SAMSUNG: Make the sleep code common for S3C64XX and newer SoCs
2011-08-12 10:26 ` Abhilash Kesavan
@ 2011-08-26 1:40 ` Kukjin Kim
-1 siblings, 0 replies; 40+ messages in thread
From: Kukjin Kim @ 2011-08-26 1:40 UTC (permalink / raw)
To: 'Abhilash Kesavan', linux-arm-kernel, linux-samsung-soc
Abhilash Kesavan wrote:
>
> The sleep code for S5PV210 and EXYNOS4 is identical; moreover it is quite
> similar
> to that for S3C64XX except for some SoC specific debug logic. S5P64X0 and
> S5PC100,
> for which support will be added soon, can also use the same procedure.
Create a
> common sleep code in the plat-samsung directory so that it can be re-used.
>
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
> arch/arm/mach-exynos4/Kconfig | 1 +
> arch/arm/mach-exynos4/Makefile | 2 +-
> arch/arm/mach-exynos4/sleep.S | 54 ---------------------------
> arch/arm/mach-s3c64xx/Kconfig | 1 +
> arch/arm/mach-s3c64xx/Makefile | 1 -
> arch/arm/mach-s3c64xx/sleep.S | 72
------------------------------------
> arch/arm/mach-s5pv210/Kconfig | 1 +
> arch/arm/mach-s5pv210/Makefile | 2 +-
> arch/arm/mach-s5pv210/sleep.S | 52 --------------------------
> arch/arm/plat-samsung/Kconfig | 7 +++
> arch/arm/plat-samsung/Makefile | 1 +
> arch/arm/plat-samsung/sleep.S | 80
> ++++++++++++++++++++++++++++++++++++++++
> 12 files changed, 93 insertions(+), 181 deletions(-)
> delete mode 100644 arch/arm/mach-exynos4/sleep.S
> delete mode 100644 arch/arm/mach-s3c64xx/sleep.S
> delete mode 100644 arch/arm/mach-s5pv210/sleep.S
> create mode 100644 arch/arm/plat-samsung/sleep.S
>
(snip)
> +ENTRY(s3c_cpu_resume)
> +#if defined(CONFIG_S3C_PM_DEBUG_LED_SMDK)
> +
Hi Abhilash,
Yes, would be nice if each sleep.S can be handled in plat-samsung for
Samsung SoCs.
Hmm...but the CONFIG_S3C_PM_DEBUG_LED_SMDK can be used on other SoCs for
same reason even though it is available only on S3C64XX now. I think, we
need to add SoC detecting here.
> +#undef S3C64XX_VA_GPIO
> +#define S3C64XX_VA_GPIO (0x0)
Please let me know why this is needed here.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 2/5] ARM: SAMSUNG: Make the sleep code common for S3C64XX and newer SoCs
@ 2011-08-26 1:40 ` Kukjin Kim
0 siblings, 0 replies; 40+ messages in thread
From: Kukjin Kim @ 2011-08-26 1:40 UTC (permalink / raw)
To: linux-arm-kernel
Abhilash Kesavan wrote:
>
> The sleep code for S5PV210 and EXYNOS4 is identical; moreover it is quite
> similar
> to that for S3C64XX except for some SoC specific debug logic. S5P64X0 and
> S5PC100,
> for which support will be added soon, can also use the same procedure.
Create a
> common sleep code in the plat-samsung directory so that it can be re-used.
>
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
> arch/arm/mach-exynos4/Kconfig | 1 +
> arch/arm/mach-exynos4/Makefile | 2 +-
> arch/arm/mach-exynos4/sleep.S | 54 ---------------------------
> arch/arm/mach-s3c64xx/Kconfig | 1 +
> arch/arm/mach-s3c64xx/Makefile | 1 -
> arch/arm/mach-s3c64xx/sleep.S | 72
------------------------------------
> arch/arm/mach-s5pv210/Kconfig | 1 +
> arch/arm/mach-s5pv210/Makefile | 2 +-
> arch/arm/mach-s5pv210/sleep.S | 52 --------------------------
> arch/arm/plat-samsung/Kconfig | 7 +++
> arch/arm/plat-samsung/Makefile | 1 +
> arch/arm/plat-samsung/sleep.S | 80
> ++++++++++++++++++++++++++++++++++++++++
> 12 files changed, 93 insertions(+), 181 deletions(-)
> delete mode 100644 arch/arm/mach-exynos4/sleep.S
> delete mode 100644 arch/arm/mach-s3c64xx/sleep.S
> delete mode 100644 arch/arm/mach-s5pv210/sleep.S
> create mode 100644 arch/arm/plat-samsung/sleep.S
>
(snip)
> +ENTRY(s3c_cpu_resume)
> +#if defined(CONFIG_S3C_PM_DEBUG_LED_SMDK)
> +
Hi Abhilash,
Yes, would be nice if each sleep.S can be handled in plat-samsung for
Samsung SoCs.
Hmm...but the CONFIG_S3C_PM_DEBUG_LED_SMDK can be used on other SoCs for
same reason even though it is available only on S3C64XX now. I think, we
need to add SoC detecting here.
> +#undef S3C64XX_VA_GPIO
> +#define S3C64XX_VA_GPIO (0x0)
Please let me know why this is needed here.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH 2/5] ARM: SAMSUNG: Make the sleep code common for S3C64XX and newer SoCs
2011-08-26 1:40 ` Kukjin Kim
@ 2011-08-26 2:10 ` Abhilash Kesavan
-1 siblings, 0 replies; 40+ messages in thread
From: Abhilash Kesavan @ 2011-08-26 2:10 UTC (permalink / raw)
To: Kukjin Kim; +Cc: linux-arm-kernel, linux-samsung-soc
Hi Mr Kim,
Thanks for your comments. Please find my reply below:
Regards,
Abhilash
On Fri, Aug 26, 2011 at 7:10 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Abhilash Kesavan wrote:
>>
>> The sleep code for S5PV210 and EXYNOS4 is identical; moreover it is quite
>> similar
>> to that for S3C64XX except for some SoC specific debug logic. S5P64X0 and
>> S5PC100,
>> for which support will be added soon, can also use the same procedure.
> Create a
>> common sleep code in the plat-samsung directory so that it can be re-used.
>>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> ---
>> arch/arm/mach-exynos4/Kconfig | 1 +
>> arch/arm/mach-exynos4/Makefile | 2 +-
>> arch/arm/mach-exynos4/sleep.S | 54 ---------------------------
>> arch/arm/mach-s3c64xx/Kconfig | 1 +
>> arch/arm/mach-s3c64xx/Makefile | 1 -
>> arch/arm/mach-s3c64xx/sleep.S | 72
> ------------------------------------
>> arch/arm/mach-s5pv210/Kconfig | 1 +
>> arch/arm/mach-s5pv210/Makefile | 2 +-
>> arch/arm/mach-s5pv210/sleep.S | 52 --------------------------
>> arch/arm/plat-samsung/Kconfig | 7 +++
>> arch/arm/plat-samsung/Makefile | 1 +
>> arch/arm/plat-samsung/sleep.S | 80
>> ++++++++++++++++++++++++++++++++++++++++
>> 12 files changed, 93 insertions(+), 181 deletions(-)
>> delete mode 100644 arch/arm/mach-exynos4/sleep.S
>> delete mode 100644 arch/arm/mach-s3c64xx/sleep.S
>> delete mode 100644 arch/arm/mach-s5pv210/sleep.S
>> create mode 100644 arch/arm/plat-samsung/sleep.S
>>
>
> (snip)
>
>> +ENTRY(s3c_cpu_resume)
>> +#if defined(CONFIG_S3C_PM_DEBUG_LED_SMDK)
>> +
>
> Hi Abhilash,
>
> Yes, would be nice if each sleep.S can be handled in plat-samsung for
> Samsung SoCs.
>
> Hmm...but the CONFIG_S3C_PM_DEBUG_LED_SMDK can be used on other SoCs for
> same reason even though it is available only on S3C64XX now. I think, we
> need to add SoC detecting here.
Quite right, it is possible to use this for other SoCs. But as of now,
my patch just intends
to move all the sleep code to a common place. The S3C64XX sleep code
has this feature
and I didn't want to disturb it in anyway, hence it has been added to
the common file.
Perhaps, generalizing it for other SoCs can be done later on top of this
>
>> +#undef S3C64XX_VA_GPIO
>> +#define S3C64XX_VA_GPIO (0x0)
>
> Please let me know why this is needed here.
The code is trying to access the registers at a stage where the MMU is
not enabled.
Hence, the VA_GPIO is being re-defined as 0 reducing S3C64XX_GPIOREG(reg) to
reg.
It has been moved as is from the existing s3c64xx sleep code.
>
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 2/5] ARM: SAMSUNG: Make the sleep code common for S3C64XX and newer SoCs
@ 2011-08-26 2:10 ` Abhilash Kesavan
0 siblings, 0 replies; 40+ messages in thread
From: Abhilash Kesavan @ 2011-08-26 2:10 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mr Kim,
Thanks for your comments. Please find my reply below:
Regards,
Abhilash
On Fri, Aug 26, 2011 at 7:10 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Abhilash Kesavan wrote:
>>
>> The sleep code for S5PV210 and EXYNOS4 is identical; moreover it is quite
>> similar
>> to that for S3C64XX except for some SoC specific debug logic. S5P64X0 and
>> S5PC100,
>> for which support will be added soon, can also use the same procedure.
> Create a
>> common sleep code in the plat-samsung directory so that it can be re-used.
>>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> ---
>> ?arch/arm/mach-exynos4/Kconfig ?| ? ?1 +
>> ?arch/arm/mach-exynos4/Makefile | ? ?2 +-
>> ?arch/arm/mach-exynos4/sleep.S ?| ? 54 ---------------------------
>> ?arch/arm/mach-s3c64xx/Kconfig ?| ? ?1 +
>> ?arch/arm/mach-s3c64xx/Makefile | ? ?1 -
>> ?arch/arm/mach-s3c64xx/sleep.S ?| ? 72
> ------------------------------------
>> ?arch/arm/mach-s5pv210/Kconfig ?| ? ?1 +
>> ?arch/arm/mach-s5pv210/Makefile | ? ?2 +-
>> ?arch/arm/mach-s5pv210/sleep.S ?| ? 52 --------------------------
>> ?arch/arm/plat-samsung/Kconfig ?| ? ?7 +++
>> ?arch/arm/plat-samsung/Makefile | ? ?1 +
>> ?arch/arm/plat-samsung/sleep.S ?| ? 80
>> ++++++++++++++++++++++++++++++++++++++++
>> ?12 files changed, 93 insertions(+), 181 deletions(-)
>> ?delete mode 100644 arch/arm/mach-exynos4/sleep.S
>> ?delete mode 100644 arch/arm/mach-s3c64xx/sleep.S
>> ?delete mode 100644 arch/arm/mach-s5pv210/sleep.S
>> ?create mode 100644 arch/arm/plat-samsung/sleep.S
>>
>
> (snip)
>
>> +ENTRY(s3c_cpu_resume)
>> +#if defined(CONFIG_S3C_PM_DEBUG_LED_SMDK)
>> +
>
> Hi Abhilash,
>
> Yes, would be nice if each sleep.S can be handled in plat-samsung for
> Samsung SoCs.
>
> Hmm...but the CONFIG_S3C_PM_DEBUG_LED_SMDK can be used on other SoCs for
> same reason even though it is available only on S3C64XX now. I think, we
> need to add SoC detecting here.
Quite right, it is possible to use this for other SoCs. But as of now,
my patch just intends
to move all the sleep code to a common place. The S3C64XX sleep code
has this feature
and I didn't want to disturb it in anyway, hence it has been added to
the common file.
Perhaps, generalizing it for other SoCs can be done later on top of this
>
>> +#undef S3C64XX_VA_GPIO
>> +#define S3C64XX_VA_GPIO (0x0)
>
> Please let me know why this is needed here.
The code is trying to access the registers at a stage where the MMU is
not enabled.
Hence, the VA_GPIO is being re-defined as 0 reducing S3C64XX_GPIOREG(reg) to
reg.
It has been moved as is from the existing s3c64xx sleep code.
>
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* RE: [PATCH 2/5] ARM: SAMSUNG: Make the sleep code common for S3C64XX and newer SoCs
2011-08-26 2:10 ` Abhilash Kesavan
@ 2011-09-07 6:01 ` Kukjin Kim
-1 siblings, 0 replies; 40+ messages in thread
From: Kukjin Kim @ 2011-09-07 6:01 UTC (permalink / raw)
To: 'Abhilash Kesavan'; +Cc: linux-arm-kernel, linux-samsung-soc
Abhilash Kesavan wrote:
>
> Hi Mr Kim,
>
> Thanks for your comments. Please find my reply below:
>
> Regards,
> Abhilash
>
> On Fri, Aug 26, 2011 at 7:10 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> > Abhilash Kesavan wrote:
> >>
> >> The sleep code for S5PV210 and EXYNOS4 is identical; moreover it is
quite
> >> similar
> >> to that for S3C64XX except for some SoC specific debug logic. S5P64X0
and
> >> S5PC100,
> >> for which support will be added soon, can also use the same procedure.
> > Create a
> >> common sleep code in the plat-samsung directory so that it can be
re-used.
> >>
> >> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> >> ---
> >> arch/arm/mach-exynos4/Kconfig | 1 +
> >> arch/arm/mach-exynos4/Makefile | 2 +-
> >> arch/arm/mach-exynos4/sleep.S | 54 ---------------------------
> >> arch/arm/mach-s3c64xx/Kconfig | 1 +
> >> arch/arm/mach-s3c64xx/Makefile | 1 -
> >> arch/arm/mach-s3c64xx/sleep.S | 72
> > ------------------------------------
> >> arch/arm/mach-s5pv210/Kconfig | 1 +
> >> arch/arm/mach-s5pv210/Makefile | 2 +-
> >> arch/arm/mach-s5pv210/sleep.S | 52 --------------------------
> >> arch/arm/plat-samsung/Kconfig | 7 +++
> >> arch/arm/plat-samsung/Makefile | 1 +
> >> arch/arm/plat-samsung/sleep.S | 80
> >> ++++++++++++++++++++++++++++++++++++++++
> >> 12 files changed, 93 insertions(+), 181 deletions(-)
> >> delete mode 100644 arch/arm/mach-exynos4/sleep.S
> >> delete mode 100644 arch/arm/mach-s3c64xx/sleep.S
> >> delete mode 100644 arch/arm/mach-s5pv210/sleep.S
> >> create mode 100644 arch/arm/plat-samsung/sleep.S
> >>
> >
> > (snip)
> >
> >> +ENTRY(s3c_cpu_resume)
> >> +#if defined(CONFIG_S3C_PM_DEBUG_LED_SMDK)
> >> +
> >
> > Hi Abhilash,
> >
> > Yes, would be nice if each sleep.S can be handled in plat-samsung for
> > Samsung SoCs.
> >
> > Hmm...but the CONFIG_S3C_PM_DEBUG_LED_SMDK can be used on other
> SoCs for
> > same reason even though it is available only on S3C64XX now. I think, we
> > need to add SoC detecting here.
> Quite right, it is possible to use this for other SoCs. But as of now,
> my patch just intends
> to move all the sleep code to a common place. The S3C64XX sleep code
> has this feature
> and I didn't want to disturb it in anyway, hence it has been added to
> the common file.
> Perhaps, generalizing it for other SoCs can be done later on top of this
Hmm, this codes should be cleaned for all Samsung SoCs because this can
break one kernel image...
> >
> >> +#undef S3C64XX_VA_GPIO
> >> +#define S3C64XX_VA_GPIO (0x0)
> >
> > Please let me know why this is needed here.
> The code is trying to access the registers at a stage where the MMU is
> not enabled.
> Hence, the VA_GPIO is being re-defined as 0 reducing S3C64XX_GPIOREG(reg)
> to
> reg.
> It has been moved as is from the existing s3c64xx sleep code.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 2/5] ARM: SAMSUNG: Make the sleep code common for S3C64XX and newer SoCs
@ 2011-09-07 6:01 ` Kukjin Kim
0 siblings, 0 replies; 40+ messages in thread
From: Kukjin Kim @ 2011-09-07 6:01 UTC (permalink / raw)
To: linux-arm-kernel
Abhilash Kesavan wrote:
>
> Hi Mr Kim,
>
> Thanks for your comments. Please find my reply below:
>
> Regards,
> Abhilash
>
> On Fri, Aug 26, 2011 at 7:10 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> > Abhilash Kesavan wrote:
> >>
> >> The sleep code for S5PV210 and EXYNOS4 is identical; moreover it is
quite
> >> similar
> >> to that for S3C64XX except for some SoC specific debug logic. S5P64X0
and
> >> S5PC100,
> >> for which support will be added soon, can also use the same procedure.
> > Create a
> >> common sleep code in the plat-samsung directory so that it can be
re-used.
> >>
> >> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> >> ---
> >> ?arch/arm/mach-exynos4/Kconfig ?| ? ?1 +
> >> ?arch/arm/mach-exynos4/Makefile | ? ?2 +-
> >> ?arch/arm/mach-exynos4/sleep.S ?| ? 54 ---------------------------
> >> ?arch/arm/mach-s3c64xx/Kconfig ?| ? ?1 +
> >> ?arch/arm/mach-s3c64xx/Makefile | ? ?1 -
> >> ?arch/arm/mach-s3c64xx/sleep.S ?| ? 72
> > ------------------------------------
> >> ?arch/arm/mach-s5pv210/Kconfig ?| ? ?1 +
> >> ?arch/arm/mach-s5pv210/Makefile | ? ?2 +-
> >> ?arch/arm/mach-s5pv210/sleep.S ?| ? 52 --------------------------
> >> ?arch/arm/plat-samsung/Kconfig ?| ? ?7 +++
> >> ?arch/arm/plat-samsung/Makefile | ? ?1 +
> >> ?arch/arm/plat-samsung/sleep.S ?| ? 80
> >> ++++++++++++++++++++++++++++++++++++++++
> >> ?12 files changed, 93 insertions(+), 181 deletions(-)
> >> ?delete mode 100644 arch/arm/mach-exynos4/sleep.S
> >> ?delete mode 100644 arch/arm/mach-s3c64xx/sleep.S
> >> ?delete mode 100644 arch/arm/mach-s5pv210/sleep.S
> >> ?create mode 100644 arch/arm/plat-samsung/sleep.S
> >>
> >
> > (snip)
> >
> >> +ENTRY(s3c_cpu_resume)
> >> +#if defined(CONFIG_S3C_PM_DEBUG_LED_SMDK)
> >> +
> >
> > Hi Abhilash,
> >
> > Yes, would be nice if each sleep.S can be handled in plat-samsung for
> > Samsung SoCs.
> >
> > Hmm...but the CONFIG_S3C_PM_DEBUG_LED_SMDK can be used on other
> SoCs for
> > same reason even though it is available only on S3C64XX now. I think, we
> > need to add SoC detecting here.
> Quite right, it is possible to use this for other SoCs. But as of now,
> my patch just intends
> to move all the sleep code to a common place. The S3C64XX sleep code
> has this feature
> and I didn't want to disturb it in anyway, hence it has been added to
> the common file.
> Perhaps, generalizing it for other SoCs can be done later on top of this
Hmm, this codes should be cleaned for all Samsung SoCs because this can
break one kernel image...
> >
> >> +#undef S3C64XX_VA_GPIO
> >> +#define S3C64XX_VA_GPIO (0x0)
> >
> > Please let me know why this is needed here.
> The code is trying to access the registers at a stage where the MMU is
> not enabled.
> Hence, the VA_GPIO is being re-defined as 0 reducing S3C64XX_GPIOREG(reg)
> to
> reg.
> It has been moved as is from the existing s3c64xx sleep code.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH 2/5] ARM: SAMSUNG: Make the sleep code common for S3C64XX and newer SoCs
2011-09-07 6:01 ` Kukjin Kim
@ 2011-09-07 6:34 ` Abhilash Kesavan
-1 siblings, 0 replies; 40+ messages in thread
From: Abhilash Kesavan @ 2011-09-07 6:34 UTC (permalink / raw)
To: Kukjin Kim; +Cc: linux-samsung-soc, linux-arm-kernel
Hi Mr Kim,
On Wed, Sep 7, 2011 at 11:31 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Abhilash Kesavan wrote:
>>
>> Hi Mr Kim,
>>
>> Thanks for your comments. Please find my reply below:
>>
>> Regards,
>> Abhilash
>>
>> On Fri, Aug 26, 2011 at 7:10 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
>> > Abhilash Kesavan wrote:
>> >>
>> >> The sleep code for S5PV210 and EXYNOS4 is identical; moreover it is
> quite
>> >> similar
>> >> to that for S3C64XX except for some SoC specific debug logic. S5P64X0
> and
>> >> S5PC100,
>> >> for which support will be added soon, can also use the same procedure.
>> > Create a
>> >> common sleep code in the plat-samsung directory so that it can be
> re-used.
>> >>
>> >> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> >> ---
>> >> arch/arm/mach-exynos4/Kconfig | 1 +
>> >> arch/arm/mach-exynos4/Makefile | 2 +-
>> >> arch/arm/mach-exynos4/sleep.S | 54 ---------------------------
>> >> arch/arm/mach-s3c64xx/Kconfig | 1 +
>> >> arch/arm/mach-s3c64xx/Makefile | 1 -
>> >> arch/arm/mach-s3c64xx/sleep.S | 72
>> > ------------------------------------
>> >> arch/arm/mach-s5pv210/Kconfig | 1 +
>> >> arch/arm/mach-s5pv210/Makefile | 2 +-
>> >> arch/arm/mach-s5pv210/sleep.S | 52 --------------------------
>> >> arch/arm/plat-samsung/Kconfig | 7 +++
>> >> arch/arm/plat-samsung/Makefile | 1 +
>> >> arch/arm/plat-samsung/sleep.S | 80
>> >> ++++++++++++++++++++++++++++++++++++++++
>> >> 12 files changed, 93 insertions(+), 181 deletions(-)
>> >> delete mode 100644 arch/arm/mach-exynos4/sleep.S
>> >> delete mode 100644 arch/arm/mach-s3c64xx/sleep.S
>> >> delete mode 100644 arch/arm/mach-s5pv210/sleep.S
>> >> create mode 100644 arch/arm/plat-samsung/sleep.S
>> >>
>> >
>> > (snip)
>> >
>> >> +ENTRY(s3c_cpu_resume)
>> >> +#if defined(CONFIG_S3C_PM_DEBUG_LED_SMDK)
>> >> +
>> >
>> > Hi Abhilash,
>> >
>> > Yes, would be nice if each sleep.S can be handled in plat-samsung for
>> > Samsung SoCs.
>> >
>> > Hmm...but the CONFIG_S3C_PM_DEBUG_LED_SMDK can be used on other
>> SoCs for
>> > same reason even though it is available only on S3C64XX now. I think, we
>> > need to add SoC detecting here.
>> Quite right, it is possible to use this for other SoCs. But as of now,
>> my patch just intends
>> to move all the sleep code to a common place. The S3C64XX sleep code
>> has this feature
>> and I didn't want to disturb it in anyway, hence it has been added to
>> the common file.
>> Perhaps, generalizing it for other SoCs can be done later on top of this
>
> Hmm, this codes should be cleaned for all Samsung SoCs because this can
> break one kernel image...
Do you mean for 24xx as well ? because that would be kind of difficult
considering that the 2412, 2410 sleep files are different.
If you feel this will prevent single image support, we can drop it.
The rationale
behind the patch was that rather than add another identical 64X0 sleep.s file
and another for C100 in the future, let me merge it.
But the patch isn't necessary as for S5P64X0 PM support as such. I can rework
the existing patches with a new sleep.S.
>
>> >
>> >> +#undef S3C64XX_VA_GPIO
>> >> +#define S3C64XX_VA_GPIO (0x0)
>> >
>> > Please let me know why this is needed here.
>> The code is trying to access the registers at a stage where the MMU is
>> not enabled.
>> Hence, the VA_GPIO is being re-defined as 0 reducing S3C64XX_GPIOREG(reg)
>> to
>> reg.
>> It has been moved as is from the existing s3c64xx sleep code.
>
>
> Thanks.
>
> Best regards,
> Kgene.
Abhilash
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 2/5] ARM: SAMSUNG: Make the sleep code common for S3C64XX and newer SoCs
@ 2011-09-07 6:34 ` Abhilash Kesavan
0 siblings, 0 replies; 40+ messages in thread
From: Abhilash Kesavan @ 2011-09-07 6:34 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mr Kim,
On Wed, Sep 7, 2011 at 11:31 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Abhilash Kesavan wrote:
>>
>> Hi Mr Kim,
>>
>> Thanks for your comments. Please find my reply below:
>>
>> Regards,
>> Abhilash
>>
>> On Fri, Aug 26, 2011 at 7:10 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
>> > Abhilash Kesavan wrote:
>> >>
>> >> The sleep code for S5PV210 and EXYNOS4 is identical; moreover it is
> quite
>> >> similar
>> >> to that for S3C64XX except for some SoC specific debug logic. S5P64X0
> and
>> >> S5PC100,
>> >> for which support will be added soon, can also use the same procedure.
>> > Create a
>> >> common sleep code in the plat-samsung directory so that it can be
> re-used.
>> >>
>> >> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> >> ---
>> >> ?arch/arm/mach-exynos4/Kconfig ?| ? ?1 +
>> >> ?arch/arm/mach-exynos4/Makefile | ? ?2 +-
>> >> ?arch/arm/mach-exynos4/sleep.S ?| ? 54 ---------------------------
>> >> ?arch/arm/mach-s3c64xx/Kconfig ?| ? ?1 +
>> >> ?arch/arm/mach-s3c64xx/Makefile | ? ?1 -
>> >> ?arch/arm/mach-s3c64xx/sleep.S ?| ? 72
>> > ------------------------------------
>> >> ?arch/arm/mach-s5pv210/Kconfig ?| ? ?1 +
>> >> ?arch/arm/mach-s5pv210/Makefile | ? ?2 +-
>> >> ?arch/arm/mach-s5pv210/sleep.S ?| ? 52 --------------------------
>> >> ?arch/arm/plat-samsung/Kconfig ?| ? ?7 +++
>> >> ?arch/arm/plat-samsung/Makefile | ? ?1 +
>> >> ?arch/arm/plat-samsung/sleep.S ?| ? 80
>> >> ++++++++++++++++++++++++++++++++++++++++
>> >> ?12 files changed, 93 insertions(+), 181 deletions(-)
>> >> ?delete mode 100644 arch/arm/mach-exynos4/sleep.S
>> >> ?delete mode 100644 arch/arm/mach-s3c64xx/sleep.S
>> >> ?delete mode 100644 arch/arm/mach-s5pv210/sleep.S
>> >> ?create mode 100644 arch/arm/plat-samsung/sleep.S
>> >>
>> >
>> > (snip)
>> >
>> >> +ENTRY(s3c_cpu_resume)
>> >> +#if defined(CONFIG_S3C_PM_DEBUG_LED_SMDK)
>> >> +
>> >
>> > Hi Abhilash,
>> >
>> > Yes, would be nice if each sleep.S can be handled in plat-samsung for
>> > Samsung SoCs.
>> >
>> > Hmm...but the CONFIG_S3C_PM_DEBUG_LED_SMDK can be used on other
>> SoCs for
>> > same reason even though it is available only on S3C64XX now. I think, we
>> > need to add SoC detecting here.
>> Quite right, it is possible to use this for other SoCs. But as of now,
>> my patch just intends
>> to move all the sleep code to a common place. The S3C64XX sleep code
>> has this feature
>> and I didn't want to disturb it in anyway, hence it has been added to
>> the common file.
>> Perhaps, generalizing it for other SoCs can be done later on top of this
>
> Hmm, this codes should be cleaned for all Samsung SoCs because this can
> break one kernel image...
Do you mean for 24xx as well ? because that would be kind of difficult
considering that the 2412, 2410 sleep files are different.
If you feel this will prevent single image support, we can drop it.
The rationale
behind the patch was that rather than add another identical 64X0 sleep.s file
and another for C100 in the future, let me merge it.
But the patch isn't necessary as for S5P64X0 PM support as such. I can rework
the existing patches with a new sleep.S.
>
>> >
>> >> +#undef S3C64XX_VA_GPIO
>> >> +#define S3C64XX_VA_GPIO (0x0)
>> >
>> > Please let me know why this is needed here.
>> The code is trying to access the registers at a stage where the MMU is
>> not enabled.
>> Hence, the VA_GPIO is being re-defined as 0 reducing S3C64XX_GPIOREG(reg)
>> to
>> reg.
>> It has been moved as is from the existing s3c64xx sleep code.
>
>
> Thanks.
>
> Best regards,
> Kgene.
Abhilash
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH 2/5] ARM: SAMSUNG: Make the sleep code common for S3C64XX and newer SoCs
2011-08-12 10:26 ` Abhilash Kesavan
@ 2011-09-07 9:55 ` Russell King - ARM Linux
-1 siblings, 0 replies; 40+ messages in thread
From: Russell King - ARM Linux @ 2011-09-07 9:55 UTC (permalink / raw)
To: Abhilash Kesavan; +Cc: kgene.kim, linux-samsung-soc, linux-arm-kernel
On Fri, Aug 12, 2011 at 03:56:24PM +0530, Abhilash Kesavan wrote:
> +ENTRY(s3c_cpu_resume)
> +#if defined(CONFIG_S3C_PM_DEBUG_LED_SMDK)
> +
> +#undef S3C64XX_VA_GPIO
> +#define S3C64XX_VA_GPIO (0x0)
> +#define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00)
> +#define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04)
> +
> +#define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
> +#define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
> +
> + /* Initialise the GPIO state if we are debugging via the SMDK LEDs,
> + * as the uboot version supplied resets these to inputs during the
> + * resume checks.
> + */
> +
> + ldr r3, =S3C64XX_PA_GPIO
> + ldr r0, [ r3, #S3C64XX_GPNCON ]
> + bic r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \
> + S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15))
> + orr r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \
> + S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15))
> + str r0, [ r3, #S3C64XX_GPNCON ]
> +
> + ldr r0, [ r3, #S3C64XX_GPNDAT ]
> + bic r0, r0, #0xf << 12 @ GPN12..15
> + orr r0, r0, #1 << 15 @ GPN15
> + str r0, [ r3, #S3C64XX_GPNDAT ]
> +#endif
This is incompatible with the aim of a single kernel booting on many ARM
platforms.
Rather than consolidating down to just one implementation, how about
consolidating to two - one for everything but SMDK, and one for the SMDK
with the LED stuff. You can then chose which you want - either the
s3c_generic_resume (which is just the magic code plus the branch)
or s3c_smdk_leds_resume (which would be the magic code plus the LEDS
stuff plus the branch.)
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 2/5] ARM: SAMSUNG: Make the sleep code common for S3C64XX and newer SoCs
@ 2011-09-07 9:55 ` Russell King - ARM Linux
0 siblings, 0 replies; 40+ messages in thread
From: Russell King - ARM Linux @ 2011-09-07 9:55 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Aug 12, 2011 at 03:56:24PM +0530, Abhilash Kesavan wrote:
> +ENTRY(s3c_cpu_resume)
> +#if defined(CONFIG_S3C_PM_DEBUG_LED_SMDK)
> +
> +#undef S3C64XX_VA_GPIO
> +#define S3C64XX_VA_GPIO (0x0)
> +#define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00)
> +#define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04)
> +
> +#define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
> +#define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
> +
> + /* Initialise the GPIO state if we are debugging via the SMDK LEDs,
> + * as the uboot version supplied resets these to inputs during the
> + * resume checks.
> + */
> +
> + ldr r3, =S3C64XX_PA_GPIO
> + ldr r0, [ r3, #S3C64XX_GPNCON ]
> + bic r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \
> + S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15))
> + orr r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \
> + S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15))
> + str r0, [ r3, #S3C64XX_GPNCON ]
> +
> + ldr r0, [ r3, #S3C64XX_GPNDAT ]
> + bic r0, r0, #0xf << 12 @ GPN12..15
> + orr r0, r0, #1 << 15 @ GPN15
> + str r0, [ r3, #S3C64XX_GPNDAT ]
> +#endif
This is incompatible with the aim of a single kernel booting on many ARM
platforms.
Rather than consolidating down to just one implementation, how about
consolidating to two - one for everything but SMDK, and one for the SMDK
with the LED stuff. You can then chose which you want - either the
s3c_generic_resume (which is just the magic code plus the branch)
or s3c_smdk_leds_resume (which would be the magic code plus the LEDS
stuff plus the branch.)
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH 2/5] ARM: SAMSUNG: Make the sleep code common for S3C64XX and newer SoCs
2011-09-07 9:55 ` Russell King - ARM Linux
@ 2011-09-07 11:30 ` Abhilash Kesavan
-1 siblings, 0 replies; 40+ messages in thread
From: Abhilash Kesavan @ 2011-09-07 11:30 UTC (permalink / raw)
To: Russell King - ARM Linux; +Cc: linux-samsung-soc, kgene.kim, linux-arm-kernel
Hi Russell,
On Wed, Sep 7, 2011 at 3:25 PM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Fri, Aug 12, 2011 at 03:56:24PM +0530, Abhilash Kesavan wrote:
>> +ENTRY(s3c_cpu_resume)
>> +#if defined(CONFIG_S3C_PM_DEBUG_LED_SMDK)
>> +
>> +#undef S3C64XX_VA_GPIO
>> +#define S3C64XX_VA_GPIO (0x0)
>> +#define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00)
>> +#define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04)
>> +
>> +#define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
>> +#define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
>> +
>> + /* Initialise the GPIO state if we are debugging via the SMDK LEDs,
>> + * as the uboot version supplied resets these to inputs during the
>> + * resume checks.
>> + */
>> +
>> + ldr r3, =S3C64XX_PA_GPIO
>> + ldr r0, [ r3, #S3C64XX_GPNCON ]
>> + bic r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \
>> + S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15))
>> + orr r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \
>> + S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15))
>> + str r0, [ r3, #S3C64XX_GPNCON ]
>> +
>> + ldr r0, [ r3, #S3C64XX_GPNDAT ]
>> + bic r0, r0, #0xf << 12 @ GPN12..15
>> + orr r0, r0, #1 << 15 @ GPN15
>> + str r0, [ r3, #S3C64XX_GPNDAT ]
>> +#endif
>
> This is incompatible with the aim of a single kernel booting on many ARM
> platforms.
>
> Rather than consolidating down to just one implementation, how about
> consolidating to two - one for everything but SMDK, and one for the SMDK
> with the LED stuff. You can then chose which you want - either the
> s3c_generic_resume (which is just the magic code plus the branch)
> or s3c_smdk_leds_resume (which would be the magic code plus the LEDS
> stuff plus the branch.)
I'll follow this suggestion for only S3C64XX and newer SoCs if that is
OK with Kukjin.
If however the consolidation is needed for all Samsung SoCs including the older
S3C24XX as well then this may not be workable.
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
Regards,
Abhilash
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 2/5] ARM: SAMSUNG: Make the sleep code common for S3C64XX and newer SoCs
@ 2011-09-07 11:30 ` Abhilash Kesavan
0 siblings, 0 replies; 40+ messages in thread
From: Abhilash Kesavan @ 2011-09-07 11:30 UTC (permalink / raw)
To: linux-arm-kernel
Hi Russell,
On Wed, Sep 7, 2011 at 3:25 PM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Fri, Aug 12, 2011 at 03:56:24PM +0530, Abhilash Kesavan wrote:
>> +ENTRY(s3c_cpu_resume)
>> +#if defined(CONFIG_S3C_PM_DEBUG_LED_SMDK)
>> +
>> +#undef S3C64XX_VA_GPIO
>> +#define S3C64XX_VA_GPIO (0x0)
>> +#define S3C64XX_GPNCON ? ? ? ? ? ? ? ? ? ? ? (S3C64XX_GPN_BASE + 0x00)
>> +#define S3C64XX_GPNDAT ? ? ? ? ? ? ? ? ? ? ? (S3C64XX_GPN_BASE + 0x04)
>> +
>> +#define S3C64XX_GPN_CONMASK(__gpio) ?(0x3 << ((__gpio) * 2))
>> +#define S3C64XX_GPN_OUTPUT(__gpio) ? (0x1 << ((__gpio) * 2))
>> +
>> + ? ? /* Initialise the GPIO state if we are debugging via the SMDK LEDs,
>> + ? ? ?* as the uboot version supplied resets these to inputs during the
>> + ? ? ?* resume checks.
>> + ? ? */
>> +
>> + ? ? ldr ? ? r3, =S3C64XX_PA_GPIO
>> + ? ? ldr ? ? r0, [ r3, #S3C64XX_GPNCON ]
>> + ? ? bic ? ? r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \
>> + ? ? ? ? ? ? ? ? ? ? ? S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15))
>> + ? ? orr ? ? r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \
>> + ? ? ? ? ? ? ? ? ? ? ? S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15))
>> + ? ? str ? ? r0, [ r3, #S3C64XX_GPNCON ]
>> +
>> + ? ? ldr ? ? r0, [ r3, #S3C64XX_GPNDAT ]
>> + ? ? bic ? ? r0, r0, #0xf << 12 ? ? ? ? ? ? ? ? ? ? ?@ GPN12..15
>> + ? ? orr ? ? r0, r0, #1 << 15 ? ? ? ? ? ? ? ? ? ? ? ?@ GPN15
>> + ? ? str ? ? r0, [ r3, #S3C64XX_GPNDAT ]
>> +#endif
>
> This is incompatible with the aim of a single kernel booting on many ARM
> platforms.
>
> Rather than consolidating down to just one implementation, how about
> consolidating to two - one for everything but SMDK, and one for the SMDK
> with the LED stuff. ?You can then chose which you want - either the
> s3c_generic_resume (which is just the magic code plus the branch)
> or s3c_smdk_leds_resume (which would be the magic code plus the LEDS
> stuff plus the branch.)
I'll follow this suggestion for only S3C64XX and newer SoCs if that is
OK with Kukjin.
If however the consolidation is needed for all Samsung SoCs including the older
S3C24XX as well then this may not be workable.
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
Regards,
Abhilash
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 3/5] ARM: S5P64X0: Add pm save/restore functions for GPIO banks
2011-08-12 10:26 ` Abhilash Kesavan
@ 2011-08-12 10:26 ` Abhilash Kesavan
-1 siblings, 0 replies; 40+ messages in thread
From: Abhilash Kesavan @ 2011-08-12 10:26 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc, kgene.kim
Fix the "no pm for GPIOXX" messages appearing during bootup due
to missing assignment of save/restore functions for those banks.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
arch/arm/mach-s5p64x0/gpiolib.c | 1 +
drivers/gpio/gpio-plat-samsung.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-s5p64x0/gpiolib.c b/arch/arm/mach-s5p64x0/gpiolib.c
index e7fb3b0..76c0924 100644
--- a/arch/arm/mach-s5p64x0/gpiolib.c
+++ b/arch/arm/mach-s5p64x0/gpiolib.c
@@ -467,6 +467,7 @@ static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
chip->chip.direction_input = s5p64x0_gpiolib_rbank_4bit2_input;
chip->chip.direction_output =
s5p64x0_gpiolib_rbank_4bit2_output;
+ chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
s3c_gpiolib_add(chip);
}
}
diff --git a/drivers/gpio/gpio-plat-samsung.c b/drivers/gpio/gpio-plat-samsung.c
index ef67f19..4f7c387 100644
--- a/drivers/gpio/gpio-plat-samsung.c
+++ b/drivers/gpio/gpio-plat-samsung.c
@@ -200,6 +200,8 @@ void __init samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
void __init samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip,
int nr_chips)
{
- for (; nr_chips > 0; nr_chips--, chip++)
+ for (; nr_chips > 0; nr_chips--, chip++) {
+ chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
s3c_gpiolib_add(chip);
+ }
}
--
1.7.4.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH 3/5] ARM: S5P64X0: Add pm save/restore functions for GPIO banks
@ 2011-08-12 10:26 ` Abhilash Kesavan
0 siblings, 0 replies; 40+ messages in thread
From: Abhilash Kesavan @ 2011-08-12 10:26 UTC (permalink / raw)
To: linux-arm-kernel
Fix the "no pm for GPIOXX" messages appearing during bootup due
to missing assignment of save/restore functions for those banks.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
arch/arm/mach-s5p64x0/gpiolib.c | 1 +
drivers/gpio/gpio-plat-samsung.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-s5p64x0/gpiolib.c b/arch/arm/mach-s5p64x0/gpiolib.c
index e7fb3b0..76c0924 100644
--- a/arch/arm/mach-s5p64x0/gpiolib.c
+++ b/arch/arm/mach-s5p64x0/gpiolib.c
@@ -467,6 +467,7 @@ static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
chip->chip.direction_input = s5p64x0_gpiolib_rbank_4bit2_input;
chip->chip.direction_output =
s5p64x0_gpiolib_rbank_4bit2_output;
+ chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
s3c_gpiolib_add(chip);
}
}
diff --git a/drivers/gpio/gpio-plat-samsung.c b/drivers/gpio/gpio-plat-samsung.c
index ef67f19..4f7c387 100644
--- a/drivers/gpio/gpio-plat-samsung.c
+++ b/drivers/gpio/gpio-plat-samsung.c
@@ -200,6 +200,8 @@ void __init samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
void __init samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip,
int nr_chips)
{
- for (; nr_chips > 0; nr_chips--, chip++)
+ for (; nr_chips > 0; nr_chips--, chip++) {
+ chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
s3c_gpiolib_add(chip);
+ }
}
--
1.7.4.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* RE: [PATCH 3/5] ARM: S5P64X0: Add pm save/restore functions for GPIO banks
2011-08-12 10:26 ` Abhilash Kesavan
@ 2011-09-07 6:01 ` Kukjin Kim
-1 siblings, 0 replies; 40+ messages in thread
From: Kukjin Kim @ 2011-09-07 6:01 UTC (permalink / raw)
To: 'Abhilash Kesavan', linux-arm-kernel, linux-samsung-soc
Abhilash Kesavan wrote:
>
> Fix the "no pm for GPIOXX" messages appearing during bootup due
> to missing assignment of save/restore functions for those banks.
>
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
> arch/arm/mach-s5p64x0/gpiolib.c | 1 +
> drivers/gpio/gpio-plat-samsung.c | 4 +++-
> 2 files changed, 4 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-s5p64x0/gpiolib.c
b/arch/arm/mach-s5p64x0/gpiolib.c
> index e7fb3b0..76c0924 100644
> --- a/arch/arm/mach-s5p64x0/gpiolib.c
> +++ b/arch/arm/mach-s5p64x0/gpiolib.c
> @@ -467,6 +467,7 @@ static void __init s5p64x0_gpio_add_rbank_4bit2(struct
> s3c_gpio_chip *chip,
> chip->chip.direction_input =
s5p64x0_gpiolib_rbank_4bit2_input;
> chip->chip.direction_output =
> s5p64x0_gpiolib_rbank_4bit2_output;
> + chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
> s3c_gpiolib_add(chip);
> }
> }
> diff --git a/drivers/gpio/gpio-plat-samsung.c
b/drivers/gpio/gpio-plat-samsung.c
> index ef67f19..4f7c387 100644
> --- a/drivers/gpio/gpio-plat-samsung.c
> +++ b/drivers/gpio/gpio-plat-samsung.c
> @@ -200,6 +200,8 @@ void __init samsung_gpiolib_add_4bit2_chips(struct
> s3c_gpio_chip *chip,
> void __init samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip,
> int nr_chips)
> {
> - for (; nr_chips > 0; nr_chips--, chip++)
> + for (; nr_chips > 0; nr_chips--, chip++) {
> + chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
> s3c_gpiolib_add(chip);
> + }
> }
> --
> 1.7.4.1
Hi Abhilash,
Since submitted gpio-samsung patch includes above changes, so we can drop
this.
If any problem, please let me know.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 40+ messages in thread* [PATCH 3/5] ARM: S5P64X0: Add pm save/restore functions for GPIO banks
@ 2011-09-07 6:01 ` Kukjin Kim
0 siblings, 0 replies; 40+ messages in thread
From: Kukjin Kim @ 2011-09-07 6:01 UTC (permalink / raw)
To: linux-arm-kernel
Abhilash Kesavan wrote:
>
> Fix the "no pm for GPIOXX" messages appearing during bootup due
> to missing assignment of save/restore functions for those banks.
>
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
> arch/arm/mach-s5p64x0/gpiolib.c | 1 +
> drivers/gpio/gpio-plat-samsung.c | 4 +++-
> 2 files changed, 4 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-s5p64x0/gpiolib.c
b/arch/arm/mach-s5p64x0/gpiolib.c
> index e7fb3b0..76c0924 100644
> --- a/arch/arm/mach-s5p64x0/gpiolib.c
> +++ b/arch/arm/mach-s5p64x0/gpiolib.c
> @@ -467,6 +467,7 @@ static void __init s5p64x0_gpio_add_rbank_4bit2(struct
> s3c_gpio_chip *chip,
> chip->chip.direction_input =
s5p64x0_gpiolib_rbank_4bit2_input;
> chip->chip.direction_output =
> s5p64x0_gpiolib_rbank_4bit2_output;
> + chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
> s3c_gpiolib_add(chip);
> }
> }
> diff --git a/drivers/gpio/gpio-plat-samsung.c
b/drivers/gpio/gpio-plat-samsung.c
> index ef67f19..4f7c387 100644
> --- a/drivers/gpio/gpio-plat-samsung.c
> +++ b/drivers/gpio/gpio-plat-samsung.c
> @@ -200,6 +200,8 @@ void __init samsung_gpiolib_add_4bit2_chips(struct
> s3c_gpio_chip *chip,
> void __init samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip,
> int nr_chips)
> {
> - for (; nr_chips > 0; nr_chips--, chip++)
> + for (; nr_chips > 0; nr_chips--, chip++) {
> + chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
> s3c_gpiolib_add(chip);
> + }
> }
> --
> 1.7.4.1
Hi Abhilash,
Since submitted gpio-samsung patch includes above changes, so we can drop
this.
If any problem, please let me know.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH 3/5] ARM: S5P64X0: Add pm save/restore functions for GPIO banks
2011-09-07 6:01 ` Kukjin Kim
@ 2011-09-07 6:36 ` Abhilash Kesavan
-1 siblings, 0 replies; 40+ messages in thread
From: Abhilash Kesavan @ 2011-09-07 6:36 UTC (permalink / raw)
To: Kukjin Kim; +Cc: linux-samsung-soc, linux-arm-kernel
Hi Mr Kim,
On Wed, Sep 7, 2011 at 11:31 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Abhilash Kesavan wrote:
>>
>> Fix the "no pm for GPIOXX" messages appearing during bootup due
>> to missing assignment of save/restore functions for those banks.
>>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> ---
>> arch/arm/mach-s5p64x0/gpiolib.c | 1 +
>> drivers/gpio/gpio-plat-samsung.c | 4 +++-
>> 2 files changed, 4 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/mach-s5p64x0/gpiolib.c
> b/arch/arm/mach-s5p64x0/gpiolib.c
>> index e7fb3b0..76c0924 100644
>> --- a/arch/arm/mach-s5p64x0/gpiolib.c
>> +++ b/arch/arm/mach-s5p64x0/gpiolib.c
>> @@ -467,6 +467,7 @@ static void __init s5p64x0_gpio_add_rbank_4bit2(struct
>> s3c_gpio_chip *chip,
>> chip->chip.direction_input =
> s5p64x0_gpiolib_rbank_4bit2_input;
>> chip->chip.direction_output =
>> s5p64x0_gpiolib_rbank_4bit2_output;
>> + chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
>> s3c_gpiolib_add(chip);
>> }
>> }
>> diff --git a/drivers/gpio/gpio-plat-samsung.c
> b/drivers/gpio/gpio-plat-samsung.c
>> index ef67f19..4f7c387 100644
>> --- a/drivers/gpio/gpio-plat-samsung.c
>> +++ b/drivers/gpio/gpio-plat-samsung.c
>> @@ -200,6 +200,8 @@ void __init samsung_gpiolib_add_4bit2_chips(struct
>> s3c_gpio_chip *chip,
>> void __init samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip,
>> int nr_chips)
>> {
>> - for (; nr_chips > 0; nr_chips--, chip++)
>> + for (; nr_chips > 0; nr_chips--, chip++) {
>> + chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
>> s3c_gpiolib_add(chip);
>> + }
>> }
>> --
>> 1.7.4.1
>
> Hi Abhilash,
>
> Since submitted gpio-samsung patch includes above changes, so we can drop
> this.
>
> If any problem, please let me know.
Sure. No problem.
>
> Thanks.
>
> Best regards,
> Kgene.
Abhilash
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 40+ messages in thread* [PATCH 3/5] ARM: S5P64X0: Add pm save/restore functions for GPIO banks
@ 2011-09-07 6:36 ` Abhilash Kesavan
0 siblings, 0 replies; 40+ messages in thread
From: Abhilash Kesavan @ 2011-09-07 6:36 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mr Kim,
On Wed, Sep 7, 2011 at 11:31 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Abhilash Kesavan wrote:
>>
>> Fix the "no pm for GPIOXX" messages appearing during bootup due
>> to missing assignment of save/restore functions for those banks.
>>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> ---
>> ?arch/arm/mach-s5p64x0/gpiolib.c ?| ? ?1 +
>> ?drivers/gpio/gpio-plat-samsung.c | ? ?4 +++-
>> ?2 files changed, 4 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/mach-s5p64x0/gpiolib.c
> b/arch/arm/mach-s5p64x0/gpiolib.c
>> index e7fb3b0..76c0924 100644
>> --- a/arch/arm/mach-s5p64x0/gpiolib.c
>> +++ b/arch/arm/mach-s5p64x0/gpiolib.c
>> @@ -467,6 +467,7 @@ static void __init s5p64x0_gpio_add_rbank_4bit2(struct
>> s3c_gpio_chip *chip,
>> ? ? ? ? ? ? ? chip->chip.direction_input =
> s5p64x0_gpiolib_rbank_4bit2_input;
>> ? ? ? ? ? ? ? chip->chip.direction_output =
>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? s5p64x0_gpiolib_rbank_4bit2_output;
>> + ? ? ? ? ? ? chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
>> ? ? ? ? ? ? ? s3c_gpiolib_add(chip);
>> ? ? ? }
>> ?}
>> diff --git a/drivers/gpio/gpio-plat-samsung.c
> b/drivers/gpio/gpio-plat-samsung.c
>> index ef67f19..4f7c387 100644
>> --- a/drivers/gpio/gpio-plat-samsung.c
>> +++ b/drivers/gpio/gpio-plat-samsung.c
>> @@ -200,6 +200,8 @@ void __init samsung_gpiolib_add_4bit2_chips(struct
>> s3c_gpio_chip *chip,
>> ?void __init samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip,
>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int nr_chips)
>> ?{
>> - ? ? for (; nr_chips > 0; nr_chips--, chip++)
>> + ? ? for (; nr_chips > 0; nr_chips--, chip++) {
>> + ? ? ? ? ? ? chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
>> ? ? ? ? ? ? ? s3c_gpiolib_add(chip);
>> + ? ? }
>> ?}
>> --
>> 1.7.4.1
>
> Hi Abhilash,
>
> Since submitted gpio-samsung patch includes above changes, so we can drop
> this.
>
> If any problem, please let me know.
Sure. No problem.
>
> Thanks.
>
> Best regards,
> Kgene.
Abhilash
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 4/5] ARM: S5P64X0: Fix incorrect serial clock name
2011-08-12 10:26 ` Abhilash Kesavan
@ 2011-08-12 10:26 ` Abhilash Kesavan
-1 siblings, 0 replies; 40+ messages in thread
From: Abhilash Kesavan @ 2011-08-12 10:26 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc, kgene.kim
The S3C6400 serial glue driver(used by S5P64X0) needs the clock name to be
pclk or uclk1. Correct the clock name in init.c to pclk and source pclk
from pclk_low to get the correct rate.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
arch/arm/mach-s5p64x0/clock-s5p6440.c | 2 +-
arch/arm/mach-s5p64x0/clock-s5p6450.c | 2 +-
arch/arm/mach-s5p64x0/init.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index 0e9cd30..4b594a4 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -554,7 +554,7 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
clk_f.rate = fclk;
clk_h.rate = hclk;
- clk_p.rate = pclk;
+ clk_p.rate = pclk_low;
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_set_clksrc(&clksrcs[ptr], true);
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index d9dc16c..eca9a57 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -613,7 +613,7 @@ void __init_or_cpufreq s5p6450_setup_clocks(void)
clk_f.rate = fclk;
clk_h.rate = hclk;
- clk_p.rate = pclk;
+ clk_p.rate = pclk_low;
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_set_clksrc(&clksrcs[ptr], true);
diff --git a/arch/arm/mach-s5p64x0/init.c b/arch/arm/mach-s5p64x0/init.c
index 79833ca..ee25e28 100644
--- a/arch/arm/mach-s5p64x0/init.c
+++ b/arch/arm/mach-s5p64x0/init.c
@@ -25,7 +25,7 @@
static struct s3c24xx_uart_clksrc s5p64x0_serial_clocks[] = {
[0] = {
- .name = "pclk_low",
+ .name = "pclk",
.divisor = 1,
.min_baud = 0,
.max_baud = 0,
--
1.7.4.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH 4/5] ARM: S5P64X0: Fix incorrect serial clock name
@ 2011-08-12 10:26 ` Abhilash Kesavan
0 siblings, 0 replies; 40+ messages in thread
From: Abhilash Kesavan @ 2011-08-12 10:26 UTC (permalink / raw)
To: linux-arm-kernel
The S3C6400 serial glue driver(used by S5P64X0) needs the clock name to be
pclk or uclk1. Correct the clock name in init.c to pclk and source pclk
from pclk_low to get the correct rate.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
arch/arm/mach-s5p64x0/clock-s5p6440.c | 2 +-
arch/arm/mach-s5p64x0/clock-s5p6450.c | 2 +-
arch/arm/mach-s5p64x0/init.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index 0e9cd30..4b594a4 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -554,7 +554,7 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
clk_f.rate = fclk;
clk_h.rate = hclk;
- clk_p.rate = pclk;
+ clk_p.rate = pclk_low;
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_set_clksrc(&clksrcs[ptr], true);
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index d9dc16c..eca9a57 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -613,7 +613,7 @@ void __init_or_cpufreq s5p6450_setup_clocks(void)
clk_f.rate = fclk;
clk_h.rate = hclk;
- clk_p.rate = pclk;
+ clk_p.rate = pclk_low;
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_set_clksrc(&clksrcs[ptr], true);
diff --git a/arch/arm/mach-s5p64x0/init.c b/arch/arm/mach-s5p64x0/init.c
index 79833ca..ee25e28 100644
--- a/arch/arm/mach-s5p64x0/init.c
+++ b/arch/arm/mach-s5p64x0/init.c
@@ -25,7 +25,7 @@
static struct s3c24xx_uart_clksrc s5p64x0_serial_clocks[] = {
[0] = {
- .name = "pclk_low",
+ .name = "pclk",
.divisor = 1,
.min_baud = 0,
.max_baud = 0,
--
1.7.4.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* RE: [PATCH 4/5] ARM: S5P64X0: Fix incorrect serial clock name
2011-08-12 10:26 ` Abhilash Kesavan
@ 2011-09-07 6:01 ` Kukjin Kim
-1 siblings, 0 replies; 40+ messages in thread
From: Kukjin Kim @ 2011-09-07 6:01 UTC (permalink / raw)
To: 'Abhilash Kesavan', linux-arm-kernel, linux-samsung-soc
Abhilash Kesavan wrote:
>
> The S3C6400 serial glue driver(used by S5P64X0) needs the clock name to be
> pclk or uclk1. Correct the clock name in init.c to pclk and source pclk
> from pclk_low to get the correct rate.
>
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
> arch/arm/mach-s5p64x0/clock-s5p6440.c | 2 +-
> arch/arm/mach-s5p64x0/clock-s5p6450.c | 2 +-
> arch/arm/mach-s5p64x0/init.c | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-
> s5p64x0/clock-s5p6440.c
> index 0e9cd30..4b594a4 100644
> --- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
> +++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
> @@ -554,7 +554,7 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
>
> clk_f.rate = fclk;
> clk_h.rate = hclk;
> - clk_p.rate = pclk;
> + clk_p.rate = pclk_low;
As you know, HCLK and PCLK are connected to IPs which are included in high
frequency domain and HCLK_LOW and PCLK_LOW are connected to IPs which are
included in low frequency domain. I wonder what value is the ARM clock on
your SMDK64X0? 533MHz or 667MHz?
Originally, the "struct clk clk_p" means PCLK not PCLK_LOW. So I think, the
rate of clk_p should be pclk
>
> for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
> s3c_set_clksrc(&clksrcs[ptr], true);
> diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-
> s5p64x0/clock-s5p6450.c
> index d9dc16c..eca9a57 100644
> --- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
> +++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
> @@ -613,7 +613,7 @@ void __init_or_cpufreq s5p6450_setup_clocks(void)
>
> clk_f.rate = fclk;
> clk_h.rate = hclk;
> - clk_p.rate = pclk;
> + clk_p.rate = pclk_low;
Same as above.
>
> for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
> s3c_set_clksrc(&clksrcs[ptr], true);
> diff --git a/arch/arm/mach-s5p64x0/init.c b/arch/arm/mach-s5p64x0/init.c
> index 79833ca..ee25e28 100644
> --- a/arch/arm/mach-s5p64x0/init.c
> +++ b/arch/arm/mach-s5p64x0/init.c
> @@ -25,7 +25,7 @@
>
> static struct s3c24xx_uart_clksrc s5p64x0_serial_clocks[] = {
> [0] = {
> - .name = "pclk_low",
> + .name = "pclk",
According to data sheet, should be pclk_low. Or if required for serial
driver, uclk1 can be used here.
> .divisor = 1,
> .min_baud = 0,
> .max_baud = 0,
> --
> 1.7.4.1
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 40+ messages in thread* [PATCH 4/5] ARM: S5P64X0: Fix incorrect serial clock name
@ 2011-09-07 6:01 ` Kukjin Kim
0 siblings, 0 replies; 40+ messages in thread
From: Kukjin Kim @ 2011-09-07 6:01 UTC (permalink / raw)
To: linux-arm-kernel
Abhilash Kesavan wrote:
>
> The S3C6400 serial glue driver(used by S5P64X0) needs the clock name to be
> pclk or uclk1. Correct the clock name in init.c to pclk and source pclk
> from pclk_low to get the correct rate.
>
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
> arch/arm/mach-s5p64x0/clock-s5p6440.c | 2 +-
> arch/arm/mach-s5p64x0/clock-s5p6450.c | 2 +-
> arch/arm/mach-s5p64x0/init.c | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-
> s5p64x0/clock-s5p6440.c
> index 0e9cd30..4b594a4 100644
> --- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
> +++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
> @@ -554,7 +554,7 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
>
> clk_f.rate = fclk;
> clk_h.rate = hclk;
> - clk_p.rate = pclk;
> + clk_p.rate = pclk_low;
As you know, HCLK and PCLK are connected to IPs which are included in high
frequency domain and HCLK_LOW and PCLK_LOW are connected to IPs which are
included in low frequency domain. I wonder what value is the ARM clock on
your SMDK64X0? 533MHz or 667MHz?
Originally, the "struct clk clk_p" means PCLK not PCLK_LOW. So I think, the
rate of clk_p should be pclk
>
> for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
> s3c_set_clksrc(&clksrcs[ptr], true);
> diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-
> s5p64x0/clock-s5p6450.c
> index d9dc16c..eca9a57 100644
> --- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
> +++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
> @@ -613,7 +613,7 @@ void __init_or_cpufreq s5p6450_setup_clocks(void)
>
> clk_f.rate = fclk;
> clk_h.rate = hclk;
> - clk_p.rate = pclk;
> + clk_p.rate = pclk_low;
Same as above.
>
> for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
> s3c_set_clksrc(&clksrcs[ptr], true);
> diff --git a/arch/arm/mach-s5p64x0/init.c b/arch/arm/mach-s5p64x0/init.c
> index 79833ca..ee25e28 100644
> --- a/arch/arm/mach-s5p64x0/init.c
> +++ b/arch/arm/mach-s5p64x0/init.c
> @@ -25,7 +25,7 @@
>
> static struct s3c24xx_uart_clksrc s5p64x0_serial_clocks[] = {
> [0] = {
> - .name = "pclk_low",
> + .name = "pclk",
According to data sheet, should be pclk_low. Or if required for serial
driver, uclk1 can be used here.
> .divisor = 1,
> .min_baud = 0,
> .max_baud = 0,
> --
> 1.7.4.1
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH 4/5] ARM: S5P64X0: Fix incorrect serial clock name
2011-09-07 6:01 ` Kukjin Kim
@ 2011-09-07 6:31 ` Abhilash Kesavan
-1 siblings, 0 replies; 40+ messages in thread
From: Abhilash Kesavan @ 2011-09-07 6:31 UTC (permalink / raw)
To: Kukjin Kim; +Cc: linux-arm-kernel, linux-samsung-soc
Hi Mr Kim,
On Wed, Sep 7, 2011 at 11:31 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Abhilash Kesavan wrote:
>>
>> The S3C6400 serial glue driver(used by S5P64X0) needs the clock name to be
>> pclk or uclk1. Correct the clock name in init.c to pclk and source pclk
>> from pclk_low to get the correct rate.
>>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> ---
>> arch/arm/mach-s5p64x0/clock-s5p6440.c | 2 +-
>> arch/arm/mach-s5p64x0/clock-s5p6450.c | 2 +-
>> arch/arm/mach-s5p64x0/init.c | 2 +-
>> 3 files changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-
>> s5p64x0/clock-s5p6440.c
>> index 0e9cd30..4b594a4 100644
>> --- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
>> +++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
>> @@ -554,7 +554,7 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
>>
>> clk_f.rate = fclk;
>> clk_h.rate = hclk;
>> - clk_p.rate = pclk;
>> + clk_p.rate = pclk_low;
>
> As you know, HCLK and PCLK are connected to IPs which are included in high
> frequency domain and HCLK_LOW and PCLK_LOW are connected to IPs which are
> included in low frequency domain. I wonder what value is the ARM clock on
> your SMDK64X0? 533MHz or 667MHz?
Mine is at 533MHz
>
> Originally, the "struct clk clk_p" means PCLK not PCLK_LOW. So I think, the
> rate of clk_p should be pclk
OK
>
>>
>> for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
>> s3c_set_clksrc(&clksrcs[ptr], true);
>> diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-
>> s5p64x0/clock-s5p6450.c
>> index d9dc16c..eca9a57 100644
>> --- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
>> +++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
>> @@ -613,7 +613,7 @@ void __init_or_cpufreq s5p6450_setup_clocks(void)
>>
>> clk_f.rate = fclk;
>> clk_h.rate = hclk;
>> - clk_p.rate = pclk;
>> + clk_p.rate = pclk_low;
>
> Same as above.
>
>>
>> for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
>> s3c_set_clksrc(&clksrcs[ptr], true);
>> diff --git a/arch/arm/mach-s5p64x0/init.c b/arch/arm/mach-s5p64x0/init.c
>> index 79833ca..ee25e28 100644
>> --- a/arch/arm/mach-s5p64x0/init.c
>> +++ b/arch/arm/mach-s5p64x0/init.c
>> @@ -25,7 +25,7 @@
>>
>> static struct s3c24xx_uart_clksrc s5p64x0_serial_clocks[] = {
>> [0] = {
>> - .name = "pclk_low",
>> + .name = "pclk",
>
> According to data sheet, should be pclk_low. Or if required for serial
> driver, uclk1 can be used here.
The serial glue driver does a string comparison with either pclk or uclk*;
You'd rather I add a uclk1 instance ?
Thanks for the review.
>
>> .divisor = 1,
>> .min_baud = 0,
>> .max_baud = 0,
>> --
>> 1.7.4.1
>
>
>
> Thanks.
>
> Best regards,
> Kgene.
Abhilash
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 40+ messages in thread* [PATCH 4/5] ARM: S5P64X0: Fix incorrect serial clock name
@ 2011-09-07 6:31 ` Abhilash Kesavan
0 siblings, 0 replies; 40+ messages in thread
From: Abhilash Kesavan @ 2011-09-07 6:31 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mr Kim,
On Wed, Sep 7, 2011 at 11:31 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Abhilash Kesavan wrote:
>>
>> The S3C6400 serial glue driver(used by S5P64X0) needs the clock name to be
>> pclk or uclk1. Correct the clock name in init.c to pclk and source pclk
>> from pclk_low to get the correct rate.
>>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> ---
>> ?arch/arm/mach-s5p64x0/clock-s5p6440.c | ? ?2 +-
>> ?arch/arm/mach-s5p64x0/clock-s5p6450.c | ? ?2 +-
>> ?arch/arm/mach-s5p64x0/init.c ? ? ? ? ?| ? ?2 +-
>> ?3 files changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-
>> s5p64x0/clock-s5p6440.c
>> index 0e9cd30..4b594a4 100644
>> --- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
>> +++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
>> @@ -554,7 +554,7 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
>>
>> ? ? ? clk_f.rate = fclk;
>> ? ? ? clk_h.rate = hclk;
>> - ? ? clk_p.rate = pclk;
>> + ? ? clk_p.rate = pclk_low;
>
> As you know, HCLK and PCLK are connected to IPs which are included in high
> frequency domain and HCLK_LOW and PCLK_LOW are connected to IPs which are
> included in low frequency domain. I wonder what value is the ARM clock on
> your SMDK64X0? 533MHz or 667MHz?
Mine is at 533MHz
>
> Originally, the "struct clk clk_p" means PCLK not PCLK_LOW. So I think, the
> rate of clk_p should be pclk
OK
>
>>
>> ? ? ? for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
>> ? ? ? ? ? ? ? s3c_set_clksrc(&clksrcs[ptr], true);
>> diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-
>> s5p64x0/clock-s5p6450.c
>> index d9dc16c..eca9a57 100644
>> --- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
>> +++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
>> @@ -613,7 +613,7 @@ void __init_or_cpufreq s5p6450_setup_clocks(void)
>>
>> ? ? ? clk_f.rate = fclk;
>> ? ? ? clk_h.rate = hclk;
>> - ? ? clk_p.rate = pclk;
>> + ? ? clk_p.rate = pclk_low;
>
> Same as above.
>
>>
>> ? ? ? for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
>> ? ? ? ? ? ? ? s3c_set_clksrc(&clksrcs[ptr], true);
>> diff --git a/arch/arm/mach-s5p64x0/init.c b/arch/arm/mach-s5p64x0/init.c
>> index 79833ca..ee25e28 100644
>> --- a/arch/arm/mach-s5p64x0/init.c
>> +++ b/arch/arm/mach-s5p64x0/init.c
>> @@ -25,7 +25,7 @@
>>
>> ?static struct s3c24xx_uart_clksrc s5p64x0_serial_clocks[] = {
>> ? ? ? [0] = {
>> - ? ? ? ? ? ? .name ? ? ? ? ? = "pclk_low",
>> + ? ? ? ? ? ? .name ? ? ? ? ? = "pclk",
>
> According to data sheet, should be pclk_low. Or if required for serial
> driver, uclk1 can be used here.
The serial glue driver does a string comparison with either pclk or uclk*;
You'd rather I add a uclk1 instance ?
Thanks for the review.
>
>> ? ? ? ? ? ? ? .divisor ? ? ? ?= 1,
>> ? ? ? ? ? ? ? .min_baud ? ? ? = 0,
>> ? ? ? ? ? ? ? .max_baud ? ? ? = 0,
>> --
>> 1.7.4.1
>
>
>
> Thanks.
>
> Best regards,
> Kgene.
Abhilash
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 5/5] ARM: S5P64X0: Add Power Management support
2011-08-12 10:26 ` Abhilash Kesavan
@ 2011-08-12 10:26 ` Abhilash Kesavan
-1 siblings, 0 replies; 40+ messages in thread
From: Abhilash Kesavan @ 2011-08-12 10:26 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc, kgene.kim
Add suspend-to-ram support for SMDK6440/50
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
arch/arm/Kconfig | 2 +-
arch/arm/mach-s5p64x0/Kconfig | 4 +
arch/arm/mach-s5p64x0/Makefile | 1 +
arch/arm/mach-s5p64x0/include/mach/map.h | 1 +
arch/arm/mach-s5p64x0/include/mach/pm-core.h | 117 +++++++++++++
arch/arm/mach-s5p64x0/include/mach/regs-clock.h | 33 ++++
arch/arm/mach-s5p64x0/include/mach/regs-gpio.h | 19 ++
arch/arm/mach-s5p64x0/irq-eint.c | 2 +
arch/arm/mach-s5p64x0/irq-pm.c | 92 ++++++++++
arch/arm/mach-s5p64x0/pm.c | 204 +++++++++++++++++++++++
10 files changed, 474 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-s5p64x0/include/mach/pm-core.h
create mode 100644 arch/arm/mach-s5p64x0/irq-pm.c
create mode 100644 arch/arm/mach-s5p64x0/pm.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2c71a8f..47aed0d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -2071,7 +2071,7 @@ menu "Power management options"
source "kernel/power/Kconfig"
config ARCH_SUSPEND_POSSIBLE
- depends on !ARCH_S5P64X0 && !ARCH_S5PC100
+ depends on !ARCH_S5PC100
depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
def_bool y
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index 65c7518..d7f034a 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -11,6 +11,8 @@ config CPU_S5P6440
bool
select S3C_PL330_DMA
select S5P_HRT
+ select SAMSUNG_SLEEP if PM
+ select SAMSUNG_WAKEMASK if PM
help
Enable S5P6440 CPU support
@@ -18,6 +20,8 @@ config CPU_S5P6450
bool
select S3C_PL330_DMA
select S5P_HRT
+ select SAMSUNG_SLEEP if PM
+ select SAMSUNG_WAKEMASK if PM
help
Enable S5P6450 CPU support
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
index 5f6afdf..acfebb7 100644
--- a/arch/arm/mach-s5p64x0/Makefile
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o gpiolib.o
obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o irq-eint.o
obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o
obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o
+obj-$(CONFIG_PM) += pm.o irq-pm.o
# machine support
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
index 95c9125..6138f7c 100644
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -85,5 +85,6 @@
#define S5P_PA_UART5 S5P6450_PA_UART(5)
#define S5P_SZ_UART SZ_256
+#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/pm-core.h b/arch/arm/mach-s5p64x0/include/mach/pm-core.h
new file mode 100644
index 0000000..aee9d85
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/pm-core.h
@@ -0,0 +1,117 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/pm-core.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * S5P64X0 - PM core support for arch/arm/plat-samsung/pm.c
+ *
+ * Based on PM core support for S3C64XX by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <mach/regs-gpio.h>
+
+static inline void s3c_pm_debug_init_uart(void)
+{
+ u32 tmp = __raw_readl(S5P64X0_CLK_GATE_PCLK);
+
+ /*
+ * As a note, since the S5P64X0 UARTs generally have multiple
+ * clock sources, we simply enable PCLK at the moment and hope
+ * that the resume settings for the UART are suitable for the
+ * use with PCLK.
+ */
+ tmp |= S5P64X0_CLKCON_PCLK_UART0;
+ tmp |= S5P64X0_CLKCON_PCLK_UART1;
+ tmp |= S5P64X0_CLKCON_PCLK_UART2;
+ tmp |= S5P64X0_CLKCON_PCLK_UART3;
+
+ __raw_writel(tmp, S5P64X0_CLK_GATE_PCLK);
+ udelay(10);
+}
+
+static inline void s3c_pm_arch_prepare_irqs(void)
+{
+ /* VIC should have already been taken care of */
+
+ /* clear any pending EINT0 interrupts */
+ __raw_writel(__raw_readl(S5P64X0_EINT0PEND), S5P64X0_EINT0PEND);
+}
+
+static inline void s3c_pm_arch_stop_clocks(void) { }
+static inline void s3c_pm_arch_show_resume_irqs(void) { }
+
+/*
+ * make these defines, we currently do not have any need to change
+ * the IRQ wake controls depending on the CPU we are running on
+ */
+#define s3c_irqwake_eintallow ((1 << 16) - 1)
+#define s3c_irqwake_intallow (~0)
+
+static inline void s3c_pm_arch_update_uart(void __iomem *regs,
+ struct pm_uart_save *save)
+{
+ u32 ucon = __raw_readl(regs + S3C2410_UCON);
+ u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
+ u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
+ u32 new_ucon;
+ u32 delta;
+
+ /*
+ * S5P64X0 UART blocks only support level interrupts, so ensure that
+ * when we restore unused UART blocks we force the level interrupt
+ * settings.
+ */
+ save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
+
+ /*
+ * We have a constraint on changing the clock type of the UART
+ * between UCLKx and PCLK, so ensure that when we restore UCON
+ * that the CLK field is correctly modified if the bootloader
+ * has changed anything.
+ */
+ if (ucon_clk != save_clk) {
+ new_ucon = save->ucon;
+ delta = ucon_clk ^ save_clk;
+
+ /*
+ * change from UCLKx => wrong PCLK,
+ * either UCLK can be tested for by a bit-test
+ * with UCLK0
+ */
+ if (ucon_clk & S3C6400_UCON_UCLK0 &&
+ !(save_clk & S3C6400_UCON_UCLK0) &&
+ delta & S3C6400_UCON_PCLK2) {
+ new_ucon &= ~S3C6400_UCON_UCLK0;
+ } else if (delta == S3C6400_UCON_PCLK2) {
+ /*
+ * as a precaution, don't change from
+ * PCLK2 => PCLK or vice-versa
+ */
+ new_ucon ^= S3C6400_UCON_PCLK2;
+ }
+
+ S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
+ ucon, new_ucon, save->ucon);
+ save->ucon = new_ucon;
+ }
+}
+
+static inline void s3c_pm_restored_gpios(void)
+{
+ /* ensure sleep mode has been cleared from the system */
+ __raw_writel(0, S5P64X0_SLPEN);
+}
+
+static inline void s3c_pm_saved_gpios(void)
+{
+ /*
+ * turn on the sleep mode and keep it there, as it seems that during
+ * suspend the xCON registers get re-set and thus you can end up with
+ * problems between going to sleep and resuming.
+ */
+ __raw_writel(S5P64X0_SLPEN_USE_xSLP, S5P64X0_SLPEN);
+}
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
index a133f22..75f66a9 100644
--- a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
@@ -41,17 +41,50 @@
#define S5P6450_DPLL_CON S5P_CLKREG(0x50)
#define S5P6450_DPLL_CON_K S5P_CLKREG(0x54)
+#define S5P64X0_AHB_CON0 S5P_CLKREG(0x100)
#define S5P64X0_CLK_SRC1 S5P_CLKREG(0x10C)
#define S5P64X0_SYS_ID S5P_CLKREG(0x118)
#define S5P64X0_SYS_OTHERS S5P_CLKREG(0x11C)
#define S5P64X0_PWR_CFG S5P_CLKREG(0x804)
+#define S5P64X0_EINT_WAKEUP_MASK S5P_CLKREG(0x808)
+#define S5P64X0_SLEEP_CFG S5P_CLKREG(0x818)
+#define S5P64X0_PWR_STABLE S5P_CLKREG(0x828)
+
#define S5P64X0_OTHERS S5P_CLKREG(0x900)
+#define S5P64X0_WAKEUP_STAT S5P_CLKREG(0x908)
+
+#define S5P64X0_INFORM0 S5P_CLKREG(0xA00)
#define S5P64X0_CLKDIV0_HCLK_SHIFT (8)
#define S5P64X0_CLKDIV0_HCLK_MASK (0xF << S5P64X0_CLKDIV0_HCLK_SHIFT)
+/* HCLK GATE Registers */
+#define S5P64X0_CLKCON_HCLK1_FIMGVG (1<<2)
+#define S5P64X0_CLKCON_SCLK1_FIMGVG (1<<2)
+
+/* PCLK GATE Registers */
+#define S5P64X0_CLKCON_PCLK_UART3 (1<<4)
+#define S5P64X0_CLKCON_PCLK_UART2 (1<<3)
+#define S5P64X0_CLKCON_PCLK_UART1 (1<<2)
+#define S5P64X0_CLKCON_PCLK_UART0 (1<<1)
+
+#define S5P64X0_PWRCFG_MMC1_DISABLE (1 << 15)
+#define S5P64X0_PWRCFG_MMC0_DISABLE (1 << 14)
+#define S5P64X0_PWRCFG_RTC_TICK_DISABLE (1 << 11)
+#define S5P64X0_PWRCFG_RTC_ALRM_DISABLE (1 << 10)
+#define S5P64X0_PWRCFG_CFG_WFI_MASK (3 << 5)
+#define S5P64X0_PWRCFG_CFG_WFI_SLEEP (3 << 5)
+
+#define S5P64X0_SLEEP_CFG_OSC_EN (1 << 0)
+
+#define S5P64X0_PWR_STABLE_CNT_VAL_4 (4 << 0)
+
+#define S5P6450_OTHERS_DISABLE_INT (1 << 31)
+#define S5P64X0_OTHERS_RET_UART (1 << 26)
+#define S5P64X0_OTHERS_RET_MMC1 (1 << 25)
+#define S5P64X0_OTHERS_RET_MMC0 (1 << 24)
#define S5P64X0_OTHERS_USB_SIG_MASK (1 << 16)
/* Compatibility defines */
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
index 6ce2547..27a2230 100644
--- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
@@ -34,14 +34,33 @@
#define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180)
#define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300)
+#define S5P64X0_SPCON0 (S5P_VA_GPIO + 0x1A0)
+#define S5P64X0_SPCON1 (S5P_VA_GPIO + 0x2B0)
+
+#define S5P64X0_MEM0CONSLP0 (S5P_VA_GPIO + 0x1C0)
+#define S5P64X0_MEM0CONSLP1 (S5P_VA_GPIO + 0x1C4)
+#define S5P64X0_MEM0DRVCON (S5P_VA_GPIO + 0x1D0)
+#define S5P64X0_MEM1DRVCON (S5P_VA_GPIO + 0x1D4)
+
+#define S5P64X0_EINT12CON (S5P_VA_GPIO + 0x200)
+#define S5P64X0_EINT12FLTCON (S5P_VA_GPIO + 0x220)
+#define S5P64X0_EINT12MASK (S5P_VA_GPIO + 0x240)
+
/* External interrupt control registers for group0 */
#define EINT0CON0_OFFSET (0x900)
+#define EINT0FLTCON0_OFFSET (0x910)
+#define EINT0FLTCON1_OFFSET (0x914)
#define EINT0MASK_OFFSET (0x920)
#define EINT0PEND_OFFSET (0x924)
#define S5P64X0_EINT0CON0 (S5P_VA_GPIO + EINT0CON0_OFFSET)
+#define S5P64X0_EINT0FLTCON0 (S5P_VA_GPIO + EINT0FLTCON0_OFFSET)
+#define S5P64X0_EINT0FLTCON1 (S5P_VA_GPIO + EINT0FLTCON1_OFFSET)
#define S5P64X0_EINT0MASK (S5P_VA_GPIO + EINT0MASK_OFFSET)
#define S5P64X0_EINT0PEND (S5P_VA_GPIO + EINT0PEND_OFFSET)
+#define S5P64X0_SLPEN (S5P_VA_GPIO + 0x930)
+#define S5P64X0_SLPEN_USE_xSLP (1 << 0)
+
#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5p64x0/irq-eint.c b/arch/arm/mach-s5p64x0/irq-eint.c
index fe7380f..3b94c6c 100644
--- a/arch/arm/mach-s5p64x0/irq-eint.c
+++ b/arch/arm/mach-s5p64x0/irq-eint.c
@@ -19,6 +19,7 @@
#include <plat/regs-irqtype.h>
#include <plat/gpio-cfg.h>
+#include <plat/pm.h>
#include <mach/regs-gpio.h>
#include <mach/regs-clock.h>
@@ -133,6 +134,7 @@ static int s5p64x0_alloc_gc(void)
ct->chip.irq_mask = irq_gc_mask_set_bit;
ct->chip.irq_unmask = irq_gc_mask_clr_bit;
ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
+ ct->chip.irq_set_wake = s3c_irqext_wake;
ct->regs.ack = EINT0PEND_OFFSET;
ct->regs.mask = EINT0MASK_OFFSET;
irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
diff --git a/arch/arm/mach-s5p64x0/irq-pm.c b/arch/arm/mach-s5p64x0/irq-pm.c
new file mode 100644
index 0000000..3e6f245
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/irq-pm.c
@@ -0,0 +1,92 @@
+/* linux/arch/arm/mach-s5p64x0/irq-pm.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * S5P64X0 - Interrupt handling Power Management
+ *
+ * Based on arch/arm/mach-s3c64xx/irq-pm.c by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/syscore_ops.h>
+#include <linux/serial_core.h>
+#include <linux/io.h>
+
+#include <plat/regs-serial.h>
+#include <plat/pm.h>
+
+#include <mach/regs-gpio.h>
+
+static struct sleep_save irq_save[] = {
+ SAVE_ITEM(S5P64X0_EINT0CON0),
+ SAVE_ITEM(S5P64X0_EINT0FLTCON0),
+ SAVE_ITEM(S5P64X0_EINT0FLTCON1),
+ SAVE_ITEM(S5P64X0_EINT0MASK),
+};
+
+static struct irq_grp_save {
+ u32 con;
+ u32 fltcon;
+ u32 mask;
+} eint_grp_save[4];
+
+static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS];
+
+static int s5p64x0_irq_pm_suspend(void)
+{
+ struct irq_grp_save *grp = eint_grp_save;
+ int i;
+
+ S3C_PMDBG("%s: suspending IRQs\n", __func__);
+
+ s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
+
+ for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
+ irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM);
+
+ for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
+ grp->con = __raw_readl(S5P64X0_EINT12CON + (i * 4));
+ grp->mask = __raw_readl(S5P64X0_EINT12MASK + (i * 4));
+ grp->fltcon = __raw_readl(S5P64X0_EINT12FLTCON + (i * 4));
+ }
+
+ return 0;
+}
+
+static void s5p64x0_irq_pm_resume(void)
+{
+ struct irq_grp_save *grp = eint_grp_save;
+ int i;
+
+ S3C_PMDBG("%s: resuming IRQs\n", __func__);
+
+ s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
+
+ for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
+ __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM);
+
+ for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
+ __raw_writel(grp->con, S5P64X0_EINT12CON + (i * 4));
+ __raw_writel(grp->mask, S5P64X0_EINT12MASK + (i * 4));
+ __raw_writel(grp->fltcon, S5P64X0_EINT12FLTCON + (i * 4));
+ }
+
+ S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
+}
+
+static struct syscore_ops s5p64x0_irq_syscore_ops = {
+ .suspend = s5p64x0_irq_pm_suspend,
+ .resume = s5p64x0_irq_pm_resume,
+};
+
+static int __init s5p64x0_syscore_init(void)
+{
+ register_syscore_ops(&s5p64x0_irq_syscore_ops);
+
+ return 0;
+}
+core_initcall(s5p64x0_syscore_init);
diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c
new file mode 100644
index 0000000..cced4fb
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/pm.c
@@ -0,0 +1,204 @@
+/* linux/arch/arm/mach-s5p64x0/pm.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * S5P64X0 Power Management Support
+ *
+ * Based on arch/arm/mach-s3c64xx/pm.c by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/suspend.h>
+#include <linux/syscore_ops.h>
+#include <linux/io.h>
+
+#include <plat/cpu.h>
+#include <plat/pm.h>
+#include <plat/regs-timer.h>
+#include <plat/wakeup-mask.h>
+
+#include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
+
+static struct sleep_save s5p64x0_core_save[] = {
+ SAVE_ITEM(S5P64X0_APLL_CON),
+ SAVE_ITEM(S5P64X0_MPLL_CON),
+ SAVE_ITEM(S5P64X0_EPLL_CON),
+ SAVE_ITEM(S5P64X0_EPLL_CON_K),
+ SAVE_ITEM(S5P64X0_CLK_SRC0),
+ SAVE_ITEM(S5P64X0_CLK_SRC1),
+ SAVE_ITEM(S5P64X0_CLK_DIV0),
+ SAVE_ITEM(S5P64X0_CLK_DIV1),
+ SAVE_ITEM(S5P64X0_CLK_DIV2),
+ SAVE_ITEM(S5P64X0_CLK_DIV3),
+ SAVE_ITEM(S5P64X0_CLK_GATE_MEM0),
+ SAVE_ITEM(S5P64X0_CLK_GATE_HCLK1),
+ SAVE_ITEM(S5P64X0_CLK_GATE_SCLK1),
+};
+
+static struct sleep_save s5p64x0_misc_save[] = {
+ SAVE_ITEM(S5P64X0_AHB_CON0),
+ SAVE_ITEM(S5P64X0_SPCON0),
+ SAVE_ITEM(S5P64X0_SPCON1),
+ SAVE_ITEM(S5P64X0_MEM0CONSLP0),
+ SAVE_ITEM(S5P64X0_MEM0CONSLP1),
+ SAVE_ITEM(S5P64X0_MEM0DRVCON),
+ SAVE_ITEM(S5P64X0_MEM1DRVCON),
+
+ SAVE_ITEM(S3C64XX_TINT_CSTAT),
+};
+
+/* DPLL is present only in S5P6450 */
+static struct sleep_save s5p6450_core_save[] = {
+ SAVE_ITEM(S5P6450_DPLL_CON),
+ SAVE_ITEM(S5P6450_DPLL_CON_K),
+};
+
+void s3c_pm_configure_extint(void)
+{
+ __raw_writel(s3c_irqwake_eintmask, S5P64X0_EINT_WAKEUP_MASK);
+}
+
+void s3c_pm_restore_core(void)
+{
+ __raw_writel(0, S5P64X0_EINT_WAKEUP_MASK);
+
+ s3c_pm_do_restore_core(s5p64x0_core_save,
+ ARRAY_SIZE(s5p64x0_core_save));
+
+ if ((__raw_readl(S5P64X0_SYS_ID) & 0xFF000) == 0x50000)
+ s3c_pm_do_restore_core(s5p6450_core_save,
+ ARRAY_SIZE(s5p6450_core_save));
+
+ s3c_pm_do_restore(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save));
+}
+
+void s3c_pm_save_core(void)
+{
+ s3c_pm_do_save(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save));
+
+ if ((__raw_readl(S5P64X0_SYS_ID) & 0xFF000) == 0x50000)
+ s3c_pm_do_save(s5p6450_core_save,
+ ARRAY_SIZE(s5p6450_core_save));
+
+ s3c_pm_do_save(s5p64x0_core_save, ARRAY_SIZE(s5p64x0_core_save));
+}
+
+static int s5p64x0_cpu_suspend(unsigned long arg)
+{
+ unsigned long tmp = 0;
+
+ /*
+ * Issue the standby signal into the pm unit. Note, we
+ * issue a write-buffer drain just in case.
+ */
+ asm("b 1f\n\t"
+ ".align 5\n\t"
+ "1:\n\t"
+ "mcr p15, 0, %0, c7, c10, 5\n\t"
+ "mcr p15, 0, %0, c7, c10, 4\n\t"
+ "mcr p15, 0, %0, c7, c0, 4" : : "r" (tmp));
+
+ /* we should never get past here */
+ panic("sleep resumed to originator?");
+}
+
+/* mapping of interrupts to parts of the wakeup mask */
+static struct samsung_wakeup_mask s5p64x0_wake_irqs[] = {
+ { .irq = IRQ_RTC_ALARM, .bit = S5P64X0_PWRCFG_RTC_ALRM_DISABLE, },
+ { .irq = IRQ_RTC_TIC, .bit = S5P64X0_PWRCFG_RTC_TICK_DISABLE, },
+ { .irq = IRQ_HSMMC0, .bit = S5P64X0_PWRCFG_MMC0_DISABLE, },
+ { .irq = IRQ_HSMMC1, .bit = S5P64X0_PWRCFG_MMC1_DISABLE, },
+};
+
+static void s5p64x0_pm_prepare(void)
+{
+ u32 tmp;
+
+ samsung_sync_wakemask(S5P64X0_PWR_CFG,
+ s5p64x0_wake_irqs, ARRAY_SIZE(s5p64x0_wake_irqs));
+
+ /* store the resume address in INFORM0 register */
+ __raw_writel(virt_to_phys(s3c_cpu_resume), S5P64X0_INFORM0);
+
+ /* setup clock gating for FIMGVG block */
+ __raw_writel((__raw_readl(S5P64X0_CLK_GATE_HCLK1) | \
+ (S5P64X0_CLKCON_HCLK1_FIMGVG)), S5P64X0_CLK_GATE_HCLK1);
+ __raw_writel((__raw_readl(S5P64X0_CLK_GATE_SCLK1) | \
+ (S5P64X0_CLKCON_SCLK1_FIMGVG)), S5P64X0_CLK_GATE_SCLK1);
+
+ /* Configure the stabilization counter with wait time required */
+ __raw_writel(S5P64X0_PWR_STABLE_CNT_VAL_4, S5P64X0_PWR_STABLE);
+
+ /* set WFI to SLEEP mode configuration */
+ tmp = __raw_readl(S5P64X0_SLEEP_CFG);
+ tmp &= ~(S5P64X0_SLEEP_CFG_OSC_EN);
+ __raw_writel(tmp, S5P64X0_SLEEP_CFG);
+
+ tmp = __raw_readl(S5P64X0_PWR_CFG);
+ tmp &= ~(S5P64X0_PWRCFG_CFG_WFI_MASK);
+ tmp |= S5P64X0_PWRCFG_CFG_WFI_SLEEP;
+ __raw_writel(tmp, S5P64X0_PWR_CFG);
+
+ /*
+ * set OTHERS register to disable interrupt before going to
+ * sleep. This bit is present only in S5P6450, it is reserved
+ * in S5P6440.
+ */
+ if ((__raw_readl(S5P64X0_SYS_ID) & 0xFF000) == 0x50000) {
+ tmp = __raw_readl(S5P64X0_OTHERS);
+ tmp |= S5P6450_OTHERS_DISABLE_INT;
+ __raw_writel(tmp, S5P64X0_OTHERS);
+ }
+
+ /* ensure previous wakeup state is cleared before sleeping */
+ __raw_writel(__raw_readl(S5P64X0_WAKEUP_STAT), S5P64X0_WAKEUP_STAT);
+
+}
+
+static int s5p64x0_pm_add(struct sys_device *sysdev)
+{
+ pm_cpu_prep = s5p64x0_pm_prepare;
+ pm_cpu_sleep = s5p64x0_cpu_suspend;
+ pm_uart_udivslot = 1;
+
+ return 0;
+}
+
+static struct sysdev_driver s5p64x0_pm_driver = {
+ .add = s5p64x0_pm_add,
+};
+
+static __init int s5p64x0_pm_drvinit(void)
+{
+ s3c_pm_init();
+
+ return sysdev_driver_register(&s5p64x0_sysclass, &s5p64x0_pm_driver);
+}
+arch_initcall(s5p64x0_pm_drvinit);
+
+static void s5p64x0_pm_resume(void)
+{
+ u32 tmp;
+
+ tmp = __raw_readl(S5P64X0_OTHERS);
+ tmp |= (S5P64X0_OTHERS_RET_MMC0 | S5P64X0_OTHERS_RET_MMC1 | \
+ S5P64X0_OTHERS_RET_UART);
+ __raw_writel(tmp , S5P64X0_OTHERS);
+}
+
+static struct syscore_ops s5p64x0_pm_syscore_ops = {
+ .resume = s5p64x0_pm_resume,
+};
+
+static __init int s5p64x0_pm_syscore_init(void)
+{
+ register_syscore_ops(&s5p64x0_pm_syscore_ops);
+
+ return 0;
+}
+arch_initcall(s5p64x0_pm_syscore_init);
--
1.7.4.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH 5/5] ARM: S5P64X0: Add Power Management support
@ 2011-08-12 10:26 ` Abhilash Kesavan
0 siblings, 0 replies; 40+ messages in thread
From: Abhilash Kesavan @ 2011-08-12 10:26 UTC (permalink / raw)
To: linux-arm-kernel
Add suspend-to-ram support for SMDK6440/50
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
arch/arm/Kconfig | 2 +-
arch/arm/mach-s5p64x0/Kconfig | 4 +
arch/arm/mach-s5p64x0/Makefile | 1 +
arch/arm/mach-s5p64x0/include/mach/map.h | 1 +
arch/arm/mach-s5p64x0/include/mach/pm-core.h | 117 +++++++++++++
arch/arm/mach-s5p64x0/include/mach/regs-clock.h | 33 ++++
arch/arm/mach-s5p64x0/include/mach/regs-gpio.h | 19 ++
arch/arm/mach-s5p64x0/irq-eint.c | 2 +
arch/arm/mach-s5p64x0/irq-pm.c | 92 ++++++++++
arch/arm/mach-s5p64x0/pm.c | 204 +++++++++++++++++++++++
10 files changed, 474 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-s5p64x0/include/mach/pm-core.h
create mode 100644 arch/arm/mach-s5p64x0/irq-pm.c
create mode 100644 arch/arm/mach-s5p64x0/pm.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2c71a8f..47aed0d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -2071,7 +2071,7 @@ menu "Power management options"
source "kernel/power/Kconfig"
config ARCH_SUSPEND_POSSIBLE
- depends on !ARCH_S5P64X0 && !ARCH_S5PC100
+ depends on !ARCH_S5PC100
depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
def_bool y
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index 65c7518..d7f034a 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -11,6 +11,8 @@ config CPU_S5P6440
bool
select S3C_PL330_DMA
select S5P_HRT
+ select SAMSUNG_SLEEP if PM
+ select SAMSUNG_WAKEMASK if PM
help
Enable S5P6440 CPU support
@@ -18,6 +20,8 @@ config CPU_S5P6450
bool
select S3C_PL330_DMA
select S5P_HRT
+ select SAMSUNG_SLEEP if PM
+ select SAMSUNG_WAKEMASK if PM
help
Enable S5P6450 CPU support
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
index 5f6afdf..acfebb7 100644
--- a/arch/arm/mach-s5p64x0/Makefile
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o gpiolib.o
obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o irq-eint.o
obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o
obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o
+obj-$(CONFIG_PM) += pm.o irq-pm.o
# machine support
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
index 95c9125..6138f7c 100644
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -85,5 +85,6 @@
#define S5P_PA_UART5 S5P6450_PA_UART(5)
#define S5P_SZ_UART SZ_256
+#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/pm-core.h b/arch/arm/mach-s5p64x0/include/mach/pm-core.h
new file mode 100644
index 0000000..aee9d85
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/pm-core.h
@@ -0,0 +1,117 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/pm-core.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * S5P64X0 - PM core support for arch/arm/plat-samsung/pm.c
+ *
+ * Based on PM core support for S3C64XX by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <mach/regs-gpio.h>
+
+static inline void s3c_pm_debug_init_uart(void)
+{
+ u32 tmp = __raw_readl(S5P64X0_CLK_GATE_PCLK);
+
+ /*
+ * As a note, since the S5P64X0 UARTs generally have multiple
+ * clock sources, we simply enable PCLK at the moment and hope
+ * that the resume settings for the UART are suitable for the
+ * use with PCLK.
+ */
+ tmp |= S5P64X0_CLKCON_PCLK_UART0;
+ tmp |= S5P64X0_CLKCON_PCLK_UART1;
+ tmp |= S5P64X0_CLKCON_PCLK_UART2;
+ tmp |= S5P64X0_CLKCON_PCLK_UART3;
+
+ __raw_writel(tmp, S5P64X0_CLK_GATE_PCLK);
+ udelay(10);
+}
+
+static inline void s3c_pm_arch_prepare_irqs(void)
+{
+ /* VIC should have already been taken care of */
+
+ /* clear any pending EINT0 interrupts */
+ __raw_writel(__raw_readl(S5P64X0_EINT0PEND), S5P64X0_EINT0PEND);
+}
+
+static inline void s3c_pm_arch_stop_clocks(void) { }
+static inline void s3c_pm_arch_show_resume_irqs(void) { }
+
+/*
+ * make these defines, we currently do not have any need to change
+ * the IRQ wake controls depending on the CPU we are running on
+ */
+#define s3c_irqwake_eintallow ((1 << 16) - 1)
+#define s3c_irqwake_intallow (~0)
+
+static inline void s3c_pm_arch_update_uart(void __iomem *regs,
+ struct pm_uart_save *save)
+{
+ u32 ucon = __raw_readl(regs + S3C2410_UCON);
+ u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
+ u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
+ u32 new_ucon;
+ u32 delta;
+
+ /*
+ * S5P64X0 UART blocks only support level interrupts, so ensure that
+ * when we restore unused UART blocks we force the level interrupt
+ * settings.
+ */
+ save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
+
+ /*
+ * We have a constraint on changing the clock type of the UART
+ * between UCLKx and PCLK, so ensure that when we restore UCON
+ * that the CLK field is correctly modified if the bootloader
+ * has changed anything.
+ */
+ if (ucon_clk != save_clk) {
+ new_ucon = save->ucon;
+ delta = ucon_clk ^ save_clk;
+
+ /*
+ * change from UCLKx => wrong PCLK,
+ * either UCLK can be tested for by a bit-test
+ * with UCLK0
+ */
+ if (ucon_clk & S3C6400_UCON_UCLK0 &&
+ !(save_clk & S3C6400_UCON_UCLK0) &&
+ delta & S3C6400_UCON_PCLK2) {
+ new_ucon &= ~S3C6400_UCON_UCLK0;
+ } else if (delta == S3C6400_UCON_PCLK2) {
+ /*
+ * as a precaution, don't change from
+ * PCLK2 => PCLK or vice-versa
+ */
+ new_ucon ^= S3C6400_UCON_PCLK2;
+ }
+
+ S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
+ ucon, new_ucon, save->ucon);
+ save->ucon = new_ucon;
+ }
+}
+
+static inline void s3c_pm_restored_gpios(void)
+{
+ /* ensure sleep mode has been cleared from the system */
+ __raw_writel(0, S5P64X0_SLPEN);
+}
+
+static inline void s3c_pm_saved_gpios(void)
+{
+ /*
+ * turn on the sleep mode and keep it there, as it seems that during
+ * suspend the xCON registers get re-set and thus you can end up with
+ * problems between going to sleep and resuming.
+ */
+ __raw_writel(S5P64X0_SLPEN_USE_xSLP, S5P64X0_SLPEN);
+}
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
index a133f22..75f66a9 100644
--- a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
@@ -41,17 +41,50 @@
#define S5P6450_DPLL_CON S5P_CLKREG(0x50)
#define S5P6450_DPLL_CON_K S5P_CLKREG(0x54)
+#define S5P64X0_AHB_CON0 S5P_CLKREG(0x100)
#define S5P64X0_CLK_SRC1 S5P_CLKREG(0x10C)
#define S5P64X0_SYS_ID S5P_CLKREG(0x118)
#define S5P64X0_SYS_OTHERS S5P_CLKREG(0x11C)
#define S5P64X0_PWR_CFG S5P_CLKREG(0x804)
+#define S5P64X0_EINT_WAKEUP_MASK S5P_CLKREG(0x808)
+#define S5P64X0_SLEEP_CFG S5P_CLKREG(0x818)
+#define S5P64X0_PWR_STABLE S5P_CLKREG(0x828)
+
#define S5P64X0_OTHERS S5P_CLKREG(0x900)
+#define S5P64X0_WAKEUP_STAT S5P_CLKREG(0x908)
+
+#define S5P64X0_INFORM0 S5P_CLKREG(0xA00)
#define S5P64X0_CLKDIV0_HCLK_SHIFT (8)
#define S5P64X0_CLKDIV0_HCLK_MASK (0xF << S5P64X0_CLKDIV0_HCLK_SHIFT)
+/* HCLK GATE Registers */
+#define S5P64X0_CLKCON_HCLK1_FIMGVG (1<<2)
+#define S5P64X0_CLKCON_SCLK1_FIMGVG (1<<2)
+
+/* PCLK GATE Registers */
+#define S5P64X0_CLKCON_PCLK_UART3 (1<<4)
+#define S5P64X0_CLKCON_PCLK_UART2 (1<<3)
+#define S5P64X0_CLKCON_PCLK_UART1 (1<<2)
+#define S5P64X0_CLKCON_PCLK_UART0 (1<<1)
+
+#define S5P64X0_PWRCFG_MMC1_DISABLE (1 << 15)
+#define S5P64X0_PWRCFG_MMC0_DISABLE (1 << 14)
+#define S5P64X0_PWRCFG_RTC_TICK_DISABLE (1 << 11)
+#define S5P64X0_PWRCFG_RTC_ALRM_DISABLE (1 << 10)
+#define S5P64X0_PWRCFG_CFG_WFI_MASK (3 << 5)
+#define S5P64X0_PWRCFG_CFG_WFI_SLEEP (3 << 5)
+
+#define S5P64X0_SLEEP_CFG_OSC_EN (1 << 0)
+
+#define S5P64X0_PWR_STABLE_CNT_VAL_4 (4 << 0)
+
+#define S5P6450_OTHERS_DISABLE_INT (1 << 31)
+#define S5P64X0_OTHERS_RET_UART (1 << 26)
+#define S5P64X0_OTHERS_RET_MMC1 (1 << 25)
+#define S5P64X0_OTHERS_RET_MMC0 (1 << 24)
#define S5P64X0_OTHERS_USB_SIG_MASK (1 << 16)
/* Compatibility defines */
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
index 6ce2547..27a2230 100644
--- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
@@ -34,14 +34,33 @@
#define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180)
#define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300)
+#define S5P64X0_SPCON0 (S5P_VA_GPIO + 0x1A0)
+#define S5P64X0_SPCON1 (S5P_VA_GPIO + 0x2B0)
+
+#define S5P64X0_MEM0CONSLP0 (S5P_VA_GPIO + 0x1C0)
+#define S5P64X0_MEM0CONSLP1 (S5P_VA_GPIO + 0x1C4)
+#define S5P64X0_MEM0DRVCON (S5P_VA_GPIO + 0x1D0)
+#define S5P64X0_MEM1DRVCON (S5P_VA_GPIO + 0x1D4)
+
+#define S5P64X0_EINT12CON (S5P_VA_GPIO + 0x200)
+#define S5P64X0_EINT12FLTCON (S5P_VA_GPIO + 0x220)
+#define S5P64X0_EINT12MASK (S5P_VA_GPIO + 0x240)
+
/* External interrupt control registers for group0 */
#define EINT0CON0_OFFSET (0x900)
+#define EINT0FLTCON0_OFFSET (0x910)
+#define EINT0FLTCON1_OFFSET (0x914)
#define EINT0MASK_OFFSET (0x920)
#define EINT0PEND_OFFSET (0x924)
#define S5P64X0_EINT0CON0 (S5P_VA_GPIO + EINT0CON0_OFFSET)
+#define S5P64X0_EINT0FLTCON0 (S5P_VA_GPIO + EINT0FLTCON0_OFFSET)
+#define S5P64X0_EINT0FLTCON1 (S5P_VA_GPIO + EINT0FLTCON1_OFFSET)
#define S5P64X0_EINT0MASK (S5P_VA_GPIO + EINT0MASK_OFFSET)
#define S5P64X0_EINT0PEND (S5P_VA_GPIO + EINT0PEND_OFFSET)
+#define S5P64X0_SLPEN (S5P_VA_GPIO + 0x930)
+#define S5P64X0_SLPEN_USE_xSLP (1 << 0)
+
#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5p64x0/irq-eint.c b/arch/arm/mach-s5p64x0/irq-eint.c
index fe7380f..3b94c6c 100644
--- a/arch/arm/mach-s5p64x0/irq-eint.c
+++ b/arch/arm/mach-s5p64x0/irq-eint.c
@@ -19,6 +19,7 @@
#include <plat/regs-irqtype.h>
#include <plat/gpio-cfg.h>
+#include <plat/pm.h>
#include <mach/regs-gpio.h>
#include <mach/regs-clock.h>
@@ -133,6 +134,7 @@ static int s5p64x0_alloc_gc(void)
ct->chip.irq_mask = irq_gc_mask_set_bit;
ct->chip.irq_unmask = irq_gc_mask_clr_bit;
ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
+ ct->chip.irq_set_wake = s3c_irqext_wake;
ct->regs.ack = EINT0PEND_OFFSET;
ct->regs.mask = EINT0MASK_OFFSET;
irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
diff --git a/arch/arm/mach-s5p64x0/irq-pm.c b/arch/arm/mach-s5p64x0/irq-pm.c
new file mode 100644
index 0000000..3e6f245
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/irq-pm.c
@@ -0,0 +1,92 @@
+/* linux/arch/arm/mach-s5p64x0/irq-pm.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * S5P64X0 - Interrupt handling Power Management
+ *
+ * Based on arch/arm/mach-s3c64xx/irq-pm.c by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/syscore_ops.h>
+#include <linux/serial_core.h>
+#include <linux/io.h>
+
+#include <plat/regs-serial.h>
+#include <plat/pm.h>
+
+#include <mach/regs-gpio.h>
+
+static struct sleep_save irq_save[] = {
+ SAVE_ITEM(S5P64X0_EINT0CON0),
+ SAVE_ITEM(S5P64X0_EINT0FLTCON0),
+ SAVE_ITEM(S5P64X0_EINT0FLTCON1),
+ SAVE_ITEM(S5P64X0_EINT0MASK),
+};
+
+static struct irq_grp_save {
+ u32 con;
+ u32 fltcon;
+ u32 mask;
+} eint_grp_save[4];
+
+static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS];
+
+static int s5p64x0_irq_pm_suspend(void)
+{
+ struct irq_grp_save *grp = eint_grp_save;
+ int i;
+
+ S3C_PMDBG("%s: suspending IRQs\n", __func__);
+
+ s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
+
+ for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
+ irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM);
+
+ for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
+ grp->con = __raw_readl(S5P64X0_EINT12CON + (i * 4));
+ grp->mask = __raw_readl(S5P64X0_EINT12MASK + (i * 4));
+ grp->fltcon = __raw_readl(S5P64X0_EINT12FLTCON + (i * 4));
+ }
+
+ return 0;
+}
+
+static void s5p64x0_irq_pm_resume(void)
+{
+ struct irq_grp_save *grp = eint_grp_save;
+ int i;
+
+ S3C_PMDBG("%s: resuming IRQs\n", __func__);
+
+ s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
+
+ for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
+ __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM);
+
+ for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
+ __raw_writel(grp->con, S5P64X0_EINT12CON + (i * 4));
+ __raw_writel(grp->mask, S5P64X0_EINT12MASK + (i * 4));
+ __raw_writel(grp->fltcon, S5P64X0_EINT12FLTCON + (i * 4));
+ }
+
+ S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
+}
+
+static struct syscore_ops s5p64x0_irq_syscore_ops = {
+ .suspend = s5p64x0_irq_pm_suspend,
+ .resume = s5p64x0_irq_pm_resume,
+};
+
+static int __init s5p64x0_syscore_init(void)
+{
+ register_syscore_ops(&s5p64x0_irq_syscore_ops);
+
+ return 0;
+}
+core_initcall(s5p64x0_syscore_init);
diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c
new file mode 100644
index 0000000..cced4fb
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/pm.c
@@ -0,0 +1,204 @@
+/* linux/arch/arm/mach-s5p64x0/pm.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * S5P64X0 Power Management Support
+ *
+ * Based on arch/arm/mach-s3c64xx/pm.c by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/suspend.h>
+#include <linux/syscore_ops.h>
+#include <linux/io.h>
+
+#include <plat/cpu.h>
+#include <plat/pm.h>
+#include <plat/regs-timer.h>
+#include <plat/wakeup-mask.h>
+
+#include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
+
+static struct sleep_save s5p64x0_core_save[] = {
+ SAVE_ITEM(S5P64X0_APLL_CON),
+ SAVE_ITEM(S5P64X0_MPLL_CON),
+ SAVE_ITEM(S5P64X0_EPLL_CON),
+ SAVE_ITEM(S5P64X0_EPLL_CON_K),
+ SAVE_ITEM(S5P64X0_CLK_SRC0),
+ SAVE_ITEM(S5P64X0_CLK_SRC1),
+ SAVE_ITEM(S5P64X0_CLK_DIV0),
+ SAVE_ITEM(S5P64X0_CLK_DIV1),
+ SAVE_ITEM(S5P64X0_CLK_DIV2),
+ SAVE_ITEM(S5P64X0_CLK_DIV3),
+ SAVE_ITEM(S5P64X0_CLK_GATE_MEM0),
+ SAVE_ITEM(S5P64X0_CLK_GATE_HCLK1),
+ SAVE_ITEM(S5P64X0_CLK_GATE_SCLK1),
+};
+
+static struct sleep_save s5p64x0_misc_save[] = {
+ SAVE_ITEM(S5P64X0_AHB_CON0),
+ SAVE_ITEM(S5P64X0_SPCON0),
+ SAVE_ITEM(S5P64X0_SPCON1),
+ SAVE_ITEM(S5P64X0_MEM0CONSLP0),
+ SAVE_ITEM(S5P64X0_MEM0CONSLP1),
+ SAVE_ITEM(S5P64X0_MEM0DRVCON),
+ SAVE_ITEM(S5P64X0_MEM1DRVCON),
+
+ SAVE_ITEM(S3C64XX_TINT_CSTAT),
+};
+
+/* DPLL is present only in S5P6450 */
+static struct sleep_save s5p6450_core_save[] = {
+ SAVE_ITEM(S5P6450_DPLL_CON),
+ SAVE_ITEM(S5P6450_DPLL_CON_K),
+};
+
+void s3c_pm_configure_extint(void)
+{
+ __raw_writel(s3c_irqwake_eintmask, S5P64X0_EINT_WAKEUP_MASK);
+}
+
+void s3c_pm_restore_core(void)
+{
+ __raw_writel(0, S5P64X0_EINT_WAKEUP_MASK);
+
+ s3c_pm_do_restore_core(s5p64x0_core_save,
+ ARRAY_SIZE(s5p64x0_core_save));
+
+ if ((__raw_readl(S5P64X0_SYS_ID) & 0xFF000) == 0x50000)
+ s3c_pm_do_restore_core(s5p6450_core_save,
+ ARRAY_SIZE(s5p6450_core_save));
+
+ s3c_pm_do_restore(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save));
+}
+
+void s3c_pm_save_core(void)
+{
+ s3c_pm_do_save(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save));
+
+ if ((__raw_readl(S5P64X0_SYS_ID) & 0xFF000) == 0x50000)
+ s3c_pm_do_save(s5p6450_core_save,
+ ARRAY_SIZE(s5p6450_core_save));
+
+ s3c_pm_do_save(s5p64x0_core_save, ARRAY_SIZE(s5p64x0_core_save));
+}
+
+static int s5p64x0_cpu_suspend(unsigned long arg)
+{
+ unsigned long tmp = 0;
+
+ /*
+ * Issue the standby signal into the pm unit. Note, we
+ * issue a write-buffer drain just in case.
+ */
+ asm("b 1f\n\t"
+ ".align 5\n\t"
+ "1:\n\t"
+ "mcr p15, 0, %0, c7, c10, 5\n\t"
+ "mcr p15, 0, %0, c7, c10, 4\n\t"
+ "mcr p15, 0, %0, c7, c0, 4" : : "r" (tmp));
+
+ /* we should never get past here */
+ panic("sleep resumed to originator?");
+}
+
+/* mapping of interrupts to parts of the wakeup mask */
+static struct samsung_wakeup_mask s5p64x0_wake_irqs[] = {
+ { .irq = IRQ_RTC_ALARM, .bit = S5P64X0_PWRCFG_RTC_ALRM_DISABLE, },
+ { .irq = IRQ_RTC_TIC, .bit = S5P64X0_PWRCFG_RTC_TICK_DISABLE, },
+ { .irq = IRQ_HSMMC0, .bit = S5P64X0_PWRCFG_MMC0_DISABLE, },
+ { .irq = IRQ_HSMMC1, .bit = S5P64X0_PWRCFG_MMC1_DISABLE, },
+};
+
+static void s5p64x0_pm_prepare(void)
+{
+ u32 tmp;
+
+ samsung_sync_wakemask(S5P64X0_PWR_CFG,
+ s5p64x0_wake_irqs, ARRAY_SIZE(s5p64x0_wake_irqs));
+
+ /* store the resume address in INFORM0 register */
+ __raw_writel(virt_to_phys(s3c_cpu_resume), S5P64X0_INFORM0);
+
+ /* setup clock gating for FIMGVG block */
+ __raw_writel((__raw_readl(S5P64X0_CLK_GATE_HCLK1) | \
+ (S5P64X0_CLKCON_HCLK1_FIMGVG)), S5P64X0_CLK_GATE_HCLK1);
+ __raw_writel((__raw_readl(S5P64X0_CLK_GATE_SCLK1) | \
+ (S5P64X0_CLKCON_SCLK1_FIMGVG)), S5P64X0_CLK_GATE_SCLK1);
+
+ /* Configure the stabilization counter with wait time required */
+ __raw_writel(S5P64X0_PWR_STABLE_CNT_VAL_4, S5P64X0_PWR_STABLE);
+
+ /* set WFI to SLEEP mode configuration */
+ tmp = __raw_readl(S5P64X0_SLEEP_CFG);
+ tmp &= ~(S5P64X0_SLEEP_CFG_OSC_EN);
+ __raw_writel(tmp, S5P64X0_SLEEP_CFG);
+
+ tmp = __raw_readl(S5P64X0_PWR_CFG);
+ tmp &= ~(S5P64X0_PWRCFG_CFG_WFI_MASK);
+ tmp |= S5P64X0_PWRCFG_CFG_WFI_SLEEP;
+ __raw_writel(tmp, S5P64X0_PWR_CFG);
+
+ /*
+ * set OTHERS register to disable interrupt before going to
+ * sleep. This bit is present only in S5P6450, it is reserved
+ * in S5P6440.
+ */
+ if ((__raw_readl(S5P64X0_SYS_ID) & 0xFF000) == 0x50000) {
+ tmp = __raw_readl(S5P64X0_OTHERS);
+ tmp |= S5P6450_OTHERS_DISABLE_INT;
+ __raw_writel(tmp, S5P64X0_OTHERS);
+ }
+
+ /* ensure previous wakeup state is cleared before sleeping */
+ __raw_writel(__raw_readl(S5P64X0_WAKEUP_STAT), S5P64X0_WAKEUP_STAT);
+
+}
+
+static int s5p64x0_pm_add(struct sys_device *sysdev)
+{
+ pm_cpu_prep = s5p64x0_pm_prepare;
+ pm_cpu_sleep = s5p64x0_cpu_suspend;
+ pm_uart_udivslot = 1;
+
+ return 0;
+}
+
+static struct sysdev_driver s5p64x0_pm_driver = {
+ .add = s5p64x0_pm_add,
+};
+
+static __init int s5p64x0_pm_drvinit(void)
+{
+ s3c_pm_init();
+
+ return sysdev_driver_register(&s5p64x0_sysclass, &s5p64x0_pm_driver);
+}
+arch_initcall(s5p64x0_pm_drvinit);
+
+static void s5p64x0_pm_resume(void)
+{
+ u32 tmp;
+
+ tmp = __raw_readl(S5P64X0_OTHERS);
+ tmp |= (S5P64X0_OTHERS_RET_MMC0 | S5P64X0_OTHERS_RET_MMC1 | \
+ S5P64X0_OTHERS_RET_UART);
+ __raw_writel(tmp , S5P64X0_OTHERS);
+}
+
+static struct syscore_ops s5p64x0_pm_syscore_ops = {
+ .resume = s5p64x0_pm_resume,
+};
+
+static __init int s5p64x0_pm_syscore_init(void)
+{
+ register_syscore_ops(&s5p64x0_pm_syscore_ops);
+
+ return 0;
+}
+arch_initcall(s5p64x0_pm_syscore_init);
--
1.7.4.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* RE: [PATCH 5/5] ARM: S5P64X0: Add Power Management support
2011-08-12 10:26 ` Abhilash Kesavan
@ 2011-09-07 6:01 ` Kukjin Kim
-1 siblings, 0 replies; 40+ messages in thread
From: Kukjin Kim @ 2011-09-07 6:01 UTC (permalink / raw)
To: 'Abhilash Kesavan', linux-arm-kernel, linux-samsung-soc
Abhilash Kesavan wrote:
>
> Add suspend-to-ram support for SMDK6440/50
>
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
> arch/arm/Kconfig | 2 +-
> arch/arm/mach-s5p64x0/Kconfig | 4 +
> arch/arm/mach-s5p64x0/Makefile | 1 +
> arch/arm/mach-s5p64x0/include/mach/map.h | 1 +
> arch/arm/mach-s5p64x0/include/mach/pm-core.h | 117 +++++++++++++
> arch/arm/mach-s5p64x0/include/mach/regs-clock.h | 33 ++++
> arch/arm/mach-s5p64x0/include/mach/regs-gpio.h | 19 ++
> arch/arm/mach-s5p64x0/irq-eint.c | 2 +
> arch/arm/mach-s5p64x0/irq-pm.c | 92 ++++++++++
> arch/arm/mach-s5p64x0/pm.c | 204
> +++++++++++++++++++++++
> 10 files changed, 474 insertions(+), 1 deletions(-)
> create mode 100644 arch/arm/mach-s5p64x0/include/mach/pm-core.h
> create mode 100644 arch/arm/mach-s5p64x0/irq-pm.c
> create mode 100644 arch/arm/mach-s5p64x0/pm.c
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 2c71a8f..47aed0d 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -2071,7 +2071,7 @@ menu "Power management options"
> source "kernel/power/Kconfig"
>
> config ARCH_SUSPEND_POSSIBLE
> - depends on !ARCH_S5P64X0 && !ARCH_S5PC100
> + depends on !ARCH_S5PC100
> depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
> CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
> def_bool y
> diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
> index 65c7518..d7f034a 100644
> --- a/arch/arm/mach-s5p64x0/Kconfig
> +++ b/arch/arm/mach-s5p64x0/Kconfig
> @@ -11,6 +11,8 @@ config CPU_S5P6440
> bool
> select S3C_PL330_DMA
> select S5P_HRT
> + select SAMSUNG_SLEEP if PM
> + select SAMSUNG_WAKEMASK if PM
> help
> Enable S5P6440 CPU support
>
> @@ -18,6 +20,8 @@ config CPU_S5P6450
> bool
> select S3C_PL330_DMA
> select S5P_HRT
> + select SAMSUNG_SLEEP if PM
> + select SAMSUNG_WAKEMASK if PM
> help
> Enable S5P6450 CPU support
>
> diff --git a/arch/arm/mach-s5p64x0/Makefile
b/arch/arm/mach-s5p64x0/Makefile
> index 5f6afdf..acfebb7 100644
> --- a/arch/arm/mach-s5p64x0/Makefile
> +++ b/arch/arm/mach-s5p64x0/Makefile
> @@ -16,6 +16,7 @@ obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o
> clock.o dma.o gpiolib.o
> obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o irq-eint.o
> obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o
> obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o
> +obj-$(CONFIG_PM) += pm.o irq-pm.o
>
> # machine support
>
> diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-
> s5p64x0/include/mach/map.h
> index 95c9125..6138f7c 100644
> --- a/arch/arm/mach-s5p64x0/include/mach/map.h
> +++ b/arch/arm/mach-s5p64x0/include/mach/map.h
> @@ -85,5 +85,6 @@
> #define S5P_PA_UART5 S5P6450_PA_UART(5)
>
> #define S5P_SZ_UART SZ_256
> +#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) *
> S3C_UART_OFFSET))
>
> #endif /* __ASM_ARCH_MAP_H */
> diff --git a/arch/arm/mach-s5p64x0/include/mach/pm-core.h b/arch/arm/mach-
> s5p64x0/include/mach/pm-core.h
> new file mode 100644
> index 0000000..aee9d85
> --- /dev/null
> +++ b/arch/arm/mach-s5p64x0/include/mach/pm-core.h
> @@ -0,0 +1,117 @@
> +/* linux/arch/arm/mach-s5p64x0/include/mach/pm-core.h
> + *
> + * Copyright (c) 2011 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com
> + *
> + * S5P64X0 - PM core support for arch/arm/plat-samsung/pm.c
> + *
> + * Based on PM core support for S3C64XX by Ben Dooks
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <mach/regs-gpio.h>
> +
> +static inline void s3c_pm_debug_init_uart(void)
> +{
> + u32 tmp = __raw_readl(S5P64X0_CLK_GATE_PCLK);
> +
> + /*
> + * As a note, since the S5P64X0 UARTs generally have multiple
> + * clock sources, we simply enable PCLK at the moment and hope
> + * that the resume settings for the UART are suitable for the
> + * use with PCLK.
> + */
> + tmp |= S5P64X0_CLKCON_PCLK_UART0;
> + tmp |= S5P64X0_CLKCON_PCLK_UART1;
> + tmp |= S5P64X0_CLKCON_PCLK_UART2;
> + tmp |= S5P64X0_CLKCON_PCLK_UART3;
> +
> + __raw_writel(tmp, S5P64X0_CLK_GATE_PCLK);
> + udelay(10);
> +}
> +
> +static inline void s3c_pm_arch_prepare_irqs(void)
> +{
> + /* VIC should have already been taken care of */
> +
> + /* clear any pending EINT0 interrupts */
> + __raw_writel(__raw_readl(S5P64X0_EINT0PEND), S5P64X0_EINT0PEND);
> +}
> +
> +static inline void s3c_pm_arch_stop_clocks(void) { }
> +static inline void s3c_pm_arch_show_resume_irqs(void) { }
> +
> +/*
> + * make these defines, we currently do not have any need to change
> + * the IRQ wake controls depending on the CPU we are running on
> + */
> +#define s3c_irqwake_eintallow ((1 << 16) - 1)
> +#define s3c_irqwake_intallow (~0)
> +
> +static inline void s3c_pm_arch_update_uart(void __iomem *regs,
> + struct pm_uart_save *save)
> +{
> + u32 ucon = __raw_readl(regs + S3C2410_UCON);
> + u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
> + u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
> + u32 new_ucon;
> + u32 delta;
> +
> + /*
> + * S5P64X0 UART blocks only support level interrupts, so ensure that
> + * when we restore unused UART blocks we force the level interrupt
> + * settings.
> + */
> + save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
> +
> + /*
> + * We have a constraint on changing the clock type of the UART
> + * between UCLKx and PCLK, so ensure that when we restore UCON
> + * that the CLK field is correctly modified if the bootloader
> + * has changed anything.
> + */
> + if (ucon_clk != save_clk) {
> + new_ucon = save->ucon;
> + delta = ucon_clk ^ save_clk;
> +
> + /*
> + * change from UCLKx => wrong PCLK,
> + * either UCLK can be tested for by a bit-test
> + * with UCLK0
> + */
> + if (ucon_clk & S3C6400_UCON_UCLK0 &&
> + !(save_clk & S3C6400_UCON_UCLK0) &&
> + delta & S3C6400_UCON_PCLK2) {
> + new_ucon &= ~S3C6400_UCON_UCLK0;
> + } else if (delta == S3C6400_UCON_PCLK2) {
> + /*
> + * as a precaution, don't change from
> + * PCLK2 => PCLK or vice-versa
> + */
> + new_ucon ^= S3C6400_UCON_PCLK2;
> + }
> +
> + S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
> + ucon, new_ucon, save->ucon);
> + save->ucon = new_ucon;
> + }
> +}
> +
> +static inline void s3c_pm_restored_gpios(void)
> +{
> + /* ensure sleep mode has been cleared from the system */
> + __raw_writel(0, S5P64X0_SLPEN);
> +}
> +
> +static inline void s3c_pm_saved_gpios(void)
> +{
> + /*
> + * turn on the sleep mode and keep it there, as it seems that during
> + * suspend the xCON registers get re-set and thus you can end up
with
> + * problems between going to sleep and resuming.
> + */
> + __raw_writel(S5P64X0_SLPEN_USE_xSLP, S5P64X0_SLPEN);
> +}
> diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
b/arch/arm/mach-
> s5p64x0/include/mach/regs-clock.h
> index a133f22..75f66a9 100644
> --- a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
> +++ b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
> @@ -41,17 +41,50 @@
> #define S5P6450_DPLL_CON S5P_CLKREG(0x50)
> #define S5P6450_DPLL_CON_K S5P_CLKREG(0x54)
>
> +#define S5P64X0_AHB_CON0 S5P_CLKREG(0x100)
> #define S5P64X0_CLK_SRC1 S5P_CLKREG(0x10C)
>
> #define S5P64X0_SYS_ID S5P_CLKREG(0x118)
> #define S5P64X0_SYS_OTHERS S5P_CLKREG(0x11C)
>
> #define S5P64X0_PWR_CFG S5P_CLKREG(0x804)
> +#define S5P64X0_EINT_WAKEUP_MASK S5P_CLKREG(0x808)
> +#define S5P64X0_SLEEP_CFG S5P_CLKREG(0x818)
> +#define S5P64X0_PWR_STABLE S5P_CLKREG(0x828)
> +
> #define S5P64X0_OTHERS S5P_CLKREG(0x900)
> +#define S5P64X0_WAKEUP_STAT S5P_CLKREG(0x908)
> +
> +#define S5P64X0_INFORM0 S5P_CLKREG(0xA00)
>
> #define S5P64X0_CLKDIV0_HCLK_SHIFT (8)
> #define S5P64X0_CLKDIV0_HCLK_MASK (0xF <<
> S5P64X0_CLKDIV0_HCLK_SHIFT)
>
> +/* HCLK GATE Registers */
> +#define S5P64X0_CLKCON_HCLK1_FIMGVG (1<<2)
Should be added blank around "<<" like (1 << 2).
And if possible, the name should be same with datasheet like
...CLK_GATE_HCLK1_FIMGVG.
Please don't make new name.
> +#define S5P64X0_CLKCON_SCLK1_FIMGVG (1<<2)
Same as above.
...CLK_GATE_SCLK1_FIMGVG
> +
> +/* PCLK GATE Registers */
> +#define S5P64X0_CLKCON_PCLK_UART3 (1<<4)
> +#define S5P64X0_CLKCON_PCLK_UART2 (1<<3)
> +#define S5P64X0_CLKCON_PCLK_UART1 (1<<2)
> +#define S5P64X0_CLKCON_PCLK_UART0 (1<<1)
Same as above.
> +
> +#define S5P64X0_PWRCFG_MMC1_DISABLE (1 << 15)
> +#define S5P64X0_PWRCFG_MMC0_DISABLE (1 << 14)
> +#define S5P64X0_PWRCFG_RTC_TICK_DISABLE (1 << 11)
> +#define S5P64X0_PWRCFG_RTC_ALRM_DISABLE (1 << 10)
> +#define S5P64X0_PWRCFG_CFG_WFI_MASK (3 << 5)
> +#define S5P64X0_PWRCFG_CFG_WFI_SLEEP (3 << 5)
> +
> +#define S5P64X0_SLEEP_CFG_OSC_EN (1 << 0)
> +
> +#define S5P64X0_PWR_STABLE_CNT_VAL_4 (4 << 0)
Same...please use same name with datasheet.
> +
> +#define S5P6450_OTHERS_DISABLE_INT (1 << 31)
> +#define S5P64X0_OTHERS_RET_UART (1 << 26)
> +#define S5P64X0_OTHERS_RET_MMC1 (1 << 25)
> +#define S5P64X0_OTHERS_RET_MMC0 (1 << 24)
> #define S5P64X0_OTHERS_USB_SIG_MASK (1 << 16)
>
> /* Compatibility defines */
> diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
b/arch/arm/mach-
> s5p64x0/include/mach/regs-gpio.h
> index 6ce2547..27a2230 100644
> --- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
> +++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
> @@ -34,14 +34,33 @@
> #define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180)
> #define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300)
>
> +#define S5P64X0_SPCON0 (S5P_VA_GPIO + 0x1A0)
> +#define S5P64X0_SPCON1 (S5P_VA_GPIO + 0x2B0)
> +
> +#define S5P64X0_MEM0CONSLP0 (S5P_VA_GPIO + 0x1C0)
> +#define S5P64X0_MEM0CONSLP1 (S5P_VA_GPIO + 0x1C4)
> +#define S5P64X0_MEM0DRVCON (S5P_VA_GPIO + 0x1D0)
> +#define S5P64X0_MEM1DRVCON (S5P_VA_GPIO + 0x1D4)
> +
> +#define S5P64X0_EINT12CON (S5P_VA_GPIO + 0x200)
> +#define S5P64X0_EINT12FLTCON (S5P_VA_GPIO + 0x220)
> +#define S5P64X0_EINT12MASK (S5P_VA_GPIO + 0x240)
> +
> /* External interrupt control registers for group0 */
>
> #define EINT0CON0_OFFSET (0x900)
> +#define EINT0FLTCON0_OFFSET (0x910)
> +#define EINT0FLTCON1_OFFSET (0x914)
> #define EINT0MASK_OFFSET (0x920)
> #define EINT0PEND_OFFSET (0x924)
>
> #define S5P64X0_EINT0CON0 (S5P_VA_GPIO +
> EINT0CON0_OFFSET)
> +#define S5P64X0_EINT0FLTCON0 (S5P_VA_GPIO +
> EINT0FLTCON0_OFFSET)
> +#define S5P64X0_EINT0FLTCON1 (S5P_VA_GPIO +
> EINT0FLTCON1_OFFSET)
> #define S5P64X0_EINT0MASK (S5P_VA_GPIO +
> EINT0MASK_OFFSET)
> #define S5P64X0_EINT0PEND (S5P_VA_GPIO +
> EINT0PEND_OFFSET)
>
> +#define S5P64X0_SLPEN (S5P_VA_GPIO + 0x930)
> +#define S5P64X0_SLPEN_USE_xSLP (1 << 0)
> +
> #endif /* __ASM_ARCH_REGS_GPIO_H */
> diff --git a/arch/arm/mach-s5p64x0/irq-eint.c
b/arch/arm/mach-s5p64x0/irq-eint.c
> index fe7380f..3b94c6c 100644
> --- a/arch/arm/mach-s5p64x0/irq-eint.c
> +++ b/arch/arm/mach-s5p64x0/irq-eint.c
> @@ -19,6 +19,7 @@
>
> #include <plat/regs-irqtype.h>
> #include <plat/gpio-cfg.h>
> +#include <plat/pm.h>
>
> #include <mach/regs-gpio.h>
> #include <mach/regs-clock.h>
> @@ -133,6 +134,7 @@ static int s5p64x0_alloc_gc(void)
> ct->chip.irq_mask = irq_gc_mask_set_bit;
> ct->chip.irq_unmask = irq_gc_mask_clr_bit;
> ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
> + ct->chip.irq_set_wake = s3c_irqext_wake;
> ct->regs.ack = EINT0PEND_OFFSET;
> ct->regs.mask = EINT0MASK_OFFSET;
> irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
> diff --git a/arch/arm/mach-s5p64x0/irq-pm.c
b/arch/arm/mach-s5p64x0/irq-pm.c
> new file mode 100644
> index 0000000..3e6f245
> --- /dev/null
> +++ b/arch/arm/mach-s5p64x0/irq-pm.c
> @@ -0,0 +1,92 @@
> +/* linux/arch/arm/mach-s5p64x0/irq-pm.c
> + *
> + * Copyright (c) 2011 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com
> + *
> + * S5P64X0 - Interrupt handling Power Management
> + *
> + * Based on arch/arm/mach-s3c64xx/irq-pm.c by Ben Dooks
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/syscore_ops.h>
> +#include <linux/serial_core.h>
> +#include <linux/io.h>
> +
> +#include <plat/regs-serial.h>
> +#include <plat/pm.h>
> +
> +#include <mach/regs-gpio.h>
> +
> +static struct sleep_save irq_save[] = {
> + SAVE_ITEM(S5P64X0_EINT0CON0),
> + SAVE_ITEM(S5P64X0_EINT0FLTCON0),
> + SAVE_ITEM(S5P64X0_EINT0FLTCON1),
> + SAVE_ITEM(S5P64X0_EINT0MASK),
> +};
> +
> +static struct irq_grp_save {
> + u32 con;
> + u32 fltcon;
> + u32 mask;
> +} eint_grp_save[4];
> +
> +static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS];
> +
> +static int s5p64x0_irq_pm_suspend(void)
> +{
> + struct irq_grp_save *grp = eint_grp_save;
> + int i;
> +
> + S3C_PMDBG("%s: suspending IRQs\n", __func__);
> +
> + s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
> +
> + for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
> + irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) +
> S3C64XX_UINTM);
> +
> + for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
> + grp->con = __raw_readl(S5P64X0_EINT12CON + (i * 4));
> + grp->mask = __raw_readl(S5P64X0_EINT12MASK + (i * 4));
> + grp->fltcon = __raw_readl(S5P64X0_EINT12FLTCON + (i * 4));
> + }
> +
> + return 0;
> +}
> +
> +static void s5p64x0_irq_pm_resume(void)
> +{
> + struct irq_grp_save *grp = eint_grp_save;
> + int i;
> +
> + S3C_PMDBG("%s: resuming IRQs\n", __func__);
> +
> + s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
> +
> + for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
> + __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) +
> S3C64XX_UINTM);
> +
> + for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
> + __raw_writel(grp->con, S5P64X0_EINT12CON + (i * 4));
> + __raw_writel(grp->mask, S5P64X0_EINT12MASK + (i * 4));
> + __raw_writel(grp->fltcon, S5P64X0_EINT12FLTCON + (i * 4));
> + }
> +
> + S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
> +}
> +
> +static struct syscore_ops s5p64x0_irq_syscore_ops = {
> + .suspend = s5p64x0_irq_pm_suspend,
> + .resume = s5p64x0_irq_pm_resume,
> +};
> +
> +static int __init s5p64x0_syscore_init(void)
> +{
> + register_syscore_ops(&s5p64x0_irq_syscore_ops);
> +
> + return 0;
> +}
> +core_initcall(s5p64x0_syscore_init);
> diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c
> new file mode 100644
> index 0000000..cced4fb
> --- /dev/null
> +++ b/arch/arm/mach-s5p64x0/pm.c
> @@ -0,0 +1,204 @@
> +/* linux/arch/arm/mach-s5p64x0/pm.c
> + *
> + * Copyright (c) 2011 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com
> + *
> + * S5P64X0 Power Management Support
> + *
> + * Based on arch/arm/mach-s3c64xx/pm.c by Ben Dooks
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#include <linux/suspend.h>
> +#include <linux/syscore_ops.h>
> +#include <linux/io.h>
> +
> +#include <plat/cpu.h>
> +#include <plat/pm.h>
> +#include <plat/regs-timer.h>
> +#include <plat/wakeup-mask.h>
> +
> +#include <mach/regs-clock.h>
> +#include <mach/regs-gpio.h>
> +
> +static struct sleep_save s5p64x0_core_save[] = {
> + SAVE_ITEM(S5P64X0_APLL_CON),
> + SAVE_ITEM(S5P64X0_MPLL_CON),
> + SAVE_ITEM(S5P64X0_EPLL_CON),
> + SAVE_ITEM(S5P64X0_EPLL_CON_K),
> + SAVE_ITEM(S5P64X0_CLK_SRC0),
> + SAVE_ITEM(S5P64X0_CLK_SRC1),
> + SAVE_ITEM(S5P64X0_CLK_DIV0),
> + SAVE_ITEM(S5P64X0_CLK_DIV1),
> + SAVE_ITEM(S5P64X0_CLK_DIV2),
> + SAVE_ITEM(S5P64X0_CLK_DIV3),
> + SAVE_ITEM(S5P64X0_CLK_GATE_MEM0),
> + SAVE_ITEM(S5P64X0_CLK_GATE_HCLK1),
> + SAVE_ITEM(S5P64X0_CLK_GATE_SCLK1),
> +};
> +
> +static struct sleep_save s5p64x0_misc_save[] = {
> + SAVE_ITEM(S5P64X0_AHB_CON0),
> + SAVE_ITEM(S5P64X0_SPCON0),
> + SAVE_ITEM(S5P64X0_SPCON1),
> + SAVE_ITEM(S5P64X0_MEM0CONSLP0),
> + SAVE_ITEM(S5P64X0_MEM0CONSLP1),
> + SAVE_ITEM(S5P64X0_MEM0DRVCON),
> + SAVE_ITEM(S5P64X0_MEM1DRVCON),
> +
> + SAVE_ITEM(S3C64XX_TINT_CSTAT),
> +};
> +
> +/* DPLL is present only in S5P6450 */
> +static struct sleep_save s5p6450_core_save[] = {
> + SAVE_ITEM(S5P6450_DPLL_CON),
> + SAVE_ITEM(S5P6450_DPLL_CON_K),
> +};
> +
> +void s3c_pm_configure_extint(void)
> +{
> + __raw_writel(s3c_irqwake_eintmask, S5P64X0_EINT_WAKEUP_MASK);
> +}
> +
> +void s3c_pm_restore_core(void)
> +{
> + __raw_writel(0, S5P64X0_EINT_WAKEUP_MASK);
> +
> + s3c_pm_do_restore_core(s5p64x0_core_save,
> + ARRAY_SIZE(s5p64x0_core_save));
> +
> + if ((__raw_readl(S5P64X0_SYS_ID) & 0xFF000) == 0x50000)
> + s3c_pm_do_restore_core(s5p6450_core_save,
> + ARRAY_SIZE(s5p6450_core_save));
You can use soc_is_xxx() here.
> +
> + s3c_pm_do_restore(s5p64x0_misc_save,
> ARRAY_SIZE(s5p64x0_misc_save));
> +}
> +
> +void s3c_pm_save_core(void)
> +{
> + s3c_pm_do_save(s5p64x0_misc_save,
> ARRAY_SIZE(s5p64x0_misc_save));
> +
> + if ((__raw_readl(S5P64X0_SYS_ID) & 0xFF000) == 0x50000)
> + s3c_pm_do_save(s5p6450_core_save,
> + ARRAY_SIZE(s5p6450_core_save));
Same.
> +
> + s3c_pm_do_save(s5p64x0_core_save,
> ARRAY_SIZE(s5p64x0_core_save));
> +}
> +
> +static int s5p64x0_cpu_suspend(unsigned long arg)
> +{
> + unsigned long tmp = 0;
> +
> + /*
> + * Issue the standby signal into the pm unit. Note, we
> + * issue a write-buffer drain just in case.
> + */
> + asm("b 1f\n\t"
> + ".align 5\n\t"
> + "1:\n\t"
> + "mcr p15, 0, %0, c7, c10, 5\n\t"
> + "mcr p15, 0, %0, c7, c10, 4\n\t"
> + "mcr p15, 0, %0, c7, c0, 4" : : "r" (tmp));
> +
> + /* we should never get past here */
> + panic("sleep resumed to originator?");
> +}
> +
> +/* mapping of interrupts to parts of the wakeup mask */
> +static struct samsung_wakeup_mask s5p64x0_wake_irqs[] = {
> + { .irq = IRQ_RTC_ALARM, .bit =
> S5P64X0_PWRCFG_RTC_ALRM_DISABLE, },
> + { .irq = IRQ_RTC_TIC, .bit =
> S5P64X0_PWRCFG_RTC_TICK_DISABLE, },
> + { .irq = IRQ_HSMMC0, .bit = S5P64X0_PWRCFG_MMC0_DISABLE, },
> + { .irq = IRQ_HSMMC1, .bit = S5P64X0_PWRCFG_MMC1_DISABLE, },
> +};
> +
> +static void s5p64x0_pm_prepare(void)
> +{
> + u32 tmp;
> +
> + samsung_sync_wakemask(S5P64X0_PWR_CFG,
> + s5p64x0_wake_irqs, ARRAY_SIZE(s5p64x0_wake_irqs));
> +
> + /* store the resume address in INFORM0 register */
> + __raw_writel(virt_to_phys(s3c_cpu_resume), S5P64X0_INFORM0);
> +
> + /* setup clock gating for FIMGVG block */
> + __raw_writel((__raw_readl(S5P64X0_CLK_GATE_HCLK1) | \
> + (S5P64X0_CLKCON_HCLK1_FIMGVG)),
> S5P64X0_CLK_GATE_HCLK1);
> + __raw_writel((__raw_readl(S5P64X0_CLK_GATE_SCLK1) | \
> + (S5P64X0_CLKCON_SCLK1_FIMGVG)),
> S5P64X0_CLK_GATE_SCLK1);
> +
> + /* Configure the stabilization counter with wait time required */
> + __raw_writel(S5P64X0_PWR_STABLE_CNT_VAL_4,
> S5P64X0_PWR_STABLE);
> +
> + /* set WFI to SLEEP mode configuration */
> + tmp = __raw_readl(S5P64X0_SLEEP_CFG);
> + tmp &= ~(S5P64X0_SLEEP_CFG_OSC_EN);
> + __raw_writel(tmp, S5P64X0_SLEEP_CFG);
> +
> + tmp = __raw_readl(S5P64X0_PWR_CFG);
> + tmp &= ~(S5P64X0_PWRCFG_CFG_WFI_MASK);
> + tmp |= S5P64X0_PWRCFG_CFG_WFI_SLEEP;
> + __raw_writel(tmp, S5P64X0_PWR_CFG);
> +
> + /*
> + * set OTHERS register to disable interrupt before going to
> + * sleep. This bit is present only in S5P6450, it is reserved
> + * in S5P6440.
> + */
> + if ((__raw_readl(S5P64X0_SYS_ID) & 0xFF000) == 0x50000) {
> + tmp = __raw_readl(S5P64X0_OTHERS);
> + tmp |= S5P6450_OTHERS_DISABLE_INT;
> + __raw_writel(tmp, S5P64X0_OTHERS);
> + }
> +
> + /* ensure previous wakeup state is cleared before sleeping */
> + __raw_writel(__raw_readl(S5P64X0_WAKEUP_STAT),
> S5P64X0_WAKEUP_STAT);
> +
> +}
> +
> +static int s5p64x0_pm_add(struct sys_device *sysdev)
> +{
> + pm_cpu_prep = s5p64x0_pm_prepare;
> + pm_cpu_sleep = s5p64x0_cpu_suspend;
> + pm_uart_udivslot = 1;
If pm_uart_udivslot has value, the UDIVSLOT3 is used...is this right on
S5P64X0?
> +
> + return 0;
> +}
> +
> +static struct sysdev_driver s5p64x0_pm_driver = {
> + .add = s5p64x0_pm_add,
> +};
> +
> +static __init int s5p64x0_pm_drvinit(void)
> +{
> + s3c_pm_init();
> +
> + return sysdev_driver_register(&s5p64x0_sysclass,
&s5p64x0_pm_driver);
> +}
> +arch_initcall(s5p64x0_pm_drvinit);
> +
> +static void s5p64x0_pm_resume(void)
> +{
> + u32 tmp;
> +
> + tmp = __raw_readl(S5P64X0_OTHERS);
> + tmp |= (S5P64X0_OTHERS_RET_MMC0 |
> S5P64X0_OTHERS_RET_MMC1 | \
> + S5P64X0_OTHERS_RET_UART);
> + __raw_writel(tmp , S5P64X0_OTHERS);
> +}
> +
> +static struct syscore_ops s5p64x0_pm_syscore_ops = {
> + .resume = s5p64x0_pm_resume,
> +};
> +
> +static __init int s5p64x0_pm_syscore_init(void)
> +{
> + register_syscore_ops(&s5p64x0_pm_syscore_ops);
> +
> + return 0;
> +}
> +arch_initcall(s5p64x0_pm_syscore_init);
> --
> 1.7.4.1
Basically, this codes need small fixing. I mean if this codes have been
tested on board and it works fine, it's ok to me.
But as you said, s5p64x0 pm is almost same with s3c64xx, so we need to clean
them up next time :)
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 40+ messages in thread* [PATCH 5/5] ARM: S5P64X0: Add Power Management support
@ 2011-09-07 6:01 ` Kukjin Kim
0 siblings, 0 replies; 40+ messages in thread
From: Kukjin Kim @ 2011-09-07 6:01 UTC (permalink / raw)
To: linux-arm-kernel
Abhilash Kesavan wrote:
>
> Add suspend-to-ram support for SMDK6440/50
>
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
> arch/arm/Kconfig | 2 +-
> arch/arm/mach-s5p64x0/Kconfig | 4 +
> arch/arm/mach-s5p64x0/Makefile | 1 +
> arch/arm/mach-s5p64x0/include/mach/map.h | 1 +
> arch/arm/mach-s5p64x0/include/mach/pm-core.h | 117 +++++++++++++
> arch/arm/mach-s5p64x0/include/mach/regs-clock.h | 33 ++++
> arch/arm/mach-s5p64x0/include/mach/regs-gpio.h | 19 ++
> arch/arm/mach-s5p64x0/irq-eint.c | 2 +
> arch/arm/mach-s5p64x0/irq-pm.c | 92 ++++++++++
> arch/arm/mach-s5p64x0/pm.c | 204
> +++++++++++++++++++++++
> 10 files changed, 474 insertions(+), 1 deletions(-)
> create mode 100644 arch/arm/mach-s5p64x0/include/mach/pm-core.h
> create mode 100644 arch/arm/mach-s5p64x0/irq-pm.c
> create mode 100644 arch/arm/mach-s5p64x0/pm.c
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 2c71a8f..47aed0d 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -2071,7 +2071,7 @@ menu "Power management options"
> source "kernel/power/Kconfig"
>
> config ARCH_SUSPEND_POSSIBLE
> - depends on !ARCH_S5P64X0 && !ARCH_S5PC100
> + depends on !ARCH_S5PC100
> depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
> CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
> def_bool y
> diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
> index 65c7518..d7f034a 100644
> --- a/arch/arm/mach-s5p64x0/Kconfig
> +++ b/arch/arm/mach-s5p64x0/Kconfig
> @@ -11,6 +11,8 @@ config CPU_S5P6440
> bool
> select S3C_PL330_DMA
> select S5P_HRT
> + select SAMSUNG_SLEEP if PM
> + select SAMSUNG_WAKEMASK if PM
> help
> Enable S5P6440 CPU support
>
> @@ -18,6 +20,8 @@ config CPU_S5P6450
> bool
> select S3C_PL330_DMA
> select S5P_HRT
> + select SAMSUNG_SLEEP if PM
> + select SAMSUNG_WAKEMASK if PM
> help
> Enable S5P6450 CPU support
>
> diff --git a/arch/arm/mach-s5p64x0/Makefile
b/arch/arm/mach-s5p64x0/Makefile
> index 5f6afdf..acfebb7 100644
> --- a/arch/arm/mach-s5p64x0/Makefile
> +++ b/arch/arm/mach-s5p64x0/Makefile
> @@ -16,6 +16,7 @@ obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o
> clock.o dma.o gpiolib.o
> obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o irq-eint.o
> obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o
> obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o
> +obj-$(CONFIG_PM) += pm.o irq-pm.o
>
> # machine support
>
> diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-
> s5p64x0/include/mach/map.h
> index 95c9125..6138f7c 100644
> --- a/arch/arm/mach-s5p64x0/include/mach/map.h
> +++ b/arch/arm/mach-s5p64x0/include/mach/map.h
> @@ -85,5 +85,6 @@
> #define S5P_PA_UART5 S5P6450_PA_UART(5)
>
> #define S5P_SZ_UART SZ_256
> +#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) *
> S3C_UART_OFFSET))
>
> #endif /* __ASM_ARCH_MAP_H */
> diff --git a/arch/arm/mach-s5p64x0/include/mach/pm-core.h b/arch/arm/mach-
> s5p64x0/include/mach/pm-core.h
> new file mode 100644
> index 0000000..aee9d85
> --- /dev/null
> +++ b/arch/arm/mach-s5p64x0/include/mach/pm-core.h
> @@ -0,0 +1,117 @@
> +/* linux/arch/arm/mach-s5p64x0/include/mach/pm-core.h
> + *
> + * Copyright (c) 2011 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com
> + *
> + * S5P64X0 - PM core support for arch/arm/plat-samsung/pm.c
> + *
> + * Based on PM core support for S3C64XX by Ben Dooks
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <mach/regs-gpio.h>
> +
> +static inline void s3c_pm_debug_init_uart(void)
> +{
> + u32 tmp = __raw_readl(S5P64X0_CLK_GATE_PCLK);
> +
> + /*
> + * As a note, since the S5P64X0 UARTs generally have multiple
> + * clock sources, we simply enable PCLK at the moment and hope
> + * that the resume settings for the UART are suitable for the
> + * use with PCLK.
> + */
> + tmp |= S5P64X0_CLKCON_PCLK_UART0;
> + tmp |= S5P64X0_CLKCON_PCLK_UART1;
> + tmp |= S5P64X0_CLKCON_PCLK_UART2;
> + tmp |= S5P64X0_CLKCON_PCLK_UART3;
> +
> + __raw_writel(tmp, S5P64X0_CLK_GATE_PCLK);
> + udelay(10);
> +}
> +
> +static inline void s3c_pm_arch_prepare_irqs(void)
> +{
> + /* VIC should have already been taken care of */
> +
> + /* clear any pending EINT0 interrupts */
> + __raw_writel(__raw_readl(S5P64X0_EINT0PEND), S5P64X0_EINT0PEND);
> +}
> +
> +static inline void s3c_pm_arch_stop_clocks(void) { }
> +static inline void s3c_pm_arch_show_resume_irqs(void) { }
> +
> +/*
> + * make these defines, we currently do not have any need to change
> + * the IRQ wake controls depending on the CPU we are running on
> + */
> +#define s3c_irqwake_eintallow ((1 << 16) - 1)
> +#define s3c_irqwake_intallow (~0)
> +
> +static inline void s3c_pm_arch_update_uart(void __iomem *regs,
> + struct pm_uart_save *save)
> +{
> + u32 ucon = __raw_readl(regs + S3C2410_UCON);
> + u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
> + u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
> + u32 new_ucon;
> + u32 delta;
> +
> + /*
> + * S5P64X0 UART blocks only support level interrupts, so ensure that
> + * when we restore unused UART blocks we force the level interrupt
> + * settings.
> + */
> + save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
> +
> + /*
> + * We have a constraint on changing the clock type of the UART
> + * between UCLKx and PCLK, so ensure that when we restore UCON
> + * that the CLK field is correctly modified if the bootloader
> + * has changed anything.
> + */
> + if (ucon_clk != save_clk) {
> + new_ucon = save->ucon;
> + delta = ucon_clk ^ save_clk;
> +
> + /*
> + * change from UCLKx => wrong PCLK,
> + * either UCLK can be tested for by a bit-test
> + * with UCLK0
> + */
> + if (ucon_clk & S3C6400_UCON_UCLK0 &&
> + !(save_clk & S3C6400_UCON_UCLK0) &&
> + delta & S3C6400_UCON_PCLK2) {
> + new_ucon &= ~S3C6400_UCON_UCLK0;
> + } else if (delta == S3C6400_UCON_PCLK2) {
> + /*
> + * as a precaution, don't change from
> + * PCLK2 => PCLK or vice-versa
> + */
> + new_ucon ^= S3C6400_UCON_PCLK2;
> + }
> +
> + S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
> + ucon, new_ucon, save->ucon);
> + save->ucon = new_ucon;
> + }
> +}
> +
> +static inline void s3c_pm_restored_gpios(void)
> +{
> + /* ensure sleep mode has been cleared from the system */
> + __raw_writel(0, S5P64X0_SLPEN);
> +}
> +
> +static inline void s3c_pm_saved_gpios(void)
> +{
> + /*
> + * turn on the sleep mode and keep it there, as it seems that during
> + * suspend the xCON registers get re-set and thus you can end up
with
> + * problems between going to sleep and resuming.
> + */
> + __raw_writel(S5P64X0_SLPEN_USE_xSLP, S5P64X0_SLPEN);
> +}
> diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
b/arch/arm/mach-
> s5p64x0/include/mach/regs-clock.h
> index a133f22..75f66a9 100644
> --- a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
> +++ b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
> @@ -41,17 +41,50 @@
> #define S5P6450_DPLL_CON S5P_CLKREG(0x50)
> #define S5P6450_DPLL_CON_K S5P_CLKREG(0x54)
>
> +#define S5P64X0_AHB_CON0 S5P_CLKREG(0x100)
> #define S5P64X0_CLK_SRC1 S5P_CLKREG(0x10C)
>
> #define S5P64X0_SYS_ID S5P_CLKREG(0x118)
> #define S5P64X0_SYS_OTHERS S5P_CLKREG(0x11C)
>
> #define S5P64X0_PWR_CFG S5P_CLKREG(0x804)
> +#define S5P64X0_EINT_WAKEUP_MASK S5P_CLKREG(0x808)
> +#define S5P64X0_SLEEP_CFG S5P_CLKREG(0x818)
> +#define S5P64X0_PWR_STABLE S5P_CLKREG(0x828)
> +
> #define S5P64X0_OTHERS S5P_CLKREG(0x900)
> +#define S5P64X0_WAKEUP_STAT S5P_CLKREG(0x908)
> +
> +#define S5P64X0_INFORM0 S5P_CLKREG(0xA00)
>
> #define S5P64X0_CLKDIV0_HCLK_SHIFT (8)
> #define S5P64X0_CLKDIV0_HCLK_MASK (0xF <<
> S5P64X0_CLKDIV0_HCLK_SHIFT)
>
> +/* HCLK GATE Registers */
> +#define S5P64X0_CLKCON_HCLK1_FIMGVG (1<<2)
Should be added blank around "<<" like (1 << 2).
And if possible, the name should be same with datasheet like
...CLK_GATE_HCLK1_FIMGVG.
Please don't make new name.
> +#define S5P64X0_CLKCON_SCLK1_FIMGVG (1<<2)
Same as above.
...CLK_GATE_SCLK1_FIMGVG
> +
> +/* PCLK GATE Registers */
> +#define S5P64X0_CLKCON_PCLK_UART3 (1<<4)
> +#define S5P64X0_CLKCON_PCLK_UART2 (1<<3)
> +#define S5P64X0_CLKCON_PCLK_UART1 (1<<2)
> +#define S5P64X0_CLKCON_PCLK_UART0 (1<<1)
Same as above.
> +
> +#define S5P64X0_PWRCFG_MMC1_DISABLE (1 << 15)
> +#define S5P64X0_PWRCFG_MMC0_DISABLE (1 << 14)
> +#define S5P64X0_PWRCFG_RTC_TICK_DISABLE (1 << 11)
> +#define S5P64X0_PWRCFG_RTC_ALRM_DISABLE (1 << 10)
> +#define S5P64X0_PWRCFG_CFG_WFI_MASK (3 << 5)
> +#define S5P64X0_PWRCFG_CFG_WFI_SLEEP (3 << 5)
> +
> +#define S5P64X0_SLEEP_CFG_OSC_EN (1 << 0)
> +
> +#define S5P64X0_PWR_STABLE_CNT_VAL_4 (4 << 0)
Same...please use same name with datasheet.
> +
> +#define S5P6450_OTHERS_DISABLE_INT (1 << 31)
> +#define S5P64X0_OTHERS_RET_UART (1 << 26)
> +#define S5P64X0_OTHERS_RET_MMC1 (1 << 25)
> +#define S5P64X0_OTHERS_RET_MMC0 (1 << 24)
> #define S5P64X0_OTHERS_USB_SIG_MASK (1 << 16)
>
> /* Compatibility defines */
> diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
b/arch/arm/mach-
> s5p64x0/include/mach/regs-gpio.h
> index 6ce2547..27a2230 100644
> --- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
> +++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
> @@ -34,14 +34,33 @@
> #define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180)
> #define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300)
>
> +#define S5P64X0_SPCON0 (S5P_VA_GPIO + 0x1A0)
> +#define S5P64X0_SPCON1 (S5P_VA_GPIO + 0x2B0)
> +
> +#define S5P64X0_MEM0CONSLP0 (S5P_VA_GPIO + 0x1C0)
> +#define S5P64X0_MEM0CONSLP1 (S5P_VA_GPIO + 0x1C4)
> +#define S5P64X0_MEM0DRVCON (S5P_VA_GPIO + 0x1D0)
> +#define S5P64X0_MEM1DRVCON (S5P_VA_GPIO + 0x1D4)
> +
> +#define S5P64X0_EINT12CON (S5P_VA_GPIO + 0x200)
> +#define S5P64X0_EINT12FLTCON (S5P_VA_GPIO + 0x220)
> +#define S5P64X0_EINT12MASK (S5P_VA_GPIO + 0x240)
> +
> /* External interrupt control registers for group0 */
>
> #define EINT0CON0_OFFSET (0x900)
> +#define EINT0FLTCON0_OFFSET (0x910)
> +#define EINT0FLTCON1_OFFSET (0x914)
> #define EINT0MASK_OFFSET (0x920)
> #define EINT0PEND_OFFSET (0x924)
>
> #define S5P64X0_EINT0CON0 (S5P_VA_GPIO +
> EINT0CON0_OFFSET)
> +#define S5P64X0_EINT0FLTCON0 (S5P_VA_GPIO +
> EINT0FLTCON0_OFFSET)
> +#define S5P64X0_EINT0FLTCON1 (S5P_VA_GPIO +
> EINT0FLTCON1_OFFSET)
> #define S5P64X0_EINT0MASK (S5P_VA_GPIO +
> EINT0MASK_OFFSET)
> #define S5P64X0_EINT0PEND (S5P_VA_GPIO +
> EINT0PEND_OFFSET)
>
> +#define S5P64X0_SLPEN (S5P_VA_GPIO + 0x930)
> +#define S5P64X0_SLPEN_USE_xSLP (1 << 0)
> +
> #endif /* __ASM_ARCH_REGS_GPIO_H */
> diff --git a/arch/arm/mach-s5p64x0/irq-eint.c
b/arch/arm/mach-s5p64x0/irq-eint.c
> index fe7380f..3b94c6c 100644
> --- a/arch/arm/mach-s5p64x0/irq-eint.c
> +++ b/arch/arm/mach-s5p64x0/irq-eint.c
> @@ -19,6 +19,7 @@
>
> #include <plat/regs-irqtype.h>
> #include <plat/gpio-cfg.h>
> +#include <plat/pm.h>
>
> #include <mach/regs-gpio.h>
> #include <mach/regs-clock.h>
> @@ -133,6 +134,7 @@ static int s5p64x0_alloc_gc(void)
> ct->chip.irq_mask = irq_gc_mask_set_bit;
> ct->chip.irq_unmask = irq_gc_mask_clr_bit;
> ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
> + ct->chip.irq_set_wake = s3c_irqext_wake;
> ct->regs.ack = EINT0PEND_OFFSET;
> ct->regs.mask = EINT0MASK_OFFSET;
> irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
> diff --git a/arch/arm/mach-s5p64x0/irq-pm.c
b/arch/arm/mach-s5p64x0/irq-pm.c
> new file mode 100644
> index 0000000..3e6f245
> --- /dev/null
> +++ b/arch/arm/mach-s5p64x0/irq-pm.c
> @@ -0,0 +1,92 @@
> +/* linux/arch/arm/mach-s5p64x0/irq-pm.c
> + *
> + * Copyright (c) 2011 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com
> + *
> + * S5P64X0 - Interrupt handling Power Management
> + *
> + * Based on arch/arm/mach-s3c64xx/irq-pm.c by Ben Dooks
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/syscore_ops.h>
> +#include <linux/serial_core.h>
> +#include <linux/io.h>
> +
> +#include <plat/regs-serial.h>
> +#include <plat/pm.h>
> +
> +#include <mach/regs-gpio.h>
> +
> +static struct sleep_save irq_save[] = {
> + SAVE_ITEM(S5P64X0_EINT0CON0),
> + SAVE_ITEM(S5P64X0_EINT0FLTCON0),
> + SAVE_ITEM(S5P64X0_EINT0FLTCON1),
> + SAVE_ITEM(S5P64X0_EINT0MASK),
> +};
> +
> +static struct irq_grp_save {
> + u32 con;
> + u32 fltcon;
> + u32 mask;
> +} eint_grp_save[4];
> +
> +static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS];
> +
> +static int s5p64x0_irq_pm_suspend(void)
> +{
> + struct irq_grp_save *grp = eint_grp_save;
> + int i;
> +
> + S3C_PMDBG("%s: suspending IRQs\n", __func__);
> +
> + s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
> +
> + for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
> + irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) +
> S3C64XX_UINTM);
> +
> + for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
> + grp->con = __raw_readl(S5P64X0_EINT12CON + (i * 4));
> + grp->mask = __raw_readl(S5P64X0_EINT12MASK + (i * 4));
> + grp->fltcon = __raw_readl(S5P64X0_EINT12FLTCON + (i * 4));
> + }
> +
> + return 0;
> +}
> +
> +static void s5p64x0_irq_pm_resume(void)
> +{
> + struct irq_grp_save *grp = eint_grp_save;
> + int i;
> +
> + S3C_PMDBG("%s: resuming IRQs\n", __func__);
> +
> + s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
> +
> + for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
> + __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) +
> S3C64XX_UINTM);
> +
> + for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
> + __raw_writel(grp->con, S5P64X0_EINT12CON + (i * 4));
> + __raw_writel(grp->mask, S5P64X0_EINT12MASK + (i * 4));
> + __raw_writel(grp->fltcon, S5P64X0_EINT12FLTCON + (i * 4));
> + }
> +
> + S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
> +}
> +
> +static struct syscore_ops s5p64x0_irq_syscore_ops = {
> + .suspend = s5p64x0_irq_pm_suspend,
> + .resume = s5p64x0_irq_pm_resume,
> +};
> +
> +static int __init s5p64x0_syscore_init(void)
> +{
> + register_syscore_ops(&s5p64x0_irq_syscore_ops);
> +
> + return 0;
> +}
> +core_initcall(s5p64x0_syscore_init);
> diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c
> new file mode 100644
> index 0000000..cced4fb
> --- /dev/null
> +++ b/arch/arm/mach-s5p64x0/pm.c
> @@ -0,0 +1,204 @@
> +/* linux/arch/arm/mach-s5p64x0/pm.c
> + *
> + * Copyright (c) 2011 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com
> + *
> + * S5P64X0 Power Management Support
> + *
> + * Based on arch/arm/mach-s3c64xx/pm.c by Ben Dooks
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#include <linux/suspend.h>
> +#include <linux/syscore_ops.h>
> +#include <linux/io.h>
> +
> +#include <plat/cpu.h>
> +#include <plat/pm.h>
> +#include <plat/regs-timer.h>
> +#include <plat/wakeup-mask.h>
> +
> +#include <mach/regs-clock.h>
> +#include <mach/regs-gpio.h>
> +
> +static struct sleep_save s5p64x0_core_save[] = {
> + SAVE_ITEM(S5P64X0_APLL_CON),
> + SAVE_ITEM(S5P64X0_MPLL_CON),
> + SAVE_ITEM(S5P64X0_EPLL_CON),
> + SAVE_ITEM(S5P64X0_EPLL_CON_K),
> + SAVE_ITEM(S5P64X0_CLK_SRC0),
> + SAVE_ITEM(S5P64X0_CLK_SRC1),
> + SAVE_ITEM(S5P64X0_CLK_DIV0),
> + SAVE_ITEM(S5P64X0_CLK_DIV1),
> + SAVE_ITEM(S5P64X0_CLK_DIV2),
> + SAVE_ITEM(S5P64X0_CLK_DIV3),
> + SAVE_ITEM(S5P64X0_CLK_GATE_MEM0),
> + SAVE_ITEM(S5P64X0_CLK_GATE_HCLK1),
> + SAVE_ITEM(S5P64X0_CLK_GATE_SCLK1),
> +};
> +
> +static struct sleep_save s5p64x0_misc_save[] = {
> + SAVE_ITEM(S5P64X0_AHB_CON0),
> + SAVE_ITEM(S5P64X0_SPCON0),
> + SAVE_ITEM(S5P64X0_SPCON1),
> + SAVE_ITEM(S5P64X0_MEM0CONSLP0),
> + SAVE_ITEM(S5P64X0_MEM0CONSLP1),
> + SAVE_ITEM(S5P64X0_MEM0DRVCON),
> + SAVE_ITEM(S5P64X0_MEM1DRVCON),
> +
> + SAVE_ITEM(S3C64XX_TINT_CSTAT),
> +};
> +
> +/* DPLL is present only in S5P6450 */
> +static struct sleep_save s5p6450_core_save[] = {
> + SAVE_ITEM(S5P6450_DPLL_CON),
> + SAVE_ITEM(S5P6450_DPLL_CON_K),
> +};
> +
> +void s3c_pm_configure_extint(void)
> +{
> + __raw_writel(s3c_irqwake_eintmask, S5P64X0_EINT_WAKEUP_MASK);
> +}
> +
> +void s3c_pm_restore_core(void)
> +{
> + __raw_writel(0, S5P64X0_EINT_WAKEUP_MASK);
> +
> + s3c_pm_do_restore_core(s5p64x0_core_save,
> + ARRAY_SIZE(s5p64x0_core_save));
> +
> + if ((__raw_readl(S5P64X0_SYS_ID) & 0xFF000) == 0x50000)
> + s3c_pm_do_restore_core(s5p6450_core_save,
> + ARRAY_SIZE(s5p6450_core_save));
You can use soc_is_xxx() here.
> +
> + s3c_pm_do_restore(s5p64x0_misc_save,
> ARRAY_SIZE(s5p64x0_misc_save));
> +}
> +
> +void s3c_pm_save_core(void)
> +{
> + s3c_pm_do_save(s5p64x0_misc_save,
> ARRAY_SIZE(s5p64x0_misc_save));
> +
> + if ((__raw_readl(S5P64X0_SYS_ID) & 0xFF000) == 0x50000)
> + s3c_pm_do_save(s5p6450_core_save,
> + ARRAY_SIZE(s5p6450_core_save));
Same.
> +
> + s3c_pm_do_save(s5p64x0_core_save,
> ARRAY_SIZE(s5p64x0_core_save));
> +}
> +
> +static int s5p64x0_cpu_suspend(unsigned long arg)
> +{
> + unsigned long tmp = 0;
> +
> + /*
> + * Issue the standby signal into the pm unit. Note, we
> + * issue a write-buffer drain just in case.
> + */
> + asm("b 1f\n\t"
> + ".align 5\n\t"
> + "1:\n\t"
> + "mcr p15, 0, %0, c7, c10, 5\n\t"
> + "mcr p15, 0, %0, c7, c10, 4\n\t"
> + "mcr p15, 0, %0, c7, c0, 4" : : "r" (tmp));
> +
> + /* we should never get past here */
> + panic("sleep resumed to originator?");
> +}
> +
> +/* mapping of interrupts to parts of the wakeup mask */
> +static struct samsung_wakeup_mask s5p64x0_wake_irqs[] = {
> + { .irq = IRQ_RTC_ALARM, .bit =
> S5P64X0_PWRCFG_RTC_ALRM_DISABLE, },
> + { .irq = IRQ_RTC_TIC, .bit =
> S5P64X0_PWRCFG_RTC_TICK_DISABLE, },
> + { .irq = IRQ_HSMMC0, .bit = S5P64X0_PWRCFG_MMC0_DISABLE, },
> + { .irq = IRQ_HSMMC1, .bit = S5P64X0_PWRCFG_MMC1_DISABLE, },
> +};
> +
> +static void s5p64x0_pm_prepare(void)
> +{
> + u32 tmp;
> +
> + samsung_sync_wakemask(S5P64X0_PWR_CFG,
> + s5p64x0_wake_irqs, ARRAY_SIZE(s5p64x0_wake_irqs));
> +
> + /* store the resume address in INFORM0 register */
> + __raw_writel(virt_to_phys(s3c_cpu_resume), S5P64X0_INFORM0);
> +
> + /* setup clock gating for FIMGVG block */
> + __raw_writel((__raw_readl(S5P64X0_CLK_GATE_HCLK1) | \
> + (S5P64X0_CLKCON_HCLK1_FIMGVG)),
> S5P64X0_CLK_GATE_HCLK1);
> + __raw_writel((__raw_readl(S5P64X0_CLK_GATE_SCLK1) | \
> + (S5P64X0_CLKCON_SCLK1_FIMGVG)),
> S5P64X0_CLK_GATE_SCLK1);
> +
> + /* Configure the stabilization counter with wait time required */
> + __raw_writel(S5P64X0_PWR_STABLE_CNT_VAL_4,
> S5P64X0_PWR_STABLE);
> +
> + /* set WFI to SLEEP mode configuration */
> + tmp = __raw_readl(S5P64X0_SLEEP_CFG);
> + tmp &= ~(S5P64X0_SLEEP_CFG_OSC_EN);
> + __raw_writel(tmp, S5P64X0_SLEEP_CFG);
> +
> + tmp = __raw_readl(S5P64X0_PWR_CFG);
> + tmp &= ~(S5P64X0_PWRCFG_CFG_WFI_MASK);
> + tmp |= S5P64X0_PWRCFG_CFG_WFI_SLEEP;
> + __raw_writel(tmp, S5P64X0_PWR_CFG);
> +
> + /*
> + * set OTHERS register to disable interrupt before going to
> + * sleep. This bit is present only in S5P6450, it is reserved
> + * in S5P6440.
> + */
> + if ((__raw_readl(S5P64X0_SYS_ID) & 0xFF000) == 0x50000) {
> + tmp = __raw_readl(S5P64X0_OTHERS);
> + tmp |= S5P6450_OTHERS_DISABLE_INT;
> + __raw_writel(tmp, S5P64X0_OTHERS);
> + }
> +
> + /* ensure previous wakeup state is cleared before sleeping */
> + __raw_writel(__raw_readl(S5P64X0_WAKEUP_STAT),
> S5P64X0_WAKEUP_STAT);
> +
> +}
> +
> +static int s5p64x0_pm_add(struct sys_device *sysdev)
> +{
> + pm_cpu_prep = s5p64x0_pm_prepare;
> + pm_cpu_sleep = s5p64x0_cpu_suspend;
> + pm_uart_udivslot = 1;
If pm_uart_udivslot has value, the UDIVSLOT3 is used...is this right on
S5P64X0?
> +
> + return 0;
> +}
> +
> +static struct sysdev_driver s5p64x0_pm_driver = {
> + .add = s5p64x0_pm_add,
> +};
> +
> +static __init int s5p64x0_pm_drvinit(void)
> +{
> + s3c_pm_init();
> +
> + return sysdev_driver_register(&s5p64x0_sysclass,
&s5p64x0_pm_driver);
> +}
> +arch_initcall(s5p64x0_pm_drvinit);
> +
> +static void s5p64x0_pm_resume(void)
> +{
> + u32 tmp;
> +
> + tmp = __raw_readl(S5P64X0_OTHERS);
> + tmp |= (S5P64X0_OTHERS_RET_MMC0 |
> S5P64X0_OTHERS_RET_MMC1 | \
> + S5P64X0_OTHERS_RET_UART);
> + __raw_writel(tmp , S5P64X0_OTHERS);
> +}
> +
> +static struct syscore_ops s5p64x0_pm_syscore_ops = {
> + .resume = s5p64x0_pm_resume,
> +};
> +
> +static __init int s5p64x0_pm_syscore_init(void)
> +{
> + register_syscore_ops(&s5p64x0_pm_syscore_ops);
> +
> + return 0;
> +}
> +arch_initcall(s5p64x0_pm_syscore_init);
> --
> 1.7.4.1
Basically, this codes need small fixing. I mean if this codes have been
tested on board and it works fine, it's ok to me.
But as you said, s5p64x0 pm is almost same with s3c64xx, so we need to clean
them up next time :)
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH 5/5] ARM: S5P64X0: Add Power Management support
2011-09-07 6:01 ` Kukjin Kim
@ 2011-09-07 6:33 ` Abhilash Kesavan
-1 siblings, 0 replies; 40+ messages in thread
From: Abhilash Kesavan @ 2011-09-07 6:33 UTC (permalink / raw)
To: Kukjin Kim; +Cc: linux-arm-kernel, linux-samsung-soc
Hi Mr Kim,
On Wed, Sep 7, 2011 at 11:31 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Abhilash Kesavan wrote:
>>
>> Add suspend-to-ram support for SMDK6440/50
>>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> ---
>> arch/arm/Kconfig | 2 +-
>> arch/arm/mach-s5p64x0/Kconfig | 4 +
>> arch/arm/mach-s5p64x0/Makefile | 1 +
>> arch/arm/mach-s5p64x0/include/mach/map.h | 1 +
>> arch/arm/mach-s5p64x0/include/mach/pm-core.h | 117 +++++++++++++
>> arch/arm/mach-s5p64x0/include/mach/regs-clock.h | 33 ++++
>> arch/arm/mach-s5p64x0/include/mach/regs-gpio.h | 19 ++
>> arch/arm/mach-s5p64x0/irq-eint.c | 2 +
>> arch/arm/mach-s5p64x0/irq-pm.c | 92 ++++++++++
>> arch/arm/mach-s5p64x0/pm.c | 204
>> +++++++++++++++++++++++
>> 10 files changed, 474 insertions(+), 1 deletions(-)
>> create mode 100644 arch/arm/mach-s5p64x0/include/mach/pm-core.h
>> create mode 100644 arch/arm/mach-s5p64x0/irq-pm.c
>> create mode 100644 arch/arm/mach-s5p64x0/pm.c
>>
>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>> index 2c71a8f..47aed0d 100644
>> --- a/arch/arm/Kconfig
>> +++ b/arch/arm/Kconfig
>> @@ -2071,7 +2071,7 @@ menu "Power management options"
>> source "kernel/power/Kconfig"
>>
>> config ARCH_SUSPEND_POSSIBLE
>> - depends on !ARCH_S5P64X0 && !ARCH_S5PC100
>> + depends on !ARCH_S5PC100
>> depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
>> CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
>> def_bool y
>> diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
>> index 65c7518..d7f034a 100644
>> --- a/arch/arm/mach-s5p64x0/Kconfig
>> +++ b/arch/arm/mach-s5p64x0/Kconfig
>> @@ -11,6 +11,8 @@ config CPU_S5P6440
>> bool
>> select S3C_PL330_DMA
>> select S5P_HRT
>> + select SAMSUNG_SLEEP if PM
>> + select SAMSUNG_WAKEMASK if PM
>> help
>> Enable S5P6440 CPU support
>>
>> @@ -18,6 +20,8 @@ config CPU_S5P6450
>> bool
>> select S3C_PL330_DMA
>> select S5P_HRT
>> + select SAMSUNG_SLEEP if PM
>> + select SAMSUNG_WAKEMASK if PM
>> help
>> Enable S5P6450 CPU support
>>
>> diff --git a/arch/arm/mach-s5p64x0/Makefile
> b/arch/arm/mach-s5p64x0/Makefile
>> index 5f6afdf..acfebb7 100644
>> --- a/arch/arm/mach-s5p64x0/Makefile
>> +++ b/arch/arm/mach-s5p64x0/Makefile
>> @@ -16,6 +16,7 @@ obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o
>> clock.o dma.o gpiolib.o
>> obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o irq-eint.o
>> obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o
>> obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o
>> +obj-$(CONFIG_PM) += pm.o irq-pm.o
>>
>> # machine support
>>
>> diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-
>> s5p64x0/include/mach/map.h
>> index 95c9125..6138f7c 100644
>> --- a/arch/arm/mach-s5p64x0/include/mach/map.h
>> +++ b/arch/arm/mach-s5p64x0/include/mach/map.h
>> @@ -85,5 +85,6 @@
>> #define S5P_PA_UART5 S5P6450_PA_UART(5)
>>
>> #define S5P_SZ_UART SZ_256
>> +#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) *
>> S3C_UART_OFFSET))
>>
>> #endif /* __ASM_ARCH_MAP_H */
>> diff --git a/arch/arm/mach-s5p64x0/include/mach/pm-core.h b/arch/arm/mach-
>> s5p64x0/include/mach/pm-core.h
>> new file mode 100644
>> index 0000000..aee9d85
>> --- /dev/null
>> +++ b/arch/arm/mach-s5p64x0/include/mach/pm-core.h
>> @@ -0,0 +1,117 @@
>> +/* linux/arch/arm/mach-s5p64x0/include/mach/pm-core.h
>> + *
>> + * Copyright (c) 2011 Samsung Electronics Co., Ltd.
>> + * http://www.samsung.com
>> + *
>> + * S5P64X0 - PM core support for arch/arm/plat-samsung/pm.c
>> + *
>> + * Based on PM core support for S3C64XX by Ben Dooks
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include <mach/regs-gpio.h>
>> +
>> +static inline void s3c_pm_debug_init_uart(void)
>> +{
>> + u32 tmp = __raw_readl(S5P64X0_CLK_GATE_PCLK);
>> +
>> + /*
>> + * As a note, since the S5P64X0 UARTs generally have multiple
>> + * clock sources, we simply enable PCLK at the moment and hope
>> + * that the resume settings for the UART are suitable for the
>> + * use with PCLK.
>> + */
>> + tmp |= S5P64X0_CLKCON_PCLK_UART0;
>> + tmp |= S5P64X0_CLKCON_PCLK_UART1;
>> + tmp |= S5P64X0_CLKCON_PCLK_UART2;
>> + tmp |= S5P64X0_CLKCON_PCLK_UART3;
>> +
>> + __raw_writel(tmp, S5P64X0_CLK_GATE_PCLK);
>> + udelay(10);
>> +}
>> +
>> +static inline void s3c_pm_arch_prepare_irqs(void)
>> +{
>> + /* VIC should have already been taken care of */
>> +
>> + /* clear any pending EINT0 interrupts */
>> + __raw_writel(__raw_readl(S5P64X0_EINT0PEND), S5P64X0_EINT0PEND);
>> +}
>> +
>> +static inline void s3c_pm_arch_stop_clocks(void) { }
>> +static inline void s3c_pm_arch_show_resume_irqs(void) { }
>> +
>> +/*
>> + * make these defines, we currently do not have any need to change
>> + * the IRQ wake controls depending on the CPU we are running on
>> + */
>> +#define s3c_irqwake_eintallow ((1 << 16) - 1)
>> +#define s3c_irqwake_intallow (~0)
>> +
>> +static inline void s3c_pm_arch_update_uart(void __iomem *regs,
>> + struct pm_uart_save *save)
>> +{
>> + u32 ucon = __raw_readl(regs + S3C2410_UCON);
>> + u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
>> + u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
>> + u32 new_ucon;
>> + u32 delta;
>> +
>> + /*
>> + * S5P64X0 UART blocks only support level interrupts, so ensure that
>> + * when we restore unused UART blocks we force the level interrupt
>> + * settings.
>> + */
>> + save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
>> +
>> + /*
>> + * We have a constraint on changing the clock type of the UART
>> + * between UCLKx and PCLK, so ensure that when we restore UCON
>> + * that the CLK field is correctly modified if the bootloader
>> + * has changed anything.
>> + */
>> + if (ucon_clk != save_clk) {
>> + new_ucon = save->ucon;
>> + delta = ucon_clk ^ save_clk;
>> +
>> + /*
>> + * change from UCLKx => wrong PCLK,
>> + * either UCLK can be tested for by a bit-test
>> + * with UCLK0
>> + */
>> + if (ucon_clk & S3C6400_UCON_UCLK0 &&
>> + !(save_clk & S3C6400_UCON_UCLK0) &&
>> + delta & S3C6400_UCON_PCLK2) {
>> + new_ucon &= ~S3C6400_UCON_UCLK0;
>> + } else if (delta == S3C6400_UCON_PCLK2) {
>> + /*
>> + * as a precaution, don't change from
>> + * PCLK2 => PCLK or vice-versa
>> + */
>> + new_ucon ^= S3C6400_UCON_PCLK2;
>> + }
>> +
>> + S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
>> + ucon, new_ucon, save->ucon);
>> + save->ucon = new_ucon;
>> + }
>> +}
>> +
>> +static inline void s3c_pm_restored_gpios(void)
>> +{
>> + /* ensure sleep mode has been cleared from the system */
>> + __raw_writel(0, S5P64X0_SLPEN);
>> +}
>> +
>> +static inline void s3c_pm_saved_gpios(void)
>> +{
>> + /*
>> + * turn on the sleep mode and keep it there, as it seems that during
>> + * suspend the xCON registers get re-set and thus you can end up
> with
>> + * problems between going to sleep and resuming.
>> + */
>> + __raw_writel(S5P64X0_SLPEN_USE_xSLP, S5P64X0_SLPEN);
>> +}
>> diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
> b/arch/arm/mach-
>> s5p64x0/include/mach/regs-clock.h
>> index a133f22..75f66a9 100644
>> --- a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
>> +++ b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
>> @@ -41,17 +41,50 @@
>> #define S5P6450_DPLL_CON S5P_CLKREG(0x50)
>> #define S5P6450_DPLL_CON_K S5P_CLKREG(0x54)
>>
>> +#define S5P64X0_AHB_CON0 S5P_CLKREG(0x100)
>> #define S5P64X0_CLK_SRC1 S5P_CLKREG(0x10C)
>>
>> #define S5P64X0_SYS_ID S5P_CLKREG(0x118)
>> #define S5P64X0_SYS_OTHERS S5P_CLKREG(0x11C)
>>
>> #define S5P64X0_PWR_CFG S5P_CLKREG(0x804)
>> +#define S5P64X0_EINT_WAKEUP_MASK S5P_CLKREG(0x808)
>> +#define S5P64X0_SLEEP_CFG S5P_CLKREG(0x818)
>> +#define S5P64X0_PWR_STABLE S5P_CLKREG(0x828)
>> +
>> #define S5P64X0_OTHERS S5P_CLKREG(0x900)
>> +#define S5P64X0_WAKEUP_STAT S5P_CLKREG(0x908)
>> +
>> +#define S5P64X0_INFORM0 S5P_CLKREG(0xA00)
>>
>> #define S5P64X0_CLKDIV0_HCLK_SHIFT (8)
>> #define S5P64X0_CLKDIV0_HCLK_MASK (0xF <<
>> S5P64X0_CLKDIV0_HCLK_SHIFT)
>>
>> +/* HCLK GATE Registers */
>> +#define S5P64X0_CLKCON_HCLK1_FIMGVG (1<<2)
>
> Should be added blank around "<<" like (1 << 2).
> And if possible, the name should be same with datasheet like
> ...CLK_GATE_HCLK1_FIMGVG.
>
> Please don't make new name.
OK..will change
>
>> +#define S5P64X0_CLKCON_SCLK1_FIMGVG (1<<2)
>
> Same as above.
OK..will change
> ...CLK_GATE_SCLK1_FIMGVG
>
>> +
>> +/* PCLK GATE Registers */
>> +#define S5P64X0_CLKCON_PCLK_UART3 (1<<4)
>> +#define S5P64X0_CLKCON_PCLK_UART2 (1<<3)
>> +#define S5P64X0_CLKCON_PCLK_UART1 (1<<2)
>> +#define S5P64X0_CLKCON_PCLK_UART0 (1<<1)
>
> Same as above.
OK..will change
>
>> +
>> +#define S5P64X0_PWRCFG_MMC1_DISABLE (1 << 15)
>> +#define S5P64X0_PWRCFG_MMC0_DISABLE (1 << 14)
>> +#define S5P64X0_PWRCFG_RTC_TICK_DISABLE (1 << 11)
>> +#define S5P64X0_PWRCFG_RTC_ALRM_DISABLE (1 << 10)
>> +#define S5P64X0_PWRCFG_CFG_WFI_MASK (3 << 5)
>> +#define S5P64X0_PWRCFG_CFG_WFI_SLEEP (3 << 5)
>> +
>> +#define S5P64X0_SLEEP_CFG_OSC_EN (1 << 0)
>> +
>> +#define S5P64X0_PWR_STABLE_CNT_VAL_4 (4 << 0)
>
> Same...please use same name with datasheet.
would you like it to be PWR_STABLE_PWR_CNT_VAL_4 ?
>
>> +
>> +#define S5P6450_OTHERS_DISABLE_INT (1 << 31)
>> +#define S5P64X0_OTHERS_RET_UART (1 << 26)
>> +#define S5P64X0_OTHERS_RET_MMC1 (1 << 25)
>> +#define S5P64X0_OTHERS_RET_MMC0 (1 << 24)
>> #define S5P64X0_OTHERS_USB_SIG_MASK (1 << 16)
>>
>> /* Compatibility defines */
>> diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
> b/arch/arm/mach-
>> s5p64x0/include/mach/regs-gpio.h
>> index 6ce2547..27a2230 100644
>> --- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
>> +++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
>> @@ -34,14 +34,33 @@
>> #define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180)
>> #define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300)
>>
>> +#define S5P64X0_SPCON0 (S5P_VA_GPIO + 0x1A0)
>> +#define S5P64X0_SPCON1 (S5P_VA_GPIO + 0x2B0)
>> +
>> +#define S5P64X0_MEM0CONSLP0 (S5P_VA_GPIO + 0x1C0)
>> +#define S5P64X0_MEM0CONSLP1 (S5P_VA_GPIO + 0x1C4)
>> +#define S5P64X0_MEM0DRVCON (S5P_VA_GPIO + 0x1D0)
>> +#define S5P64X0_MEM1DRVCON (S5P_VA_GPIO + 0x1D4)
>> +
>> +#define S5P64X0_EINT12CON (S5P_VA_GPIO + 0x200)
>> +#define S5P64X0_EINT12FLTCON (S5P_VA_GPIO + 0x220)
>> +#define S5P64X0_EINT12MASK (S5P_VA_GPIO + 0x240)
>> +
>> /* External interrupt control registers for group0 */
>>
>> #define EINT0CON0_OFFSET (0x900)
>> +#define EINT0FLTCON0_OFFSET (0x910)
>> +#define EINT0FLTCON1_OFFSET (0x914)
>> #define EINT0MASK_OFFSET (0x920)
>> #define EINT0PEND_OFFSET (0x924)
>>
>> #define S5P64X0_EINT0CON0 (S5P_VA_GPIO +
>> EINT0CON0_OFFSET)
>> +#define S5P64X0_EINT0FLTCON0 (S5P_VA_GPIO +
>> EINT0FLTCON0_OFFSET)
>> +#define S5P64X0_EINT0FLTCON1 (S5P_VA_GPIO +
>> EINT0FLTCON1_OFFSET)
>> #define S5P64X0_EINT0MASK (S5P_VA_GPIO +
>> EINT0MASK_OFFSET)
>> #define S5P64X0_EINT0PEND (S5P_VA_GPIO +
>> EINT0PEND_OFFSET)
>>
>> +#define S5P64X0_SLPEN (S5P_VA_GPIO + 0x930)
>> +#define S5P64X0_SLPEN_USE_xSLP (1 << 0)
>> +
>> #endif /* __ASM_ARCH_REGS_GPIO_H */
>> diff --git a/arch/arm/mach-s5p64x0/irq-eint.c
> b/arch/arm/mach-s5p64x0/irq-eint.c
>> index fe7380f..3b94c6c 100644
>> --- a/arch/arm/mach-s5p64x0/irq-eint.c
>> +++ b/arch/arm/mach-s5p64x0/irq-eint.c
>> @@ -19,6 +19,7 @@
>>
>> #include <plat/regs-irqtype.h>
>> #include <plat/gpio-cfg.h>
>> +#include <plat/pm.h>
>>
>> #include <mach/regs-gpio.h>
>> #include <mach/regs-clock.h>
>> @@ -133,6 +134,7 @@ static int s5p64x0_alloc_gc(void)
>> ct->chip.irq_mask = irq_gc_mask_set_bit;
>> ct->chip.irq_unmask = irq_gc_mask_clr_bit;
>> ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
>> + ct->chip.irq_set_wake = s3c_irqext_wake;
>> ct->regs.ack = EINT0PEND_OFFSET;
>> ct->regs.mask = EINT0MASK_OFFSET;
>> irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
>> diff --git a/arch/arm/mach-s5p64x0/irq-pm.c
> b/arch/arm/mach-s5p64x0/irq-pm.c
>> new file mode 100644
>> index 0000000..3e6f245
>> --- /dev/null
>> +++ b/arch/arm/mach-s5p64x0/irq-pm.c
>> @@ -0,0 +1,92 @@
>> +/* linux/arch/arm/mach-s5p64x0/irq-pm.c
>> + *
>> + * Copyright (c) 2011 Samsung Electronics Co., Ltd.
>> + * http://www.samsung.com
>> + *
>> + * S5P64X0 - Interrupt handling Power Management
>> + *
>> + * Based on arch/arm/mach-s3c64xx/irq-pm.c by Ben Dooks
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include <linux/syscore_ops.h>
>> +#include <linux/serial_core.h>
>> +#include <linux/io.h>
>> +
>> +#include <plat/regs-serial.h>
>> +#include <plat/pm.h>
>> +
>> +#include <mach/regs-gpio.h>
>> +
>> +static struct sleep_save irq_save[] = {
>> + SAVE_ITEM(S5P64X0_EINT0CON0),
>> + SAVE_ITEM(S5P64X0_EINT0FLTCON0),
>> + SAVE_ITEM(S5P64X0_EINT0FLTCON1),
>> + SAVE_ITEM(S5P64X0_EINT0MASK),
>> +};
>> +
>> +static struct irq_grp_save {
>> + u32 con;
>> + u32 fltcon;
>> + u32 mask;
>> +} eint_grp_save[4];
>> +
>> +static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS];
>> +
>> +static int s5p64x0_irq_pm_suspend(void)
>> +{
>> + struct irq_grp_save *grp = eint_grp_save;
>> + int i;
>> +
>> + S3C_PMDBG("%s: suspending IRQs\n", __func__);
>> +
>> + s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
>> +
>> + for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
>> + irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) +
>> S3C64XX_UINTM);
>> +
>> + for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
>> + grp->con = __raw_readl(S5P64X0_EINT12CON + (i * 4));
>> + grp->mask = __raw_readl(S5P64X0_EINT12MASK + (i * 4));
>> + grp->fltcon = __raw_readl(S5P64X0_EINT12FLTCON + (i * 4));
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static void s5p64x0_irq_pm_resume(void)
>> +{
>> + struct irq_grp_save *grp = eint_grp_save;
>> + int i;
>> +
>> + S3C_PMDBG("%s: resuming IRQs\n", __func__);
>> +
>> + s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
>> +
>> + for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
>> + __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) +
>> S3C64XX_UINTM);
>> +
>> + for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
>> + __raw_writel(grp->con, S5P64X0_EINT12CON + (i * 4));
>> + __raw_writel(grp->mask, S5P64X0_EINT12MASK + (i * 4));
>> + __raw_writel(grp->fltcon, S5P64X0_EINT12FLTCON + (i * 4));
>> + }
>> +
>> + S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
>> +}
>> +
>> +static struct syscore_ops s5p64x0_irq_syscore_ops = {
>> + .suspend = s5p64x0_irq_pm_suspend,
>> + .resume = s5p64x0_irq_pm_resume,
>> +};
>> +
>> +static int __init s5p64x0_syscore_init(void)
>> +{
>> + register_syscore_ops(&s5p64x0_irq_syscore_ops);
>> +
>> + return 0;
>> +}
>> +core_initcall(s5p64x0_syscore_init);
>> diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c
>> new file mode 100644
>> index 0000000..cced4fb
>> --- /dev/null
>> +++ b/arch/arm/mach-s5p64x0/pm.c
>> @@ -0,0 +1,204 @@
>> +/* linux/arch/arm/mach-s5p64x0/pm.c
>> + *
>> + * Copyright (c) 2011 Samsung Electronics Co., Ltd.
>> + * http://www.samsung.com
>> + *
>> + * S5P64X0 Power Management Support
>> + *
>> + * Based on arch/arm/mach-s3c64xx/pm.c by Ben Dooks
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> +*/
>> +
>> +#include <linux/suspend.h>
>> +#include <linux/syscore_ops.h>
>> +#include <linux/io.h>
>> +
>> +#include <plat/cpu.h>
>> +#include <plat/pm.h>
>> +#include <plat/regs-timer.h>
>> +#include <plat/wakeup-mask.h>
>> +
>> +#include <mach/regs-clock.h>
>> +#include <mach/regs-gpio.h>
>> +
>> +static struct sleep_save s5p64x0_core_save[] = {
>> + SAVE_ITEM(S5P64X0_APLL_CON),
>> + SAVE_ITEM(S5P64X0_MPLL_CON),
>> + SAVE_ITEM(S5P64X0_EPLL_CON),
>> + SAVE_ITEM(S5P64X0_EPLL_CON_K),
>> + SAVE_ITEM(S5P64X0_CLK_SRC0),
>> + SAVE_ITEM(S5P64X0_CLK_SRC1),
>> + SAVE_ITEM(S5P64X0_CLK_DIV0),
>> + SAVE_ITEM(S5P64X0_CLK_DIV1),
>> + SAVE_ITEM(S5P64X0_CLK_DIV2),
>> + SAVE_ITEM(S5P64X0_CLK_DIV3),
>> + SAVE_ITEM(S5P64X0_CLK_GATE_MEM0),
>> + SAVE_ITEM(S5P64X0_CLK_GATE_HCLK1),
>> + SAVE_ITEM(S5P64X0_CLK_GATE_SCLK1),
>> +};
>> +
>> +static struct sleep_save s5p64x0_misc_save[] = {
>> + SAVE_ITEM(S5P64X0_AHB_CON0),
>> + SAVE_ITEM(S5P64X0_SPCON0),
>> + SAVE_ITEM(S5P64X0_SPCON1),
>> + SAVE_ITEM(S5P64X0_MEM0CONSLP0),
>> + SAVE_ITEM(S5P64X0_MEM0CONSLP1),
>> + SAVE_ITEM(S5P64X0_MEM0DRVCON),
>> + SAVE_ITEM(S5P64X0_MEM1DRVCON),
>> +
>> + SAVE_ITEM(S3C64XX_TINT_CSTAT),
>> +};
>> +
>> +/* DPLL is present only in S5P6450 */
>> +static struct sleep_save s5p6450_core_save[] = {
>> + SAVE_ITEM(S5P6450_DPLL_CON),
>> + SAVE_ITEM(S5P6450_DPLL_CON_K),
>> +};
>> +
>> +void s3c_pm_configure_extint(void)
>> +{
>> + __raw_writel(s3c_irqwake_eintmask, S5P64X0_EINT_WAKEUP_MASK);
>> +}
>> +
>> +void s3c_pm_restore_core(void)
>> +{
>> + __raw_writel(0, S5P64X0_EINT_WAKEUP_MASK);
>> +
>> + s3c_pm_do_restore_core(s5p64x0_core_save,
>> + ARRAY_SIZE(s5p64x0_core_save));
>> +
>> + if ((__raw_readl(S5P64X0_SYS_ID) & 0xFF000) == 0x50000)
>> + s3c_pm_do_restore_core(s5p6450_core_save,
>> + ARRAY_SIZE(s5p6450_core_save));
>
> You can use soc_is_xxx() here.
Yep, wasn't there when I posted the series. Will change.
>
>> +
>> + s3c_pm_do_restore(s5p64x0_misc_save,
>> ARRAY_SIZE(s5p64x0_misc_save));
>> +}
>> +
>> +void s3c_pm_save_core(void)
>> +{
>> + s3c_pm_do_save(s5p64x0_misc_save,
>> ARRAY_SIZE(s5p64x0_misc_save));
>> +
>> + if ((__raw_readl(S5P64X0_SYS_ID) & 0xFF000) == 0x50000)
>> + s3c_pm_do_save(s5p6450_core_save,
>> + ARRAY_SIZE(s5p6450_core_save));
>
> Same.
>
>> +
>> + s3c_pm_do_save(s5p64x0_core_save,
>> ARRAY_SIZE(s5p64x0_core_save));
>> +}
>> +
>> +static int s5p64x0_cpu_suspend(unsigned long arg)
>> +{
>> + unsigned long tmp = 0;
>> +
>> + /*
>> + * Issue the standby signal into the pm unit. Note, we
>> + * issue a write-buffer drain just in case.
>> + */
>> + asm("b 1f\n\t"
>> + ".align 5\n\t"
>> + "1:\n\t"
>> + "mcr p15, 0, %0, c7, c10, 5\n\t"
>> + "mcr p15, 0, %0, c7, c10, 4\n\t"
>> + "mcr p15, 0, %0, c7, c0, 4" : : "r" (tmp));
>> +
>> + /* we should never get past here */
>> + panic("sleep resumed to originator?");
>> +}
>> +
>> +/* mapping of interrupts to parts of the wakeup mask */
>> +static struct samsung_wakeup_mask s5p64x0_wake_irqs[] = {
>> + { .irq = IRQ_RTC_ALARM, .bit =
>> S5P64X0_PWRCFG_RTC_ALRM_DISABLE, },
>> + { .irq = IRQ_RTC_TIC, .bit =
>> S5P64X0_PWRCFG_RTC_TICK_DISABLE, },
>> + { .irq = IRQ_HSMMC0, .bit = S5P64X0_PWRCFG_MMC0_DISABLE, },
>> + { .irq = IRQ_HSMMC1, .bit = S5P64X0_PWRCFG_MMC1_DISABLE, },
>> +};
>> +
>> +static void s5p64x0_pm_prepare(void)
>> +{
>> + u32 tmp;
>> +
>> + samsung_sync_wakemask(S5P64X0_PWR_CFG,
>> + s5p64x0_wake_irqs, ARRAY_SIZE(s5p64x0_wake_irqs));
>> +
>> + /* store the resume address in INFORM0 register */
>> + __raw_writel(virt_to_phys(s3c_cpu_resume), S5P64X0_INFORM0);
>> +
>> + /* setup clock gating for FIMGVG block */
>> + __raw_writel((__raw_readl(S5P64X0_CLK_GATE_HCLK1) | \
>> + (S5P64X0_CLKCON_HCLK1_FIMGVG)),
>> S5P64X0_CLK_GATE_HCLK1);
>> + __raw_writel((__raw_readl(S5P64X0_CLK_GATE_SCLK1) | \
>> + (S5P64X0_CLKCON_SCLK1_FIMGVG)),
>> S5P64X0_CLK_GATE_SCLK1);
>> +
>> + /* Configure the stabilization counter with wait time required */
>> + __raw_writel(S5P64X0_PWR_STABLE_CNT_VAL_4,
>> S5P64X0_PWR_STABLE);
>> +
>> + /* set WFI to SLEEP mode configuration */
>> + tmp = __raw_readl(S5P64X0_SLEEP_CFG);
>> + tmp &= ~(S5P64X0_SLEEP_CFG_OSC_EN);
>> + __raw_writel(tmp, S5P64X0_SLEEP_CFG);
>> +
>> + tmp = __raw_readl(S5P64X0_PWR_CFG);
>> + tmp &= ~(S5P64X0_PWRCFG_CFG_WFI_MASK);
>> + tmp |= S5P64X0_PWRCFG_CFG_WFI_SLEEP;
>> + __raw_writel(tmp, S5P64X0_PWR_CFG);
>> +
>> + /*
>> + * set OTHERS register to disable interrupt before going to
>> + * sleep. This bit is present only in S5P6450, it is reserved
>> + * in S5P6440.
>> + */
>> + if ((__raw_readl(S5P64X0_SYS_ID) & 0xFF000) == 0x50000) {
>> + tmp = __raw_readl(S5P64X0_OTHERS);
>> + tmp |= S5P6450_OTHERS_DISABLE_INT;
>> + __raw_writel(tmp, S5P64X0_OTHERS);
>> + }
>> +
>> + /* ensure previous wakeup state is cleared before sleeping */
>> + __raw_writel(__raw_readl(S5P64X0_WAKEUP_STAT),
>> S5P64X0_WAKEUP_STAT);
>> +
>> +}
>> +
>> +static int s5p64x0_pm_add(struct sys_device *sysdev)
>> +{
>> + pm_cpu_prep = s5p64x0_pm_prepare;
>> + pm_cpu_sleep = s5p64x0_cpu_suspend;
>> + pm_uart_udivslot = 1;
>
> If pm_uart_udivslot has value, the UDIVSLOT3 is used...is this right on
> S5P64X0?
UDIVSLOT at an offset of 2C seems fine for 64X0.
>
>> +
>> + return 0;
>> +}
>> +
>> +static struct sysdev_driver s5p64x0_pm_driver = {
>> + .add = s5p64x0_pm_add,
>> +};
>> +
>> +static __init int s5p64x0_pm_drvinit(void)
>> +{
>> + s3c_pm_init();
>> +
>> + return sysdev_driver_register(&s5p64x0_sysclass,
> &s5p64x0_pm_driver);
>> +}
>> +arch_initcall(s5p64x0_pm_drvinit);
>> +
>> +static void s5p64x0_pm_resume(void)
>> +{
>> + u32 tmp;
>> +
>> + tmp = __raw_readl(S5P64X0_OTHERS);
>> + tmp |= (S5P64X0_OTHERS_RET_MMC0 |
>> S5P64X0_OTHERS_RET_MMC1 | \
>> + S5P64X0_OTHERS_RET_UART);
>> + __raw_writel(tmp , S5P64X0_OTHERS);
>> +}
>> +
>> +static struct syscore_ops s5p64x0_pm_syscore_ops = {
>> + .resume = s5p64x0_pm_resume,
>> +};
>> +
>> +static __init int s5p64x0_pm_syscore_init(void)
>> +{
>> + register_syscore_ops(&s5p64x0_pm_syscore_ops);
>> +
>> + return 0;
>> +}
>> +arch_initcall(s5p64x0_pm_syscore_init);
>> --
>> 1.7.4.1
>
> Basically, this codes need small fixing. I mean if this codes have been
> tested on board and it works fine, it's ok to me.
>
> But as you said, s5p64x0 pm is almost same with s3c64xx, so we need to clean
> them up next time :)
Has been tested for 6440 and 6450. Thanks for the review.
>
> Thanks.
>
> Best regards,
> Kgene.
Abhilash
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 40+ messages in thread* [PATCH 5/5] ARM: S5P64X0: Add Power Management support
@ 2011-09-07 6:33 ` Abhilash Kesavan
0 siblings, 0 replies; 40+ messages in thread
From: Abhilash Kesavan @ 2011-09-07 6:33 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mr Kim,
On Wed, Sep 7, 2011 at 11:31 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Abhilash Kesavan wrote:
>>
>> Add suspend-to-ram support for SMDK6440/50
>>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> ---
>> ?arch/arm/Kconfig ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?| ? ?2 +-
>> ?arch/arm/mach-s5p64x0/Kconfig ? ? ? ? ? ? ? ? ? | ? ?4 +
>> ?arch/arm/mach-s5p64x0/Makefile ? ? ? ? ? ? ? ? ?| ? ?1 +
>> ?arch/arm/mach-s5p64x0/include/mach/map.h ? ? ? ?| ? ?1 +
>> ?arch/arm/mach-s5p64x0/include/mach/pm-core.h ? ?| ?117 +++++++++++++
>> ?arch/arm/mach-s5p64x0/include/mach/regs-clock.h | ? 33 ++++
>> ?arch/arm/mach-s5p64x0/include/mach/regs-gpio.h ?| ? 19 ++
>> ?arch/arm/mach-s5p64x0/irq-eint.c ? ? ? ? ? ? ? ?| ? ?2 +
>> ?arch/arm/mach-s5p64x0/irq-pm.c ? ? ? ? ? ? ? ? ?| ? 92 ++++++++++
>> ?arch/arm/mach-s5p64x0/pm.c ? ? ? ? ? ? ? ? ? ? ?| ?204
>> +++++++++++++++++++++++
>> ?10 files changed, 474 insertions(+), 1 deletions(-)
>> ?create mode 100644 arch/arm/mach-s5p64x0/include/mach/pm-core.h
>> ?create mode 100644 arch/arm/mach-s5p64x0/irq-pm.c
>> ?create mode 100644 arch/arm/mach-s5p64x0/pm.c
>>
>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>> index 2c71a8f..47aed0d 100644
>> --- a/arch/arm/Kconfig
>> +++ b/arch/arm/Kconfig
>> @@ -2071,7 +2071,7 @@ menu "Power management options"
>> ?source "kernel/power/Kconfig"
>>
>> ?config ARCH_SUSPEND_POSSIBLE
>> - ? ? depends on !ARCH_S5P64X0 && !ARCH_S5PC100
>> + ? ? depends on !ARCH_S5PC100
>> ? ? ? depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
>> ? ? ? ? ? ? ? CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
>> ? ? ? def_bool y
>> diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
>> index 65c7518..d7f034a 100644
>> --- a/arch/arm/mach-s5p64x0/Kconfig
>> +++ b/arch/arm/mach-s5p64x0/Kconfig
>> @@ -11,6 +11,8 @@ config CPU_S5P6440
>> ? ? ? bool
>> ? ? ? select S3C_PL330_DMA
>> ? ? ? select S5P_HRT
>> + ? ? select SAMSUNG_SLEEP if PM
>> + ? ? select SAMSUNG_WAKEMASK if PM
>> ? ? ? help
>> ? ? ? ? Enable S5P6440 CPU support
>>
>> @@ -18,6 +20,8 @@ config CPU_S5P6450
>> ? ? ? bool
>> ? ? ? select S3C_PL330_DMA
>> ? ? ? select S5P_HRT
>> + ? ? select SAMSUNG_SLEEP if PM
>> + ? ? select SAMSUNG_WAKEMASK if PM
>> ? ? ? help
>> ? ? ? ? Enable S5P6450 CPU support
>>
>> diff --git a/arch/arm/mach-s5p64x0/Makefile
> b/arch/arm/mach-s5p64x0/Makefile
>> index 5f6afdf..acfebb7 100644
>> --- a/arch/arm/mach-s5p64x0/Makefile
>> +++ b/arch/arm/mach-s5p64x0/Makefile
>> @@ -16,6 +16,7 @@ obj-$(CONFIG_ARCH_S5P64X0) ?+= cpu.o init.o
>> clock.o dma.o gpiolib.o
>> ?obj-$(CONFIG_ARCH_S5P64X0) ? += setup-i2c0.o irq-eint.o
>> ?obj-$(CONFIG_CPU_S5P6440) ? ?+= clock-s5p6440.o
>> ?obj-$(CONFIG_CPU_S5P6450) ? ?+= clock-s5p6450.o
>> +obj-$(CONFIG_PM) ? ? ? ? ? ? += pm.o irq-pm.o
>>
>> ?# machine support
>>
>> diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-
>> s5p64x0/include/mach/map.h
>> index 95c9125..6138f7c 100644
>> --- a/arch/arm/mach-s5p64x0/include/mach/map.h
>> +++ b/arch/arm/mach-s5p64x0/include/mach/map.h
>> @@ -85,5 +85,6 @@
>> ?#define S5P_PA_UART5 ? ? ? ? S5P6450_PA_UART(5)
>>
>> ?#define S5P_SZ_UART ? ? ? ? ?SZ_256
>> +#define S3C_VA_UARTx(x) ? ? ? ? ? ? ?(S3C_VA_UART + ((x) *
>> S3C_UART_OFFSET))
>>
>> ?#endif /* __ASM_ARCH_MAP_H */
>> diff --git a/arch/arm/mach-s5p64x0/include/mach/pm-core.h b/arch/arm/mach-
>> s5p64x0/include/mach/pm-core.h
>> new file mode 100644
>> index 0000000..aee9d85
>> --- /dev/null
>> +++ b/arch/arm/mach-s5p64x0/include/mach/pm-core.h
>> @@ -0,0 +1,117 @@
>> +/* linux/arch/arm/mach-s5p64x0/include/mach/pm-core.h
>> + *
>> + * Copyright (c) 2011 Samsung Electronics Co., Ltd.
>> + * ? ? ? ? ? http://www.samsung.com
>> + *
>> + * S5P64X0 - PM core support for arch/arm/plat-samsung/pm.c
>> + *
>> + * Based on PM core support for S3C64XX by Ben Dooks
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include <mach/regs-gpio.h>
>> +
>> +static inline void s3c_pm_debug_init_uart(void)
>> +{
>> + ? ? u32 tmp = __raw_readl(S5P64X0_CLK_GATE_PCLK);
>> +
>> + ? ? /*
>> + ? ? ?* As a note, since the S5P64X0 UARTs generally have multiple
>> + ? ? ?* clock sources, we simply enable PCLK at the moment and hope
>> + ? ? ?* that the resume settings for the UART are suitable for the
>> + ? ? ?* use with PCLK.
>> + ? ? ?*/
>> + ? ? tmp |= S5P64X0_CLKCON_PCLK_UART0;
>> + ? ? tmp |= S5P64X0_CLKCON_PCLK_UART1;
>> + ? ? tmp |= S5P64X0_CLKCON_PCLK_UART2;
>> + ? ? tmp |= S5P64X0_CLKCON_PCLK_UART3;
>> +
>> + ? ? __raw_writel(tmp, S5P64X0_CLK_GATE_PCLK);
>> + ? ? udelay(10);
>> +}
>> +
>> +static inline void s3c_pm_arch_prepare_irqs(void)
>> +{
>> + ? ? /* VIC should have already been taken care of */
>> +
>> + ? ? /* clear any pending EINT0 interrupts */
>> + ? ? __raw_writel(__raw_readl(S5P64X0_EINT0PEND), S5P64X0_EINT0PEND);
>> +}
>> +
>> +static inline void s3c_pm_arch_stop_clocks(void) { }
>> +static inline void s3c_pm_arch_show_resume_irqs(void) { }
>> +
>> +/*
>> + * make these defines, we currently do not have any need to change
>> + * the IRQ wake controls depending on the CPU we are running on
>> + */
>> +#define s3c_irqwake_eintallow ? ? ? ?((1 << 16) - 1)
>> +#define s3c_irqwake_intallow (~0)
>> +
>> +static inline void s3c_pm_arch_update_uart(void __iomem *regs,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct pm_uart_save *save)
>> +{
>> + ? ? u32 ucon = __raw_readl(regs + S3C2410_UCON);
>> + ? ? u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
>> + ? ? u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
>> + ? ? u32 new_ucon;
>> + ? ? u32 delta;
>> +
>> + ? ? /*
>> + ? ? ?* S5P64X0 UART blocks only support level interrupts, so ensure that
>> + ? ? ?* when we restore unused UART blocks we force the level interrupt
>> + ? ? ?* settings.
>> + ? ? ?*/
>> + ? ? save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
>> +
>> + ? ? /*
>> + ? ? ?* We have a constraint on changing the clock type of the UART
>> + ? ? ?* between UCLKx and PCLK, so ensure that when we restore UCON
>> + ? ? ?* that the CLK field is correctly modified if the bootloader
>> + ? ? ?* has changed anything.
>> + ? ? ?*/
>> + ? ? if (ucon_clk != save_clk) {
>> + ? ? ? ? ? ? new_ucon = save->ucon;
>> + ? ? ? ? ? ? delta = ucon_clk ^ save_clk;
>> +
>> + ? ? ? ? ? ? /*
>> + ? ? ? ? ? ? ?* change from UCLKx => wrong PCLK,
>> + ? ? ? ? ? ? ?* either UCLK can be tested for by a bit-test
>> + ? ? ? ? ? ? ?* with UCLK0
>> + ? ? ? ? ? ? ?*/
>> + ? ? ? ? ? ? if (ucon_clk & S3C6400_UCON_UCLK0 &&
>> + ? ? ? ? ? ? !(save_clk & S3C6400_UCON_UCLK0) &&
>> + ? ? ? ? ? ? delta & S3C6400_UCON_PCLK2) {
>> + ? ? ? ? ? ? ? ? ? ? new_ucon &= ~S3C6400_UCON_UCLK0;
>> + ? ? ? ? ? ? } else if (delta == S3C6400_UCON_PCLK2) {
>> + ? ? ? ? ? ? ? ? ? ? /*
>> + ? ? ? ? ? ? ? ? ? ? ?* as a precaution, don't change from
>> + ? ? ? ? ? ? ? ? ? ? ?* PCLK2 => PCLK or vice-versa
>> + ? ? ? ? ? ? ? ? ? ? ?*/
>> + ? ? ? ? ? ? ? ? ? ? new_ucon ^= S3C6400_UCON_PCLK2;
>> + ? ? ? ? ? ? }
>> +
>> + ? ? ? ? ? ? S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
>> + ? ? ? ? ? ? ? ? ? ? ucon, new_ucon, save->ucon);
>> + ? ? ? ? ? ? save->ucon = new_ucon;
>> + ? ? }
>> +}
>> +
>> +static inline void s3c_pm_restored_gpios(void)
>> +{
>> + ? ? /* ensure sleep mode has been cleared from the system */
>> + ? ? __raw_writel(0, S5P64X0_SLPEN);
>> +}
>> +
>> +static inline void s3c_pm_saved_gpios(void)
>> +{
>> + ? ? /*
>> + ? ? ?* turn on the sleep mode and keep it there, as it seems that during
>> + ? ? ?* suspend the xCON registers get re-set and thus you can end up
> with
>> + ? ? ?* problems between going to sleep and resuming.
>> + ? ? ?*/
>> + ? ? __raw_writel(S5P64X0_SLPEN_USE_xSLP, S5P64X0_SLPEN);
>> +}
>> diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
> b/arch/arm/mach-
>> s5p64x0/include/mach/regs-clock.h
>> index a133f22..75f66a9 100644
>> --- a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
>> +++ b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
>> @@ -41,17 +41,50 @@
>> ?#define S5P6450_DPLL_CON ? ? ? ? ? ? S5P_CLKREG(0x50)
>> ?#define S5P6450_DPLL_CON_K ? ? ? ? ? S5P_CLKREG(0x54)
>>
>> +#define S5P64X0_AHB_CON0 ? ? ? ? ? ? S5P_CLKREG(0x100)
>> ?#define S5P64X0_CLK_SRC1 ? ? ? ? ? ? S5P_CLKREG(0x10C)
>>
>> ?#define S5P64X0_SYS_ID ? ? ? ? ? ? ? ? ? ? ? S5P_CLKREG(0x118)
>> ?#define S5P64X0_SYS_OTHERS ? ? ? ? ? S5P_CLKREG(0x11C)
>>
>> ?#define S5P64X0_PWR_CFG ? ? ? ? ? ? ? ? ? ? ?S5P_CLKREG(0x804)
>> +#define S5P64X0_EINT_WAKEUP_MASK ? ? S5P_CLKREG(0x808)
>> +#define S5P64X0_SLEEP_CFG ? ? ? ? ? ?S5P_CLKREG(0x818)
>> +#define S5P64X0_PWR_STABLE ? ? ? ? ? S5P_CLKREG(0x828)
>> +
>> ?#define S5P64X0_OTHERS ? ? ? ? ? ? ? ? ? ? ? S5P_CLKREG(0x900)
>> +#define S5P64X0_WAKEUP_STAT ? ? ? ? ?S5P_CLKREG(0x908)
>> +
>> +#define S5P64X0_INFORM0 ? ? ? ? ? ? ? ? ? ? ?S5P_CLKREG(0xA00)
>>
>> ?#define S5P64X0_CLKDIV0_HCLK_SHIFT ? (8)
>> ?#define S5P64X0_CLKDIV0_HCLK_MASK ? ?(0xF <<
>> S5P64X0_CLKDIV0_HCLK_SHIFT)
>>
>> +/* HCLK GATE Registers */
>> +#define S5P64X0_CLKCON_HCLK1_FIMGVG ?(1<<2)
>
> Should be added blank around "<<" like (1 << 2).
> And if possible, the name should be same with datasheet like
> ...CLK_GATE_HCLK1_FIMGVG.
>
> Please don't make new name.
OK..will change
>
>> +#define S5P64X0_CLKCON_SCLK1_FIMGVG ?(1<<2)
>
> Same as above.
OK..will change
> ...CLK_GATE_SCLK1_FIMGVG
>
>> +
>> +/* PCLK GATE Registers */
>> +#define S5P64X0_CLKCON_PCLK_UART3 ? ?(1<<4)
>> +#define S5P64X0_CLKCON_PCLK_UART2 ? ?(1<<3)
>> +#define S5P64X0_CLKCON_PCLK_UART1 ? ?(1<<2)
>> +#define S5P64X0_CLKCON_PCLK_UART0 ? ?(1<<1)
>
> Same as above.
OK..will change
>
>> +
>> +#define S5P64X0_PWRCFG_MMC1_DISABLE ?(1 << 15)
>> +#define S5P64X0_PWRCFG_MMC0_DISABLE ?(1 << 14)
>> +#define S5P64X0_PWRCFG_RTC_TICK_DISABLE ? ? ?(1 << 11)
>> +#define S5P64X0_PWRCFG_RTC_ALRM_DISABLE ? ? ?(1 << 10)
>> +#define S5P64X0_PWRCFG_CFG_WFI_MASK ?(3 << 5)
>> +#define S5P64X0_PWRCFG_CFG_WFI_SLEEP (3 << 5)
>> +
>> +#define S5P64X0_SLEEP_CFG_OSC_EN ? ? (1 << 0)
>> +
>> +#define S5P64X0_PWR_STABLE_CNT_VAL_4 (4 << 0)
>
> Same...please use same name with datasheet.
would you like it to be PWR_STABLE_PWR_CNT_VAL_4 ?
>
>> +
>> +#define S5P6450_OTHERS_DISABLE_INT ? (1 << 31)
>> +#define S5P64X0_OTHERS_RET_UART ? ? ? ? ? ? ?(1 << 26)
>> +#define S5P64X0_OTHERS_RET_MMC1 ? ? ? ? ? ? ?(1 << 25)
>> +#define S5P64X0_OTHERS_RET_MMC0 ? ? ? ? ? ? ?(1 << 24)
>> ?#define S5P64X0_OTHERS_USB_SIG_MASK ?(1 << 16)
>>
>> ?/* Compatibility defines */
>> diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
> b/arch/arm/mach-
>> s5p64x0/include/mach/regs-gpio.h
>> index 6ce2547..27a2230 100644
>> --- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
>> +++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
>> @@ -34,14 +34,33 @@
>> ?#define S5P6450_GPQ_BASE ? ? ? ? ? ? (S5P_VA_GPIO + 0x0180)
>> ?#define S5P6450_GPS_BASE ? ? ? ? ? ? (S5P_VA_GPIO + 0x0300)
>>
>> +#define S5P64X0_SPCON0 ? ? ? ? ? ? ? ? ? ? ? (S5P_VA_GPIO + 0x1A0)
>> +#define S5P64X0_SPCON1 ? ? ? ? ? ? ? ? ? ? ? (S5P_VA_GPIO + 0x2B0)
>> +
>> +#define S5P64X0_MEM0CONSLP0 ? ? ? ? ?(S5P_VA_GPIO + 0x1C0)
>> +#define S5P64X0_MEM0CONSLP1 ? ? ? ? ?(S5P_VA_GPIO + 0x1C4)
>> +#define S5P64X0_MEM0DRVCON ? ? ? ? ? (S5P_VA_GPIO + 0x1D0)
>> +#define S5P64X0_MEM1DRVCON ? ? ? ? ? (S5P_VA_GPIO + 0x1D4)
>> +
>> +#define S5P64X0_EINT12CON ? ? ? ? ? ?(S5P_VA_GPIO + 0x200)
>> +#define S5P64X0_EINT12FLTCON ? ? ? ? (S5P_VA_GPIO + 0x220)
>> +#define S5P64X0_EINT12MASK ? ? ? ? ? (S5P_VA_GPIO + 0x240)
>> +
>> ?/* External interrupt control registers for group0 */
>>
>> ?#define EINT0CON0_OFFSET ? ? ? ? ? ? (0x900)
>> +#define EINT0FLTCON0_OFFSET ? ? ? ? ?(0x910)
>> +#define EINT0FLTCON1_OFFSET ? ? ? ? ?(0x914)
>> ?#define EINT0MASK_OFFSET ? ? ? ? ? ? (0x920)
>> ?#define EINT0PEND_OFFSET ? ? ? ? ? ? (0x924)
>>
>> ?#define S5P64X0_EINT0CON0 ? ? ? ? ? ?(S5P_VA_GPIO +
>> EINT0CON0_OFFSET)
>> +#define S5P64X0_EINT0FLTCON0 ? ? ? ? (S5P_VA_GPIO +
>> EINT0FLTCON0_OFFSET)
>> +#define S5P64X0_EINT0FLTCON1 ? ? ? ? (S5P_VA_GPIO +
>> EINT0FLTCON1_OFFSET)
>> ?#define S5P64X0_EINT0MASK ? ? ? ? ? ?(S5P_VA_GPIO +
>> EINT0MASK_OFFSET)
>> ?#define S5P64X0_EINT0PEND ? ? ? ? ? ?(S5P_VA_GPIO +
>> EINT0PEND_OFFSET)
>>
>> +#define S5P64X0_SLPEN ? ? ? ? ? ? ? ? ? ? ? ?(S5P_VA_GPIO + 0x930)
>> +#define S5P64X0_SLPEN_USE_xSLP ? ? ? ? ? ? ? (1 << 0)
>> +
>> ?#endif /* __ASM_ARCH_REGS_GPIO_H */
>> diff --git a/arch/arm/mach-s5p64x0/irq-eint.c
> b/arch/arm/mach-s5p64x0/irq-eint.c
>> index fe7380f..3b94c6c 100644
>> --- a/arch/arm/mach-s5p64x0/irq-eint.c
>> +++ b/arch/arm/mach-s5p64x0/irq-eint.c
>> @@ -19,6 +19,7 @@
>>
>> ?#include <plat/regs-irqtype.h>
>> ?#include <plat/gpio-cfg.h>
>> +#include <plat/pm.h>
>>
>> ?#include <mach/regs-gpio.h>
>> ?#include <mach/regs-clock.h>
>> @@ -133,6 +134,7 @@ static int s5p64x0_alloc_gc(void)
>> ? ? ? ct->chip.irq_mask = irq_gc_mask_set_bit;
>> ? ? ? ct->chip.irq_unmask = irq_gc_mask_clr_bit;
>> ? ? ? ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
>> + ? ? ct->chip.irq_set_wake = s3c_irqext_wake;
>> ? ? ? ct->regs.ack = EINT0PEND_OFFSET;
>> ? ? ? ct->regs.mask = EINT0MASK_OFFSET;
>> ? ? ? irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
>> diff --git a/arch/arm/mach-s5p64x0/irq-pm.c
> b/arch/arm/mach-s5p64x0/irq-pm.c
>> new file mode 100644
>> index 0000000..3e6f245
>> --- /dev/null
>> +++ b/arch/arm/mach-s5p64x0/irq-pm.c
>> @@ -0,0 +1,92 @@
>> +/* linux/arch/arm/mach-s5p64x0/irq-pm.c
>> + *
>> + * Copyright (c) 2011 Samsung Electronics Co., Ltd.
>> + * ? ? ? ? ? http://www.samsung.com
>> + *
>> + * S5P64X0 - Interrupt handling Power Management
>> + *
>> + * Based on arch/arm/mach-s3c64xx/irq-pm.c by Ben Dooks
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include <linux/syscore_ops.h>
>> +#include <linux/serial_core.h>
>> +#include <linux/io.h>
>> +
>> +#include <plat/regs-serial.h>
>> +#include <plat/pm.h>
>> +
>> +#include <mach/regs-gpio.h>
>> +
>> +static struct sleep_save irq_save[] = {
>> + ? ? SAVE_ITEM(S5P64X0_EINT0CON0),
>> + ? ? SAVE_ITEM(S5P64X0_EINT0FLTCON0),
>> + ? ? SAVE_ITEM(S5P64X0_EINT0FLTCON1),
>> + ? ? SAVE_ITEM(S5P64X0_EINT0MASK),
>> +};
>> +
>> +static struct irq_grp_save {
>> + ? ? u32 ? ? con;
>> + ? ? u32 ? ? fltcon;
>> + ? ? u32 ? ? mask;
>> +} eint_grp_save[4];
>> +
>> +static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS];
>> +
>> +static int s5p64x0_irq_pm_suspend(void)
>> +{
>> + ? ? struct irq_grp_save *grp = eint_grp_save;
>> + ? ? int i;
>> +
>> + ? ? S3C_PMDBG("%s: suspending IRQs\n", __func__);
>> +
>> + ? ? s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
>> +
>> + ? ? for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
>> + ? ? ? ? ? ? irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) +
>> S3C64XX_UINTM);
>> +
>> + ? ? for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
>> + ? ? ? ? ? ? grp->con = __raw_readl(S5P64X0_EINT12CON + (i * 4));
>> + ? ? ? ? ? ? grp->mask = __raw_readl(S5P64X0_EINT12MASK + (i * 4));
>> + ? ? ? ? ? ? grp->fltcon = __raw_readl(S5P64X0_EINT12FLTCON + (i * 4));
>> + ? ? }
>> +
>> + ? ? return 0;
>> +}
>> +
>> +static void s5p64x0_irq_pm_resume(void)
>> +{
>> + ? ? struct irq_grp_save *grp = eint_grp_save;
>> + ? ? int i;
>> +
>> + ? ? S3C_PMDBG("%s: resuming IRQs\n", __func__);
>> +
>> + ? ? s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
>> +
>> + ? ? for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
>> + ? ? ? ? ? ? __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) +
>> S3C64XX_UINTM);
>> +
>> + ? ? for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
>> + ? ? ? ? ? ? __raw_writel(grp->con, S5P64X0_EINT12CON + (i * 4));
>> + ? ? ? ? ? ? __raw_writel(grp->mask, S5P64X0_EINT12MASK + (i * 4));
>> + ? ? ? ? ? ? __raw_writel(grp->fltcon, S5P64X0_EINT12FLTCON + (i * 4));
>> + ? ? }
>> +
>> + ? ? S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
>> +}
>> +
>> +static struct syscore_ops s5p64x0_irq_syscore_ops = {
>> + ? ? .suspend = s5p64x0_irq_pm_suspend,
>> + ? ? .resume ?= s5p64x0_irq_pm_resume,
>> +};
>> +
>> +static int __init s5p64x0_syscore_init(void)
>> +{
>> + ? ? register_syscore_ops(&s5p64x0_irq_syscore_ops);
>> +
>> + ? ? return 0;
>> +}
>> +core_initcall(s5p64x0_syscore_init);
>> diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c
>> new file mode 100644
>> index 0000000..cced4fb
>> --- /dev/null
>> +++ b/arch/arm/mach-s5p64x0/pm.c
>> @@ -0,0 +1,204 @@
>> +/* linux/arch/arm/mach-s5p64x0/pm.c
>> + *
>> + * Copyright (c) 2011 Samsung Electronics Co., Ltd.
>> + * ? ? ? ? ? http://www.samsung.com
>> + *
>> + * S5P64X0 Power Management Support
>> + *
>> + * Based on arch/arm/mach-s3c64xx/pm.c by Ben Dooks
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> +*/
>> +
>> +#include <linux/suspend.h>
>> +#include <linux/syscore_ops.h>
>> +#include <linux/io.h>
>> +
>> +#include <plat/cpu.h>
>> +#include <plat/pm.h>
>> +#include <plat/regs-timer.h>
>> +#include <plat/wakeup-mask.h>
>> +
>> +#include <mach/regs-clock.h>
>> +#include <mach/regs-gpio.h>
>> +
>> +static struct sleep_save s5p64x0_core_save[] = {
>> + ? ? SAVE_ITEM(S5P64X0_APLL_CON),
>> + ? ? SAVE_ITEM(S5P64X0_MPLL_CON),
>> + ? ? SAVE_ITEM(S5P64X0_EPLL_CON),
>> + ? ? SAVE_ITEM(S5P64X0_EPLL_CON_K),
>> + ? ? SAVE_ITEM(S5P64X0_CLK_SRC0),
>> + ? ? SAVE_ITEM(S5P64X0_CLK_SRC1),
>> + ? ? SAVE_ITEM(S5P64X0_CLK_DIV0),
>> + ? ? SAVE_ITEM(S5P64X0_CLK_DIV1),
>> + ? ? SAVE_ITEM(S5P64X0_CLK_DIV2),
>> + ? ? SAVE_ITEM(S5P64X0_CLK_DIV3),
>> + ? ? SAVE_ITEM(S5P64X0_CLK_GATE_MEM0),
>> + ? ? SAVE_ITEM(S5P64X0_CLK_GATE_HCLK1),
>> + ? ? SAVE_ITEM(S5P64X0_CLK_GATE_SCLK1),
>> +};
>> +
>> +static struct sleep_save s5p64x0_misc_save[] = {
>> + ? ? SAVE_ITEM(S5P64X0_AHB_CON0),
>> + ? ? SAVE_ITEM(S5P64X0_SPCON0),
>> + ? ? SAVE_ITEM(S5P64X0_SPCON1),
>> + ? ? SAVE_ITEM(S5P64X0_MEM0CONSLP0),
>> + ? ? SAVE_ITEM(S5P64X0_MEM0CONSLP1),
>> + ? ? SAVE_ITEM(S5P64X0_MEM0DRVCON),
>> + ? ? SAVE_ITEM(S5P64X0_MEM1DRVCON),
>> +
>> + ? ? SAVE_ITEM(S3C64XX_TINT_CSTAT),
>> +};
>> +
>> +/* DPLL is present only in S5P6450 */
>> +static struct sleep_save s5p6450_core_save[] = {
>> + ? ? SAVE_ITEM(S5P6450_DPLL_CON),
>> + ? ? SAVE_ITEM(S5P6450_DPLL_CON_K),
>> +};
>> +
>> +void s3c_pm_configure_extint(void)
>> +{
>> + ? ? __raw_writel(s3c_irqwake_eintmask, S5P64X0_EINT_WAKEUP_MASK);
>> +}
>> +
>> +void s3c_pm_restore_core(void)
>> +{
>> + ? ? __raw_writel(0, S5P64X0_EINT_WAKEUP_MASK);
>> +
>> + ? ? s3c_pm_do_restore_core(s5p64x0_core_save,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARRAY_SIZE(s5p64x0_core_save));
>> +
>> + ? ? if ((__raw_readl(S5P64X0_SYS_ID) & 0xFF000) == 0x50000)
>> + ? ? ? ? ? ? s3c_pm_do_restore_core(s5p6450_core_save,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARRAY_SIZE(s5p6450_core_save));
>
> You can use soc_is_xxx() here.
Yep, wasn't there when I posted the series. Will change.
>
>> +
>> + ? ? s3c_pm_do_restore(s5p64x0_misc_save,
>> ARRAY_SIZE(s5p64x0_misc_save));
>> +}
>> +
>> +void s3c_pm_save_core(void)
>> +{
>> + ? ? s3c_pm_do_save(s5p64x0_misc_save,
>> ARRAY_SIZE(s5p64x0_misc_save));
>> +
>> + ? ? if ((__raw_readl(S5P64X0_SYS_ID) & 0xFF000) == 0x50000)
>> + ? ? ? ? ? ? s3c_pm_do_save(s5p6450_core_save,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARRAY_SIZE(s5p6450_core_save));
>
> Same.
>
>> +
>> + ? ? s3c_pm_do_save(s5p64x0_core_save,
>> ARRAY_SIZE(s5p64x0_core_save));
>> +}
>> +
>> +static int s5p64x0_cpu_suspend(unsigned long arg)
>> +{
>> + ? ? unsigned long tmp = 0;
>> +
>> + ? ? /*
>> + ? ? ?* Issue the standby signal into the pm unit. Note, we
>> + ? ? ?* issue a write-buffer drain just in case.
>> + ? ? ?*/
>> + ? ? asm("b 1f\n\t"
>> + ? ? ? ? ".align 5\n\t"
>> + ? ? ? ? "1:\n\t"
>> + ? ? ? ? "mcr p15, 0, %0, c7, c10, 5\n\t"
>> + ? ? ? ? "mcr p15, 0, %0, c7, c10, 4\n\t"
>> + ? ? ? ? "mcr p15, 0, %0, c7, c0, 4" : : "r" (tmp));
>> +
>> + ? ? /* we should never get past here */
>> + ? ? panic("sleep resumed to originator?");
>> +}
>> +
>> +/* mapping of interrupts to parts of the wakeup mask */
>> +static struct samsung_wakeup_mask s5p64x0_wake_irqs[] = {
>> + ? ? { .irq = IRQ_RTC_ALARM, .bit =
>> S5P64X0_PWRCFG_RTC_ALRM_DISABLE, },
>> + ? ? { .irq = IRQ_RTC_TIC, ? .bit =
>> S5P64X0_PWRCFG_RTC_TICK_DISABLE, },
>> + ? ? { .irq = IRQ_HSMMC0, ? ?.bit = S5P64X0_PWRCFG_MMC0_DISABLE, },
>> + ? ? { .irq = IRQ_HSMMC1, ? ?.bit = S5P64X0_PWRCFG_MMC1_DISABLE, },
>> +};
>> +
>> +static void s5p64x0_pm_prepare(void)
>> +{
>> + ? ? u32 tmp;
>> +
>> + ? ? samsung_sync_wakemask(S5P64X0_PWR_CFG,
>> + ? ? ? ? ? ? ? ? ? ? s5p64x0_wake_irqs, ARRAY_SIZE(s5p64x0_wake_irqs));
>> +
>> + ? ? /* store the resume address in INFORM0 register */
>> + ? ? __raw_writel(virt_to_phys(s3c_cpu_resume), S5P64X0_INFORM0);
>> +
>> + ? ? /* setup clock gating for FIMGVG block */
>> + ? ? __raw_writel((__raw_readl(S5P64X0_CLK_GATE_HCLK1) | \
>> + ? ? ? ? ? ? (S5P64X0_CLKCON_HCLK1_FIMGVG)),
>> S5P64X0_CLK_GATE_HCLK1);
>> + ? ? __raw_writel((__raw_readl(S5P64X0_CLK_GATE_SCLK1) | \
>> + ? ? ? ? ? ? (S5P64X0_CLKCON_SCLK1_FIMGVG)),
>> S5P64X0_CLK_GATE_SCLK1);
>> +
>> + ? ? /* Configure the stabilization counter with wait time required */
>> + ? ? __raw_writel(S5P64X0_PWR_STABLE_CNT_VAL_4,
>> S5P64X0_PWR_STABLE);
>> +
>> + ? ? /* set WFI to SLEEP mode configuration */
>> + ? ? tmp = __raw_readl(S5P64X0_SLEEP_CFG);
>> + ? ? tmp &= ~(S5P64X0_SLEEP_CFG_OSC_EN);
>> + ? ? __raw_writel(tmp, S5P64X0_SLEEP_CFG);
>> +
>> + ? ? tmp = __raw_readl(S5P64X0_PWR_CFG);
>> + ? ? tmp &= ~(S5P64X0_PWRCFG_CFG_WFI_MASK);
>> + ? ? tmp |= S5P64X0_PWRCFG_CFG_WFI_SLEEP;
>> + ? ? __raw_writel(tmp, S5P64X0_PWR_CFG);
>> +
>> + ? ? /*
>> + ? ? ?* set OTHERS register to disable interrupt before going to
>> + ? ? ?* sleep. This bit is present only in S5P6450, it is reserved
>> + ? ? ?* in S5P6440.
>> + ? ? ?*/
>> + ? ? if ((__raw_readl(S5P64X0_SYS_ID) & 0xFF000) == 0x50000) {
>> + ? ? ? ? ? ? tmp = __raw_readl(S5P64X0_OTHERS);
>> + ? ? ? ? ? ? tmp |= S5P6450_OTHERS_DISABLE_INT;
>> + ? ? ? ? ? ? __raw_writel(tmp, S5P64X0_OTHERS);
>> + ? ? }
>> +
>> + ? ? /* ensure previous wakeup state is cleared before sleeping */
>> + ? ? __raw_writel(__raw_readl(S5P64X0_WAKEUP_STAT),
>> S5P64X0_WAKEUP_STAT);
>> +
>> +}
>> +
>> +static int s5p64x0_pm_add(struct sys_device *sysdev)
>> +{
>> + ? ? pm_cpu_prep = s5p64x0_pm_prepare;
>> + ? ? pm_cpu_sleep = s5p64x0_cpu_suspend;
>> + ? ? pm_uart_udivslot = 1;
>
> If pm_uart_udivslot has value, the UDIVSLOT3 is used...is this right on
> S5P64X0?
UDIVSLOT at an offset of 2C seems fine for 64X0.
>
>> +
>> + ? ? return 0;
>> +}
>> +
>> +static struct sysdev_driver s5p64x0_pm_driver = {
>> + ? ? .add ? ? ? ? ? ?= s5p64x0_pm_add,
>> +};
>> +
>> +static __init int s5p64x0_pm_drvinit(void)
>> +{
>> + ? ? s3c_pm_init();
>> +
>> + ? ? return sysdev_driver_register(&s5p64x0_sysclass,
> &s5p64x0_pm_driver);
>> +}
>> +arch_initcall(s5p64x0_pm_drvinit);
>> +
>> +static void s5p64x0_pm_resume(void)
>> +{
>> + ? ? u32 tmp;
>> +
>> + ? ? tmp = __raw_readl(S5P64X0_OTHERS);
>> + ? ? tmp |= (S5P64X0_OTHERS_RET_MMC0 |
>> S5P64X0_OTHERS_RET_MMC1 | \
>> + ? ? ? ? ? ? ? ? ? ? S5P64X0_OTHERS_RET_UART);
>> + ? ? __raw_writel(tmp , S5P64X0_OTHERS);
>> +}
>> +
>> +static struct syscore_ops s5p64x0_pm_syscore_ops = {
>> + ? ? .resume ? ? ? ? = s5p64x0_pm_resume,
>> +};
>> +
>> +static __init int s5p64x0_pm_syscore_init(void)
>> +{
>> + ? ? register_syscore_ops(&s5p64x0_pm_syscore_ops);
>> +
>> + ? ? return 0;
>> +}
>> +arch_initcall(s5p64x0_pm_syscore_init);
>> --
>> 1.7.4.1
>
> Basically, this codes need small fixing. I mean if this codes have been
> tested on board and it works fine, it's ok to me.
>
> But as you said, s5p64x0 pm is almost same with s3c64xx, so we need to clean
> them up next time :)
Has been tested for 6440 and 6450. Thanks for the review.
>
> Thanks.
>
> Best regards,
> Kgene.
Abhilash
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* RE: [PATCH 0/5] S5P64X0 PM Support
2011-08-12 10:26 ` Abhilash Kesavan
@ 2011-08-19 14:02 ` Kukjin Kim
-1 siblings, 0 replies; 40+ messages in thread
From: Kukjin Kim @ 2011-08-19 14:02 UTC (permalink / raw)
To: 'Abhilash Kesavan', linux-arm-kernel, linux-samsung-soc
Abhilash Kesavan wrote:
>
> The patchset adds Power Mangement support for S5P64X0. The first
> four patches lay the groundwork for adding PM support, while the
> final patch adds the SoC specific PM code.
> Tested using external interrupts as wake-up sources on SMDK6440
> and SMDK6450.
>
> Abhilash Kesavan (5):
> ARM: S5P: Make the common S5P PM code conditionally compile
> ARM: SAMSUNG: Make the sleep code common for S3C64XX and newer SoCs
> ARM: S5P64X0: Add pm save/restore functions for GPIO banks
> ARM: S5P64X0: Fix incorrect serial clock name
> ARM: S5P64X0: Add Power Management support
>
> arch/arm/Kconfig | 2 +-
> arch/arm/mach-exynos4/Kconfig | 2 +
> arch/arm/mach-exynos4/Makefile | 2 +-
> arch/arm/mach-exynos4/sleep.S | 54 ------
> arch/arm/mach-s3c64xx/Kconfig | 1 +
> arch/arm/mach-s3c64xx/Makefile | 1 -
> arch/arm/mach-s3c64xx/sleep.S | 72 --------
> arch/arm/mach-s5p64x0/Kconfig | 4 +
> arch/arm/mach-s5p64x0/Makefile | 1 +
> arch/arm/mach-s5p64x0/clock-s5p6440.c | 2 +-
> arch/arm/mach-s5p64x0/clock-s5p6450.c | 2 +-
> arch/arm/mach-s5p64x0/gpiolib.c | 1 +
> arch/arm/mach-s5p64x0/include/mach/map.h | 1 +
> arch/arm/mach-s5p64x0/include/mach/pm-core.h | 117 +++++++++++++
> arch/arm/mach-s5p64x0/include/mach/regs-clock.h | 33 ++++
> arch/arm/mach-s5p64x0/include/mach/regs-gpio.h | 19 ++
> arch/arm/mach-s5p64x0/init.c | 2 +-
> arch/arm/mach-s5p64x0/irq-eint.c | 2 +
> arch/arm/mach-s5p64x0/irq-pm.c | 92 ++++++++++
> arch/arm/mach-s5p64x0/pm.c | 204
> +++++++++++++++++++++++
> arch/arm/mach-s5pv210/Kconfig | 2 +
> arch/arm/mach-s5pv210/Makefile | 2 +-
> arch/arm/mach-s5pv210/sleep.S | 52 ------
> arch/arm/plat-s5p/Kconfig | 6 +
> arch/arm/plat-s5p/Makefile | 3 +-
> arch/arm/plat-samsung/Kconfig | 7 +
> arch/arm/plat-samsung/Makefile | 1 +
> arch/arm/plat-samsung/sleep.S | 80 +++++++++
> drivers/gpio/gpio-plat-samsung.c | 4 +-
> 29 files changed, 583 insertions(+), 188 deletions(-)
> delete mode 100644 arch/arm/mach-exynos4/sleep.S
> delete mode 100644 arch/arm/mach-s3c64xx/sleep.S
> create mode 100644 arch/arm/mach-s5p64x0/include/mach/pm-core.h
> create mode 100644 arch/arm/mach-s5p64x0/irq-pm.c
> create mode 100644 arch/arm/mach-s5p64x0/pm.c
> delete mode 100644 arch/arm/mach-s5pv210/sleep.S
> create mode 100644 arch/arm/plat-samsung/sleep.S
>
> --
Hi Abhilash,
As a note, I will be back on this in the next week :)
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 0/5] S5P64X0 PM Support
@ 2011-08-19 14:02 ` Kukjin Kim
0 siblings, 0 replies; 40+ messages in thread
From: Kukjin Kim @ 2011-08-19 14:02 UTC (permalink / raw)
To: linux-arm-kernel
Abhilash Kesavan wrote:
>
> The patchset adds Power Mangement support for S5P64X0. The first
> four patches lay the groundwork for adding PM support, while the
> final patch adds the SoC specific PM code.
> Tested using external interrupts as wake-up sources on SMDK6440
> and SMDK6450.
>
> Abhilash Kesavan (5):
> ARM: S5P: Make the common S5P PM code conditionally compile
> ARM: SAMSUNG: Make the sleep code common for S3C64XX and newer SoCs
> ARM: S5P64X0: Add pm save/restore functions for GPIO banks
> ARM: S5P64X0: Fix incorrect serial clock name
> ARM: S5P64X0: Add Power Management support
>
> arch/arm/Kconfig | 2 +-
> arch/arm/mach-exynos4/Kconfig | 2 +
> arch/arm/mach-exynos4/Makefile | 2 +-
> arch/arm/mach-exynos4/sleep.S | 54 ------
> arch/arm/mach-s3c64xx/Kconfig | 1 +
> arch/arm/mach-s3c64xx/Makefile | 1 -
> arch/arm/mach-s3c64xx/sleep.S | 72 --------
> arch/arm/mach-s5p64x0/Kconfig | 4 +
> arch/arm/mach-s5p64x0/Makefile | 1 +
> arch/arm/mach-s5p64x0/clock-s5p6440.c | 2 +-
> arch/arm/mach-s5p64x0/clock-s5p6450.c | 2 +-
> arch/arm/mach-s5p64x0/gpiolib.c | 1 +
> arch/arm/mach-s5p64x0/include/mach/map.h | 1 +
> arch/arm/mach-s5p64x0/include/mach/pm-core.h | 117 +++++++++++++
> arch/arm/mach-s5p64x0/include/mach/regs-clock.h | 33 ++++
> arch/arm/mach-s5p64x0/include/mach/regs-gpio.h | 19 ++
> arch/arm/mach-s5p64x0/init.c | 2 +-
> arch/arm/mach-s5p64x0/irq-eint.c | 2 +
> arch/arm/mach-s5p64x0/irq-pm.c | 92 ++++++++++
> arch/arm/mach-s5p64x0/pm.c | 204
> +++++++++++++++++++++++
> arch/arm/mach-s5pv210/Kconfig | 2 +
> arch/arm/mach-s5pv210/Makefile | 2 +-
> arch/arm/mach-s5pv210/sleep.S | 52 ------
> arch/arm/plat-s5p/Kconfig | 6 +
> arch/arm/plat-s5p/Makefile | 3 +-
> arch/arm/plat-samsung/Kconfig | 7 +
> arch/arm/plat-samsung/Makefile | 1 +
> arch/arm/plat-samsung/sleep.S | 80 +++++++++
> drivers/gpio/gpio-plat-samsung.c | 4 +-
> 29 files changed, 583 insertions(+), 188 deletions(-)
> delete mode 100644 arch/arm/mach-exynos4/sleep.S
> delete mode 100644 arch/arm/mach-s3c64xx/sleep.S
> create mode 100644 arch/arm/mach-s5p64x0/include/mach/pm-core.h
> create mode 100644 arch/arm/mach-s5p64x0/irq-pm.c
> create mode 100644 arch/arm/mach-s5p64x0/pm.c
> delete mode 100644 arch/arm/mach-s5pv210/sleep.S
> create mode 100644 arch/arm/plat-samsung/sleep.S
>
> --
Hi Abhilash,
As a note, I will be back on this in the next week :)
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 40+ messages in thread
* RE: [PATCH 0/5] S5P64X0 PM Support
2011-08-12 10:26 ` Abhilash Kesavan
@ 2011-09-21 12:39 ` Kukjin Kim
-1 siblings, 0 replies; 40+ messages in thread
From: Kukjin Kim @ 2011-09-21 12:39 UTC (permalink / raw)
To: 'Abhilash Kesavan', linux-arm-kernel, linux-samsung-soc
Abhilash Kesavan wrote:
>
> The patchset adds Power Mangement support for S5P64X0. The first
> four patches lay the groundwork for adding PM support, while the
> final patch adds the SoC specific PM code.
> Tested using external interrupts as wake-up sources on SMDK6440
> and SMDK6450.
>
> Abhilash Kesavan (5):
> ARM: S5P: Make the common S5P PM code conditionally compile
> ARM: SAMSUNG: Make the sleep code common for S3C64XX and newer SoCs
> ARM: S5P64X0: Add pm save/restore functions for GPIO banks
> ARM: S5P64X0: Fix incorrect serial clock name
> ARM: S5P64X0: Add Power Management support
>
> arch/arm/Kconfig | 2 +-
> arch/arm/mach-exynos4/Kconfig | 2 +
> arch/arm/mach-exynos4/Makefile | 2 +-
> arch/arm/mach-exynos4/sleep.S | 54 ------
> arch/arm/mach-s3c64xx/Kconfig | 1 +
> arch/arm/mach-s3c64xx/Makefile | 1 -
> arch/arm/mach-s3c64xx/sleep.S | 72 --------
> arch/arm/mach-s5p64x0/Kconfig | 4 +
> arch/arm/mach-s5p64x0/Makefile | 1 +
> arch/arm/mach-s5p64x0/clock-s5p6440.c | 2 +-
> arch/arm/mach-s5p64x0/clock-s5p6450.c | 2 +-
> arch/arm/mach-s5p64x0/gpiolib.c | 1 +
> arch/arm/mach-s5p64x0/include/mach/map.h | 1 +
> arch/arm/mach-s5p64x0/include/mach/pm-core.h | 117 +++++++++++++
> arch/arm/mach-s5p64x0/include/mach/regs-clock.h | 33 ++++
> arch/arm/mach-s5p64x0/include/mach/regs-gpio.h | 19 ++
> arch/arm/mach-s5p64x0/init.c | 2 +-
> arch/arm/mach-s5p64x0/irq-eint.c | 2 +
> arch/arm/mach-s5p64x0/irq-pm.c | 92 ++++++++++
> arch/arm/mach-s5p64x0/pm.c | 204
> +++++++++++++++++++++++
> arch/arm/mach-s5pv210/Kconfig | 2 +
> arch/arm/mach-s5pv210/Makefile | 2 +-
> arch/arm/mach-s5pv210/sleep.S | 52 ------
> arch/arm/plat-s5p/Kconfig | 6 +
> arch/arm/plat-s5p/Makefile | 3 +-
> arch/arm/plat-samsung/Kconfig | 7 +
> arch/arm/plat-samsung/Makefile | 1 +
> arch/arm/plat-samsung/sleep.S | 80 +++++++++
> drivers/gpio/gpio-plat-samsung.c | 4 +-
> 29 files changed, 583 insertions(+), 188 deletions(-)
> delete mode 100644 arch/arm/mach-exynos4/sleep.S
> delete mode 100644 arch/arm/mach-s3c64xx/sleep.S
> create mode 100644 arch/arm/mach-s5p64x0/include/mach/pm-core.h
> create mode 100644 arch/arm/mach-s5p64x0/irq-pm.c
> create mode 100644 arch/arm/mach-s5p64x0/pm.c
> delete mode 100644 arch/arm/mach-s5pv210/sleep.S
> create mode 100644 arch/arm/plat-samsung/sleep.S
>
> --
> 1.7.4.1
Hi Abhilash,
As I know, you need to rebase this series based on latest for-next.
Please re-submit this series...and I agree with Russell's suggestion on
patch 2/5.
But it's enough to use s3c64xx_smdk_leds_resume() firstly not common smdk
now.
Of course, we need to do it later ;)
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 0/5] S5P64X0 PM Support
@ 2011-09-21 12:39 ` Kukjin Kim
0 siblings, 0 replies; 40+ messages in thread
From: Kukjin Kim @ 2011-09-21 12:39 UTC (permalink / raw)
To: linux-arm-kernel
Abhilash Kesavan wrote:
>
> The patchset adds Power Mangement support for S5P64X0. The first
> four patches lay the groundwork for adding PM support, while the
> final patch adds the SoC specific PM code.
> Tested using external interrupts as wake-up sources on SMDK6440
> and SMDK6450.
>
> Abhilash Kesavan (5):
> ARM: S5P: Make the common S5P PM code conditionally compile
> ARM: SAMSUNG: Make the sleep code common for S3C64XX and newer SoCs
> ARM: S5P64X0: Add pm save/restore functions for GPIO banks
> ARM: S5P64X0: Fix incorrect serial clock name
> ARM: S5P64X0: Add Power Management support
>
> arch/arm/Kconfig | 2 +-
> arch/arm/mach-exynos4/Kconfig | 2 +
> arch/arm/mach-exynos4/Makefile | 2 +-
> arch/arm/mach-exynos4/sleep.S | 54 ------
> arch/arm/mach-s3c64xx/Kconfig | 1 +
> arch/arm/mach-s3c64xx/Makefile | 1 -
> arch/arm/mach-s3c64xx/sleep.S | 72 --------
> arch/arm/mach-s5p64x0/Kconfig | 4 +
> arch/arm/mach-s5p64x0/Makefile | 1 +
> arch/arm/mach-s5p64x0/clock-s5p6440.c | 2 +-
> arch/arm/mach-s5p64x0/clock-s5p6450.c | 2 +-
> arch/arm/mach-s5p64x0/gpiolib.c | 1 +
> arch/arm/mach-s5p64x0/include/mach/map.h | 1 +
> arch/arm/mach-s5p64x0/include/mach/pm-core.h | 117 +++++++++++++
> arch/arm/mach-s5p64x0/include/mach/regs-clock.h | 33 ++++
> arch/arm/mach-s5p64x0/include/mach/regs-gpio.h | 19 ++
> arch/arm/mach-s5p64x0/init.c | 2 +-
> arch/arm/mach-s5p64x0/irq-eint.c | 2 +
> arch/arm/mach-s5p64x0/irq-pm.c | 92 ++++++++++
> arch/arm/mach-s5p64x0/pm.c | 204
> +++++++++++++++++++++++
> arch/arm/mach-s5pv210/Kconfig | 2 +
> arch/arm/mach-s5pv210/Makefile | 2 +-
> arch/arm/mach-s5pv210/sleep.S | 52 ------
> arch/arm/plat-s5p/Kconfig | 6 +
> arch/arm/plat-s5p/Makefile | 3 +-
> arch/arm/plat-samsung/Kconfig | 7 +
> arch/arm/plat-samsung/Makefile | 1 +
> arch/arm/plat-samsung/sleep.S | 80 +++++++++
> drivers/gpio/gpio-plat-samsung.c | 4 +-
> 29 files changed, 583 insertions(+), 188 deletions(-)
> delete mode 100644 arch/arm/mach-exynos4/sleep.S
> delete mode 100644 arch/arm/mach-s3c64xx/sleep.S
> create mode 100644 arch/arm/mach-s5p64x0/include/mach/pm-core.h
> create mode 100644 arch/arm/mach-s5p64x0/irq-pm.c
> create mode 100644 arch/arm/mach-s5p64x0/pm.c
> delete mode 100644 arch/arm/mach-s5pv210/sleep.S
> create mode 100644 arch/arm/plat-samsung/sleep.S
>
> --
> 1.7.4.1
Hi Abhilash,
As I know, you need to rebase this series based on latest for-next.
Please re-submit this series...and I agree with Russell's suggestion on
patch 2/5.
But it's enough to use s3c64xx_smdk_leds_resume() firstly not common smdk
now.
Of course, we need to do it later ;)
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 40+ messages in thread