* [PATCH v2] tune-riscv: Add support for no float
@ 2019-11-22 0:02 Alistair Francis
2019-11-22 0:33 ` Andre McCurdy
2019-11-22 0:47 ` Khem Raj
0 siblings, 2 replies; 4+ messages in thread
From: Alistair Francis @ 2019-11-22 0:02 UTC (permalink / raw)
To: openembedded-core
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
meta/conf/machine/include/riscv/arch-riscv.inc | 3 ++-
meta/conf/machine/include/riscv/tune-riscv.inc | 16 +++++++++++++++-
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/meta/conf/machine/include/riscv/arch-riscv.inc b/meta/conf/machine/include/riscv/arch-riscv.inc
index f3edcc39f7..33ad6a28e1 100644
--- a/meta/conf/machine/include/riscv/arch-riscv.inc
+++ b/meta/conf/machine/include/riscv/arch-riscv.inc
@@ -4,7 +4,8 @@ DEFAULTTUNE ?= "riscv64"
TUNE_ARCH = "${TUNE_ARCH_tune-${DEFAULTTUNE}}"
TUNE_PKGARCH = "${TUNE_PKGARCH_tune-${DEFAULTTUNE}}"
-TUNE_CCARGS .= ""
+TUNE_CCARGS_append_riscv64 = "${@bb.utils.contains('TUNE_FEATURES', 'riscv64nf', ' -mabi=lp64', ' ', d)}"
+TUNE_CCARGS_append_riscv32 = "${@bb.utils.contains('TUNE_FEATURES', 'riscv32nf', ' -mabi=ilp32', ' ', d)}"
# QEMU usermode fails with invalid instruction error (For riscv32)
MACHINE_FEATURES_BACKFILL_CONSIDERED_append = "${@bb.utils.contains('TUNE_FEATURES', 'riscv32', ' qemu-usermode', '', d)}"
diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc
index 25d0463492..b7dcd244d6 100644
--- a/meta/conf/machine/include/riscv/tune-riscv.inc
+++ b/meta/conf/machine/include/riscv/tune-riscv.inc
@@ -3,10 +3,14 @@ require conf/machine/include/riscv/arch-riscv.inc
TUNEVALID[riscv64] = "Enable 64-bit RISC-V optimizations"
TUNEVALID[riscv32] = "Enable 32-bit RISC-V optimizations"
+TUNEVALID[riscv64nf] = "Enable 64-bit RISC-V optimizations no floating point"
+TUNEVALID[riscv32nf] = "Enable 32-bit RISC-V optimizations no floating point"
+
TUNEVALID[bigendian] = "Big endian mode"
-AVAILTUNES += "riscv64 riscv32"
+AVAILTUNES += "riscv64 riscv32 riscv64nf riscv32nf"
+# Default
TUNE_FEATURES_tune-riscv64 = "riscv64"
TUNE_ARCH_tune-riscv64 = "riscv64"
TUNE_PKGARCH_tune-riscv64 = "riscv64"
@@ -17,3 +21,13 @@ TUNE_ARCH_tune-riscv32 = "riscv32"
TUNE_PKGARCH_tune-riscv32 = "riscv32"
PACKAGE_EXTRA_ARCHS_tune-riscv32 = "riscv32"
+# No float
+TUNE_FEATURES_tune-riscv64nf = "${TUNE_FEATURES_tune-riscv64} riscv64nf"
+TUNE_ARCH_tune-riscv64nf = "riscv64"
+TUNE_PKGARCH_tune-riscv64nf = "riscv64"
+PACKAGE_EXTRA_ARCHS_tune-riscv64nf = "riscv64"
+
+TUNE_FEATURES_tune-riscv32nf = "${TUNE_FEATURES_tune-riscv32} riscv32nf"
+TUNE_ARCH_tune-riscv32nf = "riscv32"
+TUNE_PKGARCH_tune-riscv32nf = "riscv32"
+PACKAGE_EXTRA_ARCHS_tune-riscv32nf = "riscv32"
--
2.24.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v2] tune-riscv: Add support for no float
2019-11-22 0:02 [PATCH v2] tune-riscv: Add support for no float Alistair Francis
@ 2019-11-22 0:33 ` Andre McCurdy
2019-11-22 0:47 ` Khem Raj
1 sibling, 0 replies; 4+ messages in thread
From: Andre McCurdy @ 2019-11-22 0:33 UTC (permalink / raw)
To: Alistair Francis; +Cc: OE Core mailing list
On Thu, Nov 21, 2019 at 4:08 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> meta/conf/machine/include/riscv/arch-riscv.inc | 3 ++-
> meta/conf/machine/include/riscv/tune-riscv.inc | 16 +++++++++++++++-
> 2 files changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/meta/conf/machine/include/riscv/arch-riscv.inc b/meta/conf/machine/include/riscv/arch-riscv.inc
> index f3edcc39f7..33ad6a28e1 100644
> --- a/meta/conf/machine/include/riscv/arch-riscv.inc
> +++ b/meta/conf/machine/include/riscv/arch-riscv.inc
> @@ -4,7 +4,8 @@ DEFAULTTUNE ?= "riscv64"
>
> TUNE_ARCH = "${TUNE_ARCH_tune-${DEFAULTTUNE}}"
> TUNE_PKGARCH = "${TUNE_PKGARCH_tune-${DEFAULTTUNE}}"
> -TUNE_CCARGS .= ""
> +TUNE_CCARGS_append_riscv64 = "${@bb.utils.contains('TUNE_FEATURES', 'riscv64nf', ' -mabi=lp64', ' ', d)}"
> +TUNE_CCARGS_append_riscv32 = "${@bb.utils.contains('TUNE_FEATURES', 'riscv32nf', ' -mabi=ilp32', ' ', d)}"
>
> # QEMU usermode fails with invalid instruction error (For riscv32)
> MACHINE_FEATURES_BACKFILL_CONSIDERED_append = "${@bb.utils.contains('TUNE_FEATURES', 'riscv32', ' qemu-usermode', '', d)}"
> diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc
> index 25d0463492..b7dcd244d6 100644
> --- a/meta/conf/machine/include/riscv/tune-riscv.inc
> +++ b/meta/conf/machine/include/riscv/tune-riscv.inc
> @@ -3,10 +3,14 @@ require conf/machine/include/riscv/arch-riscv.inc
> TUNEVALID[riscv64] = "Enable 64-bit RISC-V optimizations"
> TUNEVALID[riscv32] = "Enable 32-bit RISC-V optimizations"
>
> +TUNEVALID[riscv64nf] = "Enable 64-bit RISC-V optimizations no floating point"
> +TUNEVALID[riscv32nf] = "Enable 32-bit RISC-V optimizations no floating point"
> +
> TUNEVALID[bigendian] = "Big endian mode"
>
> -AVAILTUNES += "riscv64 riscv32"
> +AVAILTUNES += "riscv64 riscv32 riscv64nf riscv32nf"
>
> +# Default
> TUNE_FEATURES_tune-riscv64 = "riscv64"
> TUNE_ARCH_tune-riscv64 = "riscv64"
> TUNE_PKGARCH_tune-riscv64 = "riscv64"
> @@ -17,3 +21,13 @@ TUNE_ARCH_tune-riscv32 = "riscv32"
> TUNE_PKGARCH_tune-riscv32 = "riscv32"
> PACKAGE_EXTRA_ARCHS_tune-riscv32 = "riscv32"
>
> +# No float
> +TUNE_FEATURES_tune-riscv64nf = "${TUNE_FEATURES_tune-riscv64} riscv64nf"
> +TUNE_ARCH_tune-riscv64nf = "riscv64"
> +TUNE_PKGARCH_tune-riscv64nf = "riscv64"
> +PACKAGE_EXTRA_ARCHS_tune-riscv64nf = "riscv64"
This seems to be saying that a riscv64nf machine can also use riscv64 packages.
Should that be the other way around (ie riscv64 machine can also use
riscv64nf packages)?
(I thought there was a sanity check somewhere to check that
PACKAGE_EXTRA_ARCHS_tune-foo must at least contain "foo", ie a
particular tune must be able to use it's own packages. I don't
remember how or when that's triggered though... maybe it's ARM
specific?).
> +TUNE_FEATURES_tune-riscv32nf = "${TUNE_FEATURES_tune-riscv32} riscv32nf"
> +TUNE_ARCH_tune-riscv32nf = "riscv32"
> +TUNE_PKGARCH_tune-riscv32nf = "riscv32"
> +PACKAGE_EXTRA_ARCHS_tune-riscv32nf = "riscv32"
> --
> 2.24.0
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v2] tune-riscv: Add support for no float
2019-11-22 0:02 [PATCH v2] tune-riscv: Add support for no float Alistair Francis
2019-11-22 0:33 ` Andre McCurdy
@ 2019-11-22 0:47 ` Khem Raj
1 sibling, 0 replies; 4+ messages in thread
From: Khem Raj @ 2019-11-22 0:47 UTC (permalink / raw)
To: Alistair Francis; +Cc: Patches and discussions about the oe-core layer
On Thu, Nov 21, 2019 at 4:08 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> meta/conf/machine/include/riscv/arch-riscv.inc | 3 ++-
> meta/conf/machine/include/riscv/tune-riscv.inc | 16 +++++++++++++++-
> 2 files changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/meta/conf/machine/include/riscv/arch-riscv.inc b/meta/conf/machine/include/riscv/arch-riscv.inc
> index f3edcc39f7..33ad6a28e1 100644
> --- a/meta/conf/machine/include/riscv/arch-riscv.inc
> +++ b/meta/conf/machine/include/riscv/arch-riscv.inc
> @@ -4,7 +4,8 @@ DEFAULTTUNE ?= "riscv64"
>
> TUNE_ARCH = "${TUNE_ARCH_tune-${DEFAULTTUNE}}"
> TUNE_PKGARCH = "${TUNE_PKGARCH_tune-${DEFAULTTUNE}}"
> -TUNE_CCARGS .= ""
> +TUNE_CCARGS_append_riscv64 = "${@bb.utils.contains('TUNE_FEATURES', 'riscv64nf', ' -mabi=lp64', ' ', d)}"
> +TUNE_CCARGS_append_riscv32 = "${@bb.utils.contains('TUNE_FEATURES', 'riscv32nf', ' -mabi=ilp32', ' ', d)}"
>
using overrides here is not required. riscv64nf and riscv32 should
conflict with each other and such a combination would
then not exist.
> # QEMU usermode fails with invalid instruction error (For riscv32)
> MACHINE_FEATURES_BACKFILL_CONSIDERED_append = "${@bb.utils.contains('TUNE_FEATURES', 'riscv32', ' qemu-usermode', '', d)}"
> diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc
> index 25d0463492..b7dcd244d6 100644
> --- a/meta/conf/machine/include/riscv/tune-riscv.inc
> +++ b/meta/conf/machine/include/riscv/tune-riscv.inc
> @@ -3,10 +3,14 @@ require conf/machine/include/riscv/arch-riscv.inc
> TUNEVALID[riscv64] = "Enable 64-bit RISC-V optimizations"
> TUNEVALID[riscv32] = "Enable 32-bit RISC-V optimizations"
>
> +TUNEVALID[riscv64nf] = "Enable 64-bit RISC-V optimizations no floating point"
> +TUNEVALID[riscv32nf] = "Enable 32-bit RISC-V optimizations no floating point"
> +
> TUNEVALID[bigendian] = "Big endian mode"
>
> -AVAILTUNES += "riscv64 riscv32"
> +AVAILTUNES += "riscv64 riscv32 riscv64nf riscv32nf"
>
> +# Default
> TUNE_FEATURES_tune-riscv64 = "riscv64"
> TUNE_ARCH_tune-riscv64 = "riscv64"
> TUNE_PKGARCH_tune-riscv64 = "riscv64"
> @@ -17,3 +21,13 @@ TUNE_ARCH_tune-riscv32 = "riscv32"
> TUNE_PKGARCH_tune-riscv32 = "riscv32"
> PACKAGE_EXTRA_ARCHS_tune-riscv32 = "riscv32"
>
> +# No float
> +TUNE_FEATURES_tune-riscv64nf = "${TUNE_FEATURES_tune-riscv64} riscv64nf"
> +TUNE_ARCH_tune-riscv64nf = "riscv64"
> +TUNE_PKGARCH_tune-riscv64nf = "riscv64"
> +PACKAGE_EXTRA_ARCHS_tune-riscv64nf = "riscv64"
> +
> +TUNE_FEATURES_tune-riscv32nf = "${TUNE_FEATURES_tune-riscv32} riscv32nf"
> +TUNE_ARCH_tune-riscv32nf = "riscv32"
> +TUNE_PKGARCH_tune-riscv32nf = "riscv32"
> +PACKAGE_EXTRA_ARCHS_tune-riscv32nf = "riscv32"
this is not right. rv32 with float-abi wont execute on rv with soft float abi.
> --
> 2.24.0
>
> --
> _______________________________________________
> Openembedded-core mailing list
> Openembedded-core@lists.openembedded.org
> http://lists.openembedded.org/mailman/listinfo/openembedded-core
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v2] tune-riscv: Add support for no float
@ 2019-11-07 0:48 Alistair Francis
0 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2019-11-07 0:48 UTC (permalink / raw)
To: openembedded-core
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
meta/conf/machine/include/riscv/arch-riscv.inc | 3 ++-
meta/conf/machine/include/riscv/tune-riscv.inc | 16 +++++++++++++++-
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/meta/conf/machine/include/riscv/arch-riscv.inc b/meta/conf/machine/include/riscv/arch-riscv.inc
index f3edcc39f7..7ee497fe20 100644
--- a/meta/conf/machine/include/riscv/arch-riscv.inc
+++ b/meta/conf/machine/include/riscv/arch-riscv.inc
@@ -4,7 +4,8 @@ DEFAULTTUNE ?= "riscv64"
TUNE_ARCH = "${TUNE_ARCH_tune-${DEFAULTTUNE}}"
TUNE_PKGARCH = "${TUNE_PKGARCH_tune-${DEFAULTTUNE}}"
-TUNE_CCARGS .= ""
+TUNE_CCARGS_riscv64 .= "${@bb.utils.contains('TUNE_FEATURES', 'riscv64nf', ' -mabi=lp64', ' ', d)}"
+TUNE_CCARGS_riscv32 .= "${@bb.utils.contains('TUNE_FEATURES', 'riscv32nf', ' -mabi=ilp32', ' ', d)}"
# QEMU usermode fails with invalid instruction error (For riscv32)
MACHINE_FEATURES_BACKFILL_CONSIDERED_append = "${@bb.utils.contains('TUNE_FEATURES', 'riscv32', ' qemu-usermode', '', d)}"
diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc
index 25d0463492..b7dcd244d6 100644
--- a/meta/conf/machine/include/riscv/tune-riscv.inc
+++ b/meta/conf/machine/include/riscv/tune-riscv.inc
@@ -3,10 +3,14 @@ require conf/machine/include/riscv/arch-riscv.inc
TUNEVALID[riscv64] = "Enable 64-bit RISC-V optimizations"
TUNEVALID[riscv32] = "Enable 32-bit RISC-V optimizations"
+TUNEVALID[riscv64nf] = "Enable 64-bit RISC-V optimizations no floating point"
+TUNEVALID[riscv32nf] = "Enable 32-bit RISC-V optimizations no floating point"
+
TUNEVALID[bigendian] = "Big endian mode"
-AVAILTUNES += "riscv64 riscv32"
+AVAILTUNES += "riscv64 riscv32 riscv64nf riscv32nf"
+# Default
TUNE_FEATURES_tune-riscv64 = "riscv64"
TUNE_ARCH_tune-riscv64 = "riscv64"
TUNE_PKGARCH_tune-riscv64 = "riscv64"
@@ -17,3 +21,13 @@ TUNE_ARCH_tune-riscv32 = "riscv32"
TUNE_PKGARCH_tune-riscv32 = "riscv32"
PACKAGE_EXTRA_ARCHS_tune-riscv32 = "riscv32"
+# No float
+TUNE_FEATURES_tune-riscv64nf = "${TUNE_FEATURES_tune-riscv64} riscv64nf"
+TUNE_ARCH_tune-riscv64nf = "riscv64"
+TUNE_PKGARCH_tune-riscv64nf = "riscv64"
+PACKAGE_EXTRA_ARCHS_tune-riscv64nf = "riscv64"
+
+TUNE_FEATURES_tune-riscv32nf = "${TUNE_FEATURES_tune-riscv32} riscv32nf"
+TUNE_ARCH_tune-riscv32nf = "riscv32"
+TUNE_PKGARCH_tune-riscv32nf = "riscv32"
+PACKAGE_EXTRA_ARCHS_tune-riscv32nf = "riscv32"
--
2.23.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2019-11-22 0:48 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-22 0:02 [PATCH v2] tune-riscv: Add support for no float Alistair Francis
2019-11-22 0:33 ` Andre McCurdy
2019-11-22 0:47 ` Khem Raj
-- strict thread matches above, loose matches on Subject: below --
2019-11-07 0:48 Alistair Francis
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.