* [PATCH v1 0/1] gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq
@ 2021-12-14 4:02 ` Steven Lee
0 siblings, 0 replies; 10+ messages in thread
From: Steven Lee @ 2021-12-14 4:02 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, Joel Stanley, Andrew Jeffery,
open list:GPIO SUBSYSTEM,
moderated list:ARM/ASPEED MACHINE SUPPORT,
moderated list:ARM/ASPEED MACHINE SUPPORT, open list
Cc: steven_lee, Hongweiz, ryan_chen, billy_tsai
Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins)
The hwirq base for each sgpio bank should be multiples of 64 rather than
multiples of 32.
This patch series contains a patch for fixing wrong hwirq base in
irq handler.
Please help to review.
Steven Lee (1):
gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler
drivers/gpio/gpio-aspeed-sgpio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--
2.17.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v1 0/1] gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq
@ 2021-12-14 4:02 ` Steven Lee
0 siblings, 0 replies; 10+ messages in thread
From: Steven Lee @ 2021-12-14 4:02 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, Joel Stanley, Andrew Jeffery,
open list:GPIO SUBSYSTEM,
moderated list:ARM/ASPEED MACHINE SUPPORT,
moderated list:ARM/ASPEED MACHINE SUPPORT, open list
Cc: steven_lee, Hongweiz, ryan_chen, billy_tsai
Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins)
The hwirq base for each sgpio bank should be multiples of 64 rather than
multiples of 32.
This patch series contains a patch for fixing wrong hwirq base in
irq handler.
Please help to review.
Steven Lee (1):
gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler
drivers/gpio/gpio-aspeed-sgpio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v1 1/1] gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler
2021-12-14 4:02 ` Steven Lee
@ 2021-12-14 4:02 ` Steven Lee
-1 siblings, 0 replies; 10+ messages in thread
From: Steven Lee @ 2021-12-14 4:02 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, Joel Stanley, Andrew Jeffery,
open list:GPIO SUBSYSTEM,
moderated list:ARM/ASPEED MACHINE SUPPORT,
moderated list:ARM/ASPEED MACHINE SUPPORT, open list
Cc: steven_lee, Hongweiz, ryan_chen, billy_tsai
Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins).
The hwirq base for each sgpio bank should be multiples of 64 rather than
multiples of 32.
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
drivers/gpio/gpio-aspeed-sgpio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index 3d6ef37a7702..b3a9b8488f11 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -395,7 +395,7 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
reg = ioread32(bank_reg(data, bank, reg_irq_status));
for_each_set_bit(p, ®, 32)
- generic_handle_domain_irq(gc->irq.domain, i * 32 + p * 2);
+ generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2);
}
chained_irq_exit(ic, desc);
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v1 1/1] gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler
@ 2021-12-14 4:02 ` Steven Lee
0 siblings, 0 replies; 10+ messages in thread
From: Steven Lee @ 2021-12-14 4:02 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, Joel Stanley, Andrew Jeffery,
open list:GPIO SUBSYSTEM,
moderated list:ARM/ASPEED MACHINE SUPPORT,
moderated list:ARM/ASPEED MACHINE SUPPORT, open list
Cc: steven_lee, Hongweiz, ryan_chen, billy_tsai
Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins).
The hwirq base for each sgpio bank should be multiples of 64 rather than
multiples of 32.
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
drivers/gpio/gpio-aspeed-sgpio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index 3d6ef37a7702..b3a9b8488f11 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -395,7 +395,7 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
reg = ioread32(bank_reg(data, bank, reg_irq_status));
for_each_set_bit(p, ®, 32)
- generic_handle_domain_irq(gc->irq.domain, i * 32 + p * 2);
+ generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2);
}
chained_irq_exit(ic, desc);
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v1 1/1] gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler
2021-12-14 4:02 ` Steven Lee
@ 2021-12-22 9:18 ` Bartosz Golaszewski
-1 siblings, 0 replies; 10+ messages in thread
From: Bartosz Golaszewski @ 2021-12-22 9:18 UTC (permalink / raw)
To: Steven Lee, Joel Stanley, Andrew Jeffery
Cc: Linus Walleij, open list:GPIO SUBSYSTEM,
moderated list:ARM/ASPEED MACHINE SUPPORT,
moderated list:ARM/ASPEED MACHINE SUPPORT, open list,
Hongwei Zhang, ryan_chen, billy_tsai
On Tue, Dec 14, 2021 at 5:03 AM Steven Lee <steven_lee@aspeedtech.com> wrote:
>
> Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins).
> The hwirq base for each sgpio bank should be multiples of 64 rather than
> multiples of 32.
>
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> ---
> drivers/gpio/gpio-aspeed-sgpio.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
> index 3d6ef37a7702..b3a9b8488f11 100644
> --- a/drivers/gpio/gpio-aspeed-sgpio.c
> +++ b/drivers/gpio/gpio-aspeed-sgpio.c
> @@ -395,7 +395,7 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
> reg = ioread32(bank_reg(data, bank, reg_irq_status));
>
> for_each_set_bit(p, ®, 32)
> - generic_handle_domain_irq(gc->irq.domain, i * 32 + p * 2);
> + generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2);
> }
>
> chained_irq_exit(ic, desc);
> --
> 2.17.1
>
Joel, Andrew: any comments on this? I'd like to send it upstream tomorrow.
Bart
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v1 1/1] gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler
@ 2021-12-22 9:18 ` Bartosz Golaszewski
0 siblings, 0 replies; 10+ messages in thread
From: Bartosz Golaszewski @ 2021-12-22 9:18 UTC (permalink / raw)
To: Steven Lee, Joel Stanley, Andrew Jeffery
Cc: Linus Walleij, open list:GPIO SUBSYSTEM,
moderated list:ARM/ASPEED MACHINE SUPPORT,
moderated list:ARM/ASPEED MACHINE SUPPORT, open list,
Hongwei Zhang, ryan_chen, billy_tsai
On Tue, Dec 14, 2021 at 5:03 AM Steven Lee <steven_lee@aspeedtech.com> wrote:
>
> Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins).
> The hwirq base for each sgpio bank should be multiples of 64 rather than
> multiples of 32.
>
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> ---
> drivers/gpio/gpio-aspeed-sgpio.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
> index 3d6ef37a7702..b3a9b8488f11 100644
> --- a/drivers/gpio/gpio-aspeed-sgpio.c
> +++ b/drivers/gpio/gpio-aspeed-sgpio.c
> @@ -395,7 +395,7 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
> reg = ioread32(bank_reg(data, bank, reg_irq_status));
>
> for_each_set_bit(p, ®, 32)
> - generic_handle_domain_irq(gc->irq.domain, i * 32 + p * 2);
> + generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2);
> }
>
> chained_irq_exit(ic, desc);
> --
> 2.17.1
>
Joel, Andrew: any comments on this? I'd like to send it upstream tomorrow.
Bart
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v1 1/1] gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler
2021-12-22 9:18 ` Bartosz Golaszewski
@ 2022-01-03 9:50 ` Bartosz Golaszewski
-1 siblings, 0 replies; 10+ messages in thread
From: Bartosz Golaszewski @ 2022-01-03 9:50 UTC (permalink / raw)
To: Steven Lee, Joel Stanley, Andrew Jeffery
Cc: Linus Walleij, open list:GPIO SUBSYSTEM,
moderated list:ARM/ASPEED MACHINE SUPPORT,
moderated list:ARM/ASPEED MACHINE SUPPORT, open list,
Hongwei Zhang, ryan_chen, billy_tsai
On Wed, Dec 22, 2021 at 10:18 AM Bartosz Golaszewski <brgl@bgdev.pl> wrote:
>
> On Tue, Dec 14, 2021 at 5:03 AM Steven Lee <steven_lee@aspeedtech.com> wrote:
> >
> > Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins).
> > The hwirq base for each sgpio bank should be multiples of 64 rather than
> > multiples of 32.
> >
> > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> > ---
> > drivers/gpio/gpio-aspeed-sgpio.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
> > index 3d6ef37a7702..b3a9b8488f11 100644
> > --- a/drivers/gpio/gpio-aspeed-sgpio.c
> > +++ b/drivers/gpio/gpio-aspeed-sgpio.c
> > @@ -395,7 +395,7 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
> > reg = ioread32(bank_reg(data, bank, reg_irq_status));
> >
> > for_each_set_bit(p, ®, 32)
> > - generic_handle_domain_irq(gc->irq.domain, i * 32 + p * 2);
> > + generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2);
> > }
> >
> > chained_irq_exit(ic, desc);
> > --
> > 2.17.1
> >
>
> Joel, Andrew: any comments on this? I'd like to send it upstream tomorrow.
>
> Bart
I don't want to delay it anymore, it looks good so I queued it for fixes.
Bart
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v1 1/1] gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler
@ 2022-01-03 9:50 ` Bartosz Golaszewski
0 siblings, 0 replies; 10+ messages in thread
From: Bartosz Golaszewski @ 2022-01-03 9:50 UTC (permalink / raw)
To: Steven Lee, Joel Stanley, Andrew Jeffery
Cc: Linus Walleij, open list:GPIO SUBSYSTEM,
moderated list:ARM/ASPEED MACHINE SUPPORT,
moderated list:ARM/ASPEED MACHINE SUPPORT, open list,
Hongwei Zhang, ryan_chen, billy_tsai
On Wed, Dec 22, 2021 at 10:18 AM Bartosz Golaszewski <brgl@bgdev.pl> wrote:
>
> On Tue, Dec 14, 2021 at 5:03 AM Steven Lee <steven_lee@aspeedtech.com> wrote:
> >
> > Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins).
> > The hwirq base for each sgpio bank should be multiples of 64 rather than
> > multiples of 32.
> >
> > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> > ---
> > drivers/gpio/gpio-aspeed-sgpio.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
> > index 3d6ef37a7702..b3a9b8488f11 100644
> > --- a/drivers/gpio/gpio-aspeed-sgpio.c
> > +++ b/drivers/gpio/gpio-aspeed-sgpio.c
> > @@ -395,7 +395,7 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
> > reg = ioread32(bank_reg(data, bank, reg_irq_status));
> >
> > for_each_set_bit(p, ®, 32)
> > - generic_handle_domain_irq(gc->irq.domain, i * 32 + p * 2);
> > + generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2);
> > }
> >
> > chained_irq_exit(ic, desc);
> > --
> > 2.17.1
> >
>
> Joel, Andrew: any comments on this? I'd like to send it upstream tomorrow.
>
> Bart
I don't want to delay it anymore, it looks good so I queued it for fixes.
Bart
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v1 1/1] gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler
2022-01-03 9:50 ` Bartosz Golaszewski
@ 2022-01-12 0:53 ` Joel Stanley
-1 siblings, 0 replies; 10+ messages in thread
From: Joel Stanley @ 2022-01-12 0:53 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Steven Lee, Andrew Jeffery, Linus Walleij,
open list:GPIO SUBSYSTEM,
moderated list:ARM/ASPEED MACHINE SUPPORT,
moderated list:ARM/ASPEED MACHINE SUPPORT, open list,
Hongwei Zhang, Ryan Chen, Billy Tsai
On Mon, 3 Jan 2022 at 09:50, Bartosz Golaszewski <brgl@bgdev.pl> wrote:
>
> On Wed, Dec 22, 2021 at 10:18 AM Bartosz Golaszewski <brgl@bgdev.pl> wrote:
> >
> > On Tue, Dec 14, 2021 at 5:03 AM Steven Lee <steven_lee@aspeedtech.com> wrote:
> > >
> > > Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins).
> > > The hwirq base for each sgpio bank should be multiples of 64 rather than
> > > multiples of 32.
> > >
> > > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> > > ---
> > > drivers/gpio/gpio-aspeed-sgpio.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
> > > index 3d6ef37a7702..b3a9b8488f11 100644
> > > --- a/drivers/gpio/gpio-aspeed-sgpio.c
> > > +++ b/drivers/gpio/gpio-aspeed-sgpio.c
> > > @@ -395,7 +395,7 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
> > > reg = ioread32(bank_reg(data, bank, reg_irq_status));
> > >
> > > for_each_set_bit(p, ®, 32)
> > > - generic_handle_domain_irq(gc->irq.domain, i * 32 + p * 2);
> > > + generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2);
> > > }
> > >
> > > chained_irq_exit(ic, desc);
> > > --
> > > 2.17.1
> > >
> >
> > Joel, Andrew: any comments on this? I'd like to send it upstream tomorrow.
> >
> > Bart
>
> I don't want to delay it anymore, it looks good so I queued it for fixes.
Thanks for queuing. We were on leave over the holiday break, so no
time for reviewing kernel patches.
Cheers,
Joel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v1 1/1] gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler
@ 2022-01-12 0:53 ` Joel Stanley
0 siblings, 0 replies; 10+ messages in thread
From: Joel Stanley @ 2022-01-12 0:53 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Steven Lee, Andrew Jeffery, Linus Walleij,
open list:GPIO SUBSYSTEM,
moderated list:ARM/ASPEED MACHINE SUPPORT,
moderated list:ARM/ASPEED MACHINE SUPPORT, open list,
Hongwei Zhang, Ryan Chen, Billy Tsai
On Mon, 3 Jan 2022 at 09:50, Bartosz Golaszewski <brgl@bgdev.pl> wrote:
>
> On Wed, Dec 22, 2021 at 10:18 AM Bartosz Golaszewski <brgl@bgdev.pl> wrote:
> >
> > On Tue, Dec 14, 2021 at 5:03 AM Steven Lee <steven_lee@aspeedtech.com> wrote:
> > >
> > > Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins).
> > > The hwirq base for each sgpio bank should be multiples of 64 rather than
> > > multiples of 32.
> > >
> > > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> > > ---
> > > drivers/gpio/gpio-aspeed-sgpio.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
> > > index 3d6ef37a7702..b3a9b8488f11 100644
> > > --- a/drivers/gpio/gpio-aspeed-sgpio.c
> > > +++ b/drivers/gpio/gpio-aspeed-sgpio.c
> > > @@ -395,7 +395,7 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
> > > reg = ioread32(bank_reg(data, bank, reg_irq_status));
> > >
> > > for_each_set_bit(p, ®, 32)
> > > - generic_handle_domain_irq(gc->irq.domain, i * 32 + p * 2);
> > > + generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2);
> > > }
> > >
> > > chained_irq_exit(ic, desc);
> > > --
> > > 2.17.1
> > >
> >
> > Joel, Andrew: any comments on this? I'd like to send it upstream tomorrow.
> >
> > Bart
>
> I don't want to delay it anymore, it looks good so I queued it for fixes.
Thanks for queuing. We were on leave over the holiday break, so no
time for reviewing kernel patches.
Cheers,
Joel
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2022-01-12 0:54 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-14 4:02 [PATCH v1 0/1] gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq Steven Lee
2021-12-14 4:02 ` Steven Lee
2021-12-14 4:02 ` [PATCH v1 1/1] gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler Steven Lee
2021-12-14 4:02 ` Steven Lee
2021-12-22 9:18 ` Bartosz Golaszewski
2021-12-22 9:18 ` Bartosz Golaszewski
2022-01-03 9:50 ` Bartosz Golaszewski
2022-01-03 9:50 ` Bartosz Golaszewski
2022-01-12 0:53 ` Joel Stanley
2022-01-12 0:53 ` Joel Stanley
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