[PATCH v1 0/3] Add BananaPi R2 Pro board

[PATCH v1 0/3] Add BananaPi R2 Pro board

[Frank Wunderlich]

From: Frank Wunderlich <frank-w@public-files.de>

This Series adds RK3568 based Bananapi R2 Board.

While testing new dts with dtbs_check we've found an issue with
mainline gmac0 node in rk3568.dtsi which breaks dtbs_check. So first
Patch fixes this problem.

Frank Wunderlich (3):
  dts64: rk3568: drop pclk_xpcs from gmac0
  dt-bindings: rockchip: Add BananaPi R2 Pro Board
  dts64: rockchip: Add Bananapi R2 Pro

 .../devicetree/bindings/arm/rockchip.yaml     |   5 +
 arch/arm64/boot/dts/rockchip/Makefile         |   1 +
 .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts   | 428 ++++++++++++++++++
 arch/arm64/boot/dts/rockchip/rk3568.dtsi      |   6 +-
 4 files changed, 436 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts

-- 
2.25.1

[PATCH v1 0/3] Add BananaPi R2 Pro board

[Frank Wunderlich]

From: Frank Wunderlich <frank-w@public-files.de>

This Series adds RK3568 based Bananapi R2 Board.

While testing new dts with dtbs_check we've found an issue with
mainline gmac0 node in rk3568.dtsi which breaks dtbs_check. So first
Patch fixes this problem.

Frank Wunderlich (3):
  dts64: rk3568: drop pclk_xpcs from gmac0
  dt-bindings: rockchip: Add BananaPi R2 Pro Board
  dts64: rockchip: Add Bananapi R2 Pro

 .../devicetree/bindings/arm/rockchip.yaml     |   5 +
 arch/arm64/boot/dts/rockchip/Makefile         |   1 +
 .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts   | 428 ++++++++++++++++++
 arch/arm64/boot/dts/rockchip/rk3568.dtsi      |   6 +-
 4 files changed, 436 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts

-- 
2.25.1


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[PATCH v1 0/3] Add BananaPi R2 Pro board

[Frank Wunderlich]

From: Frank Wunderlich <frank-w@public-files.de>

This Series adds RK3568 based Bananapi R2 Board.

While testing new dts with dtbs_check we've found an issue with
mainline gmac0 node in rk3568.dtsi which breaks dtbs_check. So first
Patch fixes this problem.

Frank Wunderlich (3):
  dts64: rk3568: drop pclk_xpcs from gmac0
  dt-bindings: rockchip: Add BananaPi R2 Pro Board
  dts64: rockchip: Add Bananapi R2 Pro

 .../devicetree/bindings/arm/rockchip.yaml     |   5 +
 arch/arm64/boot/dts/rockchip/Makefile         |   1 +
 .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts   | 428 ++++++++++++++++++
 arch/arm64/boot/dts/rockchip/rk3568.dtsi      |   6 +-
 4 files changed, 436 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts

-- 
2.25.1


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[PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Frank Wunderlich]

From: Frank Wunderlich <frank-w@public-files.de>

pclk_xpcs is not supported and breaks dtbs_check, so remove it

following warnings occour, and many more

rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clocks:
    [[15, 386], [15, 389], [15, 389], [15, 184], [15, 180], [15, 181],
    [15, 389], [15, 185], [15, 172]] is too long
	From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clock-names:
    ['stmmaceth', 'mac_clk_rx', 'mac_clk_tx', 'clk_mac_refout', 'aclk_mac',
    'pclk_mac', 'clk_mac_speed', 'ptp_ref', 'pclk_xpcs'] is too long
	From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml

after removing the clock the other warnings are also gone.

Co-developed-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
 arch/arm64/boot/dts/rockchip/rk3568.dtsi | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index 2fd313a295f8..d91df1cde736 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -32,13 +32,11 @@ gmac0: ethernet@fe2a0000 {
 		clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
 			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
 			 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
-			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
-			 <&cru PCLK_XPCS>;
+			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
 		clock-names = "stmmaceth", "mac_clk_rx",
 			      "mac_clk_tx", "clk_mac_refout",
 			      "aclk_mac", "pclk_mac",
-			      "clk_mac_speed", "ptp_ref",
-			      "pclk_xpcs";
+			      "clk_mac_speed", "ptp_ref";
 		resets = <&cru SRST_A_GMAC0>;
 		reset-names = "stmmaceth";
 		rockchip,grf = <&grf>;
-- 
2.25.1

[PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Frank Wunderlich]

From: Frank Wunderlich <frank-w@public-files.de>

pclk_xpcs is not supported and breaks dtbs_check, so remove it

following warnings occour, and many more

rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clocks:
    [[15, 386], [15, 389], [15, 389], [15, 184], [15, 180], [15, 181],
    [15, 389], [15, 185], [15, 172]] is too long
	From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clock-names:
    ['stmmaceth', 'mac_clk_rx', 'mac_clk_tx', 'clk_mac_refout', 'aclk_mac',
    'pclk_mac', 'clk_mac_speed', 'ptp_ref', 'pclk_xpcs'] is too long
	From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml

after removing the clock the other warnings are also gone.

Co-developed-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
 arch/arm64/boot/dts/rockchip/rk3568.dtsi | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index 2fd313a295f8..d91df1cde736 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -32,13 +32,11 @@ gmac0: ethernet@fe2a0000 {
 		clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
 			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
 			 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
-			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
-			 <&cru PCLK_XPCS>;
+			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
 		clock-names = "stmmaceth", "mac_clk_rx",
 			      "mac_clk_tx", "clk_mac_refout",
 			      "aclk_mac", "pclk_mac",
-			      "clk_mac_speed", "ptp_ref",
-			      "pclk_xpcs";
+			      "clk_mac_speed", "ptp_ref";
 		resets = <&cru SRST_A_GMAC0>;
 		reset-names = "stmmaceth";
 		rockchip,grf = <&grf>;
-- 
2.25.1


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[PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Frank Wunderlich]

From: Frank Wunderlich <frank-w@public-files.de>

pclk_xpcs is not supported and breaks dtbs_check, so remove it

following warnings occour, and many more

rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clocks:
    [[15, 386], [15, 389], [15, 389], [15, 184], [15, 180], [15, 181],
    [15, 389], [15, 185], [15, 172]] is too long
	From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clock-names:
    ['stmmaceth', 'mac_clk_rx', 'mac_clk_tx', 'clk_mac_refout', 'aclk_mac',
    'pclk_mac', 'clk_mac_speed', 'ptp_ref', 'pclk_xpcs'] is too long
	From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml

after removing the clock the other warnings are also gone.

Co-developed-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
 arch/arm64/boot/dts/rockchip/rk3568.dtsi | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index 2fd313a295f8..d91df1cde736 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -32,13 +32,11 @@ gmac0: ethernet@fe2a0000 {
 		clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
 			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
 			 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
-			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
-			 <&cru PCLK_XPCS>;
+			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
 		clock-names = "stmmaceth", "mac_clk_rx",
 			      "mac_clk_tx", "clk_mac_refout",
 			      "aclk_mac", "pclk_mac",
-			      "clk_mac_speed", "ptp_ref",
-			      "pclk_xpcs";
+			      "clk_mac_speed", "ptp_ref";
 		resets = <&cru SRST_A_GMAC0>;
 		reset-names = "stmmaceth";
 		rockchip,grf = <&grf>;
-- 
2.25.1


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[PATCH v1 2/3] dt-bindings: rockchip: Add BananaPi R2 Pro Board

[Frank Wunderlich]

From: Frank Wunderlich <frank-w@public-files.de>

Add Devicetree Binding for Bananapi R2 Pro Board based on rk3568 SoC

Co-developed-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
 Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index 4aed16176434..33d6423fe6c3 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -651,6 +651,11 @@ properties:
           - const: rockchip,rk3568-evb1-v10
           - const: rockchip,rk3568
 
+      - description: Rockchip RK3568 Banana Pi R2 Pro
+        items:
+          - const: rockchip,rk3568-bpi-r2pro
+          - const: rockchip,rk3568
+
 additionalProperties: true
 
 ...
-- 
2.25.1

[PATCH v1 2/3] dt-bindings: rockchip: Add BananaPi R2 Pro Board

[Frank Wunderlich]

From: Frank Wunderlich <frank-w@public-files.de>

Add Devicetree Binding for Bananapi R2 Pro Board based on rk3568 SoC

Co-developed-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
 Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index 4aed16176434..33d6423fe6c3 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -651,6 +651,11 @@ properties:
           - const: rockchip,rk3568-evb1-v10
           - const: rockchip,rk3568
 
+      - description: Rockchip RK3568 Banana Pi R2 Pro
+        items:
+          - const: rockchip,rk3568-bpi-r2pro
+          - const: rockchip,rk3568
+
 additionalProperties: true
 
 ...
-- 
2.25.1


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http://lists.infradead.org/mailman/listinfo/linux-rockchip

[PATCH v1 2/3] dt-bindings: rockchip: Add BananaPi R2 Pro Board

[Frank Wunderlich]

From: Frank Wunderlich <frank-w@public-files.de>

Add Devicetree Binding for Bananapi R2 Pro Board based on rk3568 SoC

Co-developed-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
 Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index 4aed16176434..33d6423fe6c3 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -651,6 +651,11 @@ properties:
           - const: rockchip,rk3568-evb1-v10
           - const: rockchip,rk3568
 
+      - description: Rockchip RK3568 Banana Pi R2 Pro
+        items:
+          - const: rockchip,rk3568-bpi-r2pro
+          - const: rockchip,rk3568
+
 additionalProperties: true
 
 ...
-- 
2.25.1


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[PATCH v1 3/3] dts64: rockchip: Add Bananapi R2 Pro

[Frank Wunderlich]

From: Frank Wunderlich <frank-w@public-files.de>

This patch add rk3568-bpi-r2-pro.dts for Bananapi R2 Pro based on RK3568.
Add uart/emmc/i2c/rk809/tsadc node for basic function.
Gmac0 is directly connected to wan-port so usable without additional
driver.
On gmac1 there is a switch (rtl8367rb) is connected which have not yet a
driver in mainline. A DSA driver for it is about to be merged.

Patch also prepares nodes for GPIO header.

Co-developed-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
 arch/arm64/boot/dts/rockchip/Makefile         |   1 +
 .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts   | 428 ++++++++++++++++++
 2 files changed, 429 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts

diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 479906f3ad7b..70007b370d87 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -58,3 +58,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
new file mode 100644
index 000000000000..3455980dd393
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
@@ -0,0 +1,428 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Author: Frank Wunderlich <frank-w@public-files.de>
+ *
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "Bananapi-R2 Pro (RK3568) DDR4 V00 Board";
+	compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568";
+
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+		bootargs = "earlycon=uart8250,mmio32,0xfe660000";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-green {
+			label = "gpio-green";
+			gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		led-blue {
+			label = "gpio-blue";
+			gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+
+	dc_12v: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+};
+
+&gmac0 {
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
+	clock_in_out = "input";
+	phy-handle = <&rgmii_phy0>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+
+	tx_delay = <0x3c>;
+	rx_delay = <0x2f>;
+
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>;
+		rockchip,system-power-controller;
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		wakeup-source;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+				regulator-always-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2c5 {
+	/* pin 3 + 4 of header con2 */
+	status = "disabled";
+};
+
+&mdio0 {
+	rgmii_phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x0>;
+	};
+};
+
+&pinctrl {
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins =
+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_3v3>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&pwm10 {
+	/* pin 7 of header con2 */
+	status = "disabled";
+};
+
+&pwm11 {
+	/* pin 15 of header con2 */
+	status = "disabled";
+};
+
+&pwm12 {
+	/* pin 21 of header con2 */
+	status = "disabled";
+};
+
+&pwm13 {
+	/* pin 24 of header con2 */
+	status = "disabled";
+};
+
+&pwm14 {
+	/* pin 23 of header con2 */
+	status = "disabled";
+};
+
+&pwm15 {
+	/* pin 19 of header con2 */
+	status = "disabled";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&spi3 {
+	/* pin 19 + 21 + 23 of header con2 */
+	status = "disabled";
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&uart0 {
+	/* pin 8 + 10 (RTS:16, CTS: 18) of header con2 */
+	status = "disabled";
+};
+
+&uart2 {
+	/* debug-uart */
+	status = "okay";
+};
+
+&uart7 {
+	/* pin 11 + 13 of header con2 */
+	status = "disabled";
+};
+
+&uart9 {
+	/* pin 21 + 24 of header con2 */
+	status = "disabled";
+};
-- 
2.25.1

[PATCH v1 3/3] dts64: rockchip: Add Bananapi R2 Pro

[Frank Wunderlich]

From: Frank Wunderlich <frank-w@public-files.de>

This patch add rk3568-bpi-r2-pro.dts for Bananapi R2 Pro based on RK3568.
Add uart/emmc/i2c/rk809/tsadc node for basic function.
Gmac0 is directly connected to wan-port so usable without additional
driver.
On gmac1 there is a switch (rtl8367rb) is connected which have not yet a
driver in mainline. A DSA driver for it is about to be merged.

Patch also prepares nodes for GPIO header.

Co-developed-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
 arch/arm64/boot/dts/rockchip/Makefile         |   1 +
 .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts   | 428 ++++++++++++++++++
 2 files changed, 429 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts

diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 479906f3ad7b..70007b370d87 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -58,3 +58,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
new file mode 100644
index 000000000000..3455980dd393
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
@@ -0,0 +1,428 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Author: Frank Wunderlich <frank-w@public-files.de>
+ *
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "Bananapi-R2 Pro (RK3568) DDR4 V00 Board";
+	compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568";
+
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+		bootargs = "earlycon=uart8250,mmio32,0xfe660000";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-green {
+			label = "gpio-green";
+			gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		led-blue {
+			label = "gpio-blue";
+			gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+
+	dc_12v: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+};
+
+&gmac0 {
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
+	clock_in_out = "input";
+	phy-handle = <&rgmii_phy0>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+
+	tx_delay = <0x3c>;
+	rx_delay = <0x2f>;
+
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>;
+		rockchip,system-power-controller;
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		wakeup-source;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+				regulator-always-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2c5 {
+	/* pin 3 + 4 of header con2 */
+	status = "disabled";
+};
+
+&mdio0 {
+	rgmii_phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x0>;
+	};
+};
+
+&pinctrl {
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins =
+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_3v3>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&pwm10 {
+	/* pin 7 of header con2 */
+	status = "disabled";
+};
+
+&pwm11 {
+	/* pin 15 of header con2 */
+	status = "disabled";
+};
+
+&pwm12 {
+	/* pin 21 of header con2 */
+	status = "disabled";
+};
+
+&pwm13 {
+	/* pin 24 of header con2 */
+	status = "disabled";
+};
+
+&pwm14 {
+	/* pin 23 of header con2 */
+	status = "disabled";
+};
+
+&pwm15 {
+	/* pin 19 of header con2 */
+	status = "disabled";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&spi3 {
+	/* pin 19 + 21 + 23 of header con2 */
+	status = "disabled";
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&uart0 {
+	/* pin 8 + 10 (RTS:16, CTS: 18) of header con2 */
+	status = "disabled";
+};
+
+&uart2 {
+	/* debug-uart */
+	status = "okay";
+};
+
+&uart7 {
+	/* pin 11 + 13 of header con2 */
+	status = "disabled";
+};
+
+&uart9 {
+	/* pin 21 + 24 of header con2 */
+	status = "disabled";
+};
-- 
2.25.1


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[PATCH v1 3/3] dts64: rockchip: Add Bananapi R2 Pro

[Frank Wunderlich]

From: Frank Wunderlich <frank-w@public-files.de>

This patch add rk3568-bpi-r2-pro.dts for Bananapi R2 Pro based on RK3568.
Add uart/emmc/i2c/rk809/tsadc node for basic function.
Gmac0 is directly connected to wan-port so usable without additional
driver.
On gmac1 there is a switch (rtl8367rb) is connected which have not yet a
driver in mainline. A DSA driver for it is about to be merged.

Patch also prepares nodes for GPIO header.

Co-developed-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
 arch/arm64/boot/dts/rockchip/Makefile         |   1 +
 .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts   | 428 ++++++++++++++++++
 2 files changed, 429 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts

diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 479906f3ad7b..70007b370d87 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -58,3 +58,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
new file mode 100644
index 000000000000..3455980dd393
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
@@ -0,0 +1,428 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Author: Frank Wunderlich <frank-w@public-files.de>
+ *
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "Bananapi-R2 Pro (RK3568) DDR4 V00 Board";
+	compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568";
+
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+		bootargs = "earlycon=uart8250,mmio32,0xfe660000";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-green {
+			label = "gpio-green";
+			gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		led-blue {
+			label = "gpio-blue";
+			gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+
+	dc_12v: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+};
+
+&gmac0 {
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
+	clock_in_out = "input";
+	phy-handle = <&rgmii_phy0>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+
+	tx_delay = <0x3c>;
+	rx_delay = <0x2f>;
+
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>;
+		rockchip,system-power-controller;
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		wakeup-source;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+				regulator-always-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2c5 {
+	/* pin 3 + 4 of header con2 */
+	status = "disabled";
+};
+
+&mdio0 {
+	rgmii_phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x0>;
+	};
+};
+
+&pinctrl {
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins =
+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_3v3>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&pwm10 {
+	/* pin 7 of header con2 */
+	status = "disabled";
+};
+
+&pwm11 {
+	/* pin 15 of header con2 */
+	status = "disabled";
+};
+
+&pwm12 {
+	/* pin 21 of header con2 */
+	status = "disabled";
+};
+
+&pwm13 {
+	/* pin 24 of header con2 */
+	status = "disabled";
+};
+
+&pwm14 {
+	/* pin 23 of header con2 */
+	status = "disabled";
+};
+
+&pwm15 {
+	/* pin 19 of header con2 */
+	status = "disabled";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&spi3 {
+	/* pin 19 + 21 + 23 of header con2 */
+	status = "disabled";
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&uart0 {
+	/* pin 8 + 10 (RTS:16, CTS: 18) of header con2 */
+	status = "disabled";
+};
+
+&uart2 {
+	/* debug-uart */
+	status = "okay";
+};
+
+&uart7 {
+	/* pin 11 + 13 of header con2 */
+	status = "disabled";
+};
+
+&uart9 {
+	/* pin 21 + 24 of header con2 */
+	status = "disabled";
+};
-- 
2.25.1


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Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Michael Riesch]

Hello Frank,

On 1/16/22 13:49, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w@public-files.de>
> 
> pclk_xpcs is not supported and breaks dtbs_check, so remove it
> 
> following warnings occour, and many more
> 
> rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clocks:
>     [[15, 386], [15, 389], [15, 389], [15, 184], [15, 180], [15, 181],
>     [15, 389], [15, 185], [15, 172]] is too long
> 	From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
> rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clock-names:
>     ['stmmaceth', 'mac_clk_rx', 'mac_clk_tx', 'clk_mac_refout', 'aclk_mac',
>     'pclk_mac', 'clk_mac_speed', 'ptp_ref', 'pclk_xpcs'] is too long
> 	From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
> 
> after removing the clock the other warnings are also gone.
> 
> Co-developed-by: Peter Geis <pgwipeout@gmail.com>
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> ---
>  arch/arm64/boot/dts/rockchip/rk3568.dtsi | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> index 2fd313a295f8..d91df1cde736 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> @@ -32,13 +32,11 @@ gmac0: ethernet@fe2a0000 {
>  		clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
>  			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
>  			 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
> -			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
> -			 <&cru PCLK_XPCS>;
> +			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
>  		clock-names = "stmmaceth", "mac_clk_rx",
>  			      "mac_clk_tx", "clk_mac_refout",
>  			      "aclk_mac", "pclk_mac",
> -			      "clk_mac_speed", "ptp_ref",
> -			      "pclk_xpcs";
> +			      "clk_mac_speed", "ptp_ref";
>  		resets = <&cru SRST_A_GMAC0>;
>  		reset-names = "stmmaceth";
>  		rockchip,grf = <&grf>;

This has been on my TODO list for a while, but I never found the time to
submit this cleanup. As far as I am concerned:

Acked-by: Michael Riesch <michael.riesch@wolfvision.net>

Thanks and best regards,
Michael

Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Michael Riesch]

Hello Frank,

On 1/16/22 13:49, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w@public-files.de>
> 
> pclk_xpcs is not supported and breaks dtbs_check, so remove it
> 
> following warnings occour, and many more
> 
> rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clocks:
>     [[15, 386], [15, 389], [15, 389], [15, 184], [15, 180], [15, 181],
>     [15, 389], [15, 185], [15, 172]] is too long
> 	From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
> rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clock-names:
>     ['stmmaceth', 'mac_clk_rx', 'mac_clk_tx', 'clk_mac_refout', 'aclk_mac',
>     'pclk_mac', 'clk_mac_speed', 'ptp_ref', 'pclk_xpcs'] is too long
> 	From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
> 
> after removing the clock the other warnings are also gone.
> 
> Co-developed-by: Peter Geis <pgwipeout@gmail.com>
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> ---
>  arch/arm64/boot/dts/rockchip/rk3568.dtsi | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> index 2fd313a295f8..d91df1cde736 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> @@ -32,13 +32,11 @@ gmac0: ethernet@fe2a0000 {
>  		clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
>  			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
>  			 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
> -			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
> -			 <&cru PCLK_XPCS>;
> +			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
>  		clock-names = "stmmaceth", "mac_clk_rx",
>  			      "mac_clk_tx", "clk_mac_refout",
>  			      "aclk_mac", "pclk_mac",
> -			      "clk_mac_speed", "ptp_ref",
> -			      "pclk_xpcs";
> +			      "clk_mac_speed", "ptp_ref";
>  		resets = <&cru SRST_A_GMAC0>;
>  		reset-names = "stmmaceth";
>  		rockchip,grf = <&grf>;

This has been on my TODO list for a while, but I never found the time to
submit this cleanup. As far as I am concerned:

Acked-by: Michael Riesch <michael.riesch@wolfvision.net>

Thanks and best regards,
Michael

_______________________________________________
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Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Michael Riesch]

Hello Frank,

On 1/16/22 13:49, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w@public-files.de>
> 
> pclk_xpcs is not supported and breaks dtbs_check, so remove it
> 
> following warnings occour, and many more
> 
> rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clocks:
>     [[15, 386], [15, 389], [15, 389], [15, 184], [15, 180], [15, 181],
>     [15, 389], [15, 185], [15, 172]] is too long
> 	From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
> rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clock-names:
>     ['stmmaceth', 'mac_clk_rx', 'mac_clk_tx', 'clk_mac_refout', 'aclk_mac',
>     'pclk_mac', 'clk_mac_speed', 'ptp_ref', 'pclk_xpcs'] is too long
> 	From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
> 
> after removing the clock the other warnings are also gone.
> 
> Co-developed-by: Peter Geis <pgwipeout@gmail.com>
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> ---
>  arch/arm64/boot/dts/rockchip/rk3568.dtsi | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> index 2fd313a295f8..d91df1cde736 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> @@ -32,13 +32,11 @@ gmac0: ethernet@fe2a0000 {
>  		clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
>  			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
>  			 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
> -			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
> -			 <&cru PCLK_XPCS>;
> +			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
>  		clock-names = "stmmaceth", "mac_clk_rx",
>  			      "mac_clk_tx", "clk_mac_refout",
>  			      "aclk_mac", "pclk_mac",
> -			      "clk_mac_speed", "ptp_ref",
> -			      "pclk_xpcs";
> +			      "clk_mac_speed", "ptp_ref";
>  		resets = <&cru SRST_A_GMAC0>;
>  		reset-names = "stmmaceth";
>  		rockchip,grf = <&grf>;

This has been on my TODO list for a while, but I never found the time to
submit this cleanup. As far as I am concerned:

Acked-by: Michael Riesch <michael.riesch@wolfvision.net>

Thanks and best regards,
Michael

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Johan Jonker]

Hi Frank,

Despite that the DT is hosted in the kernel tree
DT and mainline kernel driver support are 2 separate things.
PCLK_XPCS might be in use elsewhere.

Given the link below pclk_xpcs is only needed for rk3568.
Maybe gmac1 should have a PCLK_XPCS too, because one can select between
them.

ethernet: stmicro: stmmac: Add SGMII/QSGMII support for RK3568
https://github.com/rockchip-linux/kernel/commit/1fc7cbfe9e227c700c692f1de3137914b3ea6ca6

The original dtsi did have PCLK_XPCS in both nodes.
https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L2121
https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L1492

Maybe fix the document or leave it as it is for now as long the driver
isn't updated and someone has tested it.
That's up to the DT maintainer.

Johan

===

XPCS is also part of PD_PIPE.
See Rockchip RK3568 TRM Part1 V1.0-20210111.pdf page 475.
Please advise if the power-domain@RK3568_PD_PIPE does need a PCLK_XPCS
fix or is PCLK_PIPE enough in combination with a PHY driver?

PD_PIPE:

BIU_PIPE
USB3OTG
PCIE20
PCIE30
SATA
XPCS


	power-domain@RK3568_PD_PIPE {
		reg = <RK3568_PD_PIPE>;
		clocks = <&cru PCLK_PIPE>;
		pm_qos = <&qos_pcie2x1>,
			 <&qos_pcie3x1>,
			 <&qos_pcie3x2>,
			 <&qos_sata0>,
			 <&qos_sata1>,
			 <&qos_sata2>,
			 <&qos_usb3_0>,
			 <&qos_usb3_1>;
		#power-domain-cells = <0>;
	};



On 1/16/22 1:49 PM, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w@public-files.de>
> 
> pclk_xpcs is not supported and breaks dtbs_check, so remove it
> 
> following warnings occour, and many more
> 
> rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clocks:
>     [[15, 386], [15, 389], [15, 389], [15, 184], [15, 180], [15, 181],
>     [15, 389], [15, 185], [15, 172]] is too long
> 	From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
> rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clock-names:
>     ['stmmaceth', 'mac_clk_rx', 'mac_clk_tx', 'clk_mac_refout', 'aclk_mac',
>     'pclk_mac', 'clk_mac_speed', 'ptp_ref', 'pclk_xpcs'] is too long
> 	From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
> 
> after removing the clock the other warnings are also gone.
> 
> Co-developed-by: Peter Geis <pgwipeout@gmail.com>
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> ---
>  arch/arm64/boot/dts/rockchip/rk3568.dtsi | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> index 2fd313a295f8..d91df1cde736 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> @@ -32,13 +32,11 @@ gmac0: ethernet@fe2a0000 {
>  		clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
>  			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
>  			 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
> -			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
> -			 <&cru PCLK_XPCS>;
> +			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
>  		clock-names = "stmmaceth", "mac_clk_rx",
>  			      "mac_clk_tx", "clk_mac_refout",
>  			      "aclk_mac", "pclk_mac",
> -			      "clk_mac_speed", "ptp_ref",
> -			      "pclk_xpcs";
> +			      "clk_mac_speed", "ptp_ref";
>  		resets = <&cru SRST_A_GMAC0>;
>  		reset-names = "stmmaceth";
>  		rockchip,grf = <&grf>;
> 

Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Johan Jonker]

Hi Frank,

Despite that the DT is hosted in the kernel tree
DT and mainline kernel driver support are 2 separate things.
PCLK_XPCS might be in use elsewhere.

Given the link below pclk_xpcs is only needed for rk3568.
Maybe gmac1 should have a PCLK_XPCS too, because one can select between
them.

ethernet: stmicro: stmmac: Add SGMII/QSGMII support for RK3568
https://github.com/rockchip-linux/kernel/commit/1fc7cbfe9e227c700c692f1de3137914b3ea6ca6

The original dtsi did have PCLK_XPCS in both nodes.
https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L2121
https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L1492

Maybe fix the document or leave it as it is for now as long the driver
isn't updated and someone has tested it.
That's up to the DT maintainer.

Johan

===

XPCS is also part of PD_PIPE.
See Rockchip RK3568 TRM Part1 V1.0-20210111.pdf page 475.
Please advise if the power-domain@RK3568_PD_PIPE does need a PCLK_XPCS
fix or is PCLK_PIPE enough in combination with a PHY driver?

PD_PIPE:

BIU_PIPE
USB3OTG
PCIE20
PCIE30
SATA
XPCS


	power-domain@RK3568_PD_PIPE {
		reg = <RK3568_PD_PIPE>;
		clocks = <&cru PCLK_PIPE>;
		pm_qos = <&qos_pcie2x1>,
			 <&qos_pcie3x1>,
			 <&qos_pcie3x2>,
			 <&qos_sata0>,
			 <&qos_sata1>,
			 <&qos_sata2>,
			 <&qos_usb3_0>,
			 <&qos_usb3_1>;
		#power-domain-cells = <0>;
	};



On 1/16/22 1:49 PM, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w@public-files.de>
> 
> pclk_xpcs is not supported and breaks dtbs_check, so remove it
> 
> following warnings occour, and many more
> 
> rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clocks:
>     [[15, 386], [15, 389], [15, 389], [15, 184], [15, 180], [15, 181],
>     [15, 389], [15, 185], [15, 172]] is too long
> 	From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
> rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clock-names:
>     ['stmmaceth', 'mac_clk_rx', 'mac_clk_tx', 'clk_mac_refout', 'aclk_mac',
>     'pclk_mac', 'clk_mac_speed', 'ptp_ref', 'pclk_xpcs'] is too long
> 	From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
> 
> after removing the clock the other warnings are also gone.
> 
> Co-developed-by: Peter Geis <pgwipeout@gmail.com>
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> ---
>  arch/arm64/boot/dts/rockchip/rk3568.dtsi | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> index 2fd313a295f8..d91df1cde736 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> @@ -32,13 +32,11 @@ gmac0: ethernet@fe2a0000 {
>  		clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
>  			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
>  			 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
> -			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
> -			 <&cru PCLK_XPCS>;
> +			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
>  		clock-names = "stmmaceth", "mac_clk_rx",
>  			      "mac_clk_tx", "clk_mac_refout",
>  			      "aclk_mac", "pclk_mac",
> -			      "clk_mac_speed", "ptp_ref",
> -			      "pclk_xpcs";
> +			      "clk_mac_speed", "ptp_ref";
>  		resets = <&cru SRST_A_GMAC0>;
>  		reset-names = "stmmaceth";
>  		rockchip,grf = <&grf>;
> 

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Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Johan Jonker]

Hi Frank,

Despite that the DT is hosted in the kernel tree
DT and mainline kernel driver support are 2 separate things.
PCLK_XPCS might be in use elsewhere.

Given the link below pclk_xpcs is only needed for rk3568.
Maybe gmac1 should have a PCLK_XPCS too, because one can select between
them.

ethernet: stmicro: stmmac: Add SGMII/QSGMII support for RK3568
https://github.com/rockchip-linux/kernel/commit/1fc7cbfe9e227c700c692f1de3137914b3ea6ca6

The original dtsi did have PCLK_XPCS in both nodes.
https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L2121
https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L1492

Maybe fix the document or leave it as it is for now as long the driver
isn't updated and someone has tested it.
That's up to the DT maintainer.

Johan

===

XPCS is also part of PD_PIPE.
See Rockchip RK3568 TRM Part1 V1.0-20210111.pdf page 475.
Please advise if the power-domain@RK3568_PD_PIPE does need a PCLK_XPCS
fix or is PCLK_PIPE enough in combination with a PHY driver?

PD_PIPE:

BIU_PIPE
USB3OTG
PCIE20
PCIE30
SATA
XPCS


	power-domain@RK3568_PD_PIPE {
		reg = <RK3568_PD_PIPE>;
		clocks = <&cru PCLK_PIPE>;
		pm_qos = <&qos_pcie2x1>,
			 <&qos_pcie3x1>,
			 <&qos_pcie3x2>,
			 <&qos_sata0>,
			 <&qos_sata1>,
			 <&qos_sata2>,
			 <&qos_usb3_0>,
			 <&qos_usb3_1>;
		#power-domain-cells = <0>;
	};



On 1/16/22 1:49 PM, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w@public-files.de>
> 
> pclk_xpcs is not supported and breaks dtbs_check, so remove it
> 
> following warnings occour, and many more
> 
> rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clocks:
>     [[15, 386], [15, 389], [15, 389], [15, 184], [15, 180], [15, 181],
>     [15, 389], [15, 185], [15, 172]] is too long
> 	From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
> rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clock-names:
>     ['stmmaceth', 'mac_clk_rx', 'mac_clk_tx', 'clk_mac_refout', 'aclk_mac',
>     'pclk_mac', 'clk_mac_speed', 'ptp_ref', 'pclk_xpcs'] is too long
> 	From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
> 
> after removing the clock the other warnings are also gone.
> 
> Co-developed-by: Peter Geis <pgwipeout@gmail.com>
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> ---
>  arch/arm64/boot/dts/rockchip/rk3568.dtsi | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> index 2fd313a295f8..d91df1cde736 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> @@ -32,13 +32,11 @@ gmac0: ethernet@fe2a0000 {
>  		clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
>  			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
>  			 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
> -			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
> -			 <&cru PCLK_XPCS>;
> +			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
>  		clock-names = "stmmaceth", "mac_clk_rx",
>  			      "mac_clk_tx", "clk_mac_refout",
>  			      "aclk_mac", "pclk_mac",
> -			      "clk_mac_speed", "ptp_ref",
> -			      "pclk_xpcs";
> +			      "clk_mac_speed", "ptp_ref";
>  		resets = <&cru SRST_A_GMAC0>;
>  		reset-names = "stmmaceth";
>  		rockchip,grf = <&grf>;
> 

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Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Heiko Stübner]

Am Montag, 17. Januar 2022, 11:47:16 CET schrieb Johan Jonker:
> Hi Frank,
> 
> Despite that the DT is hosted in the kernel tree
> DT and mainline kernel driver support are 2 separate things.
> PCLK_XPCS might be in use elsewhere.

I've just looked through the rk3568 TRM and I guess the
pclk_xpcs belongs to the QSGMII_PCS block living at
the 0xfda00000 address in the memory map.

From glancing at the documentation that PCS thingy
can sit in between the dmac and the phy to "optimize" things
like power consumption.

Looking at the PIPE_GRF_XPCS_CON0, we can see that
bit1 decides which mac is to be selected to use the sgmii
interface to that PCS block.

As the QSGMII_PCS block should have its own driver
due to also its own config registers (see above), the pclk_xpcs
also will belong to it and should be modeled there.

Also I guess boards currently in production will use
regular gmii network interfaces?



> Given the link below pclk_xpcs is only needed for rk3568.
> Maybe gmac1 should have a PCLK_XPCS too, because one can select between
> them.
> 
> ethernet: stmicro: stmmac: Add SGMII/QSGMII support for RK3568
> https://github.com/rockchip-linux/kernel/commit/1fc7cbfe9e227c700c692f1de3137914b3ea6ca6
> 
> The original dtsi did have PCLK_XPCS in both nodes.
> https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L2121
> https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L1492
> 
> Maybe fix the document or leave it as it is for now as long the driver
> isn't updated and someone has tested it.
> That's up to the DT maintainer.
> 
> Johan
> 
> ===
> 
> XPCS is also part of PD_PIPE.
> See Rockchip RK3568 TRM Part1 V1.0-20210111.pdf page 475.
> Please advise if the power-domain@RK3568_PD_PIPE does need a PCLK_XPCS
> fix or is PCLK_PIPE enough in combination with a PHY driver?
> 
> PD_PIPE:
> 
> BIU_PIPE
> USB3OTG
> PCIE20
> PCIE30
> SATA
> XPCS
> 
> 
> 	power-domain@RK3568_PD_PIPE {
> 		reg = <RK3568_PD_PIPE>;
> 		clocks = <&cru PCLK_PIPE>;
> 		pm_qos = <&qos_pcie2x1>,
> 			 <&qos_pcie3x1>,
> 			 <&qos_pcie3x2>,
> 			 <&qos_sata0>,
> 			 <&qos_sata1>,
> 			 <&qos_sata2>,
> 			 <&qos_usb3_0>,
> 			 <&qos_usb3_1>;
> 		#power-domain-cells = <0>;
> 	};
> 
> 
> 
> On 1/16/22 1:49 PM, Frank Wunderlich wrote:
> > From: Frank Wunderlich <frank-w@public-files.de>
> > 
> > pclk_xpcs is not supported and breaks dtbs_check, so remove it
> > 
> > following warnings occour, and many more
> > 
> > rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clocks:
> >     [[15, 386], [15, 389], [15, 389], [15, 184], [15, 180], [15, 181],
> >     [15, 389], [15, 185], [15, 172]] is too long
> > 	From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
> > rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clock-names:
> >     ['stmmaceth', 'mac_clk_rx', 'mac_clk_tx', 'clk_mac_refout', 'aclk_mac',
> >     'pclk_mac', 'clk_mac_speed', 'ptp_ref', 'pclk_xpcs'] is too long
> > 	From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
> > 
> > after removing the clock the other warnings are also gone.
> > 
> > Co-developed-by: Peter Geis <pgwipeout@gmail.com>
> > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> > ---
> >  arch/arm64/boot/dts/rockchip/rk3568.dtsi | 6 ++----
> >  1 file changed, 2 insertions(+), 4 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> > index 2fd313a295f8..d91df1cde736 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> > @@ -32,13 +32,11 @@ gmac0: ethernet@fe2a0000 {
> >  		clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
> >  			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
> >  			 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
> > -			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
> > -			 <&cru PCLK_XPCS>;
> > +			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
> >  		clock-names = "stmmaceth", "mac_clk_rx",
> >  			      "mac_clk_tx", "clk_mac_refout",
> >  			      "aclk_mac", "pclk_mac",
> > -			      "clk_mac_speed", "ptp_ref",
> > -			      "pclk_xpcs";
> > +			      "clk_mac_speed", "ptp_ref";
> >  		resets = <&cru SRST_A_GMAC0>;
> >  		reset-names = "stmmaceth";
> >  		rockchip,grf = <&grf>;
> > 
> 

Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Heiko Stübner]

Am Montag, 17. Januar 2022, 11:47:16 CET schrieb Johan Jonker:
> Hi Frank,
> 
> Despite that the DT is hosted in the kernel tree
> DT and mainline kernel driver support are 2 separate things.
> PCLK_XPCS might be in use elsewhere.

I've just looked through the rk3568 TRM and I guess the
pclk_xpcs belongs to the QSGMII_PCS block living at
the 0xfda00000 address in the memory map.

From glancing at the documentation that PCS thingy
can sit in between the dmac and the phy to "optimize" things
like power consumption.

Looking at the PIPE_GRF_XPCS_CON0, we can see that
bit1 decides which mac is to be selected to use the sgmii
interface to that PCS block.

As the QSGMII_PCS block should have its own driver
due to also its own config registers (see above), the pclk_xpcs
also will belong to it and should be modeled there.

Also I guess boards currently in production will use
regular gmii network interfaces?



> Given the link below pclk_xpcs is only needed for rk3568.
> Maybe gmac1 should have a PCLK_XPCS too, because one can select between
> them.
> 
> ethernet: stmicro: stmmac: Add SGMII/QSGMII support for RK3568
> https://github.com/rockchip-linux/kernel/commit/1fc7cbfe9e227c700c692f1de3137914b3ea6ca6
> 
> The original dtsi did have PCLK_XPCS in both nodes.
> https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L2121
> https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L1492
> 
> Maybe fix the document or leave it as it is for now as long the driver
> isn't updated and someone has tested it.
> That's up to the DT maintainer.
> 
> Johan
> 
> ===
> 
> XPCS is also part of PD_PIPE.
> See Rockchip RK3568 TRM Part1 V1.0-20210111.pdf page 475.
> Please advise if the power-domain@RK3568_PD_PIPE does need a PCLK_XPCS
> fix or is PCLK_PIPE enough in combination with a PHY driver?
> 
> PD_PIPE:
> 
> BIU_PIPE
> USB3OTG
> PCIE20
> PCIE30
> SATA
> XPCS
> 
> 
> 	power-domain@RK3568_PD_PIPE {
> 		reg = <RK3568_PD_PIPE>;
> 		clocks = <&cru PCLK_PIPE>;
> 		pm_qos = <&qos_pcie2x1>,
> 			 <&qos_pcie3x1>,
> 			 <&qos_pcie3x2>,
> 			 <&qos_sata0>,
> 			 <&qos_sata1>,
> 			 <&qos_sata2>,
> 			 <&qos_usb3_0>,
> 			 <&qos_usb3_1>;
> 		#power-domain-cells = <0>;
> 	};
> 
> 
> 
> On 1/16/22 1:49 PM, Frank Wunderlich wrote:
> > From: Frank Wunderlich <frank-w@public-files.de>
> > 
> > pclk_xpcs is not supported and breaks dtbs_check, so remove it
> > 
> > following warnings occour, and many more
> > 
> > rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clocks:
> >     [[15, 386], [15, 389], [15, 389], [15, 184], [15, 180], [15, 181],
> >     [15, 389], [15, 185], [15, 172]] is too long
> > 	From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
> > rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clock-names:
> >     ['stmmaceth', 'mac_clk_rx', 'mac_clk_tx', 'clk_mac_refout', 'aclk_mac',
> >     'pclk_mac', 'clk_mac_speed', 'ptp_ref', 'pclk_xpcs'] is too long
> > 	From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
> > 
> > after removing the clock the other warnings are also gone.
> > 
> > Co-developed-by: Peter Geis <pgwipeout@gmail.com>
> > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> > ---
> >  arch/arm64/boot/dts/rockchip/rk3568.dtsi | 6 ++----
> >  1 file changed, 2 insertions(+), 4 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> > index 2fd313a295f8..d91df1cde736 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> > @@ -32,13 +32,11 @@ gmac0: ethernet@fe2a0000 {
> >  		clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
> >  			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
> >  			 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
> > -			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
> > -			 <&cru PCLK_XPCS>;
> > +			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
> >  		clock-names = "stmmaceth", "mac_clk_rx",
> >  			      "mac_clk_tx", "clk_mac_refout",
> >  			      "aclk_mac", "pclk_mac",
> > -			      "clk_mac_speed", "ptp_ref",
> > -			      "pclk_xpcs";
> > +			      "clk_mac_speed", "ptp_ref";
> >  		resets = <&cru SRST_A_GMAC0>;
> >  		reset-names = "stmmaceth";
> >  		rockchip,grf = <&grf>;
> > 
> 





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Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Heiko Stübner]

Am Montag, 17. Januar 2022, 11:47:16 CET schrieb Johan Jonker:
> Hi Frank,
> 
> Despite that the DT is hosted in the kernel tree
> DT and mainline kernel driver support are 2 separate things.
> PCLK_XPCS might be in use elsewhere.

I've just looked through the rk3568 TRM and I guess the
pclk_xpcs belongs to the QSGMII_PCS block living at
the 0xfda00000 address in the memory map.

From glancing at the documentation that PCS thingy
can sit in between the dmac and the phy to "optimize" things
like power consumption.

Looking at the PIPE_GRF_XPCS_CON0, we can see that
bit1 decides which mac is to be selected to use the sgmii
interface to that PCS block.

As the QSGMII_PCS block should have its own driver
due to also its own config registers (see above), the pclk_xpcs
also will belong to it and should be modeled there.

Also I guess boards currently in production will use
regular gmii network interfaces?



> Given the link below pclk_xpcs is only needed for rk3568.
> Maybe gmac1 should have a PCLK_XPCS too, because one can select between
> them.
> 
> ethernet: stmicro: stmmac: Add SGMII/QSGMII support for RK3568
> https://github.com/rockchip-linux/kernel/commit/1fc7cbfe9e227c700c692f1de3137914b3ea6ca6
> 
> The original dtsi did have PCLK_XPCS in both nodes.
> https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L2121
> https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L1492
> 
> Maybe fix the document or leave it as it is for now as long the driver
> isn't updated and someone has tested it.
> That's up to the DT maintainer.
> 
> Johan
> 
> ===
> 
> XPCS is also part of PD_PIPE.
> See Rockchip RK3568 TRM Part1 V1.0-20210111.pdf page 475.
> Please advise if the power-domain@RK3568_PD_PIPE does need a PCLK_XPCS
> fix or is PCLK_PIPE enough in combination with a PHY driver?
> 
> PD_PIPE:
> 
> BIU_PIPE
> USB3OTG
> PCIE20
> PCIE30
> SATA
> XPCS
> 
> 
> 	power-domain@RK3568_PD_PIPE {
> 		reg = <RK3568_PD_PIPE>;
> 		clocks = <&cru PCLK_PIPE>;
> 		pm_qos = <&qos_pcie2x1>,
> 			 <&qos_pcie3x1>,
> 			 <&qos_pcie3x2>,
> 			 <&qos_sata0>,
> 			 <&qos_sata1>,
> 			 <&qos_sata2>,
> 			 <&qos_usb3_0>,
> 			 <&qos_usb3_1>;
> 		#power-domain-cells = <0>;
> 	};
> 
> 
> 
> On 1/16/22 1:49 PM, Frank Wunderlich wrote:
> > From: Frank Wunderlich <frank-w@public-files.de>
> > 
> > pclk_xpcs is not supported and breaks dtbs_check, so remove it
> > 
> > following warnings occour, and many more
> > 
> > rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clocks:
> >     [[15, 386], [15, 389], [15, 389], [15, 184], [15, 180], [15, 181],
> >     [15, 389], [15, 185], [15, 172]] is too long
> > 	From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
> > rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clock-names:
> >     ['stmmaceth', 'mac_clk_rx', 'mac_clk_tx', 'clk_mac_refout', 'aclk_mac',
> >     'pclk_mac', 'clk_mac_speed', 'ptp_ref', 'pclk_xpcs'] is too long
> > 	From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
> > 
> > after removing the clock the other warnings are also gone.
> > 
> > Co-developed-by: Peter Geis <pgwipeout@gmail.com>
> > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> > ---
> >  arch/arm64/boot/dts/rockchip/rk3568.dtsi | 6 ++----
> >  1 file changed, 2 insertions(+), 4 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> > index 2fd313a295f8..d91df1cde736 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> > @@ -32,13 +32,11 @@ gmac0: ethernet@fe2a0000 {
> >  		clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
> >  			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
> >  			 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
> > -			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
> > -			 <&cru PCLK_XPCS>;
> > +			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
> >  		clock-names = "stmmaceth", "mac_clk_rx",
> >  			      "mac_clk_tx", "clk_mac_refout",
> >  			      "aclk_mac", "pclk_mac",
> > -			      "clk_mac_speed", "ptp_ref",
> > -			      "pclk_xpcs";
> > +			      "clk_mac_speed", "ptp_ref";
> >  		resets = <&cru SRST_A_GMAC0>;
> >  		reset-names = "stmmaceth";
> >  		rockchip,grf = <&grf>;
> > 
> 





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Aw: Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Frank Wunderlich]

Hi

> Gesendet: Montag, 17. Januar 2022 um 11:47 Uhr
> Von: "Johan Jonker" <jbx6244@gmail.com>
> Hi Frank,
>
> Despite that the DT is hosted in the kernel tree
> DT and mainline kernel driver support are 2 separate things.
> PCLK_XPCS might be in use elsewhere.
>
> Given the link below pclk_xpcs is only needed for rk3568.
> Maybe gmac1 should have a PCLK_XPCS too, because one can select between
> them.
>
> ethernet: stmicro: stmmac: Add SGMII/QSGMII support for RK3568
> https://github.com/rockchip-linux/kernel/commit/1fc7cbfe9e227c700c692f1de3137914b3ea6ca6
>
> The original dtsi did have PCLK_XPCS in both nodes.
> https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L2121
> https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L1492
>
> Maybe fix the document or leave it as it is for now as long the driver
> isn't updated and someone has tested it.
> That's up to the DT maintainer.
>
> Johan

as far as i understand, the PCLK_XPCS is part of the naneng combphy, which is not yet available in mainline.
Naneng driver needs some changes and imho this should be part of it (including change documentation). That also makes it clear why this clock is added.
But leaving an unused property with sideeffects is imho no good choice.

So this was the easiest way to fix the dtbs_check. Else i got no usable result for it. Maybe adding it to Documentation is also easy, but have not yet looked into it as it currently unused from my POV.

But i leave it as decision for Maintainer to drop this patch as it is not needed for my Board DTS.

> ===
>
> XPCS is also part of PD_PIPE.
> See Rockchip RK3568 TRM Part1 V1.0-20210111.pdf page 475.
> Please advise if the power-domain@RK3568_PD_PIPE does need a PCLK_XPCS
> fix or is PCLK_PIPE enough in combination with a PHY driver?
>
> PD_PIPE:
>
> BIU_PIPE
> USB3OTG
> PCIE20
> PCIE30
> SATA
> XPCS
>
>
> 	power-domain@RK3568_PD_PIPE {
> 		reg = <RK3568_PD_PIPE>;
> 		clocks = <&cru PCLK_PIPE>;
> 		pm_qos = <&qos_pcie2x1>,
> 			 <&qos_pcie3x1>,
> 			 <&qos_pcie3x2>,
> 			 <&qos_sata0>,
> 			 <&qos_sata1>,
> 			 <&qos_sata2>,
> 			 <&qos_usb3_0>,
> 			 <&qos_usb3_1>;
> 		#power-domain-cells = <0>;
> 	};

PD_PIPE is imho also part of Naneng. But more for usage as USB3/SATA/... phy. This is not part of Mainline too.

But thanks for pointing.

regards Frank

Aw: Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Frank Wunderlich]

Hi

> Gesendet: Montag, 17. Januar 2022 um 11:47 Uhr
> Von: "Johan Jonker" <jbx6244@gmail.com>
> Hi Frank,
>
> Despite that the DT is hosted in the kernel tree
> DT and mainline kernel driver support are 2 separate things.
> PCLK_XPCS might be in use elsewhere.
>
> Given the link below pclk_xpcs is only needed for rk3568.
> Maybe gmac1 should have a PCLK_XPCS too, because one can select between
> them.
>
> ethernet: stmicro: stmmac: Add SGMII/QSGMII support for RK3568
> https://github.com/rockchip-linux/kernel/commit/1fc7cbfe9e227c700c692f1de3137914b3ea6ca6
>
> The original dtsi did have PCLK_XPCS in both nodes.
> https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L2121
> https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L1492
>
> Maybe fix the document or leave it as it is for now as long the driver
> isn't updated and someone has tested it.
> That's up to the DT maintainer.
>
> Johan

as far as i understand, the PCLK_XPCS is part of the naneng combphy, which is not yet available in mainline.
Naneng driver needs some changes and imho this should be part of it (including change documentation). That also makes it clear why this clock is added.
But leaving an unused property with sideeffects is imho no good choice.

So this was the easiest way to fix the dtbs_check. Else i got no usable result for it. Maybe adding it to Documentation is also easy, but have not yet looked into it as it currently unused from my POV.

But i leave it as decision for Maintainer to drop this patch as it is not needed for my Board DTS.

> ===
>
> XPCS is also part of PD_PIPE.
> See Rockchip RK3568 TRM Part1 V1.0-20210111.pdf page 475.
> Please advise if the power-domain@RK3568_PD_PIPE does need a PCLK_XPCS
> fix or is PCLK_PIPE enough in combination with a PHY driver?
>
> PD_PIPE:
>
> BIU_PIPE
> USB3OTG
> PCIE20
> PCIE30
> SATA
> XPCS
>
>
> 	power-domain@RK3568_PD_PIPE {
> 		reg = <RK3568_PD_PIPE>;
> 		clocks = <&cru PCLK_PIPE>;
> 		pm_qos = <&qos_pcie2x1>,
> 			 <&qos_pcie3x1>,
> 			 <&qos_pcie3x2>,
> 			 <&qos_sata0>,
> 			 <&qos_sata1>,
> 			 <&qos_sata2>,
> 			 <&qos_usb3_0>,
> 			 <&qos_usb3_1>;
> 		#power-domain-cells = <0>;
> 	};

PD_PIPE is imho also part of Naneng. But more for usage as USB3/SATA/... phy. This is not part of Mainline too.

But thanks for pointing.

regards Frank

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Aw: Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Frank Wunderlich]

Hi

> Gesendet: Montag, 17. Januar 2022 um 11:47 Uhr
> Von: "Johan Jonker" <jbx6244@gmail.com>
> Hi Frank,
>
> Despite that the DT is hosted in the kernel tree
> DT and mainline kernel driver support are 2 separate things.
> PCLK_XPCS might be in use elsewhere.
>
> Given the link below pclk_xpcs is only needed for rk3568.
> Maybe gmac1 should have a PCLK_XPCS too, because one can select between
> them.
>
> ethernet: stmicro: stmmac: Add SGMII/QSGMII support for RK3568
> https://github.com/rockchip-linux/kernel/commit/1fc7cbfe9e227c700c692f1de3137914b3ea6ca6
>
> The original dtsi did have PCLK_XPCS in both nodes.
> https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L2121
> https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L1492
>
> Maybe fix the document or leave it as it is for now as long the driver
> isn't updated and someone has tested it.
> That's up to the DT maintainer.
>
> Johan

as far as i understand, the PCLK_XPCS is part of the naneng combphy, which is not yet available in mainline.
Naneng driver needs some changes and imho this should be part of it (including change documentation). That also makes it clear why this clock is added.
But leaving an unused property with sideeffects is imho no good choice.

So this was the easiest way to fix the dtbs_check. Else i got no usable result for it. Maybe adding it to Documentation is also easy, but have not yet looked into it as it currently unused from my POV.

But i leave it as decision for Maintainer to drop this patch as it is not needed for my Board DTS.

> ===
>
> XPCS is also part of PD_PIPE.
> See Rockchip RK3568 TRM Part1 V1.0-20210111.pdf page 475.
> Please advise if the power-domain@RK3568_PD_PIPE does need a PCLK_XPCS
> fix or is PCLK_PIPE enough in combination with a PHY driver?
>
> PD_PIPE:
>
> BIU_PIPE
> USB3OTG
> PCIE20
> PCIE30
> SATA
> XPCS
>
>
> 	power-domain@RK3568_PD_PIPE {
> 		reg = <RK3568_PD_PIPE>;
> 		clocks = <&cru PCLK_PIPE>;
> 		pm_qos = <&qos_pcie2x1>,
> 			 <&qos_pcie3x1>,
> 			 <&qos_pcie3x2>,
> 			 <&qos_sata0>,
> 			 <&qos_sata1>,
> 			 <&qos_sata2>,
> 			 <&qos_usb3_0>,
> 			 <&qos_usb3_1>;
> 		#power-domain-cells = <0>;
> 	};

PD_PIPE is imho also part of Naneng. But more for usage as USB3/SATA/... phy. This is not part of Mainline too.

But thanks for pointing.

regards Frank

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Re: Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Peter Geis]

On Mon, Jan 17, 2022 at 6:59 AM Frank Wunderlich
<frank-w@public-files.de> wrote:
>
> Hi
>
> > Gesendet: Montag, 17. Januar 2022 um 11:47 Uhr
> > Von: "Johan Jonker" <jbx6244@gmail.com>
> > Hi Frank,
> >
> > Despite that the DT is hosted in the kernel tree
> > DT and mainline kernel driver support are 2 separate things.
> > PCLK_XPCS might be in use elsewhere.
> >
> > Given the link below pclk_xpcs is only needed for rk3568.
> > Maybe gmac1 should have a PCLK_XPCS too, because one can select between
> > them.
> >
> > ethernet: stmicro: stmmac: Add SGMII/QSGMII support for RK3568
> > https://github.com/rockchip-linux/kernel/commit/1fc7cbfe9e227c700c692f1de3137914b3ea6ca6
> >
> > The original dtsi did have PCLK_XPCS in both nodes.
> > https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L2121
> > https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L1492
> >
> > Maybe fix the document or leave it as it is for now as long the driver
> > isn't updated and someone has tested it.
> > That's up to the DT maintainer.
> >
> > Johan
>
> as far as i understand, the PCLK_XPCS is part of the naneng combphy, which is not yet available in mainline.
> Naneng driver needs some changes and imho this should be part of it (including change documentation). That also makes it clear why this clock is added.
> But leaving an unused property with sideeffects is imho no good choice.
>
> So this was the easiest way to fix the dtbs_check. Else i got no usable result for it. Maybe adding it to Documentation is also easy, but have not yet looked into it as it currently unused from my POV.
>
> But i leave it as decision for Maintainer to drop this patch as it is not needed for my Board DTS.

As both the current submission of the combophy driver and the gmac
driver do not support xpcs, I elected to remove the clock vice adding
documentation for something which is not currently supported.
This is especially true as it only leaked through for the gmac0 port,
the gmac1 port is modeled to the current support level.

Once xpcs support is introduced, the clock can be added to the
documentation and both controllers as part of the same patch series.

Do you concur, Heiko?

>
> > ===
> >
> > XPCS is also part of PD_PIPE.
> > See Rockchip RK3568 TRM Part1 V1.0-20210111.pdf page 475.
> > Please advise if the power-domain@RK3568_PD_PIPE does need a PCLK_XPCS
> > fix or is PCLK_PIPE enough in combination with a PHY driver?
> >
> > PD_PIPE:
> >
> > BIU_PIPE
> > USB3OTG
> > PCIE20
> > PCIE30
> > SATA
> > XPCS
> >
> >
> >       power-domain@RK3568_PD_PIPE {
> >               reg = <RK3568_PD_PIPE>;
> >               clocks = <&cru PCLK_PIPE>;
> >               pm_qos = <&qos_pcie2x1>,
> >                        <&qos_pcie3x1>,
> >                        <&qos_pcie3x2>,
> >                        <&qos_sata0>,
> >                        <&qos_sata1>,
> >                        <&qos_sata2>,
> >                        <&qos_usb3_0>,
> >                        <&qos_usb3_1>;
> >               #power-domain-cells = <0>;
> >       };
>
> PD_PIPE is imho also part of Naneng. But more for usage as USB3/SATA/... phy. This is not part of Mainline too.
>
> But thanks for pointing.
>
> regards Frank

Re: Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Peter Geis]

On Mon, Jan 17, 2022 at 6:59 AM Frank Wunderlich
<frank-w@public-files.de> wrote:
>
> Hi
>
> > Gesendet: Montag, 17. Januar 2022 um 11:47 Uhr
> > Von: "Johan Jonker" <jbx6244@gmail.com>
> > Hi Frank,
> >
> > Despite that the DT is hosted in the kernel tree
> > DT and mainline kernel driver support are 2 separate things.
> > PCLK_XPCS might be in use elsewhere.
> >
> > Given the link below pclk_xpcs is only needed for rk3568.
> > Maybe gmac1 should have a PCLK_XPCS too, because one can select between
> > them.
> >
> > ethernet: stmicro: stmmac: Add SGMII/QSGMII support for RK3568
> > https://github.com/rockchip-linux/kernel/commit/1fc7cbfe9e227c700c692f1de3137914b3ea6ca6
> >
> > The original dtsi did have PCLK_XPCS in both nodes.
> > https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L2121
> > https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L1492
> >
> > Maybe fix the document or leave it as it is for now as long the driver
> > isn't updated and someone has tested it.
> > That's up to the DT maintainer.
> >
> > Johan
>
> as far as i understand, the PCLK_XPCS is part of the naneng combphy, which is not yet available in mainline.
> Naneng driver needs some changes and imho this should be part of it (including change documentation). That also makes it clear why this clock is added.
> But leaving an unused property with sideeffects is imho no good choice.
>
> So this was the easiest way to fix the dtbs_check. Else i got no usable result for it. Maybe adding it to Documentation is also easy, but have not yet looked into it as it currently unused from my POV.
>
> But i leave it as decision for Maintainer to drop this patch as it is not needed for my Board DTS.

As both the current submission of the combophy driver and the gmac
driver do not support xpcs, I elected to remove the clock vice adding
documentation for something which is not currently supported.
This is especially true as it only leaked through for the gmac0 port,
the gmac1 port is modeled to the current support level.

Once xpcs support is introduced, the clock can be added to the
documentation and both controllers as part of the same patch series.

Do you concur, Heiko?

>
> > ===
> >
> > XPCS is also part of PD_PIPE.
> > See Rockchip RK3568 TRM Part1 V1.0-20210111.pdf page 475.
> > Please advise if the power-domain@RK3568_PD_PIPE does need a PCLK_XPCS
> > fix or is PCLK_PIPE enough in combination with a PHY driver?
> >
> > PD_PIPE:
> >
> > BIU_PIPE
> > USB3OTG
> > PCIE20
> > PCIE30
> > SATA
> > XPCS
> >
> >
> >       power-domain@RK3568_PD_PIPE {
> >               reg = <RK3568_PD_PIPE>;
> >               clocks = <&cru PCLK_PIPE>;
> >               pm_qos = <&qos_pcie2x1>,
> >                        <&qos_pcie3x1>,
> >                        <&qos_pcie3x2>,
> >                        <&qos_sata0>,
> >                        <&qos_sata1>,
> >                        <&qos_sata2>,
> >                        <&qos_usb3_0>,
> >                        <&qos_usb3_1>;
> >               #power-domain-cells = <0>;
> >       };
>
> PD_PIPE is imho also part of Naneng. But more for usage as USB3/SATA/... phy. This is not part of Mainline too.
>
> But thanks for pointing.
>
> regards Frank

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Re: Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Peter Geis]

On Mon, Jan 17, 2022 at 6:59 AM Frank Wunderlich
<frank-w@public-files.de> wrote:
>
> Hi
>
> > Gesendet: Montag, 17. Januar 2022 um 11:47 Uhr
> > Von: "Johan Jonker" <jbx6244@gmail.com>
> > Hi Frank,
> >
> > Despite that the DT is hosted in the kernel tree
> > DT and mainline kernel driver support are 2 separate things.
> > PCLK_XPCS might be in use elsewhere.
> >
> > Given the link below pclk_xpcs is only needed for rk3568.
> > Maybe gmac1 should have a PCLK_XPCS too, because one can select between
> > them.
> >
> > ethernet: stmicro: stmmac: Add SGMII/QSGMII support for RK3568
> > https://github.com/rockchip-linux/kernel/commit/1fc7cbfe9e227c700c692f1de3137914b3ea6ca6
> >
> > The original dtsi did have PCLK_XPCS in both nodes.
> > https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L2121
> > https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L1492
> >
> > Maybe fix the document or leave it as it is for now as long the driver
> > isn't updated and someone has tested it.
> > That's up to the DT maintainer.
> >
> > Johan
>
> as far as i understand, the PCLK_XPCS is part of the naneng combphy, which is not yet available in mainline.
> Naneng driver needs some changes and imho this should be part of it (including change documentation). That also makes it clear why this clock is added.
> But leaving an unused property with sideeffects is imho no good choice.
>
> So this was the easiest way to fix the dtbs_check. Else i got no usable result for it. Maybe adding it to Documentation is also easy, but have not yet looked into it as it currently unused from my POV.
>
> But i leave it as decision for Maintainer to drop this patch as it is not needed for my Board DTS.

As both the current submission of the combophy driver and the gmac
driver do not support xpcs, I elected to remove the clock vice adding
documentation for something which is not currently supported.
This is especially true as it only leaked through for the gmac0 port,
the gmac1 port is modeled to the current support level.

Once xpcs support is introduced, the clock can be added to the
documentation and both controllers as part of the same patch series.

Do you concur, Heiko?

>
> > ===
> >
> > XPCS is also part of PD_PIPE.
> > See Rockchip RK3568 TRM Part1 V1.0-20210111.pdf page 475.
> > Please advise if the power-domain@RK3568_PD_PIPE does need a PCLK_XPCS
> > fix or is PCLK_PIPE enough in combination with a PHY driver?
> >
> > PD_PIPE:
> >
> > BIU_PIPE
> > USB3OTG
> > PCIE20
> > PCIE30
> > SATA
> > XPCS
> >
> >
> >       power-domain@RK3568_PD_PIPE {
> >               reg = <RK3568_PD_PIPE>;
> >               clocks = <&cru PCLK_PIPE>;
> >               pm_qos = <&qos_pcie2x1>,
> >                        <&qos_pcie3x1>,
> >                        <&qos_pcie3x2>,
> >                        <&qos_sata0>,
> >                        <&qos_sata1>,
> >                        <&qos_sata2>,
> >                        <&qos_usb3_0>,
> >                        <&qos_usb3_1>;
> >               #power-domain-cells = <0>;
> >       };
>
> PD_PIPE is imho also part of Naneng. But more for usage as USB3/SATA/... phy. This is not part of Mainline too.
>
> But thanks for pointing.
>
> regards Frank

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Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Heiko Stübner]

Am Montag, 17. Januar 2022, 19:26:27 CET schrieb Peter Geis:
> On Mon, Jan 17, 2022 at 6:59 AM Frank Wunderlich
> <frank-w@public-files.de> wrote:
> >
> > Hi
> >
> > > Gesendet: Montag, 17. Januar 2022 um 11:47 Uhr
> > > Von: "Johan Jonker" <jbx6244@gmail.com>
> > > Hi Frank,
> > >
> > > Despite that the DT is hosted in the kernel tree
> > > DT and mainline kernel driver support are 2 separate things.
> > > PCLK_XPCS might be in use elsewhere.
> > >
> > > Given the link below pclk_xpcs is only needed for rk3568.
> > > Maybe gmac1 should have a PCLK_XPCS too, because one can select between
> > > them.
> > >
> > > ethernet: stmicro: stmmac: Add SGMII/QSGMII support for RK3568
> > > https://github.com/rockchip-linux/kernel/commit/1fc7cbfe9e227c700c692f1de3137914b3ea6ca6
> > >
> > > The original dtsi did have PCLK_XPCS in both nodes.
> > > https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L2121
> > > https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L1492
> > >
> > > Maybe fix the document or leave it as it is for now as long the driver
> > > isn't updated and someone has tested it.
> > > That's up to the DT maintainer.
> > >
> > > Johan
> >
> > as far as i understand, the PCLK_XPCS is part of the naneng combphy, which is not yet available in mainline.
> > Naneng driver needs some changes and imho this should be part of it (including change documentation). That also makes it clear why this clock is added.
> > But leaving an unused property with sideeffects is imho no good choice.
> >
> > So this was the easiest way to fix the dtbs_check. Else i got no usable result for it. Maybe adding it to Documentation is also easy, but have not yet looked into it as it currently unused from my POV.
> >
> > But i leave it as decision for Maintainer to drop this patch as it is not needed for my Board DTS.
> 
> As both the current submission of the combophy driver and the gmac
> driver do not support xpcs, I elected to remove the clock vice adding
> documentation for something which is not currently supported.
> This is especially true as it only leaked through for the gmac0 port,
> the gmac1 port is modeled to the current support level.
> 
> Once xpcs support is introduced, the clock can be added to the
> documentation and both controllers as part of the same patch series.
> 
> Do you concur, Heiko?

Did you see my own reply from some hours ago?
From looking at the documentation I got the impression that the
pclk_xpcs is related to the separate qsgmii_pcs in the memory map.

So yes, I fully agree to dropping this clock from here and then adding
them to whatever ip block really needs it.


Heiko


> > > ===
> > >
> > > XPCS is also part of PD_PIPE.
> > > See Rockchip RK3568 TRM Part1 V1.0-20210111.pdf page 475.
> > > Please advise if the power-domain@RK3568_PD_PIPE does need a PCLK_XPCS
> > > fix or is PCLK_PIPE enough in combination with a PHY driver?
> > >
> > > PD_PIPE:
> > >
> > > BIU_PIPE
> > > USB3OTG
> > > PCIE20
> > > PCIE30
> > > SATA
> > > XPCS
> > >
> > >
> > >       power-domain@RK3568_PD_PIPE {
> > >               reg = <RK3568_PD_PIPE>;
> > >               clocks = <&cru PCLK_PIPE>;
> > >               pm_qos = <&qos_pcie2x1>,
> > >                        <&qos_pcie3x1>,
> > >                        <&qos_pcie3x2>,
> > >                        <&qos_sata0>,
> > >                        <&qos_sata1>,
> > >                        <&qos_sata2>,
> > >                        <&qos_usb3_0>,
> > >                        <&qos_usb3_1>;
> > >               #power-domain-cells = <0>;
> > >       };
> >
> > PD_PIPE is imho also part of Naneng. But more for usage as USB3/SATA/... phy. This is not part of Mainline too.
> >
> > But thanks for pointing.
> >
> > regards Frank
> 

Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Heiko Stübner]

Am Montag, 17. Januar 2022, 19:26:27 CET schrieb Peter Geis:
> On Mon, Jan 17, 2022 at 6:59 AM Frank Wunderlich
> <frank-w@public-files.de> wrote:
> >
> > Hi
> >
> > > Gesendet: Montag, 17. Januar 2022 um 11:47 Uhr
> > > Von: "Johan Jonker" <jbx6244@gmail.com>
> > > Hi Frank,
> > >
> > > Despite that the DT is hosted in the kernel tree
> > > DT and mainline kernel driver support are 2 separate things.
> > > PCLK_XPCS might be in use elsewhere.
> > >
> > > Given the link below pclk_xpcs is only needed for rk3568.
> > > Maybe gmac1 should have a PCLK_XPCS too, because one can select between
> > > them.
> > >
> > > ethernet: stmicro: stmmac: Add SGMII/QSGMII support for RK3568
> > > https://github.com/rockchip-linux/kernel/commit/1fc7cbfe9e227c700c692f1de3137914b3ea6ca6
> > >
> > > The original dtsi did have PCLK_XPCS in both nodes.
> > > https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L2121
> > > https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L1492
> > >
> > > Maybe fix the document or leave it as it is for now as long the driver
> > > isn't updated and someone has tested it.
> > > That's up to the DT maintainer.
> > >
> > > Johan
> >
> > as far as i understand, the PCLK_XPCS is part of the naneng combphy, which is not yet available in mainline.
> > Naneng driver needs some changes and imho this should be part of it (including change documentation). That also makes it clear why this clock is added.
> > But leaving an unused property with sideeffects is imho no good choice.
> >
> > So this was the easiest way to fix the dtbs_check. Else i got no usable result for it. Maybe adding it to Documentation is also easy, but have not yet looked into it as it currently unused from my POV.
> >
> > But i leave it as decision for Maintainer to drop this patch as it is not needed for my Board DTS.
> 
> As both the current submission of the combophy driver and the gmac
> driver do not support xpcs, I elected to remove the clock vice adding
> documentation for something which is not currently supported.
> This is especially true as it only leaked through for the gmac0 port,
> the gmac1 port is modeled to the current support level.
> 
> Once xpcs support is introduced, the clock can be added to the
> documentation and both controllers as part of the same patch series.
> 
> Do you concur, Heiko?

Did you see my own reply from some hours ago?
From looking at the documentation I got the impression that the
pclk_xpcs is related to the separate qsgmii_pcs in the memory map.

So yes, I fully agree to dropping this clock from here and then adding
them to whatever ip block really needs it.


Heiko


> > > ===
> > >
> > > XPCS is also part of PD_PIPE.
> > > See Rockchip RK3568 TRM Part1 V1.0-20210111.pdf page 475.
> > > Please advise if the power-domain@RK3568_PD_PIPE does need a PCLK_XPCS
> > > fix or is PCLK_PIPE enough in combination with a PHY driver?
> > >
> > > PD_PIPE:
> > >
> > > BIU_PIPE
> > > USB3OTG
> > > PCIE20
> > > PCIE30
> > > SATA
> > > XPCS
> > >
> > >
> > >       power-domain@RK3568_PD_PIPE {
> > >               reg = <RK3568_PD_PIPE>;
> > >               clocks = <&cru PCLK_PIPE>;
> > >               pm_qos = <&qos_pcie2x1>,
> > >                        <&qos_pcie3x1>,
> > >                        <&qos_pcie3x2>,
> > >                        <&qos_sata0>,
> > >                        <&qos_sata1>,
> > >                        <&qos_sata2>,
> > >                        <&qos_usb3_0>,
> > >                        <&qos_usb3_1>;
> > >               #power-domain-cells = <0>;
> > >       };
> >
> > PD_PIPE is imho also part of Naneng. But more for usage as USB3/SATA/... phy. This is not part of Mainline too.
> >
> > But thanks for pointing.
> >
> > regards Frank
> 





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Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Heiko Stübner]

Am Montag, 17. Januar 2022, 19:26:27 CET schrieb Peter Geis:
> On Mon, Jan 17, 2022 at 6:59 AM Frank Wunderlich
> <frank-w@public-files.de> wrote:
> >
> > Hi
> >
> > > Gesendet: Montag, 17. Januar 2022 um 11:47 Uhr
> > > Von: "Johan Jonker" <jbx6244@gmail.com>
> > > Hi Frank,
> > >
> > > Despite that the DT is hosted in the kernel tree
> > > DT and mainline kernel driver support are 2 separate things.
> > > PCLK_XPCS might be in use elsewhere.
> > >
> > > Given the link below pclk_xpcs is only needed for rk3568.
> > > Maybe gmac1 should have a PCLK_XPCS too, because one can select between
> > > them.
> > >
> > > ethernet: stmicro: stmmac: Add SGMII/QSGMII support for RK3568
> > > https://github.com/rockchip-linux/kernel/commit/1fc7cbfe9e227c700c692f1de3137914b3ea6ca6
> > >
> > > The original dtsi did have PCLK_XPCS in both nodes.
> > > https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L2121
> > > https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi#L1492
> > >
> > > Maybe fix the document or leave it as it is for now as long the driver
> > > isn't updated and someone has tested it.
> > > That's up to the DT maintainer.
> > >
> > > Johan
> >
> > as far as i understand, the PCLK_XPCS is part of the naneng combphy, which is not yet available in mainline.
> > Naneng driver needs some changes and imho this should be part of it (including change documentation). That also makes it clear why this clock is added.
> > But leaving an unused property with sideeffects is imho no good choice.
> >
> > So this was the easiest way to fix the dtbs_check. Else i got no usable result for it. Maybe adding it to Documentation is also easy, but have not yet looked into it as it currently unused from my POV.
> >
> > But i leave it as decision for Maintainer to drop this patch as it is not needed for my Board DTS.
> 
> As both the current submission of the combophy driver and the gmac
> driver do not support xpcs, I elected to remove the clock vice adding
> documentation for something which is not currently supported.
> This is especially true as it only leaked through for the gmac0 port,
> the gmac1 port is modeled to the current support level.
> 
> Once xpcs support is introduced, the clock can be added to the
> documentation and both controllers as part of the same patch series.
> 
> Do you concur, Heiko?

Did you see my own reply from some hours ago?
From looking at the documentation I got the impression that the
pclk_xpcs is related to the separate qsgmii_pcs in the memory map.

So yes, I fully agree to dropping this clock from here and then adding
them to whatever ip block really needs it.


Heiko


> > > ===
> > >
> > > XPCS is also part of PD_PIPE.
> > > See Rockchip RK3568 TRM Part1 V1.0-20210111.pdf page 475.
> > > Please advise if the power-domain@RK3568_PD_PIPE does need a PCLK_XPCS
> > > fix or is PCLK_PIPE enough in combination with a PHY driver?
> > >
> > > PD_PIPE:
> > >
> > > BIU_PIPE
> > > USB3OTG
> > > PCIE20
> > > PCIE30
> > > SATA
> > > XPCS
> > >
> > >
> > >       power-domain@RK3568_PD_PIPE {
> > >               reg = <RK3568_PD_PIPE>;
> > >               clocks = <&cru PCLK_PIPE>;
> > >               pm_qos = <&qos_pcie2x1>,
> > >                        <&qos_pcie3x1>,
> > >                        <&qos_pcie3x2>,
> > >                        <&qos_sata0>,
> > >                        <&qos_sata1>,
> > >                        <&qos_sata2>,
> > >                        <&qos_usb3_0>,
> > >                        <&qos_usb3_1>;
> > >               #power-domain-cells = <0>;
> > >       };
> >
> > PD_PIPE is imho also part of Naneng. But more for usage as USB3/SATA/... phy. This is not part of Mainline too.
> >
> > But thanks for pointing.
> >
> > regards Frank
> 





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Aw: Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Frank Wunderlich]

Hi,

i plan to send a v2 of the series after 5.17-rc1 is out, because i have now verified
the functions from gpio header and found some pinctrl-changes. V1 had only prepared
the nodes to know which devices are present on this header.

should i include this patch again or do you pull it from v1 (maybe as fix)?

regards Frank


> Gesendet: Montag, 17. Januar 2022 um 22:05 Uhr
> Von: "Heiko Stübner" <heiko@sntech.de>

> From looking at the documentation I got the impression that the
> pclk_xpcs is related to the separate qsgmii_pcs in the memory map.
> 
> So yes, I fully agree to dropping this clock from here and then adding
> them to whatever ip block really needs it.

Aw: Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Frank Wunderlich]

Hi,

i plan to send a v2 of the series after 5.17-rc1 is out, because i have now verified
the functions from gpio header and found some pinctrl-changes. V1 had only prepared
the nodes to know which devices are present on this header.

should i include this patch again or do you pull it from v1 (maybe as fix)?

regards Frank


> Gesendet: Montag, 17. Januar 2022 um 22:05 Uhr
> Von: "Heiko Stübner" <heiko@sntech.de>

> From looking at the documentation I got the impression that the
> pclk_xpcs is related to the separate qsgmii_pcs in the memory map.
> 
> So yes, I fully agree to dropping this clock from here and then adding
> them to whatever ip block really needs it.

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Aw: Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Frank Wunderlich]

Hi,

i plan to send a v2 of the series after 5.17-rc1 is out, because i have now verified
the functions from gpio header and found some pinctrl-changes. V1 had only prepared
the nodes to know which devices are present on this header.

should i include this patch again or do you pull it from v1 (maybe as fix)?

regards Frank


> Gesendet: Montag, 17. Januar 2022 um 22:05 Uhr
> Von: "Heiko Stübner" <heiko@sntech.de>

> From looking at the documentation I got the impression that the
> pclk_xpcs is related to the separate qsgmii_pcs in the memory map.
> 
> So yes, I fully agree to dropping this clock from here and then adding
> them to whatever ip block really needs it.

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Re: Aw: Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Heiko Stuebner]

Hi Frank,

Am Samstag, 22. Januar 2022, 15:50:25 CET schrieb Frank Wunderlich:
> i plan to send a v2 of the series after 5.17-rc1 is out, because i have now verified
> the functions from gpio header and found some pinctrl-changes. V1 had only prepared
> the nodes to know which devices are present on this header.
> 
> should i include this patch again or do you pull it from v1 (maybe as fix)?

I do plan to include this as fix after -rc1, but I just saw that you already sent
a separate patch of it, so I'll take that one instead :-)

Heiko

> 
> regards Frank
> 
> 
> > Gesendet: Montag, 17. Januar 2022 um 22:05 Uhr
> > Von: "Heiko Stübner" <heiko@sntech.de>
> 
> > From looking at the documentation I got the impression that the
> > pclk_xpcs is related to the separate qsgmii_pcs in the memory map.
> > 
> > So yes, I fully agree to dropping this clock from here and then adding
> > them to whatever ip block really needs it.
> 

Re: Aw: Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Heiko Stuebner]

Hi Frank,

Am Samstag, 22. Januar 2022, 15:50:25 CET schrieb Frank Wunderlich:
> i plan to send a v2 of the series after 5.17-rc1 is out, because i have now verified
> the functions from gpio header and found some pinctrl-changes. V1 had only prepared
> the nodes to know which devices are present on this header.
> 
> should i include this patch again or do you pull it from v1 (maybe as fix)?

I do plan to include this as fix after -rc1, but I just saw that you already sent
a separate patch of it, so I'll take that one instead :-)

Heiko

> 
> regards Frank
> 
> 
> > Gesendet: Montag, 17. Januar 2022 um 22:05 Uhr
> > Von: "Heiko Stübner" <heiko@sntech.de>
> 
> > From looking at the documentation I got the impression that the
> > pclk_xpcs is related to the separate qsgmii_pcs in the memory map.
> > 
> > So yes, I fully agree to dropping this clock from here and then adding
> > them to whatever ip block really needs it.
> 





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Re: Aw: Re: [PATCH v1 1/3] dts64: rk3568: drop pclk_xpcs from gmac0

[Heiko Stuebner]

Hi Frank,

Am Samstag, 22. Januar 2022, 15:50:25 CET schrieb Frank Wunderlich:
> i plan to send a v2 of the series after 5.17-rc1 is out, because i have now verified
> the functions from gpio header and found some pinctrl-changes. V1 had only prepared
> the nodes to know which devices are present on this header.
> 
> should i include this patch again or do you pull it from v1 (maybe as fix)?

I do plan to include this as fix after -rc1, but I just saw that you already sent
a separate patch of it, so I'll take that one instead :-)

Heiko

> 
> regards Frank
> 
> 
> > Gesendet: Montag, 17. Januar 2022 um 22:05 Uhr
> > Von: "Heiko Stübner" <heiko@sntech.de>
> 
> > From looking at the documentation I got the impression that the
> > pclk_xpcs is related to the separate qsgmii_pcs in the memory map.
> > 
> > So yes, I fully agree to dropping this clock from here and then adding
> > them to whatever ip block really needs it.
> 





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