Re: [PATCH 7/9] arm64: dts: rockchip: adjust rk3568 pll clocks

[Peter Geis <pgwipeout@gmail.com>]

On Wed, Jul 28, 2021 at 10:09 AM Heiko Stübner <heiko@sntech.de> wrote:
>
> Hi Peter,
>
> Am Mittwoch, 28. Juli 2021, 15:55:32 CEST schrieb Peter Geis:
> > The rk3568 gpll should run at 1200mhz and the ppll should run at 200mhz.
> > These are set incorrectly by the bootloader, so fix them here.
>
> Can you specify where the "should run at" comes from?
> Normally I'd assume setting desired PLL frequencies would be quite
> board-specific.

gpll boots at 1188mhz, but to get accurate dividers for all
gpll_dividers it needs to run
at 1200mhz, otherwise everyone downstream isn't quite right.

ppll feeds the combophys, which has a divide by 2 clock, so 200mhz is
required to reach a 100mhz clock input for them.
Downstream also makes this fix.

rk356x has a number of dividers that produce expected clock values for
various peripherals, so changing the defaults would mean reclocking a
number of child dividers.

>
> So if we're setting defaults for all boards, I'd like some reasoning
> behind that ;-) ... especially when the other option would be to
> fix the bootloader.

Currently we are forced to use downstream u-boot (mainline isn't ready yet).
Downstream doesn't seem to want to assign clocks correctly, so the
simplest method right now is to have the kernel ensure they are
correct.

>
> Thanks
> Heiko
>
> >
> > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > ---
> >  arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > index 8ba0516eedd8..91ae3c541c1a 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > @@ -230,6 +230,8 @@ cru: clock-controller@fdd20000 {
> >               rockchip,grf = <&grf>;
> >               #clock-cells = <1>;
> >               #reset-cells = <1>;
> > +             assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
> > +             assigned-clock-rates = <1200000000>, <200000000>;
> >       };
> >
> >       i2c0: i2c@fdd40000 {
> >
>
>
>
>