Re: [PATCH 0/2] staging: mt7621-pci-phy: dt: bindings: convert bindings file from txt to yaml

[Sergio Paracuellos <sergio.paracuellos@gmail.com>]

Hi Neil,

On Sat, Apr 11, 2020 at 5:45 AM NeilBrown <neil@brown.name> wrote:
>
>
> Hi Sergio,
>  thanks for your continuing work on mt7621-pci.
>  I've looked through you patches and while things seem to make sense I
>  don't have the expertise to review them properly.
>
>  I've just a build a kernel based on v5.6.3 with the patches listed
>  below applied from your various emails over the last couple of months.
>
>  I have confirm that PCI works and in particular I don't get the
>  cold-boot hangs that are common without these patches.  So that is an
>  excellent result.

Yes, it seems it is not hanging anymore and that is always a good thing :-).
For me the pci phy driver is ready to be mainlined if the two phys
approach is correct.
and for the pci controller part I need to review how interrupts are
being mapped and
then convert bindings into a yaml file and get feedback about what to
do with the clock stuff.
According to this thread and because there is not a clock plan for
mt7621 assumptions should not be done for peripherals clocks:

http://archive.lwn.net:8080/devicetree/20190724022310.28010-1-gch981213@gmail.com/

So maybe we can just forget about clocks and clock-names stuff in the
pci controller binding and do what we are doing with the clock gate
now which is setting up the bit manually as other similar drivers do.

What do you think? (your tree has the patches of the thread I am
pointed out here applied)

>
> Thanks,
> NeilBrown

Best regards,
    Sergio Paracuellos
>
> 7e4350e416ed staging: mt7621-pci: simplify 'mt7621_pcie_init_virtual_bridges' function
> 283e56fe3f49 staging: mt7621-pci: enable clock bit for each port
> 5edfd9ca31ad MIPS: ralink: mt7621: introduce 'soc_device' initialization
> 7ce68fa530ad staging: mt7621-pci: use gpios for properly reset
> ccffb8f9a204 staging: mt7621-pci: change value for 'PERST_DELAY_MS'
> 840b0de42c22 staging: mt7621-dts: make use of 'reset-gpios' property for pci
> bd44f2c46e60 staging: mt7621-pci: bindings: update doc accordly to last changes
> a83cb7040463 staging: mt7621-pci: release gpios after pci initialization
> 51ae5f557464 staging: mt7621-pci: delete no more needed 'mt7621_reset_port'
> 6d5af2af8fdd staging: mt7621-pci-phy: add 'mt7621_phy_rmw' to simplify code
> 8f4e9d5f57ca staging: mt7621-pci: fix io space and properly set resource limits
> d907c205371d staging: mt7621-pci: fix register to set up virtual bridges
> 1a87910faf27 staging: mt7621-pci: don't return if get gpio fails
> dcd05b5bda59 staging: mt7621-pci-phy: avoid to create to different phys for a dual port one
> b2c3746212ae staging: mt7621-dts: set up only two pcie phys
> ef178ecf08bd staging: mt7621-pci: use only two phys from device tree
> 2553c237ffdc staging: mt7621-pci: change variable to print for slot
> 0bcb3caed96e staging: mt7621-pci: be sure gpio descriptor is null on fails
> 07d3877ebc7e staging: mt7621-pci: avoid to poweroff the phy for slot one
> ba5687b6220b staging: mt7621-dts: gpio 8 and 9 are vendor specific
> 04c8eb6ff776 staging: mt7621-pci: delete release gpios related code
> d3b3de21837b staging: mt7621-pci: use builtin_platform_driver()
> 41cd2464a89e staging: mt7621-pci: add myself as a contributor of the driver
^^^^
This one is not applied to the tree. This should be do throug the
MAINTAINERS file. Will do when this is mainlined.

> 815535a5b6ad staging: mt7621-pci-phy: use builtin_platform_driver()
> 8c26a5eec020 staging: mt7621-pci-phy: re-do 'xtal_mode' detection
> ccaa47aeb530 staging: mt7621-pci: avoid to set 'iomem_resource' addresses
> 28dd5daf3b55 staging: mt7621-pci: properly power off dual-ported pcie phy
> 10e6aa437d6e staging: mt7621-pci-phy: dt: bindings: add mediatek,mt7621-pci-phy.yaml
> 8dc6eec861d2 staging: mt7621-pci-phy: dt: bindings: remove bindings txt file