From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
To: Chuanhong Guo <gch981213@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
John Crispin <john@phrozen.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Weijie Gao <hackpascal@gmail.com>,
jiaxun.yang@flygoat.com,
"open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
open list <linux-kernel@vger.kernel.org>,
"open list:MIPS" <linux-mips@vger.kernel.org>,
"open list:STAGING SUBSYSTEM" <devel@driverdev.osuosl.org>
Subject: Re: [PATCH 0/7] MIPS: ralink: add CPU clock detection and clock gate driver for MT7621
Date: Thu, 12 Nov 2020 06:23:46 +0100 [thread overview]
Message-ID: <CAMhs-H85RCK=a_y+fVm-oR3hOEfr=rtVcLvX09YH4F65enz3oA@mail.gmail.com> (raw)
In-Reply-To: <CAJsYDVKWuygjbBErQt1B5XD8Bp06-TdrziBzDdYmMGhU_8X-aA@mail.gmail.com>
Hi,
On Thu, Nov 12, 2020 at 2:34 AM Chuanhong Guo <gch981213@gmail.com> wrote:
>
> On Thu, Nov 12, 2020 at 9:26 AM Chuanhong Guo <gch981213@gmail.com> wrote:
> >
> > I've already said in previous threads that clock assignment in
> > current linux kernel is not trustworthy.
> > I've got the clock plan for mt7621 now. (Can't share it, sorry.)
> > Most of your clock assumptions above are incorrect.
> > I've made a clock driver with gate support a few months ago.[0]
> > but I don't have much time to really finish it.
> > Maybe you could rework your clock gate driver based on it.
> >
> > [0] https://github.com/981213/linux/commit/2eca1f045e4c3db18c941135464c0d7422ad8133
>
> hsdma/eth/pio clocks are still missing in mediatek doc and
> I just made them up in the driver. Correct clock frequency for
> them aren't really important for them to work though.
> And another part I didn't finish is checking clock support for
> every drivers mt7621 used. Many drivers don't explicitly
> enable the clock and may be problematic when kernel
> gates unused clocks.
>
Well, I think they are not important either. Also, by default gate
register has all the gate bits enabled. When a gate driver is added,
the kernel by default will try to disable those clocks that haven't
been requested. To avoid weird behaviour because of some drivers are
not using properly clocks we have the CLK_IGNORED_UNUSED, which as you
can see is currently being used in my code. Using that all seems to
work as expected as it is now.
> --
> Regards,
> Chuanhong Guo
Best regards,
Sergio Paracuellos
WARNING: multiple messages have this Message-ID (diff)
From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
To: Chuanhong Guo <gch981213@gmail.com>
Cc: Weijie Gao <hackpascal@gmail.com>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Stephen Boyd <sboyd@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Michael Turquette <mturquette@baylibre.com>,
"open list:STAGING SUBSYSTEM" <devel@driverdev.osuosl.org>,
open list <linux-kernel@vger.kernel.org>,
jiaxun.yang@flygoat.com,
"open list:MIPS" <linux-mips@vger.kernel.org>,
Rob Herring <robh+dt@kernel.org>, John Crispin <john@phrozen.org>,
"open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>
Subject: Re: [PATCH 0/7] MIPS: ralink: add CPU clock detection and clock gate driver for MT7621
Date: Thu, 12 Nov 2020 06:23:46 +0100 [thread overview]
Message-ID: <CAMhs-H85RCK=a_y+fVm-oR3hOEfr=rtVcLvX09YH4F65enz3oA@mail.gmail.com> (raw)
In-Reply-To: <CAJsYDVKWuygjbBErQt1B5XD8Bp06-TdrziBzDdYmMGhU_8X-aA@mail.gmail.com>
Hi,
On Thu, Nov 12, 2020 at 2:34 AM Chuanhong Guo <gch981213@gmail.com> wrote:
>
> On Thu, Nov 12, 2020 at 9:26 AM Chuanhong Guo <gch981213@gmail.com> wrote:
> >
> > I've already said in previous threads that clock assignment in
> > current linux kernel is not trustworthy.
> > I've got the clock plan for mt7621 now. (Can't share it, sorry.)
> > Most of your clock assumptions above are incorrect.
> > I've made a clock driver with gate support a few months ago.[0]
> > but I don't have much time to really finish it.
> > Maybe you could rework your clock gate driver based on it.
> >
> > [0] https://github.com/981213/linux/commit/2eca1f045e4c3db18c941135464c0d7422ad8133
>
> hsdma/eth/pio clocks are still missing in mediatek doc and
> I just made them up in the driver. Correct clock frequency for
> them aren't really important for them to work though.
> And another part I didn't finish is checking clock support for
> every drivers mt7621 used. Many drivers don't explicitly
> enable the clock and may be problematic when kernel
> gates unused clocks.
>
Well, I think they are not important either. Also, by default gate
register has all the gate bits enabled. When a gate driver is added,
the kernel by default will try to disable those clocks that haven't
been requested. To avoid weird behaviour because of some drivers are
not using properly clocks we have the CLK_IGNORED_UNUSED, which as you
can see is currently being used in my code. Using that all seems to
work as expected as it is now.
> --
> Regards,
> Chuanhong Guo
Best regards,
Sergio Paracuellos
_______________________________________________
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http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
next prev parent reply other threads:[~2020-11-12 5:39 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-11 16:30 [PATCH 0/7] MIPS: ralink: add CPU clock detection and clock gate driver for MT7621 Sergio Paracuellos
2020-11-11 16:30 ` Sergio Paracuellos
2020-11-11 16:30 ` [PATCH 1/7] dt-bindings: clock: add dt binding header for mt7621 clocks Sergio Paracuellos
2020-11-11 16:30 ` Sergio Paracuellos
2020-11-11 16:30 ` [PATCH 2/7] dt: bindings: add mt7621-pll device tree binding documentation Sergio Paracuellos
2020-11-11 16:30 ` Sergio Paracuellos
2020-11-16 19:16 ` Rob Herring
2020-11-16 19:16 ` Rob Herring
2020-11-17 5:38 ` Sergio Paracuellos
2020-11-17 5:38 ` Sergio Paracuellos
2020-11-11 16:30 ` [PATCH 3/7] dt: bindings: add mt7621-clk " Sergio Paracuellos
2020-11-11 16:30 ` Sergio Paracuellos
2020-11-11 16:30 ` [PATCH 4/7] MIPS: ralink: add clock device providing cpu/ahb/apb clock for mt7621 Sergio Paracuellos
2020-11-11 16:30 ` Sergio Paracuellos
2020-11-11 16:30 ` [PATCH 5/7] clk: ralink: add clock gate driver for mt7621 SoC Sergio Paracuellos
2020-11-11 16:30 ` Sergio Paracuellos
2020-11-11 16:30 ` [PATCH 6/7] staging: mt7621-dts: make use of new 'mt7621-pll' and 'mt7621-clk' Sergio Paracuellos
2020-11-11 16:30 ` Sergio Paracuellos
2020-11-11 16:30 ` [PATCH 7/7] MAINTAINERS: add MT7621 CLOCK maintainer Sergio Paracuellos
2020-11-11 16:30 ` Sergio Paracuellos
2020-11-12 1:26 ` [PATCH 0/7] MIPS: ralink: add CPU clock detection and clock gate driver for MT7621 Chuanhong Guo
2020-11-12 1:26 ` Chuanhong Guo
2020-11-12 1:33 ` Chuanhong Guo
2020-11-12 1:33 ` Chuanhong Guo
2020-11-12 5:23 ` Sergio Paracuellos [this message]
2020-11-12 5:23 ` Sergio Paracuellos
2020-11-13 0:40 ` Chuanhong Guo
2020-11-13 0:40 ` Chuanhong Guo
2020-11-13 5:32 ` Sergio Paracuellos
2020-11-13 5:32 ` Sergio Paracuellos
2020-11-12 5:18 ` Sergio Paracuellos
2020-11-12 5:18 ` Sergio Paracuellos
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