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From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
To: Greg KH <gregkh@linuxfoundation.org>
Cc: Vinod Koul <vkoul@kernel.org>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	 "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
	<devicetree@vger.kernel.org>,
	linux-phy@lists.infradead.org,  Rob Herring <robh+dt@kernel.org>,
	linux-staging@lists.linux.dev,  NeilBrown <neil@brown.name>,
	Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Subject: Re: [PATCH RESEND v2 0/6] phy: ralink: mt7621-pci-phy: some improvements
Date: Fri, 14 May 2021 13:30:16 +0200	[thread overview]
Message-ID: <CAMhs-H8kjL-TdX97mvw+Q3X-HybR3Ox8KrXUY3vJp2jKwv4Q8g@mail.gmail.com> (raw)
In-Reply-To: <YJ5ddkGytGI+kAt9@kroah.com>

On Fri, May 14, 2021 at 1:22 PM Greg KH <gregkh@linuxfoundation.org> wrote:
>
> On Fri, May 14, 2021 at 01:19:18PM +0200, Sergio Paracuellos wrote:
> > On Fri, May 14, 2021 at 12:46 PM Vinod Koul <vkoul@kernel.org> wrote:
> > >
> > > On 08-05-21, 09:09, Sergio Paracuellos wrote:
> > > > Hi all,
> > > >
> > > > This series contains some improvements in the pci phy driver
> > > > for MT7621 SoCs.
> > > >
> > > > MT7621 SoC clock driver has already mainlined in
> > > > 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")'
> > > >
> > > > Because of this we can update schema documentation and device tree
> > > > to add related clock entries and avoid custom architecture code
> > > > in favour of using the clock kernel framework to retrieve clock
> > > > frequency needed to properly configure the PCIe related Phys.
> > > >
> > > > After this changes there is no problem to properly enable this
> > > > driver for COMPILE_TEST.
> > > >
> > > > Configuration has also modified from 'tristate' to 'bool' depending
> > > > on PCI_MT7621 which seems to have more sense.
> > >
> > > Applied 2-6, thanks
> >
> > Thanks, Vinod.
> >
> > Greg, can you take patch 1 through your tree?
>
> Sure, can you resend it?

Thanks, I have just resent it.

>
> thanks,
>
> greg k-h

Best regards,
     Sergio Paracuellos

WARNING: multiple messages have this Message-ID (diff)
From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
To: Greg KH <gregkh@linuxfoundation.org>
Cc: Vinod Koul <vkoul@kernel.org>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	 "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
	<devicetree@vger.kernel.org>,
	linux-phy@lists.infradead.org,  Rob Herring <robh+dt@kernel.org>,
	linux-staging@lists.linux.dev,  NeilBrown <neil@brown.name>,
	Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Subject: Re: [PATCH RESEND v2 0/6] phy: ralink: mt7621-pci-phy: some improvements
Date: Fri, 14 May 2021 13:30:16 +0200	[thread overview]
Message-ID: <CAMhs-H8kjL-TdX97mvw+Q3X-HybR3Ox8KrXUY3vJp2jKwv4Q8g@mail.gmail.com> (raw)
In-Reply-To: <YJ5ddkGytGI+kAt9@kroah.com>

On Fri, May 14, 2021 at 1:22 PM Greg KH <gregkh@linuxfoundation.org> wrote:
>
> On Fri, May 14, 2021 at 01:19:18PM +0200, Sergio Paracuellos wrote:
> > On Fri, May 14, 2021 at 12:46 PM Vinod Koul <vkoul@kernel.org> wrote:
> > >
> > > On 08-05-21, 09:09, Sergio Paracuellos wrote:
> > > > Hi all,
> > > >
> > > > This series contains some improvements in the pci phy driver
> > > > for MT7621 SoCs.
> > > >
> > > > MT7621 SoC clock driver has already mainlined in
> > > > 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")'
> > > >
> > > > Because of this we can update schema documentation and device tree
> > > > to add related clock entries and avoid custom architecture code
> > > > in favour of using the clock kernel framework to retrieve clock
> > > > frequency needed to properly configure the PCIe related Phys.
> > > >
> > > > After this changes there is no problem to properly enable this
> > > > driver for COMPILE_TEST.
> > > >
> > > > Configuration has also modified from 'tristate' to 'bool' depending
> > > > on PCI_MT7621 which seems to have more sense.
> > >
> > > Applied 2-6, thanks
> >
> > Thanks, Vinod.
> >
> > Greg, can you take patch 1 through your tree?
>
> Sure, can you resend it?

Thanks, I have just resent it.

>
> thanks,
>
> greg k-h

Best regards,
     Sergio Paracuellos

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

  reply	other threads:[~2021-05-14 11:30 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-08  7:09 [PATCH RESEND v2 0/6] phy: ralink: mt7621-pci-phy: some improvements Sergio Paracuellos
2021-05-08  7:09 ` Sergio Paracuellos
2021-05-08  7:09 ` [PATCH RESEND v2 1/6] staging: mt7621-dts: use clock in pci phy nodes Sergio Paracuellos
2021-05-08  7:09   ` Sergio Paracuellos
2021-05-08  7:09 ` [PATCH RESEND v2 2/6] dt-bindings: phy: mediatek,mt7621-pci-phy: add clock entries Sergio Paracuellos
2021-05-08  7:09   ` [PATCH RESEND v2 2/6] dt-bindings: phy: mediatek, mt7621-pci-phy: " Sergio Paracuellos
2021-05-10 16:01   ` [PATCH RESEND v2 2/6] dt-bindings: phy: mediatek,mt7621-pci-phy: " Rob Herring
2021-05-10 16:01     ` [PATCH RESEND v2 2/6] dt-bindings: phy: mediatek, mt7621-pci-phy: " Rob Herring
2021-05-08  7:09 ` [PATCH RESEND v2 3/6] phy: ralink: phy-mt7621-pci: use kernel clock APIS Sergio Paracuellos
2021-05-08  7:09   ` Sergio Paracuellos
2021-05-08  7:09 ` [PATCH RESEND v2 4/6] phy: ralink: Kconfig: enable COMPILE_TEST on mt7621-pci-phy driver Sergio Paracuellos
2021-05-08  7:09   ` Sergio Paracuellos
2021-05-08  7:09 ` [PATCH RESEND v2 5/6] phy: ralink: Kconfig: convert mt7621-pci-phy into 'bool' Sergio Paracuellos
2021-05-08  7:09   ` Sergio Paracuellos
2021-05-08  7:09 ` [PATCH RESEND v2 6/6] phy: ralink: phy-mt7621-pci: properly print pointer address Sergio Paracuellos
2021-05-08  7:09   ` Sergio Paracuellos
2021-05-14 10:46 ` [PATCH RESEND v2 0/6] phy: ralink: mt7621-pci-phy: some improvements Vinod Koul
2021-05-14 10:46   ` Vinod Koul
2021-05-14 11:19   ` Sergio Paracuellos
2021-05-14 11:19     ` Sergio Paracuellos
2021-05-14 11:19     ` Sergio Paracuellos
2021-05-14 11:22     ` Greg KH
2021-05-14 11:22       ` Greg KH
2021-05-14 11:22       ` Greg KH
2021-05-14 11:30       ` Sergio Paracuellos [this message]
2021-05-14 11:30         ` Sergio Paracuellos
2021-05-14 11:30         ` Sergio Paracuellos

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