Re: ardb/for-kernelci bisection: baseline.login on meson-gxl-s905d-p230

Re: ardb/for-kernelci bisection: baseline.login on meson-gxl-s905d-p230

[Ard Biesheuvel]

On Fri, 1 Jul 2022 at 16:37, Mark Brown <broonie@kernel.org> wrote:
>
> On Fri, Jul 01, 2022 at 07:21:15AM -0700, KernelCI bot wrote:
>
> The KernelCI bot found a boot failure in Ard's test branch on at
> least meson-gxl-s905d-p230 (an arm64 platform) with
> defconfig+BIG_ENDIAN triggered by ce6caf72d162d ("arm64: head:
> avoid cache invalidation when entering with the MMU on").  I've
> left the full report below including links to things like full
> boot logs, in the failing case the kernel dies with no output (as
> might be expected for a change in early boot).
>
> > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
> > * This automated bisection report was sent to you on the basis  *
> > * that you may be involved with the breaking commit it has      *
> > * found.  No manual investigation has been done to verify it,   *
> > * and the root cause of the problem may be somewhere else.      *
> > *                                                               *
> > * If you do send a fix, please include this trailer:            *
> > *   Reported-by: "kernelci.org bot" <bot@kernelci.org>          *
> > *                                                               *
> > * Hope this helps!                                              *
> > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
> >
> > ardb/for-kernelci bisection: baseline.login on meson-gxl-s905d-p230
> >
> > Summary:
> >   Start:      3ed2d2fa189b2 arm64: mm: add support for WXN memory translation attribute
> >   Plain log:  https://storage.kernelci.org/ardb/for-kernelci/v5.19-rc3-44-g3ed2d2fa189b/arm64/defconfig+CONFIG_CPU_BIG_ENDIAN=y/gcc-10/lab-baylibre/baseline-meson-gxl-s905d-p230.txt
> >   HTML log:   https://storage.kernelci.org/ardb/for-kernelci/v5.19-rc3-44-g3ed2d2fa189b/arm64/defconfig+CONFIG_CPU_BIG_ENDIAN=y/gcc-10/lab-baylibre/baseline-meson-gxl-s905d-p230.html
> >   Result:     ce6caf72d162d arm64: head: avoid cache invalidation when entering with the MMU on
> >

This is quite interesting, actually, as it suggests that, on this
particular platform, we enter with the MMU enabled, as this patch
should have no effect whatsoever otherwise.

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Re: ardb/for-kernelci bisection: baseline.login on meson-gxl-s905d-p230

[Mark Brown]

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On Fri, Jul 01, 2022 at 06:23:35PM +0200, Ard Biesheuvel wrote:
> On Fri, 1 Jul 2022 at 16:37, Mark Brown <broonie@kernel.org> wrote:

> > >   Plain log:  https://storage.kernelci.org/ardb/for-kernelci/v5.19-rc3-44-g3ed2d2fa189b/arm64/defconfig+CONFIG_CPU_BIG_ENDIAN=y/gcc-10/lab-baylibre/baseline-meson-gxl-s905d-p230.txt
> > >   HTML log:   https://storage.kernelci.org/ardb/for-kernelci/v5.19-rc3-44-g3ed2d2fa189b/arm64/defconfig+CONFIG_CPU_BIG_ENDIAN=y/gcc-10/lab-baylibre/baseline-meson-gxl-s905d-p230.html

> This is quite interesting, actually, as it suggests that, on this
> particular platform, we enter with the MMU enabled, as this patch
> should have no effect whatsoever otherwise.

Ah, indeed.  FWIW this system appears to be booting using a vendor
rather than upstream u-boot (the version string is
2015.01-01166-gffd40ecd0ea2-dirty and there's some logging that looks
suspiciously non-upstream).

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Re: ardb/for-kernelci bisection: baseline.login on meson-gxl-s905d-p230

[Mark Brown]

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On Fri, Jul 01, 2022 at 07:21:15AM -0700, KernelCI bot wrote:

The KernelCI bot found a boot failure in Ard's test branch on at
least meson-gxl-s905d-p230 (an arm64 platform) with
defconfig+BIG_ENDIAN triggered by ce6caf72d162d ("arm64: head:
avoid cache invalidation when entering with the MMU on").  I've
left the full report below including links to things like full
boot logs, in the failing case the kernel dies with no output (as
might be expected for a change in early boot).

> * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
> * This automated bisection report was sent to you on the basis  *
> * that you may be involved with the breaking commit it has      *
> * found.  No manual investigation has been done to verify it,   *
> * and the root cause of the problem may be somewhere else.      *
> *                                                               *
> * If you do send a fix, please include this trailer:            *
> *   Reported-by: "kernelci.org bot" <bot@kernelci.org>          *
> *                                                               *
> * Hope this helps!                                              *
> * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
> 
> ardb/for-kernelci bisection: baseline.login on meson-gxl-s905d-p230
> 
> Summary:
>   Start:      3ed2d2fa189b2 arm64: mm: add support for WXN memory translation attribute
>   Plain log:  https://storage.kernelci.org/ardb/for-kernelci/v5.19-rc3-44-g3ed2d2fa189b/arm64/defconfig+CONFIG_CPU_BIG_ENDIAN=y/gcc-10/lab-baylibre/baseline-meson-gxl-s905d-p230.txt
>   HTML log:   https://storage.kernelci.org/ardb/for-kernelci/v5.19-rc3-44-g3ed2d2fa189b/arm64/defconfig+CONFIG_CPU_BIG_ENDIAN=y/gcc-10/lab-baylibre/baseline-meson-gxl-s905d-p230.html
>   Result:     ce6caf72d162d arm64: head: avoid cache invalidation when entering with the MMU on
> 
> Checks:
>   revert:     PASS
>   verify:     PASS
> 
> Parameters:
>   Tree:       ardb
>   URL:        https://git.kernel.org/pub/scm/linux/kernel/git/ardb/linux.git
>   Branch:     for-kernelci
>   Target:     meson-gxl-s905d-p230
>   CPU arch:   arm64
>   Lab:        lab-baylibre
>   Compiler:   gcc-10
>   Config:     defconfig+CONFIG_CPU_BIG_ENDIAN=y
>   Test case:  baseline.login
> 
> Breaking commit found:
> 
> -------------------------------------------------------------------------------
> commit ce6caf72d162db53c94659e935916eb7c6176239
> Author: Ard Biesheuvel <ardb@kernel.org>
> Date:   Wed Mar 30 12:15:44 2022 +0200
> 
>     arm64: head: avoid cache invalidation when entering with the MMU on
>     
>     If we enter with the MMU on, there is no need for explicit cache
>     invalidation for stores to memory, as they will be coherent with the
>     caches.
>     
>     Let's take advantage of this, and create the ID map with the MMU still
>     enabled if that is how we entered, and avoid any cache invalidation
>     calls in that case.
>     
>     Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
> 
> diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
> index a79c842395eeb..42fc7e980b352 100644
> --- a/arch/arm64/kernel/head.S
> +++ b/arch/arm64/kernel/head.S
> @@ -88,9 +88,9 @@
>  SYM_CODE_START(primary_entry)
>  	bl	record_mmu_state
>  	bl	preserve_boot_args
> +	bl	create_idmap
>  	bl	init_kernel_el			// w0=cpu_boot_mode
>  	mov	x20, x0
> -	bl	create_idmap
>  
>  	/*
>  	 * The following calls CPU setup code, see arch/arm64/mm/proc.S for
> @@ -130,11 +130,13 @@ SYM_CODE_START_LOCAL(preserve_boot_args)
>  	stp	x21, x1, [x0]			// x0 .. x3 at kernel entry
>  	stp	x2, x3, [x0, #16]
>  
> +	cbnz	x19, 0f				// skip cache invalidation if MMU is on
>  	dmb	sy				// needed before dc ivac with
>  						// MMU off
>  
>  	add	x1, x0, #0x20			// 4 x 8 bytes
>  	b	dcache_inval_poc		// tail call
> +0:	ret
>  SYM_CODE_END(preserve_boot_args)
>  
>  SYM_FUNC_START_LOCAL(clear_page_tables)
> @@ -371,12 +373,13 @@ SYM_FUNC_START_LOCAL(create_idmap)
>  	 * accesses (MMU disabled), invalidate those tables again to
>  	 * remove any speculatively loaded cache lines.
>  	 */
> +	cbnz	x19, 0f				// skip cache invalidation if MMU is on
>  	dmb	sy
>  
>  	adrp	x0, init_idmap_pg_dir
>  	adrp	x1, init_idmap_pg_end
>  	bl	dcache_inval_poc
> -	ret	x28
> +0:	ret	x28
>  SYM_FUNC_END(create_idmap)
>  
>  SYM_FUNC_START_LOCAL(create_kernel_mapping)
> -------------------------------------------------------------------------------
> 
> 
> Git bisection log:
> 
> -------------------------------------------------------------------------------
> git bisect start
> # good: [a111daf0c53ae91e71fd2bfe7497862d14132e3e] Linux 5.19-rc3
> git bisect good a111daf0c53ae91e71fd2bfe7497862d14132e3e
> # bad: [3ed2d2fa189b2f472547045b3af344e7806f7779] arm64: mm: add support for WXN memory translation attribute
> git bisect bad 3ed2d2fa189b2f472547045b3af344e7806f7779
> # good: [fbf6ad5efe95665c188248b6abee94f4bf296604] arm64: lds: use PROVIDE instead of conditional definitions
> git bisect good fbf6ad5efe95665c188248b6abee94f4bf296604
> # bad: [ce6caf72d162db53c94659e935916eb7c6176239] arm64: head: avoid cache invalidation when entering with the MMU on
> git bisect bad ce6caf72d162db53c94659e935916eb7c6176239
> # good: [af03256f03e5778febc5ed68fdc9bc57187b5cef] Merge remote-tracking branch 'arm64/for-next/kpti' into HEAD
> git bisect good af03256f03e5778febc5ed68fdc9bc57187b5cef
> # good: [cfb53f613ffaea171638847cb20f4079d5c4943a] arm64: lds: reduce effective minimum image alignment to 64k
> git bisect good cfb53f613ffaea171638847cb20f4079d5c4943a
> # good: [37eb93735927e84eef73523556c769c4d65ac634] arm64: head: record the MMU state at primary entry
> git bisect good 37eb93735927e84eef73523556c769c4d65ac634
> # first bad commit: [ce6caf72d162db53c94659e935916eb7c6176239] arm64: head: avoid cache invalidation when entering with the MMU on
> -------------------------------------------------------------------------------
> 
> 
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