* [Qemu-devel] [PATCH 0/4] target/xtensa: Convert to TranslatorOps
@ 2018-05-12 17:57 Richard Henderson
2018-05-12 17:57 ` [Qemu-devel] [PATCH 1/4] target/xtensa: Replace DISAS_UPDATE with DISAS_NORETURN Richard Henderson
` (4 more replies)
0 siblings, 5 replies; 10+ messages in thread
From: Richard Henderson @ 2018-05-12 17:57 UTC (permalink / raw)
To: qemu-devel; +Cc: jcmvbkbc
I have one xtensa image against which to test this.
There are enough options going on here in the xtensa
frontend that this probably needs a better work-out.
r~
Richard Henderson (4):
target/xtensa: Replace DISAS_UPDATE with DISAS_NORETURN
target/xtensa: Convert to DisasContextBase
target/xtensa: Change gen_intermediate_code dc to pointer
target/xtensa: Convert to TranslatorOps
target/xtensa/translate.c | 345 +++++++++++++++++++-------------------
1 file changed, 177 insertions(+), 168 deletions(-)
--
2.17.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Qemu-devel] [PATCH 1/4] target/xtensa: Replace DISAS_UPDATE with DISAS_NORETURN
2018-05-12 17:57 [Qemu-devel] [PATCH 0/4] target/xtensa: Convert to TranslatorOps Richard Henderson
@ 2018-05-12 17:57 ` Richard Henderson
2018-05-12 17:57 ` [Qemu-devel] [PATCH 2/4] target/xtensa: Convert to DisasContextBase Richard Henderson
` (3 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: Richard Henderson @ 2018-05-12 17:57 UTC (permalink / raw)
To: qemu-devel; +Cc: jcmvbkbc
The usage of DISAS_UPDATE is after noreturn helpers.
It is thus indistinguishable from DISAS_NORETURN.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/xtensa/translate.c | 21 +++++++++------------
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index aad496347d..a1e63f9661 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -47,9 +47,6 @@
#include "exec/log.h"
-/* is_jmp field values */
-#define DISAS_UPDATE DISAS_TARGET_0 /* cpu state was modified dynamically */
-
struct DisasContext {
const XtensaConfig *config;
TranslationBlock *tb;
@@ -317,7 +314,7 @@ static void gen_exception_cause(DisasContext *dc, uint32_t cause)
tcg_temp_free(tcause);
if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
cause == SYSCALL_CAUSE) {
- dc->is_jmp = DISAS_UPDATE;
+ dc->is_jmp = DISAS_NORETURN;
}
}
@@ -339,7 +336,7 @@ static void gen_debug_exception(DisasContext *dc, uint32_t cause)
tcg_temp_free(tpc);
tcg_temp_free(tcause);
if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
- dc->is_jmp = DISAS_UPDATE;
+ dc->is_jmp = DISAS_NORETURN;
}
}
@@ -351,7 +348,7 @@ static bool gen_check_privilege(DisasContext *dc)
}
#endif
gen_exception_cause(dc, PRIVILEGED_CAUSE);
- dc->is_jmp = DISAS_UPDATE;
+ dc->is_jmp = DISAS_NORETURN;
return false;
}
@@ -360,7 +357,7 @@ static bool gen_check_cpenable(DisasContext *dc, unsigned cp)
if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) &&
!(dc->cpenable & (1 << cp))) {
gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp);
- dc->is_jmp = DISAS_UPDATE;
+ dc->is_jmp = DISAS_NORETURN;
return false;
}
return true;
@@ -382,7 +379,7 @@ static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
tcg_gen_exit_tb(0);
}
}
- dc->is_jmp = DISAS_UPDATE;
+ dc->is_jmp = DISAS_NORETURN;
}
static void gen_jump(DisasContext *dc, TCGv dest)
@@ -918,7 +915,7 @@ static bool gen_window_check1(DisasContext *dc, unsigned r1)
TCGv_i32 w = tcg_const_i32(r1 / 4);
gen_helper_window_check(cpu_env, pc, w);
- dc->is_jmp = DISAS_UPDATE;
+ dc->is_jmp = DISAS_NORETURN;
return false;
}
return true;
@@ -1103,14 +1100,14 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
tcg_gen_insn_start(dc.pc);
++insn_count;
gen_exception(&dc, EXCP_YIELD);
- dc.is_jmp = DISAS_UPDATE;
+ dc.is_jmp = DISAS_NORETURN;
goto done;
}
if (tb->flags & XTENSA_TBFLAG_EXCEPTION) {
tcg_gen_insn_start(dc.pc);
++insn_count;
gen_exception(&dc, EXCP_DEBUG);
- dc.is_jmp = DISAS_UPDATE;
+ dc.is_jmp = DISAS_NORETURN;
goto done;
}
@@ -1121,7 +1118,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) {
tcg_gen_movi_i32(cpu_pc, dc.pc);
gen_exception(&dc, EXCP_DEBUG);
- dc.is_jmp = DISAS_UPDATE;
+ dc.is_jmp = DISAS_NORETURN;
/* The address covered by the breakpoint must be included in
[tb->pc, tb->pc + tb->size) in order to for it to be
properly cleared -- thus we increment the PC here so that
--
2.17.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Qemu-devel] [PATCH 2/4] target/xtensa: Convert to DisasContextBase
2018-05-12 17:57 [Qemu-devel] [PATCH 0/4] target/xtensa: Convert to TranslatorOps Richard Henderson
2018-05-12 17:57 ` [Qemu-devel] [PATCH 1/4] target/xtensa: Replace DISAS_UPDATE with DISAS_NORETURN Richard Henderson
@ 2018-05-12 17:57 ` Richard Henderson
2018-05-12 17:57 ` [Qemu-devel] [PATCH 3/4] target/xtensa: Change gen_intermediate_code dc to pointer Richard Henderson
` (2 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: Richard Henderson @ 2018-05-12 17:57 UTC (permalink / raw)
To: qemu-devel; +Cc: jcmvbkbc
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/xtensa/translate.c | 89 +++++++++++++++++++--------------------
1 file changed, 43 insertions(+), 46 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index a1e63f9661..cc48d105e9 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -48,16 +48,13 @@
struct DisasContext {
+ DisasContextBase base;
const XtensaConfig *config;
- TranslationBlock *tb;
uint32_t pc;
- uint32_t next_pc;
int cring;
int ring;
uint32_t lbeg;
uint32_t lend;
- int is_jmp;
- int singlestep_enabled;
bool sar_5bit;
bool sar_m32_5bit;
@@ -314,7 +311,7 @@ static void gen_exception_cause(DisasContext *dc, uint32_t cause)
tcg_temp_free(tcause);
if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
cause == SYSCALL_CAUSE) {
- dc->is_jmp = DISAS_NORETURN;
+ dc->base.is_jmp = DISAS_NORETURN;
}
}
@@ -336,7 +333,7 @@ static void gen_debug_exception(DisasContext *dc, uint32_t cause)
tcg_temp_free(tpc);
tcg_temp_free(tcause);
if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
- dc->is_jmp = DISAS_NORETURN;
+ dc->base.is_jmp = DISAS_NORETURN;
}
}
@@ -348,7 +345,7 @@ static bool gen_check_privilege(DisasContext *dc)
}
#endif
gen_exception_cause(dc, PRIVILEGED_CAUSE);
- dc->is_jmp = DISAS_NORETURN;
+ dc->base.is_jmp = DISAS_NORETURN;
return false;
}
@@ -357,7 +354,7 @@ static bool gen_check_cpenable(DisasContext *dc, unsigned cp)
if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) &&
!(dc->cpenable & (1 << cp))) {
gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp);
- dc->is_jmp = DISAS_NORETURN;
+ dc->base.is_jmp = DISAS_NORETURN;
return false;
}
return true;
@@ -369,17 +366,17 @@ static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
if (dc->icount) {
tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
}
- if (dc->singlestep_enabled) {
+ if (dc->base.singlestep_enabled) {
gen_exception(dc, EXCP_DEBUG);
} else {
if (slot >= 0) {
tcg_gen_goto_tb(slot);
- tcg_gen_exit_tb((uintptr_t)dc->tb + slot);
+ tcg_gen_exit_tb((uintptr_t)dc->base.tb + slot);
} else {
tcg_gen_exit_tb(0);
}
}
- dc->is_jmp = DISAS_NORETURN;
+ dc->base.is_jmp = DISAS_NORETURN;
}
static void gen_jump(DisasContext *dc, TCGv dest)
@@ -391,7 +388,7 @@ static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
{
TCGv_i32 tmp = tcg_const_i32(dest);
#ifndef CONFIG_USER_ONLY
- if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
+ if (((dc->base.pc_first ^ dest) & TARGET_PAGE_MASK) != 0) {
slot = -1;
}
#endif
@@ -408,7 +405,7 @@ static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
tcg_temp_free(tcallinc);
tcg_gen_movi_i32(cpu_R[callinc << 2],
- (callinc << 30) | (dc->next_pc & 0x3fffffff));
+ (callinc << 30) | (dc->base.pc_next & 0x3fffffff));
gen_jump_slot(dc, dest, slot);
}
@@ -421,7 +418,7 @@ static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
{
TCGv_i32 tmp = tcg_const_i32(dest);
#ifndef CONFIG_USER_ONLY
- if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
+ if (((dc->base.pc_first ^ dest) & TARGET_PAGE_MASK) != 0) {
slot = -1;
}
#endif
@@ -432,15 +429,15 @@ static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
static bool gen_check_loop_end(DisasContext *dc, int slot)
{
if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
- !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
- dc->next_pc == dc->lend) {
+ !(dc->base.tb->flags & XTENSA_TBFLAG_EXCM) &&
+ dc->base.pc_next == dc->lend) {
TCGLabel *label = gen_new_label();
tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
gen_jumpi(dc, dc->lbeg, slot);
gen_set_label(label);
- gen_jumpi(dc, dc->next_pc, -1);
+ gen_jumpi(dc, dc->base.pc_next, -1);
return true;
}
return false;
@@ -449,7 +446,7 @@ static bool gen_check_loop_end(DisasContext *dc, int slot)
static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
{
if (!gen_check_loop_end(dc, slot)) {
- gen_jumpi(dc, dc->next_pc, slot);
+ gen_jumpi(dc, dc->base.pc_next, slot);
}
}
@@ -500,12 +497,12 @@ static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
#ifndef CONFIG_USER_ONLY
static bool gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
{
- if (tb_cflags(dc->tb) & CF_USE_ICOUNT) {
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_update_ccount(cpu_env);
tcg_gen_mov_i32(d, cpu_SR[sr]);
- if (tb_cflags(dc->tb) & CF_USE_ICOUNT) {
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
gen_io_end();
return true;
}
@@ -689,11 +686,11 @@ static bool gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
static void gen_check_interrupts(DisasContext *dc)
{
- if (tb_cflags(dc->tb) & CF_USE_ICOUNT) {
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_check_interrupts(cpu_env);
- if (tb_cflags(dc->tb) & CF_USE_ICOUNT) {
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
gen_io_end();
}
}
@@ -747,11 +744,11 @@ static bool gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
static bool gen_wsr_ccount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
{
- if (tb_cflags(dc->tb) & CF_USE_ICOUNT) {
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_wsr_ccount(cpu_env, v);
- if (tb_cflags(dc->tb) & CF_USE_ICOUNT) {
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
gen_io_end();
gen_jumpi_check_loop_end(dc, 0);
return true;
@@ -788,11 +785,11 @@ static bool gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
tcg_gen_mov_i32(cpu_SR[sr], v);
tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
- if (tb_cflags(dc->tb) & CF_USE_ICOUNT) {
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_update_ccompare(cpu_env, tmp);
- if (tb_cflags(dc->tb) & CF_USE_ICOUNT) {
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
gen_io_end();
gen_jumpi_check_loop_end(dc, 0);
ret = true;
@@ -892,14 +889,14 @@ static void gen_load_store_alignment(DisasContext *dc, int shift,
#ifndef CONFIG_USER_ONLY
static void gen_waiti(DisasContext *dc, uint32_t imm4)
{
- TCGv_i32 pc = tcg_const_i32(dc->next_pc);
+ TCGv_i32 pc = tcg_const_i32(dc->base.pc_next);
TCGv_i32 intlevel = tcg_const_i32(imm4);
- if (tb_cflags(dc->tb) & CF_USE_ICOUNT) {
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_waiti(cpu_env, pc, intlevel);
- if (tb_cflags(dc->tb) & CF_USE_ICOUNT) {
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
gen_io_end();
}
tcg_temp_free(pc);
@@ -915,7 +912,7 @@ static bool gen_window_check1(DisasContext *dc, unsigned r1)
TCGv_i32 w = tcg_const_i32(r1 / 4);
gen_helper_window_check(cpu_env, pc, w);
- dc->is_jmp = DISAS_NORETURN;
+ dc->base.is_jmp = DISAS_NORETURN;
return false;
}
return true;
@@ -966,7 +963,7 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
return;
}
- dc->next_pc = dc->pc + len;
+ dc->base.pc_next = dc->pc + len;
for (i = 1; i < len; ++i) {
b[i] = cpu_ldub_code(env, dc->pc + i);
}
@@ -1026,10 +1023,10 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
return;
}
}
- if (dc->is_jmp == DISAS_NEXT) {
+ if (dc->base.is_jmp == DISAS_NEXT) {
gen_check_loop_end(dc, 0);
}
- dc->pc = dc->next_pc;
+ dc->pc = dc->base.pc_next;
}
static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc)
@@ -1068,14 +1065,14 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
}
dc.config = env->config;
- dc.singlestep_enabled = cs->singlestep_enabled;
- dc.tb = tb;
+ dc.base.singlestep_enabled = cs->singlestep_enabled;
+ dc.base.tb = tb;
dc.pc = pc_start;
dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
dc.lbeg = env->sregs[LBEG];
dc.lend = env->sregs[LEND];
- dc.is_jmp = DISAS_NEXT;
+ dc.base.is_jmp = DISAS_NEXT;
dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG;
dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT;
dc.cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
@@ -1100,14 +1097,14 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
tcg_gen_insn_start(dc.pc);
++insn_count;
gen_exception(&dc, EXCP_YIELD);
- dc.is_jmp = DISAS_NORETURN;
+ dc.base.is_jmp = DISAS_NORETURN;
goto done;
}
if (tb->flags & XTENSA_TBFLAG_EXCEPTION) {
tcg_gen_insn_start(dc.pc);
++insn_count;
gen_exception(&dc, EXCP_DEBUG);
- dc.is_jmp = DISAS_NORETURN;
+ dc.base.is_jmp = DISAS_NORETURN;
goto done;
}
@@ -1118,7 +1115,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) {
tcg_gen_movi_i32(cpu_pc, dc.pc);
gen_exception(&dc, EXCP_DEBUG);
- dc.is_jmp = DISAS_NORETURN;
+ dc.base.is_jmp = DISAS_NORETURN;
/* The address covered by the breakpoint must be included in
[tb->pc, tb->pc + tb->size) in order to for it to be
properly cleared -- thus we increment the PC here so that
@@ -1156,7 +1153,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
gen_exception(&dc, EXCP_DEBUG);
break;
}
- } while (dc.is_jmp == DISAS_NEXT &&
+ } while (dc.base.is_jmp == DISAS_NEXT &&
insn_count < max_insns &&
dc.pc - page_start < TARGET_PAGE_SIZE &&
dc.pc - page_start + xtensa_insn_len(env, &dc) <= TARGET_PAGE_SIZE
@@ -1175,7 +1172,7 @@ done:
gen_io_end();
}
- if (dc.is_jmp == DISAS_NEXT) {
+ if (dc.base.is_jmp == DISAS_NEXT) {
gen_jumpi(&dc, dc.pc, 0);
}
gen_tb_end(tb, insn_count);
@@ -1480,7 +1477,7 @@ static void translate_break(DisasContext *dc, const uint32_t arg[],
static void translate_call0(DisasContext *dc, const uint32_t arg[],
const uint32_t par[])
{
- tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
+ tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next);
gen_jumpi(dc, arg[0], 0);
}
@@ -1498,7 +1495,7 @@ static void translate_callx0(DisasContext *dc, const uint32_t arg[],
if (gen_window_check1(dc, arg[0])) {
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_mov_i32(tmp, cpu_R[arg[0]]);
- tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
+ tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next);
gen_jump(dc, tmp);
tcg_temp_free(tmp);
}
@@ -1700,7 +1697,7 @@ static void translate_l32r(DisasContext *dc, const uint32_t arg[],
if (gen_window_check1(dc, arg[0])) {
TCGv_i32 tmp;
- if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
+ if (dc->base.tb->flags & XTENSA_TBFLAG_LITBASE) {
tmp = tcg_const_i32(dc->raw_arg[1] - 1);
tcg_gen_add_i32(tmp, cpu_SR[LITBASE], tmp);
} else {
@@ -1719,7 +1716,7 @@ static void translate_loop(DisasContext *dc, const uint32_t arg[],
TCGv_i32 tmp = tcg_const_i32(lend);
tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[arg[0]], 1);
- tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc);
+ tcg_gen_movi_i32(cpu_SR[LBEG], dc->base.pc_next);
gen_helper_wsr_lend(cpu_env, tmp);
tcg_temp_free(tmp);
@@ -1730,7 +1727,7 @@ static void translate_loop(DisasContext *dc, const uint32_t arg[],
gen_set_label(label);
}
- gen_jumpi(dc, dc->next_pc, 0);
+ gen_jumpi(dc, dc->base.pc_next, 0);
}
}
--
2.17.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Qemu-devel] [PATCH 3/4] target/xtensa: Change gen_intermediate_code dc to pointer
2018-05-12 17:57 [Qemu-devel] [PATCH 0/4] target/xtensa: Convert to TranslatorOps Richard Henderson
2018-05-12 17:57 ` [Qemu-devel] [PATCH 1/4] target/xtensa: Replace DISAS_UPDATE with DISAS_NORETURN Richard Henderson
2018-05-12 17:57 ` [Qemu-devel] [PATCH 2/4] target/xtensa: Convert to DisasContextBase Richard Henderson
@ 2018-05-12 17:57 ` Richard Henderson
2018-05-12 17:57 ` [Qemu-devel] [PATCH 4/4] target/xtensa: Convert to TranslatorOps Richard Henderson
2018-05-22 9:39 ` [Qemu-devel] [PATCH 0/4] " Max Filippov
4 siblings, 0 replies; 10+ messages in thread
From: Richard Henderson @ 2018-05-12 17:57 UTC (permalink / raw)
To: qemu-devel; +Cc: jcmvbkbc
This will reduce the size of the patch in the next patch,
where the context will have to be a pointer.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/xtensa/translate.c | 122 +++++++++++++++++++-------------------
1 file changed, 61 insertions(+), 61 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index cc48d105e9..45f32dc71f 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -1051,7 +1051,7 @@ static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
{
CPUXtensaState *env = cs->env_ptr;
- DisasContext dc;
+ DisasContext dc1, *dc = &dc1;
int insn_count = 0;
int max_insns = tb_cflags(tb) & CF_COUNT_MASK;
uint32_t pc_start = tb->pc;
@@ -1064,63 +1064,63 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
max_insns = TCG_MAX_INSNS;
}
- dc.config = env->config;
- dc.base.singlestep_enabled = cs->singlestep_enabled;
- dc.base.tb = tb;
- dc.pc = pc_start;
- dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
- dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
- dc.lbeg = env->sregs[LBEG];
- dc.lend = env->sregs[LEND];
- dc.base.is_jmp = DISAS_NEXT;
- dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG;
- dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT;
- dc.cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
+ dc->config = env->config;
+ dc->base.singlestep_enabled = cs->singlestep_enabled;
+ dc->base.tb = tb;
+ dc->pc = pc_start;
+ dc->ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
+ dc->cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring;
+ dc->lbeg = env->sregs[LBEG];
+ dc->lend = env->sregs[LEND];
+ dc->base.is_jmp = DISAS_NEXT;
+ dc->debug = tb->flags & XTENSA_TBFLAG_DEBUG;
+ dc->icount = tb->flags & XTENSA_TBFLAG_ICOUNT;
+ dc->cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
XTENSA_TBFLAG_CPENABLE_SHIFT;
- dc.window = ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >>
+ dc->window = ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >>
XTENSA_TBFLAG_WINDOW_SHIFT);
- if (dc.config->isa) {
- dc.insnbuf = xtensa_insnbuf_alloc(dc.config->isa);
- dc.slotbuf = xtensa_insnbuf_alloc(dc.config->isa);
+ if (dc->config->isa) {
+ dc->insnbuf = xtensa_insnbuf_alloc(dc->config->isa);
+ dc->slotbuf = xtensa_insnbuf_alloc(dc->config->isa);
}
- init_sar_tracker(&dc);
- if (dc.icount) {
- dc.next_icount = tcg_temp_local_new_i32();
+ init_sar_tracker(dc);
+ if (dc->icount) {
+ dc->next_icount = tcg_temp_local_new_i32();
}
gen_tb_start(tb);
if ((tb_cflags(tb) & CF_USE_ICOUNT) &&
(tb->flags & XTENSA_TBFLAG_YIELD)) {
- tcg_gen_insn_start(dc.pc);
+ tcg_gen_insn_start(dc->pc);
++insn_count;
- gen_exception(&dc, EXCP_YIELD);
- dc.base.is_jmp = DISAS_NORETURN;
+ gen_exception(dc, EXCP_YIELD);
+ dc->base.is_jmp = DISAS_NORETURN;
goto done;
}
if (tb->flags & XTENSA_TBFLAG_EXCEPTION) {
- tcg_gen_insn_start(dc.pc);
+ tcg_gen_insn_start(dc->pc);
++insn_count;
- gen_exception(&dc, EXCP_DEBUG);
- dc.base.is_jmp = DISAS_NORETURN;
+ gen_exception(dc, EXCP_DEBUG);
+ dc->base.is_jmp = DISAS_NORETURN;
goto done;
}
do {
- tcg_gen_insn_start(dc.pc);
+ tcg_gen_insn_start(dc->pc);
++insn_count;
- if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) {
- tcg_gen_movi_i32(cpu_pc, dc.pc);
- gen_exception(&dc, EXCP_DEBUG);
- dc.base.is_jmp = DISAS_NORETURN;
+ if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
+ tcg_gen_movi_i32(cpu_pc, dc->pc);
+ gen_exception(dc, EXCP_DEBUG);
+ dc->base.is_jmp = DISAS_NORETURN;
/* The address covered by the breakpoint must be included in
[tb->pc, tb->pc + tb->size) in order to for it to be
properly cleared -- thus we increment the PC here so that
the logic setting tb->size below does the right thing. */
- dc.pc += 2;
+ dc->pc += 2;
break;
}
@@ -1128,52 +1128,52 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
gen_io_start();
}
- if (dc.icount) {
+ if (dc->icount) {
TCGLabel *label = gen_new_label();
- tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1);
- tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label);
- tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]);
- if (dc.debug) {
- gen_debug_exception(&dc, DEBUGCAUSE_IC);
+ tcg_gen_addi_i32(dc->next_icount, cpu_SR[ICOUNT], 1);
+ tcg_gen_brcondi_i32(TCG_COND_NE, dc->next_icount, 0, label);
+ tcg_gen_mov_i32(dc->next_icount, cpu_SR[ICOUNT]);
+ if (dc->debug) {
+ gen_debug_exception(dc, DEBUGCAUSE_IC);
}
gen_set_label(label);
}
- if (dc.debug) {
- gen_ibreak_check(env, &dc);
+ if (dc->debug) {
+ gen_ibreak_check(env, dc);
}
- disas_xtensa_insn(env, &dc);
- if (dc.icount) {
- tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
+ disas_xtensa_insn(env, dc);
+ if (dc->icount) {
+ tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
}
- if (cs->singlestep_enabled) {
- tcg_gen_movi_i32(cpu_pc, dc.pc);
- gen_exception(&dc, EXCP_DEBUG);
+ if (dc->base.singlestep_enabled) {
+ tcg_gen_movi_i32(cpu_pc, dc->pc);
+ gen_exception(dc, EXCP_DEBUG);
break;
}
- } while (dc.base.is_jmp == DISAS_NEXT &&
- insn_count < max_insns &&
- dc.pc - page_start < TARGET_PAGE_SIZE &&
- dc.pc - page_start + xtensa_insn_len(env, &dc) <= TARGET_PAGE_SIZE
- && !tcg_op_buf_full());
+ } while (dc->base.is_jmp == DISAS_NEXT &&
+ insn_count < max_insns &&
+ dc->pc - page_start < TARGET_PAGE_SIZE &&
+ dc->pc - page_start + xtensa_insn_len(env, dc) <= TARGET_PAGE_SIZE
+ && !tcg_op_buf_full());
done:
- reset_sar_tracker(&dc);
- if (dc.icount) {
- tcg_temp_free(dc.next_icount);
+ reset_sar_tracker(dc);
+ if (dc->icount) {
+ tcg_temp_free(dc->next_icount);
}
- if (dc.config->isa) {
- xtensa_insnbuf_free(dc.config->isa, dc.insnbuf);
- xtensa_insnbuf_free(dc.config->isa, dc.slotbuf);
+ if (dc->config->isa) {
+ xtensa_insnbuf_free(dc->config->isa, dc->insnbuf);
+ xtensa_insnbuf_free(dc->config->isa, dc->slotbuf);
}
if (tb_cflags(tb) & CF_LAST_IO) {
gen_io_end();
}
- if (dc.base.is_jmp == DISAS_NEXT) {
- gen_jumpi(&dc, dc.pc, 0);
+ if (dc->base.is_jmp == DISAS_NEXT) {
+ gen_jumpi(dc, dc->pc, 0);
}
gen_tb_end(tb, insn_count);
@@ -1183,12 +1183,12 @@ done:
qemu_log_lock();
qemu_log("----------------\n");
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, dc.pc - pc_start);
+ log_target_disas(cs, pc_start, dc->pc - pc_start);
qemu_log("\n");
qemu_log_unlock();
}
#endif
- tb->size = dc.pc - pc_start;
+ tb->size = dc->pc - pc_start;
tb->icount = insn_count;
}
--
2.17.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Qemu-devel] [PATCH 4/4] target/xtensa: Convert to TranslatorOps
2018-05-12 17:57 [Qemu-devel] [PATCH 0/4] target/xtensa: Convert to TranslatorOps Richard Henderson
` (2 preceding siblings ...)
2018-05-12 17:57 ` [Qemu-devel] [PATCH 3/4] target/xtensa: Change gen_intermediate_code dc to pointer Richard Henderson
@ 2018-05-12 17:57 ` Richard Henderson
2018-05-13 17:25 ` Max Filippov
2018-05-13 18:37 ` Max Filippov
2018-05-22 9:39 ` [Qemu-devel] [PATCH 0/4] " Max Filippov
4 siblings, 2 replies; 10+ messages in thread
From: Richard Henderson @ 2018-05-12 17:57 UTC (permalink / raw)
To: qemu-devel; +Cc: jcmvbkbc
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/xtensa/translate.c | 229 ++++++++++++++++++++------------------
1 file changed, 122 insertions(+), 107 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 45f32dc71f..9de45e4be4 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -1048,148 +1048,163 @@ static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
}
}
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
+static void xtensa_tr_init_disas_context(DisasContextBase *dcbase,
+ CPUState *cpu)
{
- CPUXtensaState *env = cs->env_ptr;
- DisasContext dc1, *dc = &dc1;
- int insn_count = 0;
- int max_insns = tb_cflags(tb) & CF_COUNT_MASK;
- uint32_t pc_start = tb->pc;
- uint32_t page_start = pc_start & TARGET_PAGE_MASK;
-
- if (max_insns == 0) {
- max_insns = CF_COUNT_MASK;
- }
- if (max_insns > TCG_MAX_INSNS) {
- max_insns = TCG_MAX_INSNS;
- }
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
+ CPUXtensaState *env = cpu->env_ptr;
+ uint32_t tb_flags = dc->base.tb->flags;
dc->config = env->config;
- dc->base.singlestep_enabled = cs->singlestep_enabled;
- dc->base.tb = tb;
- dc->pc = pc_start;
- dc->ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
- dc->cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring;
+ dc->pc = dc->base.pc_first;
+ dc->ring = tb_flags & XTENSA_TBFLAG_RING_MASK;
+ dc->cring = (tb_flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring;
dc->lbeg = env->sregs[LBEG];
dc->lend = env->sregs[LEND];
- dc->base.is_jmp = DISAS_NEXT;
- dc->debug = tb->flags & XTENSA_TBFLAG_DEBUG;
- dc->icount = tb->flags & XTENSA_TBFLAG_ICOUNT;
- dc->cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
+ dc->debug = tb_flags & XTENSA_TBFLAG_DEBUG;
+ dc->icount = tb_flags & XTENSA_TBFLAG_ICOUNT;
+ dc->cpenable = (tb_flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
XTENSA_TBFLAG_CPENABLE_SHIFT;
- dc->window = ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >>
+ dc->window = ((tb_flags & XTENSA_TBFLAG_WINDOW_MASK) >>
XTENSA_TBFLAG_WINDOW_SHIFT);
if (dc->config->isa) {
dc->insnbuf = xtensa_insnbuf_alloc(dc->config->isa);
dc->slotbuf = xtensa_insnbuf_alloc(dc->config->isa);
}
-
init_sar_tracker(dc);
+}
+
+static void xtensa_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
+
if (dc->icount) {
dc->next_icount = tcg_temp_local_new_i32();
}
+}
- gen_tb_start(tb);
+static void xtensa_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
+{
+ tcg_gen_insn_start(dcbase->pc_next);
+}
- if ((tb_cflags(tb) & CF_USE_ICOUNT) &&
- (tb->flags & XTENSA_TBFLAG_YIELD)) {
- tcg_gen_insn_start(dc->pc);
- ++insn_count;
+static bool xtensa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
+ const CPUBreakpoint *bp)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
+
+ tcg_gen_movi_i32(cpu_pc, dc->base.pc_next);
+ gen_exception(dc, EXCP_DEBUG);
+ dc->base.is_jmp = DISAS_NORETURN;
+ /* The address covered by the breakpoint must be included in
+ [tb->pc, tb->pc + tb->size) in order to for it to be
+ properly cleared -- thus we increment the PC here so that
+ the logic setting tb->size below does the right thing. */
+ dc->base.pc_next += 2;
+ return true;
+}
+
+static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
+ CPUXtensaState *env = cpu->env_ptr;
+ target_ulong page_start;
+
+ /* These two conditions only apply to the first insn in the TB,
+ but this is the first TranslateOps hook that allows exiting. */
+ if ((tb_cflags(dc->base.tb) & CF_USE_ICOUNT)
+ && (dc->base.tb->flags & XTENSA_TBFLAG_YIELD)) {
gen_exception(dc, EXCP_YIELD);
dc->base.is_jmp = DISAS_NORETURN;
- goto done;
+ return;
}
- if (tb->flags & XTENSA_TBFLAG_EXCEPTION) {
- tcg_gen_insn_start(dc->pc);
- ++insn_count;
+ if (dc->base.tb->flags & XTENSA_TBFLAG_EXCEPTION) {
gen_exception(dc, EXCP_DEBUG);
dc->base.is_jmp = DISAS_NORETURN;
- goto done;
+ return;
}
- do {
- tcg_gen_insn_start(dc->pc);
- ++insn_count;
-
- if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
- tcg_gen_movi_i32(cpu_pc, dc->pc);
- gen_exception(dc, EXCP_DEBUG);
- dc->base.is_jmp = DISAS_NORETURN;
- /* The address covered by the breakpoint must be included in
- [tb->pc, tb->pc + tb->size) in order to for it to be
- properly cleared -- thus we increment the PC here so that
- the logic setting tb->size below does the right thing. */
- dc->pc += 2;
- break;
- }
-
- if (insn_count == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
- gen_io_start();
- }
-
- if (dc->icount) {
- TCGLabel *label = gen_new_label();
-
- tcg_gen_addi_i32(dc->next_icount, cpu_SR[ICOUNT], 1);
- tcg_gen_brcondi_i32(TCG_COND_NE, dc->next_icount, 0, label);
- tcg_gen_mov_i32(dc->next_icount, cpu_SR[ICOUNT]);
- if (dc->debug) {
- gen_debug_exception(dc, DEBUGCAUSE_IC);
- }
- gen_set_label(label);
- }
-
- if (dc->debug) {
- gen_ibreak_check(env, dc);
- }
-
- disas_xtensa_insn(env, dc);
- if (dc->icount) {
- tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
- }
- if (dc->base.singlestep_enabled) {
- tcg_gen_movi_i32(cpu_pc, dc->pc);
- gen_exception(dc, EXCP_DEBUG);
- break;
- }
- } while (dc->base.is_jmp == DISAS_NEXT &&
- insn_count < max_insns &&
- dc->pc - page_start < TARGET_PAGE_SIZE &&
- dc->pc - page_start + xtensa_insn_len(env, dc) <= TARGET_PAGE_SIZE
- && !tcg_op_buf_full());
-done:
- reset_sar_tracker(dc);
if (dc->icount) {
- tcg_temp_free(dc->next_icount);
+ TCGLabel *label = gen_new_label();
+
+ tcg_gen_addi_i32(dc->next_icount, cpu_SR[ICOUNT], 1);
+ tcg_gen_brcondi_i32(TCG_COND_NE, dc->next_icount, 0, label);
+ tcg_gen_mov_i32(dc->next_icount, cpu_SR[ICOUNT]);
+ if (dc->debug) {
+ gen_debug_exception(dc, DEBUGCAUSE_IC);
+ }
+ gen_set_label(label);
}
+
+ if (dc->debug) {
+ gen_ibreak_check(env, dc);
+ }
+
+ disas_xtensa_insn(env, dc);
+
+ if (dc->icount) {
+ tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
+ }
+
+ /* End the TB if the next insn will cross into the next page. */
+ page_start = dc->base.pc_first & TARGET_PAGE_MASK;
+ if (dc->base.is_jmp == DISAS_NEXT &&
+ dc->pc - page_start < TARGET_PAGE_SIZE &&
+ dc->pc - page_start + xtensa_insn_len(env, dc) <= TARGET_PAGE_SIZE) {
+ dc->base.is_jmp = DISAS_TOO_MANY;
+ }
+}
+
+static void xtensa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
+
+ reset_sar_tracker(dc);
if (dc->config->isa) {
xtensa_insnbuf_free(dc->config->isa, dc->insnbuf);
xtensa_insnbuf_free(dc->config->isa, dc->slotbuf);
}
-
- if (tb_cflags(tb) & CF_LAST_IO) {
- gen_io_end();
+ if (dc->icount) {
+ tcg_temp_free(dc->next_icount);
}
- if (dc->base.is_jmp == DISAS_NEXT) {
- gen_jumpi(dc, dc->pc, 0);
+ switch (dc->base.is_jmp) {
+ case DISAS_NORETURN:
+ break;
+ case DISAS_TOO_MANY:
+ if (dc->base.singlestep_enabled) {
+ tcg_gen_movi_i32(cpu_pc, dc->pc);
+ gen_exception(dc, EXCP_DEBUG);
+ } else {
+ gen_jumpi(dc, dc->pc, 0);
+ }
+ break;
+ default:
+ g_assert_not_reached();
}
- gen_tb_end(tb, insn_count);
+}
-#ifdef DEBUG_DISAS
- if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
- && qemu_log_in_addr_range(pc_start)) {
- qemu_log_lock();
- qemu_log("----------------\n");
- qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, dc->pc - pc_start);
- qemu_log("\n");
- qemu_log_unlock();
- }
-#endif
- tb->size = dc->pc - pc_start;
- tb->icount = insn_count;
+static void xtensa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
+{
+ qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
+ log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
+}
+
+static const TranslatorOps xtensa_translator_ops = {
+ .init_disas_context = xtensa_tr_init_disas_context,
+ .tb_start = xtensa_tr_tb_start,
+ .insn_start = xtensa_tr_insn_start,
+ .breakpoint_check = xtensa_tr_breakpoint_check,
+ .translate_insn = xtensa_tr_translate_insn,
+ .tb_stop = xtensa_tr_tb_stop,
+ .disas_log = xtensa_tr_disas_log,
+};
+
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
+{
+ DisasContext dc = {};
+ translator_loop(&xtensa_translator_ops, &dc.base, cpu, tb);
}
void xtensa_cpu_dump_state(CPUState *cs, FILE *f,
--
2.17.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PATCH 4/4] target/xtensa: Convert to TranslatorOps
2018-05-12 17:57 ` [Qemu-devel] [PATCH 4/4] target/xtensa: Convert to TranslatorOps Richard Henderson
@ 2018-05-13 17:25 ` Max Filippov
2018-05-13 18:37 ` Max Filippov
1 sibling, 0 replies; 10+ messages in thread
From: Max Filippov @ 2018-05-13 17:25 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Sat, May 12, 2018 at 10:57 AM, Richard Henderson
<richard.henderson@linaro.org> wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/xtensa/translate.c | 229 ++++++++++++++++++++------------------
> 1 file changed, 122 insertions(+), 107 deletions(-)
This patch breaks tests/tcg/xtensa/test_mmu.S cross_page_tb test.
Looking at it...
--
Thanks.
-- Max
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PATCH 4/4] target/xtensa: Convert to TranslatorOps
2018-05-12 17:57 ` [Qemu-devel] [PATCH 4/4] target/xtensa: Convert to TranslatorOps Richard Henderson
2018-05-13 17:25 ` Max Filippov
@ 2018-05-13 18:37 ` Max Filippov
1 sibling, 0 replies; 10+ messages in thread
From: Max Filippov @ 2018-05-13 18:37 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Sat, May 12, 2018 at 10:57 AM, Richard Henderson
<richard.henderson@linaro.org> wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/xtensa/translate.c | 229 ++++++++++++++++++++------------------
> 1 file changed, 122 insertions(+), 107 deletions(-)
[...]
> - } while (dc->base.is_jmp == DISAS_NEXT &&
> - insn_count < max_insns &&
> - dc->pc - page_start < TARGET_PAGE_SIZE &&
> - dc->pc - page_start + xtensa_insn_len(env, dc) <= TARGET_PAGE_SIZE
> - && !tcg_op_buf_full());
> -done:
[...]
> + /* End the TB if the next insn will cross into the next page. */
> + page_start = dc->base.pc_first & TARGET_PAGE_MASK;
> + if (dc->base.is_jmp == DISAS_NEXT &&
> + dc->pc - page_start < TARGET_PAGE_SIZE &&
> + dc->pc - page_start + xtensa_insn_len(env, dc) <= TARGET_PAGE_SIZE) {
Originally it was the condition to continue translation.
To end the TB when the next instruction will cross into the next page the
condition must be changed to something like
if (dc->base.is_jmp == DISAS_NEXT &&
(dc->pc - page_start >= TARGET_PAGE_SIZE ||
dc->pc - page_start + xtensa_insn_len(env, dc) > TARGET_PAGE_SIZE)) {
With that change all tests in tests/tcg/xtensa are passing.
I'll play with it some more...
--
Thanks.
-- Max
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PATCH 0/4] target/xtensa: Convert to TranslatorOps
2018-05-12 17:57 [Qemu-devel] [PATCH 0/4] target/xtensa: Convert to TranslatorOps Richard Henderson
` (3 preceding siblings ...)
2018-05-12 17:57 ` [Qemu-devel] [PATCH 4/4] target/xtensa: Convert to TranslatorOps Richard Henderson
@ 2018-05-22 9:39 ` Max Filippov
2018-05-22 20:58 ` Richard Henderson
4 siblings, 1 reply; 10+ messages in thread
From: Max Filippov @ 2018-05-22 9:39 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
Hi Richard,
On Sat, May 12, 2018 at 10:57 AM, Richard Henderson
<richard.henderson@linaro.org> wrote:
> I have one xtensa image against which to test this.
> There are enough options going on here in the xtensa
> frontend that this probably needs a better work-out.
>
>
> r~
>
>
> Richard Henderson (4):
> target/xtensa: Replace DISAS_UPDATE with DISAS_NORETURN
> target/xtensa: Convert to DisasContextBase
> target/xtensa: Change gen_intermediate_code dc to pointer
> target/xtensa: Convert to TranslatorOps
>
> target/xtensa/translate.c | 345 +++++++++++++++++++-------------------
> 1 file changed, 177 insertions(+), 168 deletions(-)
With the change that I've mentioned in response to 4/4:
Tested-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
for the series.
Would you like to do that change and carry the series yourself
or should I take it?
--
Thanks.
-- Max
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PATCH 0/4] target/xtensa: Convert to TranslatorOps
2018-05-22 9:39 ` [Qemu-devel] [PATCH 0/4] " Max Filippov
@ 2018-05-22 20:58 ` Richard Henderson
2018-05-23 8:36 ` Max Filippov
0 siblings, 1 reply; 10+ messages in thread
From: Richard Henderson @ 2018-05-22 20:58 UTC (permalink / raw)
To: Max Filippov; +Cc: qemu-devel
On 05/22/2018 02:39 AM, Max Filippov wrote:
> With the change that I've mentioned in response to 4/4:
> Tested-by: Max Filippov <jcmvbkbc@gmail.com>
> Acked-by: Max Filippov <jcmvbkbc@gmail.com>
> for the series.
Thanks.
> Would you like to do that change and carry the series yourself
> or should I take it?
Would you take it, please.
r~
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PATCH 0/4] target/xtensa: Convert to TranslatorOps
2018-05-22 20:58 ` Richard Henderson
@ 2018-05-23 8:36 ` Max Filippov
0 siblings, 0 replies; 10+ messages in thread
From: Max Filippov @ 2018-05-23 8:36 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Tue, May 22, 2018 at 1:58 PM, Richard Henderson
<richard.henderson@linaro.org> wrote:
> On 05/22/2018 02:39 AM, Max Filippov wrote:
>> Would you like to do that change and carry the series yourself
>> or should I take it?
>
> Would you take it, please.
Sure.
--
Thanks.
-- Max
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2018-05-23 8:36 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-05-12 17:57 [Qemu-devel] [PATCH 0/4] target/xtensa: Convert to TranslatorOps Richard Henderson
2018-05-12 17:57 ` [Qemu-devel] [PATCH 1/4] target/xtensa: Replace DISAS_UPDATE with DISAS_NORETURN Richard Henderson
2018-05-12 17:57 ` [Qemu-devel] [PATCH 2/4] target/xtensa: Convert to DisasContextBase Richard Henderson
2018-05-12 17:57 ` [Qemu-devel] [PATCH 3/4] target/xtensa: Change gen_intermediate_code dc to pointer Richard Henderson
2018-05-12 17:57 ` [Qemu-devel] [PATCH 4/4] target/xtensa: Convert to TranslatorOps Richard Henderson
2018-05-13 17:25 ` Max Filippov
2018-05-13 18:37 ` Max Filippov
2018-05-22 9:39 ` [Qemu-devel] [PATCH 0/4] " Max Filippov
2018-05-22 20:58 ` Richard Henderson
2018-05-23 8:36 ` Max Filippov
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