From: Max Filippov <jcmvbkbc@gmail.com>
To: Thomas Huth <thuth@redhat.com>
Cc: "Alex Bennée" <alex.bennee@linaro.org>,
"Marcel Apfelbaum" <marcel@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
qemu-devel <qemu-devel@nongnu.org>,
"Eduardo Habkost" <ehabkost@redhat.com>
Subject: Re: [Qemu-devel] [RFC PATCH] hw/core: expand description of null-machine
Date: Thu, 26 Apr 2018 11:55:32 -0700 [thread overview]
Message-ID: <CAMo8BfKJwZOCaQrSCnFMVNy=L8Z0yo7sAw3q5Sfaof-ko_+NjQ@mail.gmail.com> (raw)
In-Reply-To: <2f69532c-8651-ef67-0910-1fad91808608@redhat.com>
On Thu, Apr 26, 2018 at 11:18 AM, Thomas Huth <thuth@redhat.com> wrote:
> On 26.04.2018 18:09, Alex Bennée wrote:
>> Thomas Huth <thuth@redhat.com> writes:
>>> Actually, with certain CPUs, you can really use the "none" machine as a
>>> pure instruction set testing system. For example, on m68k, there used to
>>> be an explicit "dummy" machine for this job, and we removed it in favour
>>> of the "none" machine:
>>>
>>> https://git.qemu.org/?p=qemu.git;a=commitdiff;h=22f2dbe7eaf3e12e38c9c210
>>
>> Ahh OK. Do you know what other CPUs can be used in this way?
>
> I think it should be possible with at least all the boards that have a
> "sim" machine, e.g. xtensa, mips, moxie and openrisc.
xtensa sim machine is a bit more than just instruction simulator:
it instantiates CPU-configuration-specific local memories. It is meant
to be compatible with Xtensa ISS from Xtensa development tools.
--
Thanks.
-- Max
prev parent reply other threads:[~2018-04-26 18:55 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-25 15:33 [Qemu-devel] [RFC PATCH] hw/core: expand description of null-machine Alex Bennée
2018-04-25 15:52 ` Thomas Huth
2018-04-26 16:09 ` Alex Bennée
2018-04-26 18:18 ` Thomas Huth
2018-04-26 18:31 ` Peter Maydell
2018-04-26 18:44 ` Alex Bennée
2018-04-26 18:53 ` Thomas Huth
2018-05-03 19:29 ` Eduardo Habkost
2018-04-26 18:55 ` Max Filippov [this message]
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