* [U-Boot] [PATCH v4 01/12] m68k: add basic set of devicetrees
@ 2018-12-16 11:22 Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 02/12] m68k: architecture changes to support fdt Angelo Dureghello
` (10 more replies)
0 siblings, 11 replies; 15+ messages in thread
From: Angelo Dureghello @ 2018-12-16 11:22 UTC (permalink / raw)
To: u-boot
This patch adds a basic group of devicetrees, one for each
cpu family, including actually just uart and dspi devices,
since these are the drivers supporting devicetree (support
added in this patch-set).
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
---
Changes for v2:
- add mcf54xx.dtsi and mcf537x.dtsi
Changes for v3:
- none
Changes for v4:
- none
---
arch/m68k/dts/mcf5208.dtsi | 36 ++++++++
arch/m68k/dts/mcf5227x.dtsi | 48 ++++++++++
arch/m68k/dts/mcf523x.dtsi | 44 ++++++++++
arch/m68k/dts/mcf5249.dtsi | 38 ++++++++
arch/m68k/dts/mcf5253.dtsi | 44 ++++++++++
arch/m68k/dts/mcf5271.dtsi | 44 ++++++++++
arch/m68k/dts/mcf5272.dtsi | 38 ++++++++
arch/m68k/dts/mcf5275.dtsi | 44 ++++++++++
arch/m68k/dts/mcf5282.dtsi | 44 ++++++++++
arch/m68k/dts/mcf5301x.dtsi | 48 ++++++++++
arch/m68k/dts/mcf5307.dtsi | 39 +++++++++
arch/m68k/dts/mcf5329.dtsi | 36 ++++++++
arch/m68k/dts/mcf537x.dtsi | 36 ++++++++
arch/m68k/dts/mcf5441x.dtsi | 87 +++++++++++++++++++
arch/m68k/dts/mcf5445x.dtsi | 48 ++++++++++
arch/m68k/dts/mcf54xx.dtsi | 40 +++++++++
doc/device-tree-bindings/serial/mcf-uart.txt | 19 ++++
doc/device-tree-bindings/spi/spi-mcf-dspi.txt | 30 +++++++
18 files changed, 763 insertions(+)
create mode 100644 arch/m68k/dts/mcf5208.dtsi
create mode 100644 arch/m68k/dts/mcf5227x.dtsi
create mode 100644 arch/m68k/dts/mcf523x.dtsi
create mode 100644 arch/m68k/dts/mcf5249.dtsi
create mode 100644 arch/m68k/dts/mcf5253.dtsi
create mode 100644 arch/m68k/dts/mcf5271.dtsi
create mode 100644 arch/m68k/dts/mcf5272.dtsi
create mode 100644 arch/m68k/dts/mcf5275.dtsi
create mode 100644 arch/m68k/dts/mcf5282.dtsi
create mode 100644 arch/m68k/dts/mcf5301x.dtsi
create mode 100644 arch/m68k/dts/mcf5307.dtsi
create mode 100644 arch/m68k/dts/mcf5329.dtsi
create mode 100644 arch/m68k/dts/mcf537x.dtsi
create mode 100644 arch/m68k/dts/mcf5441x.dtsi
create mode 100644 arch/m68k/dts/mcf5445x.dtsi
create mode 100644 arch/m68k/dts/mcf54xx.dtsi
create mode 100644 doc/device-tree-bindings/serial/mcf-uart.txt
create mode 100644 doc/device-tree-bindings/spi/spi-mcf-dspi.txt
diff --git a/arch/m68k/dts/mcf5208.dtsi b/arch/m68k/dts/mcf5208.dtsi
new file mode 100644
index 0000000000..558d8bf41a
--- /dev/null
+++ b/arch/m68k/dts/mcf5208.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5208";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart at fc060000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc060000 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart at fc064000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc064000 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart at fc068000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc068000 0x40>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/m68k/dts/mcf5227x.dtsi b/arch/m68k/dts/mcf5227x.dtsi
new file mode 100644
index 0000000000..8c95edddb6
--- /dev/null
+++ b/arch/m68k/dts/mcf5227x.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5227x";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &dspi0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart at fc060000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc060000 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart at fc064000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc064000 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart at fc068000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc068000 0x40>;
+ status = "disabled";
+ };
+
+ dspi0: dspi at fc05c000 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfc05c000 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/m68k/dts/mcf523x.dtsi b/arch/m68k/dts/mcf523x.dtsi
new file mode 100644
index 0000000000..9e79d472ec
--- /dev/null
+++ b/arch/m68k/dts/mcf523x.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf523x";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ipsbar: ipsbar at 4000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x40000000 0x40000000>;
+ reg = <0x40000000 0x40000000>;
+
+ uart0: uart at 200 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x200 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart at 240 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x240 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart at 280 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x280 0x40>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/m68k/dts/mcf5249.dtsi b/arch/m68k/dts/mcf5249.dtsi
new file mode 100644
index 0000000000..248b3dc68b
--- /dev/null
+++ b/arch/m68k/dts/mcf5249.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5249";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mbar: mbar at 10000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x10000000 0x10000>;
+ reg = <0x10000000 0x10000>;
+
+ uart0: uart at 1c0 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x1c0 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart at 200 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x200 0x40>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/m68k/dts/mcf5253.dtsi b/arch/m68k/dts/mcf5253.dtsi
new file mode 100644
index 0000000000..3bde2d6202
--- /dev/null
+++ b/arch/m68k/dts/mcf5253.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5253";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mbar: mbar at 10000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x10000000 0x10000>;
+ reg = <0x10000000 0x10000>;
+
+ uart0: uart at 1c0 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x1c0 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart at 200 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x200 0x40>;
+ status = "disabled";
+ };
+
+ uart3: uart at c00 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xc00 0x40>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/m68k/dts/mcf5271.dtsi b/arch/m68k/dts/mcf5271.dtsi
new file mode 100644
index 0000000000..29355528d0
--- /dev/null
+++ b/arch/m68k/dts/mcf5271.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5271";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ipsbar: ipsbar at 4000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x40000000 0x40000000>;
+ reg = <0x40000000 0x40000000>;
+
+ uart0: uart at 200 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x200 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart at 240 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x240 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart at 280 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x280 0x40>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/m68k/dts/mcf5272.dtsi b/arch/m68k/dts/mcf5272.dtsi
new file mode 100644
index 0000000000..a56117728b
--- /dev/null
+++ b/arch/m68k/dts/mcf5272.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5272";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mbar: mbar at 10000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x10000000 0x10000>;
+ reg = <0x10000000 0x10000>;
+
+ uart0: uart at 100 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x100 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart at 140 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x140 0x40>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/m68k/dts/mcf5275.dtsi b/arch/m68k/dts/mcf5275.dtsi
new file mode 100644
index 0000000000..b375609d4a
--- /dev/null
+++ b/arch/m68k/dts/mcf5275.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5275";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ipsbar: ipsbar at 4000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x40000000 0x40000000>;
+ reg = <0x40000000 0x40000000>;
+
+ uart0: uart at 200 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x200 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart at 240 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x240 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart at 280 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x280 0x40>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/m68k/dts/mcf5282.dtsi b/arch/m68k/dts/mcf5282.dtsi
new file mode 100644
index 0000000000..3ad1be7bb5
--- /dev/null
+++ b/arch/m68k/dts/mcf5282.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5282";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ipsbar: ipsbar at 4000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x40000000 0x40000000>;
+ reg = <0x40000000 0x40000000>;
+
+ uart0: uart at 200 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x200 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart at 240 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x240 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart at 280 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x280 0x40>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/m68k/dts/mcf5301x.dtsi b/arch/m68k/dts/mcf5301x.dtsi
new file mode 100644
index 0000000000..0891e4dfd5
--- /dev/null
+++ b/arch/m68k/dts/mcf5301x.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5301x";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &dspi0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart at fc060000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc060000 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart at fc064000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc064000 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart at fc068000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc068000 0x40>;
+ status = "disabled";
+ };
+
+ dspi0: dspi at fc05c000 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfc05c000 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/m68k/dts/mcf5307.dtsi b/arch/m68k/dts/mcf5307.dtsi
new file mode 100644
index 0000000000..e199cf9991
--- /dev/null
+++ b/arch/m68k/dts/mcf5307.dtsi
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5307";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* MBAR */
+ mbar: mbar at 10000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x10000000 0x10000>;
+ reg = <0x10000000 0x10000>;
+
+ uart0: uart at 1c0 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x1c0 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart at 200 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x200 0x40>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/m68k/dts/mcf5329.dtsi b/arch/m68k/dts/mcf5329.dtsi
new file mode 100644
index 0000000000..aeaa6430af
--- /dev/null
+++ b/arch/m68k/dts/mcf5329.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5329";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart at fc060000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc060000 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart at fc064000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc064000 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart at fc068000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc068000 0x40>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/m68k/dts/mcf537x.dtsi b/arch/m68k/dts/mcf537x.dtsi
new file mode 100644
index 0000000000..aeaa6430af
--- /dev/null
+++ b/arch/m68k/dts/mcf537x.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5329";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart at fc060000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc060000 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart at fc064000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc064000 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart at fc068000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc068000 0x40>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/m68k/dts/mcf5441x.dtsi b/arch/m68k/dts/mcf5441x.dtsi
new file mode 100644
index 0000000000..71b392adc3
--- /dev/null
+++ b/arch/m68k/dts/mcf5441x.dtsi
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5441x";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &dspi0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart at fc060000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc060000 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart at fc064000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc064000 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart at fc068000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc068000 0x40>;
+ status = "disabled";
+ };
+
+ uart3: uart at fc06c000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc06c000 0x40>;
+ status = "disabled";
+ };
+
+ dspi0: dspi at fc05c000 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfc05c000 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ status = "disabled";
+ };
+
+ dspi1: dspi at fc03c000 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfc03c000 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ status = "disabled";
+ };
+
+ dspi2: dspi at ec038000 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xec038000 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ status = "disabled";
+ };
+
+ dspi3: dspi at ec03c000 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xec03c00 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/m68k/dts/mcf5445x.dtsi b/arch/m68k/dts/mcf5445x.dtsi
new file mode 100644
index 0000000000..ccbee29a6c
--- /dev/null
+++ b/arch/m68k/dts/mcf5445x.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5445x";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &dspi0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart at fc060000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc060000 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart at fc064000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc064000 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart at fc068000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc068000 0x40>;
+ status = "disabled";
+ };
+
+ dspi0: dspi at fc05c000 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfc05c000 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/m68k/dts/mcf54xx.dtsi b/arch/m68k/dts/mcf54xx.dtsi
new file mode 100644
index 0000000000..537bb424f3
--- /dev/null
+++ b/arch/m68k/dts/mcf54xx.dtsi
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf54x5";
+
+ aliases {
+ /* TO DO, clarify on serial, this SoC seems to have SPC and
+ * no UARTS.
+ */
+ spi0 = &dspi0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mbar: mbar at 80000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x80000000 0x10000>;
+ reg = <0x80000000 0x10000>;
+
+ dspi0: dspi at 8a00 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x8a00 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/doc/device-tree-bindings/serial/mcf-uart.txt b/doc/device-tree-bindings/serial/mcf-uart.txt
new file mode 100644
index 0000000000..d73f764c01
--- /dev/null
+++ b/doc/device-tree-bindings/serial/mcf-uart.txt
@@ -0,0 +1,19 @@
+Freescale ColdFire UART
+
+Required properties:
+- compatible : should be "fsl,mcf-uart"
+- reg: start address and size of the registers
+
+Example:
+
+soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart at fc060000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc060000 0x40>;
+ status = "disabled";
+ };
+};
diff --git a/doc/device-tree-bindings/spi/spi-mcf-dspi.txt b/doc/device-tree-bindings/spi/spi-mcf-dspi.txt
new file mode 100644
index 0000000000..860eb8ac85
--- /dev/null
+++ b/doc/device-tree-bindings/spi/spi-mcf-dspi.txt
@@ -0,0 +1,30 @@
+Freescale ColdFire DSPI controller
+
+Required properties:
+- compatible : "fsl,mcf-dspi"
+- #address-cells: <1>, as required by generic SPI binding
+- #size-cells: <0>, also as required by generic SPI binding
+- reg : offset and length of the register set for the device
+
+Optional properties:
+- spi-max-frequency : max supported spi frequency
+- num-cs : the number of the chipselect signals
+- spi-mode: spi motorola mode, 0 to 3
+- ctar-params: CTAR0 to 7 register configuration, as an array
+ of 8 integer fields for each register, where each register
+ is defined as: <fmsz, pcssck, pasc, pdt, cssck, asc, dt, br>.
+
+Example:
+
+dspi0: dspi at fc05c000 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfc05c000 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ ctar-fields = <7, 0, 0, 0, 0, 0, 1, 6>,
+ <7, 0, 0, 0, 0, 0, 1, 6>,
+ <7, 0, 0, 0, 0, 0, 1, 6>;
+};
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v4 02/12] m68k: architecture changes to support fdt
2018-12-16 11:22 [U-Boot] [PATCH v4 01/12] m68k: add basic set of devicetrees Angelo Dureghello
@ 2018-12-16 11:22 ` Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 03/12] m68k: add initial dts files for all m68k boards Angelo Dureghello
` (9 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Angelo Dureghello @ 2018-12-16 11:22 UTC (permalink / raw)
To: u-boot
This patch adds fdt support to the m68k architecture.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
---
Changes for v2:
- add OF_CONTROL, DM and DM_SERIAL as default config options
for all cpu families
Changes for v3:
- none
Changes for v4:
- bisectability, moved SUPPORT_OF_CONTROL to next patch
---
arch/m68k/Kconfig | 33 +++++++++++++++++++++++++++++++++
arch/m68k/cpu/u-boot.lds | 6 ++++--
2 files changed, 37 insertions(+), 2 deletions(-)
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index 1f6df5c870..fef108105b 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -6,36 +6,69 @@ config SYS_ARCH
# processor family
config MCF520x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF52x2
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF523x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF530x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF5301x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF532x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF537x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF5441x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF5445x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF5227x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF547x_8x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
# processor type
diff --git a/arch/m68k/cpu/u-boot.lds b/arch/m68k/cpu/u-boot.lds
index 96451208e5..64cf2ff5ef 100644
--- a/arch/m68k/cpu/u-boot.lds
+++ b/arch/m68k/cpu/u-boot.lds
@@ -68,13 +68,15 @@ SECTIONS
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
- . = ALIGN(256);
+ . = ALIGN(4);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
- . = ALIGN(256);
+ . = ALIGN(4);
__init_end = .;
+ _end = .;
+
__bss_start = .;
.bss (NOLOAD) :
{
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v4 03/12] m68k: add initial dts files for all m68k boards
2018-12-16 11:22 [U-Boot] [PATCH v4 01/12] m68k: add basic set of devicetrees Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 02/12] m68k: architecture changes to support fdt Angelo Dureghello
@ 2018-12-16 11:22 ` Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 04/12] m68k: enabling long jumps on mcf54x5 SoCs Angelo Dureghello
` (8 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Angelo Dureghello @ 2018-12-16 11:22 UTC (permalink / raw)
To: u-boot
This patch adds basic dts files for all the m68k boards.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
---
Changes for v2:
- new patch
Changes for v3:
- none
Changes for v4:
- none
---
arch/m68k/dts/M5208EVBE.dts | 22 +++++++
arch/m68k/dts/M52277EVB.dts | 25 ++++++++
arch/m68k/dts/M52277EVB_stmicro.dts | 22 +++++++
arch/m68k/dts/M5235EVB.dts | 22 +++++++
arch/m68k/dts/M5235EVB_Flash32.dts | 22 +++++++
arch/m68k/dts/M5249EVB.dts | 22 +++++++
arch/m68k/dts/M5253DEMO.dts | 22 +++++++
arch/m68k/dts/M5272C3.dts | 22 +++++++
arch/m68k/dts/M5275EVB.dts | 22 +++++++
arch/m68k/dts/M5282EVB.dts | 22 +++++++
arch/m68k/dts/M53017EVB.dts | 22 +++++++
arch/m68k/dts/M5329AFEE.dts | 22 +++++++
arch/m68k/dts/M5329BFEE.dts | 22 +++++++
arch/m68k/dts/M5373EVB.dts | 22 +++++++
arch/m68k/dts/M54418TWR.dts | 25 ++++++++
arch/m68k/dts/M54418TWR_nand_mii.dts | 25 ++++++++
arch/m68k/dts/M54418TWR_nand_rmii.dts | 25 ++++++++
arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts | 25 ++++++++
arch/m68k/dts/M54418TWR_serial_mii.dts | 25 ++++++++
arch/m68k/dts/M54418TWR_serial_rmii.dts | 25 ++++++++
arch/m68k/dts/M54451EVB.dts | 25 ++++++++
arch/m68k/dts/M54451EVB_stmicro.dts | 25 ++++++++
arch/m68k/dts/M54455EVB.dts | 25 ++++++++
arch/m68k/dts/M54455EVB_a66.dts | 25 ++++++++
arch/m68k/dts/M54455EVB_i66.dts | 25 ++++++++
arch/m68k/dts/M54455EVB_intel.dts | 26 +++++++++
arch/m68k/dts/M54455EVB_stm33.dts | 25 ++++++++
arch/m68k/dts/M5475AFE.dts | 13 +++++
arch/m68k/dts/M5475BFE.dts | 13 +++++
arch/m68k/dts/M5475CFE.dts | 13 +++++
arch/m68k/dts/M5475DFE.dts | 13 +++++
arch/m68k/dts/M5475EFE.dts | 13 +++++
arch/m68k/dts/M5475FFE.dts | 13 +++++
arch/m68k/dts/M5475GFE.dts | 13 +++++
arch/m68k/dts/M5485AFE.dts | 17 ++++++
arch/m68k/dts/M5485BFE.dts | 17 ++++++
arch/m68k/dts/M5485CFE.dts | 17 ++++++
arch/m68k/dts/M5485DFE.dts | 17 ++++++
arch/m68k/dts/M5485EFE.dts | 17 ++++++
arch/m68k/dts/M5485FFE.dts | 17 ++++++
arch/m68k/dts/M5485GFE.dts | 17 ++++++
arch/m68k/dts/M5485HFE.dts | 17 ++++++
arch/m68k/dts/Makefile | 58 +++++++++++++++++++
arch/m68k/dts/amcore.dts | 22 +++++++
arch/m68k/dts/astro_mcf5373l.dts | 22 +++++++
arch/m68k/dts/cobra5272.dts | 22 +++++++
arch/m68k/dts/eb_cpu5282.dts | 22 +++++++
arch/m68k/dts/eb_cpu5282_internal.dts | 22 +++++++
arch/m68k/dts/stmark2.dts | 34 +++++++++++
49 files changed, 1066 insertions(+)
create mode 100644 arch/m68k/dts/M5208EVBE.dts
create mode 100644 arch/m68k/dts/M52277EVB.dts
create mode 100644 arch/m68k/dts/M52277EVB_stmicro.dts
create mode 100644 arch/m68k/dts/M5235EVB.dts
create mode 100644 arch/m68k/dts/M5235EVB_Flash32.dts
create mode 100644 arch/m68k/dts/M5249EVB.dts
create mode 100644 arch/m68k/dts/M5253DEMO.dts
create mode 100644 arch/m68k/dts/M5272C3.dts
create mode 100644 arch/m68k/dts/M5275EVB.dts
create mode 100644 arch/m68k/dts/M5282EVB.dts
create mode 100644 arch/m68k/dts/M53017EVB.dts
create mode 100644 arch/m68k/dts/M5329AFEE.dts
create mode 100644 arch/m68k/dts/M5329BFEE.dts
create mode 100644 arch/m68k/dts/M5373EVB.dts
create mode 100644 arch/m68k/dts/M54418TWR.dts
create mode 100644 arch/m68k/dts/M54418TWR_nand_mii.dts
create mode 100644 arch/m68k/dts/M54418TWR_nand_rmii.dts
create mode 100644 arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts
create mode 100644 arch/m68k/dts/M54418TWR_serial_mii.dts
create mode 100644 arch/m68k/dts/M54418TWR_serial_rmii.dts
create mode 100644 arch/m68k/dts/M54451EVB.dts
create mode 100644 arch/m68k/dts/M54451EVB_stmicro.dts
create mode 100644 arch/m68k/dts/M54455EVB.dts
create mode 100644 arch/m68k/dts/M54455EVB_a66.dts
create mode 100644 arch/m68k/dts/M54455EVB_i66.dts
create mode 100644 arch/m68k/dts/M54455EVB_intel.dts
create mode 100644 arch/m68k/dts/M54455EVB_stm33.dts
create mode 100644 arch/m68k/dts/M5475AFE.dts
create mode 100644 arch/m68k/dts/M5475BFE.dts
create mode 100644 arch/m68k/dts/M5475CFE.dts
create mode 100644 arch/m68k/dts/M5475DFE.dts
create mode 100644 arch/m68k/dts/M5475EFE.dts
create mode 100644 arch/m68k/dts/M5475FFE.dts
create mode 100644 arch/m68k/dts/M5475GFE.dts
create mode 100644 arch/m68k/dts/M5485AFE.dts
create mode 100644 arch/m68k/dts/M5485BFE.dts
create mode 100644 arch/m68k/dts/M5485CFE.dts
create mode 100644 arch/m68k/dts/M5485DFE.dts
create mode 100644 arch/m68k/dts/M5485EFE.dts
create mode 100644 arch/m68k/dts/M5485FFE.dts
create mode 100644 arch/m68k/dts/M5485GFE.dts
create mode 100644 arch/m68k/dts/M5485HFE.dts
create mode 100644 arch/m68k/dts/Makefile
create mode 100644 arch/m68k/dts/amcore.dts
create mode 100644 arch/m68k/dts/astro_mcf5373l.dts
create mode 100644 arch/m68k/dts/cobra5272.dts
create mode 100644 arch/m68k/dts/eb_cpu5282.dts
create mode 100644 arch/m68k/dts/eb_cpu5282_internal.dts
create mode 100644 arch/m68k/dts/stmark2.dts
diff --git a/arch/m68k/dts/M5208EVBE.dts b/arch/m68k/dts/M5208EVBE.dts
new file mode 100644
index 0000000000..e78513f3b8
--- /dev/null
+++ b/arch/m68k/dts/M5208EVBE.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5208.dtsi"
+
+/ {
+ model = "Freescale M5208EVBE";
+ compatible = "fsl,M5208EVBE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
diff --git a/arch/m68k/dts/M52277EVB.dts b/arch/m68k/dts/M52277EVB.dts
new file mode 100644
index 0000000000..a2210c8811
--- /dev/null
+++ b/arch/m68k/dts/M52277EVB.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5227x.dtsi"
+
+/ {
+ model = "Freescale M52277EVB";
+ compatible = "fsl,M52277EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
diff --git a/arch/m68k/dts/M52277EVB_stmicro.dts b/arch/m68k/dts/M52277EVB_stmicro.dts
new file mode 100644
index 0000000000..5fd3ca5efd
--- /dev/null
+++ b/arch/m68k/dts/M52277EVB_stmicro.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5227x.dtsi"
+
+/ {
+ model = "Freescale M52277_stmicro";
+ compatible = "fsl,M52277_stmicro";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
diff --git a/arch/m68k/dts/M5235EVB.dts b/arch/m68k/dts/M5235EVB.dts
new file mode 100644
index 0000000000..1a32539323
--- /dev/null
+++ b/arch/m68k/dts/M5235EVB.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf523x.dtsi"
+
+/ {
+ model = "Freescale M5235EVB";
+ compatible = "fsl,M5235EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
diff --git a/arch/m68k/dts/M5235EVB_Flash32.dts b/arch/m68k/dts/M5235EVB_Flash32.dts
new file mode 100644
index 0000000000..fcbffb23f5
--- /dev/null
+++ b/arch/m68k/dts/M5235EVB_Flash32.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf523x.dtsi"
+
+/ {
+ model = "Freescale M5235EVB_Flash32";
+ compatible = "fsl,M5235EVB_Flash32";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
diff --git a/arch/m68k/dts/M5249EVB.dts b/arch/m68k/dts/M5249EVB.dts
new file mode 100644
index 0000000000..b2a1be9090
--- /dev/null
+++ b/arch/m68k/dts/M5249EVB.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5249.dtsi"
+
+/ {
+ model = "Freescale M5249EVB";
+ compatible = "fsl,M5249EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
diff --git a/arch/m68k/dts/M5253DEMO.dts b/arch/m68k/dts/M5253DEMO.dts
new file mode 100644
index 0000000000..7ebaa9a2e0
--- /dev/null
+++ b/arch/m68k/dts/M5253DEMO.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5253.dtsi"
+
+/ {
+ model = "Freescale M5253DEMO";
+ compatible = "fsl,M5253DEMO";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
diff --git a/arch/m68k/dts/M5272C3.dts b/arch/m68k/dts/M5272C3.dts
new file mode 100644
index 0000000000..6efb8a4cc5
--- /dev/null
+++ b/arch/m68k/dts/M5272C3.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5272.dtsi"
+
+/ {
+ model = "Freescale M5272C3";
+ compatible = "fsl,M5272C3";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
diff --git a/arch/m68k/dts/M5275EVB.dts b/arch/m68k/dts/M5275EVB.dts
new file mode 100644
index 0000000000..cd9eb7d145
--- /dev/null
+++ b/arch/m68k/dts/M5275EVB.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5275.dtsi"
+
+/ {
+ model = "Freescale M5275EVB";
+ compatible = "fsl,M5275EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
diff --git a/arch/m68k/dts/M5282EVB.dts b/arch/m68k/dts/M5282EVB.dts
new file mode 100644
index 0000000000..9527caafc2
--- /dev/null
+++ b/arch/m68k/dts/M5282EVB.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5282.dtsi"
+
+/ {
+ model = "Freescale M5282EVB";
+ compatible = "fsl,M5282EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
diff --git a/arch/m68k/dts/M53017EVB.dts b/arch/m68k/dts/M53017EVB.dts
new file mode 100644
index 0000000000..b267488e0f
--- /dev/null
+++ b/arch/m68k/dts/M53017EVB.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5301x.dtsi"
+
+/ {
+ model = "Freescale M53017EVB";
+ compatible = "fsl,M53017EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
diff --git a/arch/m68k/dts/M5329AFEE.dts b/arch/m68k/dts/M5329AFEE.dts
new file mode 100644
index 0000000000..7d121d68e7
--- /dev/null
+++ b/arch/m68k/dts/M5329AFEE.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5329.dtsi"
+
+/ {
+ model = "Freescale M5329AFEE";
+ compatible = "fsl,M5329AFEE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
diff --git a/arch/m68k/dts/M5329BFEE.dts b/arch/m68k/dts/M5329BFEE.dts
new file mode 100644
index 0000000000..cd087b6ea6
--- /dev/null
+++ b/arch/m68k/dts/M5329BFEE.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5329.dtsi"
+
+/ {
+ model = "Freescale M5329BFEE";
+ compatible = "fsl,M5329BFEE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
diff --git a/arch/m68k/dts/M5373EVB.dts b/arch/m68k/dts/M5373EVB.dts
new file mode 100644
index 0000000000..930f911d4a
--- /dev/null
+++ b/arch/m68k/dts/M5373EVB.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf537x.dtsi"
+
+/ {
+ model = "Freescale M5373EVB";
+ compatible = "fsl,M5373EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
diff --git a/arch/m68k/dts/M54418TWR.dts b/arch/m68k/dts/M54418TWR.dts
new file mode 100644
index 0000000000..7765c7abbb
--- /dev/null
+++ b/arch/m68k/dts/M54418TWR.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+ model = "Freescale M54418TWR";
+ compatible = "fsl,M54418TWR";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
diff --git a/arch/m68k/dts/M54418TWR_nand_mii.dts b/arch/m68k/dts/M54418TWR_nand_mii.dts
new file mode 100644
index 0000000000..9b1cb85325
--- /dev/null
+++ b/arch/m68k/dts/M54418TWR_nand_mii.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+ model = "Freescale M54418TWR_nand_mii";
+ compatible = "fsl,M54418TWR_nand_mii";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
diff --git a/arch/m68k/dts/M54418TWR_nand_rmii.dts b/arch/m68k/dts/M54418TWR_nand_rmii.dts
new file mode 100644
index 0000000000..824a66af48
--- /dev/null
+++ b/arch/m68k/dts/M54418TWR_nand_rmii.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+ model = "Freescale M54418TWR_nand_rmii";
+ compatible = "fsl,M54418TWR_nand_rmii";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
diff --git a/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts b/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts
new file mode 100644
index 0000000000..74fa197ea9
--- /dev/null
+++ b/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+ model = "Freescale M54418TWR_nand_rmii_lowfreq";
+ compatible = "fsl,M54418TWR_nand_rmii_lowfreq";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
diff --git a/arch/m68k/dts/M54418TWR_serial_mii.dts b/arch/m68k/dts/M54418TWR_serial_mii.dts
new file mode 100644
index 0000000000..22f27b5612
--- /dev/null
+++ b/arch/m68k/dts/M54418TWR_serial_mii.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+ model = "Freescale M54418TWR_serial_mii";
+ compatible = "fsl,M54418TWR_serial_mii";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
diff --git a/arch/m68k/dts/M54418TWR_serial_rmii.dts b/arch/m68k/dts/M54418TWR_serial_rmii.dts
new file mode 100644
index 0000000000..0ddefd9da2
--- /dev/null
+++ b/arch/m68k/dts/M54418TWR_serial_rmii.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+ model = "Freescale M54418TWR_serial_rmii";
+ compatible = "fsl,M54418TWR_serial_rmii";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
diff --git a/arch/m68k/dts/M54451EVB.dts b/arch/m68k/dts/M54451EVB.dts
new file mode 100644
index 0000000000..b57bfea2cb
--- /dev/null
+++ b/arch/m68k/dts/M54451EVB.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+ model = "Freescale M54451EVB";
+ compatible = "fsl,M54451EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
diff --git a/arch/m68k/dts/M54451EVB_stmicro.dts b/arch/m68k/dts/M54451EVB_stmicro.dts
new file mode 100644
index 0000000000..9a088e16d0
--- /dev/null
+++ b/arch/m68k/dts/M54451EVB_stmicro.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+ model = "Freescale M54451EVB_stmicro";
+ compatible = "fsl,M54451EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
diff --git a/arch/m68k/dts/M54455EVB.dts b/arch/m68k/dts/M54455EVB.dts
new file mode 100644
index 0000000000..dd11181033
--- /dev/null
+++ b/arch/m68k/dts/M54455EVB.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+ model = "Freescale M54455EVB";
+ compatible = "fsl,M54455EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
diff --git a/arch/m68k/dts/M54455EVB_a66.dts b/arch/m68k/dts/M54455EVB_a66.dts
new file mode 100644
index 0000000000..70d544b72d
--- /dev/null
+++ b/arch/m68k/dts/M54455EVB_a66.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+ model = "Freescale M54455EVB_a66";
+ compatible = "fsl,M54455EVB_a66";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
diff --git a/arch/m68k/dts/M54455EVB_i66.dts b/arch/m68k/dts/M54455EVB_i66.dts
new file mode 100644
index 0000000000..b37a87213f
--- /dev/null
+++ b/arch/m68k/dts/M54455EVB_i66.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+ model = "Freescale M54455EVB_i66";
+ compatible = "fsl,M54455EVB_i66";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
diff --git a/arch/m68k/dts/M54455EVB_intel.dts b/arch/m68k/dts/M54455EVB_intel.dts
new file mode 100644
index 0000000000..c92228fc8b
--- /dev/null
+++ b/arch/m68k/dts/M54455EVB_intel.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+ model = "Freescale M54455EVB_intel";
+ compatible = "fsl,M5275EVB_intel";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
+
diff --git a/arch/m68k/dts/M54455EVB_stm33.dts b/arch/m68k/dts/M54455EVB_stm33.dts
new file mode 100644
index 0000000000..9e467f94a1
--- /dev/null
+++ b/arch/m68k/dts/M54455EVB_stm33.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+ model = "Freescale M54455EVB_stm33";
+ compatible = "fsl,M5275EVB_stm33";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
diff --git a/arch/m68k/dts/M5475AFE.dts b/arch/m68k/dts/M5475AFE.dts
new file mode 100644
index 0000000000..0c0a79befa
--- /dev/null
+++ b/arch/m68k/dts/M5475AFE.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5475AFE";
+ compatible = "fsl,M5475AFE";
+};
+
diff --git a/arch/m68k/dts/M5475BFE.dts b/arch/m68k/dts/M5475BFE.dts
new file mode 100644
index 0000000000..c4d14097cd
--- /dev/null
+++ b/arch/m68k/dts/M5475BFE.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5475BFE";
+ compatible = "fsl,M5475BFE";
+};
+
diff --git a/arch/m68k/dts/M5475CFE.dts b/arch/m68k/dts/M5475CFE.dts
new file mode 100644
index 0000000000..4c92c332ba
--- /dev/null
+++ b/arch/m68k/dts/M5475CFE.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5475CFE";
+ compatible = "fsl,M5475CFE";
+};
+
diff --git a/arch/m68k/dts/M5475DFE.dts b/arch/m68k/dts/M5475DFE.dts
new file mode 100644
index 0000000000..c41c1b3c12
--- /dev/null
+++ b/arch/m68k/dts/M5475DFE.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5475DFE";
+ compatible = "fsl,M5475DFE";
+};
+
diff --git a/arch/m68k/dts/M5475EFE.dts b/arch/m68k/dts/M5475EFE.dts
new file mode 100644
index 0000000000..5a920b241a
--- /dev/null
+++ b/arch/m68k/dts/M5475EFE.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5475EFE";
+ compatible = "fsl,M5475EFE";
+};
+
diff --git a/arch/m68k/dts/M5475FFE.dts b/arch/m68k/dts/M5475FFE.dts
new file mode 100644
index 0000000000..d312a6ae8d
--- /dev/null
+++ b/arch/m68k/dts/M5475FFE.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5475FFE";
+ compatible = "fsl,M5475FFE";
+};
+
diff --git a/arch/m68k/dts/M5475GFE.dts b/arch/m68k/dts/M5475GFE.dts
new file mode 100644
index 0000000000..9e794dafa6
--- /dev/null
+++ b/arch/m68k/dts/M5475GFE.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5475GFE";
+ compatible = "fsl,M5475GFE";
+};
+
diff --git a/arch/m68k/dts/M5485AFE.dts b/arch/m68k/dts/M5485AFE.dts
new file mode 100644
index 0000000000..3466751174
--- /dev/null
+++ b/arch/m68k/dts/M5485AFE.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5485AFE";
+ compatible = "fsl,M5485AFE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
diff --git a/arch/m68k/dts/M5485BFE.dts b/arch/m68k/dts/M5485BFE.dts
new file mode 100644
index 0000000000..6d48795a4d
--- /dev/null
+++ b/arch/m68k/dts/M5485BFE.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5485BFE";
+ compatible = "fsl,M5485BFE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
diff --git a/arch/m68k/dts/M5485CFE.dts b/arch/m68k/dts/M5485CFE.dts
new file mode 100644
index 0000000000..d1a7d9d383
--- /dev/null
+++ b/arch/m68k/dts/M5485CFE.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5485CFE";
+ compatible = "fsl,M5485CFE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
diff --git a/arch/m68k/dts/M5485DFE.dts b/arch/m68k/dts/M5485DFE.dts
new file mode 100644
index 0000000000..7c362e26e5
--- /dev/null
+++ b/arch/m68k/dts/M5485DFE.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5485DFE";
+ compatible = "fsl,M5485DFE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
diff --git a/arch/m68k/dts/M5485EFE.dts b/arch/m68k/dts/M5485EFE.dts
new file mode 100644
index 0000000000..4c688dce2b
--- /dev/null
+++ b/arch/m68k/dts/M5485EFE.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5485EFE";
+ compatible = "fsl,M5485EFE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
diff --git a/arch/m68k/dts/M5485FFE.dts b/arch/m68k/dts/M5485FFE.dts
new file mode 100644
index 0000000000..87ec2c543d
--- /dev/null
+++ b/arch/m68k/dts/M5485FFE.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5485FFE";
+ compatible = "fsl,M5485FFE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
diff --git a/arch/m68k/dts/M5485GFE.dts b/arch/m68k/dts/M5485GFE.dts
new file mode 100644
index 0000000000..9f67e5516b
--- /dev/null
+++ b/arch/m68k/dts/M5485GFE.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5485GFE";
+ compatible = "fsl,M5485GFE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
diff --git a/arch/m68k/dts/M5485HFE.dts b/arch/m68k/dts/M5485HFE.dts
new file mode 100644
index 0000000000..2eb2213d78
--- /dev/null
+++ b/arch/m68k/dts/M5485HFE.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5485HFE";
+ compatible = "fsl,M5485HFE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
diff --git a/arch/m68k/dts/Makefile b/arch/m68k/dts/Makefile
new file mode 100644
index 0000000000..53a53d6dc8
--- /dev/null
+++ b/arch/m68k/dts/Makefile
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+dtb-$(CONFIG_TARGET_M52277EVB) += M52277EVB.dtb \
+ M52277EVB_stmicro.dtb
+dtb-$(CONFIG_TARGET_M5235EVB) += M5235EVB.dtb \
+ M5235EVB_Flash32.dtb
+dtb-$(CONFIG_TARGET_COBRA5272) += cobra5272.dtb
+dtb-$(CONFIG_TARGET_EB_CPU5282) += eb_cpu5282.dtb \
+ eb_cpu5282_internal.dtb
+dtb-$(CONFIG_TARGET_M5208EVBE) += M5208EVBE.dtb
+dtb-$(CONFIG_TARGET_M5249EVB) += M5249EVB.dtb
+dtb-$(CONFIG_TARGET_M5253DEMO) += M5253DEMO.dtb
+dtb-$(CONFIG_TARGET_M5272C3) += M5272C3.dtb
+dtb-$(CONFIG_TARGET_M5275EVB) += M5275EVB.dtb
+dtb-$(CONFIG_TARGET_M5282EVB) += M5282EVB.dtb
+dtb-$(CONFIG_TARGET_ASTRO_MCF5373L) += astro_mcf5373l.dtb
+dtb-$(CONFIG_TARGET_M53017EVB) += M53017EVB.dtb
+dtb-$(CONFIG_TARGET_M5373EVB) += M5373EVB.dtb
+dtb-$(CONFIG_TARGET_M54418TWR) += M54418TWR.dtb \
+ M54418TWR_nand_mii.dtb \
+ M54418TWR_nand_rmii.dtb \
+ M54418TWR_serial_mii.dtb \
+ M54418TWR_serial_rmii.dtb \
+ M54418TWR_nand_rmii_lowfreq.dtb
+dtb-$(CONFIG_TARGET_M54451EVB) += M54451EVB.dtb \
+ M54451EVB_stmicro.dtb
+dtb-$(CONFIG_TARGET_M54455EVB) += M54455EVB.dtb \
+ M54455EVB_intel.dtb \
+ M54455EVB_stm33.dtb \
+ M54455EVB_a66.dtb \
+ M54455EVB_i66.dtb
+dtb-$(CONFIG_TARGET_AMCORE) += amcore.dtb
+dtb-$(CONFIG_TARGET_STMARK2) += stmark2.dtb
+dtb-$(CONFIG_TARGET_M5475EVB) += M5475AFE.dtb \
+ M5475BFE.dtb \
+ M5475CFE.dtb \
+ M5475DFE.dtb \
+ M5475EFE.dtb \
+ M5475FFE.dtb \
+ M5475GFE.dtb
+dtb-$(CONFIG_TARGET_M5485EVB) += M5485AFE.dtb \
+ M5485BFE.dtb \
+ M5485CFE.dtb \
+ M5485DFE.dtb \
+ M5485EFE.dtb \
+ M5485FFE.dtb \
+ M5485GFE.dtb \
+ M5485HFE.dtb
+
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+ @:
+
+clean-files := *.dtb
diff --git a/arch/m68k/dts/amcore.dts b/arch/m68k/dts/amcore.dts
new file mode 100644
index 0000000000..c21fb8ff79
--- /dev/null
+++ b/arch/m68k/dts/amcore.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5307.dtsi"
+
+/ {
+ model = "Sysam AMCORE";
+ compatible = "sysam,AMCORE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
diff --git a/arch/m68k/dts/astro_mcf5373l.dts b/arch/m68k/dts/astro_mcf5373l.dts
new file mode 100644
index 0000000000..1b1a46ac2d
--- /dev/null
+++ b/arch/m68k/dts/astro_mcf5373l.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf537x.dtsi"
+
+/ {
+ model = "Astro mcf5373l";
+ compatible = "astro,mcf5373l";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
diff --git a/arch/m68k/dts/cobra5272.dts b/arch/m68k/dts/cobra5272.dts
new file mode 100644
index 0000000000..f3b74975de
--- /dev/null
+++ b/arch/m68k/dts/cobra5272.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5272.dtsi"
+
+/ {
+ model = "Cobra 5272";
+ compatible = "cobra,M5272";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
diff --git a/arch/m68k/dts/eb_cpu5282.dts b/arch/m68k/dts/eb_cpu5282.dts
new file mode 100644
index 0000000000..4641e9cb56
--- /dev/null
+++ b/arch/m68k/dts/eb_cpu5282.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5282.dtsi"
+
+/ {
+ model = "BuS eb_cpuM5282";
+ compatible = "bus,eb_cpuM5282";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
diff --git a/arch/m68k/dts/eb_cpu5282_internal.dts b/arch/m68k/dts/eb_cpu5282_internal.dts
new file mode 100644
index 0000000000..0acb7935f4
--- /dev/null
+++ b/arch/m68k/dts/eb_cpu5282_internal.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5282.dtsi"
+
+/ {
+ model = "BuS eb_cpu5282_internals";
+ compatible = "bus,eb_cpu5282_internals";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
diff --git a/arch/m68k/dts/stmark2.dts b/arch/m68k/dts/stmark2.dts
new file mode 100644
index 0000000000..fd8ce4fa35
--- /dev/null
+++ b/arch/m68k/dts/stmark2.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+ model = "Sysam stmark2";
+ compatible = "sysam,stmark2";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ spi-mode = <3>;
+ status = "okay";
+
+ flash: is25lp128 at 1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <60000000>;
+ reg = <1>;
+ };
+};
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v4 04/12] m68k: enabling long jumps on mcf54x5 SoCs
2018-12-16 11:22 [U-Boot] [PATCH v4 01/12] m68k: add basic set of devicetrees Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 02/12] m68k: architecture changes to support fdt Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 03/12] m68k: add initial dts files for all m68k boards Angelo Dureghello
@ 2018-12-16 11:22 ` Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 05/12] configs: enable use of DT for all m68k boards Angelo Dureghello
` (7 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Angelo Dureghello @ 2018-12-16 11:22 UTC (permalink / raw)
To: u-boot
Growing of binary size asks for long assembly jumps.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
---
Changes for v2:
- new patch
Changes for v3:
- none
Changes for v4:
- none
---
arch/m68k/cpu/mcf547x_8x/start.S | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/m68k/cpu/mcf547x_8x/start.S b/arch/m68k/cpu/mcf547x_8x/start.S
index 7cb5db7ff0..4dd57bf39c 100644
--- a/arch/m68k/cpu/mcf547x_8x/start.S
+++ b/arch/m68k/cpu/mcf547x_8x/start.S
@@ -131,7 +131,8 @@ _start:
* then (and always) gd struct space will be reserved
*/
move.l %sp, -(%sp)
- bsr board_init_f_alloc_reserve
+ move.l #board_init_f_alloc_reserve, %a1
+ jsr (%a1)
/* update stack and frame-pointers */
move.l %d0, %sp
@@ -139,7 +140,8 @@ _start:
/* initialize reserved area */
move.l %d0, -(%sp)
- bsr board_init_f_init_reserve
+ move.l #board_init_f_init_reserve, %a1
+ jsr (%a1)
/* run low-level CPU init code (from flash) */
jbsr cpu_init_f
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v4 05/12] configs: enable use of DT for all m68k boards
2018-12-16 11:22 [U-Boot] [PATCH v4 01/12] m68k: add basic set of devicetrees Angelo Dureghello
` (2 preceding siblings ...)
2018-12-16 11:22 ` [U-Boot] [PATCH v4 04/12] m68k: enabling long jumps on mcf54x5 SoCs Angelo Dureghello
@ 2018-12-16 11:22 ` Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 06/12] drivers: spi: cf_spi: add Kconfig option Angelo Dureghello
` (6 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Angelo Dureghello @ 2018-12-16 11:22 UTC (permalink / raw)
To: u-boot
Enable DT usage for all m68k boards. To provide a
working single binary, the dts has been kept as embedded.
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
---
Changes for v2:
- new patch
Changes for v3:
- none
Changes for v4:
- remove CONFIG_OF_EMBED=y
---
configs/M5208EVBE_defconfig | 1 +
configs/M52277EVB_defconfig | 1 +
configs/M52277EVB_stmicro_defconfig | 1 +
configs/M5235EVB_Flash32_defconfig | 1 +
configs/M5235EVB_defconfig | 1 +
configs/M5249EVB_defconfig | 1 +
configs/M5253DEMO_defconfig | 1 +
configs/M5272C3_defconfig | 1 +
configs/M5275EVB_defconfig | 1 +
configs/M5282EVB_defconfig | 1 +
configs/M53017EVB_defconfig | 1 +
configs/M5329AFEE_defconfig | 1 +
configs/M5329BFEE_defconfig | 1 +
configs/M5373EVB_defconfig | 1 +
configs/M54418TWR_defconfig | 1 +
configs/M54418TWR_nand_mii_defconfig | 1 +
configs/M54418TWR_nand_rmii_defconfig | 1 +
configs/M54418TWR_nand_rmii_lowfreq_defconfig | 1 +
configs/M54418TWR_serial_mii_defconfig | 1 +
configs/M54418TWR_serial_rmii_defconfig | 1 +
configs/M54451EVB_defconfig | 1 +
configs/M54451EVB_stmicro_defconfig | 1 +
configs/M54455EVB_a66_defconfig | 1 +
configs/M54455EVB_defconfig | 1 +
configs/M54455EVB_i66_defconfig | 1 +
configs/M54455EVB_intel_defconfig | 1 +
configs/M54455EVB_stm33_defconfig | 1 +
configs/M5475AFE_defconfig | 1 +
configs/M5475BFE_defconfig | 1 +
configs/M5475CFE_defconfig | 1 +
configs/M5475DFE_defconfig | 1 +
configs/M5475EFE_defconfig | 1 +
configs/M5475FFE_defconfig | 1 +
configs/M5475GFE_defconfig | 1 +
configs/M5485AFE_defconfig | 1 +
configs/M5485BFE_defconfig | 1 +
configs/M5485CFE_defconfig | 1 +
configs/M5485DFE_defconfig | 1 +
configs/M5485EFE_defconfig | 1 +
configs/M5485FFE_defconfig | 1 +
configs/M5485GFE_defconfig | 1 +
configs/M5485HFE_defconfig | 1 +
configs/amcore_defconfig | 1 +
configs/astro_mcf5373l_defconfig | 1 +
configs/cobra5272_defconfig | 1 +
configs/eb_cpu5282_defconfig | 1 +
configs/eb_cpu5282_internal_defconfig | 1 +
configs/stmark2_defconfig | 1 +
48 files changed, 48 insertions(+)
diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig
index 934cda4aa6..01b2c97b66 100644
--- a/configs/M5208EVBE_defconfig
+++ b/configs/M5208EVBE_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_TARGET_M5208EVBE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5208EVBE"
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/M52277EVB_defconfig b/configs/M52277EVB_defconfig
index efa5e7102b..87d5e852f0 100644
--- a/configs/M52277EVB_defconfig
+++ b/configs/M52277EVB_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_TARGET_M52277EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M52277EVB"
CONFIG_SYS_EXTRA_OPTIONS="SYS_SPANSION_BOOT"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/M52277EVB_stmicro_defconfig b/configs/M52277EVB_stmicro_defconfig
index 3628729a48..ed24d3e11d 100644
--- a/configs/M52277EVB_stmicro_defconfig
+++ b/configs/M52277EVB_stmicro_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x43E00000
CONFIG_TARGET_M52277EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M52277EVB_stmicro"
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig
index fff57436c7..aef8281319 100644
--- a/configs/M5235EVB_Flash32_defconfig
+++ b/configs/M5235EVB_Flash32_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFFC00000
CONFIG_TARGET_M5235EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5235EVB_Flash32"
CONFIG_SYS_EXTRA_OPTIONS="NORFLASH_PS32BIT"
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig
index 07e0f4f50b..efc03179c9 100644
--- a/configs/M5235EVB_defconfig
+++ b/configs/M5235EVB_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_TARGET_M5235EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5235EVB"
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/M5249EVB_defconfig b/configs/M5249EVB_defconfig
index 908f6a1ab1..3f76665efd 100644
--- a/configs/M5249EVB_defconfig
+++ b/configs/M5249EVB_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_TARGET_M5249EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5249EVB"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig
index 4685c4eb83..2dbbd22f54 100644
--- a/configs/M5253DEMO_defconfig
+++ b/configs/M5253DEMO_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5253DEMO=y
+CONFIG_DEFAULT_DEVICE_TREE="M5253DEMO"
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig
index 85283d40e4..dc4d045e36 100644
--- a/configs/M5272C3_defconfig
+++ b/configs/M5272C3_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_TARGET_M5272C3=y
+CONFIG_DEFAULT_DEVICE_TREE="M5272C3"
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig
index 5ff262425c..2e1f60cf88 100644
--- a/configs/M5275EVB_defconfig
+++ b/configs/M5275EVB_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_TARGET_M5275EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5275EVB"
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig
index 289922ba33..f904d90012 100644
--- a/configs/M5282EVB_defconfig
+++ b/configs/M5282EVB_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_TARGET_M5282EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5282EVB"
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig
index 0b1073af61..9eef96df48 100644
--- a/configs/M53017EVB_defconfig
+++ b/configs/M53017EVB_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_TARGET_M53017EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M53017EVB"
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock3 rw rootfstype=jffs2"
diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig
index c6dff0e27b..6899ac1c52 100644
--- a/configs/M5329AFEE_defconfig
+++ b/configs/M5329AFEE_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_TARGET_M5329EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5329AFEE"
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=0"
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig
index 56dba26f6f..16777c10eb 100644
--- a/configs/M5329BFEE_defconfig
+++ b/configs/M5329BFEE_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_TARGET_M5329EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5329BFEE"
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig
index 39823200ee..95cf43a6f3 100644
--- a/configs/M5373EVB_defconfig
+++ b/configs/M5373EVB_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_TARGET_M5373EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5373EVB"
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/M54418TWR_defconfig b/configs/M54418TWR_defconfig
index f69f405d5a..3b35bcec4f 100644
--- a/configs/M54418TWR_defconfig
+++ b/configs/M54418TWR_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_TARGET_M54418TWR=y
+CONFIG_DEFAULT_DEVICE_TREE="M54418TWR"
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.1.1:/tftpboot/192.168.1.2 ip=192.168.1.2:192.168.1.1:192.168.1.1: 255.255.255.0::eth0:off:rw console=ttyS0,115200"
diff --git a/configs/M54418TWR_nand_mii_defconfig b/configs/M54418TWR_nand_mii_defconfig
index 04ca3a8114..c53c9d4512 100644
--- a/configs/M54418TWR_nand_mii_defconfig
+++ b/configs/M54418TWR_nand_mii_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_TARGET_M54418TWR=y
+CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_mii"
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=25000000"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro,-(jffs2) console=ttyS0,115200"
diff --git a/configs/M54418TWR_nand_rmii_defconfig b/configs/M54418TWR_nand_rmii_defconfig
index f6acf6019d..822d34928a 100644
--- a/configs/M54418TWR_nand_rmii_defconfig
+++ b/configs/M54418TWR_nand_rmii_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_TARGET_M54418TWR=y
+CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_rmii"
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=50000000"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro,-(jffs2) console=ttyS0,115200"
diff --git a/configs/M54418TWR_nand_rmii_lowfreq_defconfig b/configs/M54418TWR_nand_rmii_lowfreq_defconfig
index 6b631d6d4b..dda2864e18 100644
--- a/configs/M54418TWR_nand_rmii_lowfreq_defconfig
+++ b/configs/M54418TWR_nand_rmii_lowfreq_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_TARGET_M54418TWR=y
+CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_rmii_lowfreq"
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,LOW_MCFCLK,SYS_INPUT_CLKSRC=50000000"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro,-(jffs2) console=ttyS0,115200"
diff --git a/configs/M54418TWR_serial_mii_defconfig b/configs/M54418TWR_serial_mii_defconfig
index b2266a0577..25d8c4c72c 100644
--- a/configs/M54418TWR_serial_mii_defconfig
+++ b/configs/M54418TWR_serial_mii_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_TARGET_M54418TWR=y
+CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_serial_mii"
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=25000000"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.1.1:/tftpboot/192.168.1.2 ip=192.168.1.2:192.168.1.1:192.168.1.1: 255.255.255.0::eth0:off:rw console=ttyS0,115200"
diff --git a/configs/M54418TWR_serial_rmii_defconfig b/configs/M54418TWR_serial_rmii_defconfig
index f69f405d5a..29490e2faa 100644
--- a/configs/M54418TWR_serial_rmii_defconfig
+++ b/configs/M54418TWR_serial_rmii_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_TARGET_M54418TWR=y
+CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_serial_rmii"
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000"
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.1.1:/tftpboot/192.168.1.2 ip=192.168.1.2:192.168.1.1:192.168.1.1: 255.255.255.0::eth0:off:rw console=ttyS0,115200"
diff --git a/configs/M54451EVB_defconfig b/configs/M54451EVB_defconfig
index 8448b6cfbf..067eaa1369 100644
--- a/configs/M54451EVB_defconfig
+++ b/configs/M54451EVB_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_TARGET_M54451EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M54451EVB"
CONFIG_SYS_EXTRA_OPTIONS="SYS_INPUT_CLKSRC=24000000"
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
diff --git a/configs/M54451EVB_stmicro_defconfig b/configs/M54451EVB_stmicro_defconfig
index ce5f65666c..95b54612c9 100644
--- a/configs/M54451EVB_stmicro_defconfig
+++ b/configs/M54451EVB_stmicro_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_TARGET_M54451EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M54451EVB_stmicro"
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_INPUT_CLKSRC=24000000"
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
diff --git a/configs/M54455EVB_a66_defconfig b/configs/M54455EVB_a66_defconfig
index f9be1c3773..e131460ca9 100644
--- a/configs/M54455EVB_a66_defconfig
+++ b/configs/M54455EVB_a66_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_TARGET_M54455EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_a66"
CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=66666666"
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
diff --git a/configs/M54455EVB_defconfig b/configs/M54455EVB_defconfig
index abb69a966a..cda5702f07 100644
--- a/configs/M54455EVB_defconfig
+++ b/configs/M54455EVB_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_TARGET_M54455EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M54455EVB"
CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=33333333"
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
diff --git a/configs/M54455EVB_i66_defconfig b/configs/M54455EVB_i66_defconfig
index 6050df5d51..701f746b15 100644
--- a/configs/M54455EVB_i66_defconfig
+++ b/configs/M54455EVB_i66_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_TARGET_M54455EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_i66"
CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=66666666"
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
diff --git a/configs/M54455EVB_intel_defconfig b/configs/M54455EVB_intel_defconfig
index 686c00e318..eaa46842b5 100644
--- a/configs/M54455EVB_intel_defconfig
+++ b/configs/M54455EVB_intel_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_TARGET_M54455EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_intel"
CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=33333333"
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
diff --git a/configs/M54455EVB_stm33_defconfig b/configs/M54455EVB_stm33_defconfig
index fc19de50d1..6e08f91894 100644
--- a/configs/M54455EVB_stm33_defconfig
+++ b/configs/M54455EVB_stm33_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x4FE00000
CONFIG_TARGET_M54455EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_stm33"
CONFIG_SYS_EXTRA_OPTIONS="SYS_STMICRO_BOOT,CF_SBF,SYS_INPUT_CLKSRC=33333333"
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
diff --git a/configs/M5475AFE_defconfig b/configs/M5475AFE_defconfig
index b0296acff0..71e78fdaf0 100644
--- a/configs/M5475AFE_defconfig
+++ b/configs/M5475AFE_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5475EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475AFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/M5475BFE_defconfig b/configs/M5475BFE_defconfig
index 7fc61bd249..9db3d28e44 100644
--- a/configs/M5475BFE_defconfig
+++ b/configs/M5475BFE_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5475EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475BFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/M5475CFE_defconfig b/configs/M5475CFE_defconfig
index 22d1074521..4069d59a52 100644
--- a/configs/M5475CFE_defconfig
+++ b/configs/M5475CFE_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5475EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475CFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/M5475DFE_defconfig b/configs/M5475DFE_defconfig
index ee8c2abfba..fb5ecbb2ca 100644
--- a/configs/M5475DFE_defconfig
+++ b/configs/M5475DFE_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5475EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475DFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/M5475EFE_defconfig b/configs/M5475EFE_defconfig
index 939e56b28e..45d6f233c2 100644
--- a/configs/M5475EFE_defconfig
+++ b/configs/M5475EFE_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5475EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475EFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/M5475FFE_defconfig b/configs/M5475FFE_defconfig
index 1fef8fffd6..43d5c964dc 100644
--- a/configs/M5475FFE_defconfig
+++ b/configs/M5475FFE_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5475EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475FFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/M5475GFE_defconfig b/configs/M5475GFE_defconfig
index d78cafffed..11ea9cd454 100644
--- a/configs/M5475GFE_defconfig
+++ b/configs/M5475GFE_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5475EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475GFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/M5485AFE_defconfig b/configs/M5485AFE_defconfig
index 5cda25a99a..8f9aaa9856 100644
--- a/configs/M5485AFE_defconfig
+++ b/configs/M5485AFE_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5485EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485AFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/M5485BFE_defconfig b/configs/M5485BFE_defconfig
index 7cd4a5355b..ce26bed66b 100644
--- a/configs/M5485BFE_defconfig
+++ b/configs/M5485BFE_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5485EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485BFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/M5485CFE_defconfig b/configs/M5485CFE_defconfig
index ff5e8ef043..47b27323bc 100644
--- a/configs/M5485CFE_defconfig
+++ b/configs/M5485CFE_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5485EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485CFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/M5485DFE_defconfig b/configs/M5485DFE_defconfig
index c4dd6c3ae9..eb0d19b7c2 100644
--- a/configs/M5485DFE_defconfig
+++ b/configs/M5485DFE_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5485EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485DFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/M5485EFE_defconfig b/configs/M5485EFE_defconfig
index 4e84828f48..9504b26090 100644
--- a/configs/M5485EFE_defconfig
+++ b/configs/M5485EFE_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5485EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485EFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/M5485FFE_defconfig b/configs/M5485FFE_defconfig
index f6264e8c5e..f2bc3a0cb0 100644
--- a/configs/M5485FFE_defconfig
+++ b/configs/M5485FFE_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5485EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485FFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/M5485GFE_defconfig b/configs/M5485GFE_defconfig
index 9a589e0ae2..43ddd41b54 100644
--- a/configs/M5485GFE_defconfig
+++ b/configs/M5485GFE_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5485EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485GFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/M5485HFE_defconfig b/configs/M5485HFE_defconfig
index edc50c8f53..820d5aadd5 100644
--- a/configs/M5485HFE_defconfig
+++ b/configs/M5485HFE_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_TARGET_M5485EVB=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485HFE"
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/amcore_defconfig b/configs/amcore_defconfig
index 43e71cd6c2..de56175e17 100644
--- a/configs/amcore_defconfig
+++ b/configs/amcore_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFFC00000
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_TARGET_AMCORE=y
+CONFIG_DEFAULT_DEVICE_TREE="amcore"
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig
index 230c4cb921..6d72beca7c 100644
--- a/configs/astro_mcf5373l_defconfig
+++ b/configs/astro_mcf5373l_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_TARGET_ASTRO_MCF5373L=y
+CONFIG_DEFAULT_DEVICE_TREE="astro_mcf5373l"
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS=" console=ttyS2,115200 rootfstype=romfs loaderversion=$loaderversion"
diff --git a/configs/cobra5272_defconfig b/configs/cobra5272_defconfig
index fc295af114..7b9c6c6608 100644
--- a/configs/cobra5272_defconfig
+++ b/configs/cobra5272_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_TARGET_COBRA5272=y
+CONFIG_DEFAULT_DEVICE_TREE="cobra5272"
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig
index 3632706f33..8d3106edcc 100644
--- a/configs/eb_cpu5282_defconfig
+++ b/configs/eb_cpu5282_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF000000
CONFIG_TARGET_EB_CPU5282=y
+CONFIG_DEFAULT_DEVICE_TREE="eb_cpu5282"
CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xFF000400"
CONFIG_BOOTDELAY=5
# CONFIG_CONSOLE_MUX is not set
diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig
index 73c6744e7f..e3240c1f82 100644
--- a/configs/eb_cpu5282_internal_defconfig
+++ b/configs/eb_cpu5282_internal_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xF0000000
CONFIG_TARGET_EB_CPU5282=y
+CONFIG_DEFAULT_DEVICE_TREE="eb_cpu5282_internal"
CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xF0000418"
CONFIG_BOOTDELAY=5
# CONFIG_CONSOLE_MUX is not set
diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig
index 2d9173a3d3..f69fe5bc86 100644
--- a/configs/stmark2_defconfig
+++ b/configs/stmark2_defconfig
@@ -1,6 +1,7 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_TARGET_STMARK2=y
+CONFIG_DEFAULT_DEVICE_TREE="stmark2"
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=30000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v4 06/12] drivers: spi: cf_spi: add Kconfig option
2018-12-16 11:22 [U-Boot] [PATCH v4 01/12] m68k: add basic set of devicetrees Angelo Dureghello
` (3 preceding siblings ...)
2018-12-16 11:22 ` [U-Boot] [PATCH v4 05/12] configs: enable use of DT for all m68k boards Angelo Dureghello
@ 2018-12-16 11:22 ` Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 07/12] drivers: spi: cf_spi: convert to driver model Angelo Dureghello
` (5 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Angelo Dureghello @ 2018-12-16 11:22 UTC (permalink / raw)
To: u-boot
This patch adds cf_spi DM Kconfig option.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
---
Changes for v2:
- new patch
Changes for v3:
- re-put SOFT_SPI in place, options are out of alphabetical order
Changes for v4:
- none
---
drivers/spi/Kconfig | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index a7bb5b35c2..9057abcd32 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -87,6 +87,12 @@ config CADENCE_QSPI
used to access the SPI NOR flash on platforms embedding this
Cadence IP core.
+config CF_SPI
+ bool "ColdFire SPI driver"
+ help
+ Enable the ColdFire SPI driver. This driver can be used on
+ some m68k SoCs.
+
config DESIGNWARE_SPI
bool "Designware SPI driver"
help
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v4 07/12] drivers: spi: cf_spi: convert to driver model
2018-12-16 11:22 [U-Boot] [PATCH v4 01/12] m68k: add basic set of devicetrees Angelo Dureghello
` (4 preceding siblings ...)
2018-12-16 11:22 ` [U-Boot] [PATCH v4 06/12] drivers: spi: cf_spi: add Kconfig option Angelo Dureghello
@ 2018-12-16 11:22 ` Angelo Dureghello
2019-03-08 6:00 ` Jagan Teki
2018-12-16 11:22 ` [U-Boot] [PATCH v4 08/12] configs: add DM_SPI config option Angelo Dureghello
` (4 subsequent siblings)
10 siblings, 1 reply; 15+ messages in thread
From: Angelo Dureghello @ 2018-12-16 11:22 UTC (permalink / raw)
To: u-boot
Converting to driver model and removes non-dm code.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
---
Changes for v2:
- removed non DM code part
- add default setup of CTAR registers
- add DT CTAR register setup support
Changes for v3:
- changed commit head
- removed spi_slave reference
- add #ifdefs for the case OF_PLATDATA is used
Changes for v4:
- remove all internal static functions that are no more needed including
their code in the standard driver methods
- add helper macro for ctrl setup
- fix wrong fifo level check on spi tx
- move code inside same #if (avoid multiple #if on same option)
- removed externals and moved bus control code here
---
drivers/spi/cf_spi.c | 539 ++++++++++++++++--------
include/dm/platform_data/spi_coldfire.h | 29 ++
2 files changed, 401 insertions(+), 167 deletions(-)
create mode 100644 include/dm/platform_data/spi_coldfire.h
diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c
index 522631cbbf..3d02c87637 100644
--- a/drivers/spi/cf_spi.c
+++ b/drivers/spi/cf_spi.c
@@ -6,23 +6,31 @@
*
* Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew at freescale.com)
+ *
+ * Support for DM and DT, non-DM code removed.
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ *
+ * TODO: fsl_dspi.c should work as a driver for the DSPI module.
*/
#include <common.h>
+#include <dm.h>
+#include <dm/platform_data/spi_coldfire.h>
#include <spi.h>
#include <malloc.h>
+#include <wait_bit.h>
+#include <asm/coldfire/dspi.h>
#include <asm/immap.h>
+#include <asm/io.h>
-struct cf_spi_slave {
- struct spi_slave slave;
+struct coldfire_spi_priv {
+ struct dspi *regs;
+ struct gpio *gpio_regs;
uint baudrate;
+ int mode;
int charbit;
};
-extern void cfspi_port_conf(void);
-extern int cfspi_claim_bus(uint bus, uint cs);
-extern void cfspi_release_bus(uint bus, uint cs);
-
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SPI_IDLE_VAL
@@ -33,149 +41,267 @@ DECLARE_GLOBAL_DATA_PTR;
#endif
#endif
-#if defined(CONFIG_CF_DSPI)
/* DSPI specific mode */
#define SPI_MODE_MOD 0x00200000
#define SPI_DBLRATE 0x00100000
-static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave)
+#define MCF_DSPI_MAX_CTAR_REGS 8
+
+/* Default values */
+#define MCF_DSPI_DEFAULT_SCK_FREQ 10000000
+#define MCF_DSPI_DEFAULT_MAX_CS 4
+#define MCF_DSPI_DEFAULT_MODE 0
+
+#define MCF_DSPI_DEFAULT_CTAR (DSPI_CTAR_TRSZ(7) | \
+ DSPI_CTAR_PCSSCK_1CLK | \
+ DSPI_CTAR_PASC(0) | \
+ DSPI_CTAR_PDT(0) | \
+ DSPI_CTAR_CSSCK(0) | \
+ DSPI_CTAR_ASC(0) | \
+ DSPI_CTAR_DT(1) | \
+ DSPI_CTAR_BR(6))
+
+#define setup_ctrl(ctrl, cs) ((ctrl & 0xFF000000) | ((1 << cs) << 16))
+
+static inline void cfspi_tx(struct coldfire_spi_priv *cfspi,
+ u32 ctrl, u16 data)
{
- return container_of(slave, struct cf_spi_slave, slave);
+ /*
+ * Need to check fifo level here
+ */
+ while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 0x4000)
+ ;
+
+ writel(ctrl | data, &cfspi->regs->tfr);
}
-static void cfspi_init(void)
+static inline u16 cfspi_rx(struct coldfire_spi_priv *cfspi)
{
- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-
- cfspi_port_conf(); /* port configuration */
+ while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0)
+ ;
- dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
- DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
- DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
- DSPI_MCR_CRXF | DSPI_MCR_CTXF;
+ return readw(&cfspi->regs->rfr);
+}
- /* Default setting in platform configuration */
-#ifdef CONFIG_SYS_DSPI_CTAR0
- dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0;
-#endif
-#ifdef CONFIG_SYS_DSPI_CTAR1
- dspi->ctar[1] = CONFIG_SYS_DSPI_CTAR1;
-#endif
-#ifdef CONFIG_SYS_DSPI_CTAR2
- dspi->ctar[2] = CONFIG_SYS_DSPI_CTAR2;
-#endif
-#ifdef CONFIG_SYS_DSPI_CTAR3
- dspi->ctar[3] = CONFIG_SYS_DSPI_CTAR3;
-#endif
-#ifdef CONFIG_SYS_DSPI_CTAR4
- dspi->ctar[4] = CONFIG_SYS_DSPI_CTAR4;
+static int coldfire_spi_claim_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev->parent;
+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+ struct dspi *dspi = cfspi->regs;
+#if defined(CONFIG_MCF5445x) || \
+ defined(CONFIG_MCF5441x) || defined(CONFIG_MCF5227x)
+ struct dm_spi_slave_platdata *slave_plat =
+ dev_get_parent_platdata(dev);
+ struct gpio *gpio = cfspi->gpio_regs;
#endif
-#ifdef CONFIG_SYS_DSPI_CTAR5
- dspi->ctar[5] = CONFIG_SYS_DSPI_CTAR5;
+
+ if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
+ return -1;
+
+ /* Clear FIFO and resume transfer */
+ clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+
+#ifdef CONFIG_MCF5445x
+ switch (slave_plat->cs) {
+ case 0:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+ setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+ break;
+ case 1:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
+ setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
+ break;
+ case 2:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
+ setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
+ break;
+ case 3:
+ clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
+ setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
+ break;
+ case 5:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
+ setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
+ break;
+ }
#endif
-#ifdef CONFIG_SYS_DSPI_CTAR6
- dspi->ctar[6] = CONFIG_SYS_DSPI_CTAR6;
+
+#ifdef CONFIG_MCF5441x
+ switch (slave_plat->cs) {
+ case 0:
+ clrbits_8(&gpio->par_dspi0, ~GPIO_PAR_DSPI0_PCS0_MASK);
+ setbits_8(&gpio->par_dspi0, GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
+ break;
+ case 1:
+ clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
+ setbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
+ break;
+ }
#endif
-#ifdef CONFIG_SYS_DSPI_CTAR7
- dspi->ctar[7] = CONFIG_SYS_DSPI_CTAR7;
+
+#ifdef CONFIG_MCF5227x
+ switch (slave_plat->cs) {
+ case 0:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
+ setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+ break;
+ case 2:
+ clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
+ setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
+ break;
+ }
#endif
+ return 0;
}
-static void cfspi_tx(u32 ctrl, u16 data)
+static int coldfire_spi_release_bus(struct udevice *dev)
{
- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-
- while ((dspi->sr & 0x0000F000) >= 4) ;
-
- dspi->tfr = (ctrl | data);
-}
+ struct udevice *bus = dev->parent;
+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+ struct dspi *dspi = cfspi->regs;
+#if defined(CONFIG_MCF5445x) || \
+ defined(CONFIG_MCF5441x) || defined(CONFIG_MCF5227x)
+ struct dm_spi_slave_platdata *slave_plat =
+ dev_get_parent_platdata(dev);
+ struct gpio *gpio = cfspi->gpio_regs;
+#endif
-static u16 cfspi_rx(void)
-{
- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+ /* Clear FIFO */
+ clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+
+#ifdef CONFIG_MCF5445x
+ switch (slave_plat->cs) {
+ case 0:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+ break;
+ case 1:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
+ break;
+ case 2:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
+ break;
+ case 3:
+ clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
+ break;
+ case 5:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
+ break;
+ }
+#endif
- while ((dspi->sr & 0x000000F0) == 0) ;
+#ifdef CONFIG_MCF5441x
+ if (slave_plat->cs == 1)
+ clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
+#endif
- return (dspi->rfr & 0xFFFF);
+#ifdef CONFIG_MCF5227x
+ switch (slave_plat->cs) {
+ case 0:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+ break;
+ case 2:
+ clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
+ break;
+ }
+#endif
+ return 0;
}
-static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
- void *din, ulong flags)
+static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din,
+ unsigned long flags)
{
- struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
+ struct udevice *bus = dev_get_parent(dev);
+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
u8 *spi_rd = NULL, *spi_wr = NULL;
- static u32 ctrl = 0;
+ static u32 ctrl;
uint len = bitlen >> 3;
- if (cfslave->charbit == 16) {
+ if (cfspi->charbit == 16) {
bitlen >>= 1;
- spi_wr16 = (u16 *) dout;
- spi_rd16 = (u16 *) din;
+ spi_wr16 = (u16 *)dout;
+ spi_rd16 = (u16 *)din;
} else {
- spi_wr = (u8 *) dout;
- spi_rd = (u8 *) din;
+ spi_wr = (u8 *)dout;
+ spi_rd = (u8 *)din;
}
if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
ctrl |= DSPI_TFR_CONT;
- ctrl = (ctrl & 0xFF000000) | ((1 << slave->cs) << 16);
+ ctrl = setup_ctrl(ctrl, slave_plat->cs);
if (len > 1) {
int tmp_len = len - 1;
+
while (tmp_len--) {
- if (dout != NULL) {
- if (cfslave->charbit == 16)
- cfspi_tx(ctrl, *spi_wr16++);
+ if (dout) {
+ if (cfspi->charbit == 16)
+ cfspi_tx(cfspi, ctrl, *spi_wr16++);
else
- cfspi_tx(ctrl, *spi_wr++);
- cfspi_rx();
+ cfspi_tx(cfspi, ctrl, *spi_wr++);
+ cfspi_rx(cfspi);
}
- if (din != NULL) {
- cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
- if (cfslave->charbit == 16)
- *spi_rd16++ = cfspi_rx();
+ if (din) {
+ cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
+ if (cfspi->charbit == 16)
+ *spi_rd16++ = cfspi_rx(cfspi);
else
- *spi_rd++ = cfspi_rx();
+ *spi_rd++ = cfspi_rx(cfspi);
}
}
len = 1; /* remaining byte */
}
- if ((flags & SPI_XFER_END) == SPI_XFER_END)
+ if (flags & SPI_XFER_END)
ctrl &= ~DSPI_TFR_CONT;
if (len) {
- if (dout != NULL) {
- if (cfslave->charbit == 16)
- cfspi_tx(ctrl, *spi_wr16);
+ if (dout) {
+ if (cfspi->charbit == 16)
+ cfspi_tx(cfspi, ctrl, *spi_wr16);
else
- cfspi_tx(ctrl, *spi_wr);
- cfspi_rx();
+ cfspi_tx(cfspi, ctrl, *spi_wr);
+ cfspi_rx(cfspi);
}
- if (din != NULL) {
- cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
- if (cfslave->charbit == 16)
- *spi_rd16 = cfspi_rx();
+ if (din) {
+ cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
+ if (cfspi->charbit == 16)
+ *spi_rd16 = cfspi_rx(cfspi);
else
- *spi_rd = cfspi_rx();
+ *spi_rd = cfspi_rx(cfspi);
}
} else {
/* dummy read */
- cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
- cfspi_rx();
+ cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
+ cfspi_rx(cfspi);
}
return 0;
}
-static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
- uint mode)
+static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz)
{
+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+ struct dspi *dspi = cfspi->regs;
+ int prescaler[] = { 2, 3, 5, 7 };
+ int scaler[] = {
+ 2, 4, 6, 8,
+ 16, 32, 64, 128,
+ 256, 512, 1024, 2048,
+ 4096, 8192, 16384, 32768
+ };
+ int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
+ int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed;
+ u32 bus_setup;
+
+ cfspi->baudrate = max_hz;
+
/*
* bit definition for mode:
* bit 31 - 28: Transfer size 3 to 16 bits
@@ -189,66 +315,37 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
* 11 - 8: Delay after transfer scaler
* 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
*/
- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- int prescaler[] = { 2, 3, 5, 7 };
- int scaler[] = {
- 2, 4, 6, 8,
- 16, 32, 64, 128,
- 256, 512, 1024, 2048,
- 4096, 8192, 16384, 32768
- };
- int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
- int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed;
- u32 bus_setup = 0;
+
+ /* Read current setup */
+ bus_setup = readl(&dspi->ctar[bus->seq]);
tmp = (prescaler[3] * scaler[15]);
/* Maximum and minimum baudrate it can handle */
- if ((cfslave->baudrate > (gd->bus_clk >> 1)) ||
- (cfslave->baudrate < (gd->bus_clk / tmp))) {
+ if ((cfspi->baudrate > (gd->bus_clk >> 1)) ||
+ (cfspi->baudrate < (gd->bus_clk / tmp))) {
printf("Exceed baudrate limitation: Max %d - Min %d\n",
(int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
- return NULL;
+ return -1;
}
/* Activate Double Baud when it exceed 1/4 the bus clk */
- if ((CONFIG_SYS_DSPI_CTAR0 & DSPI_CTAR_DBR) ||
- (cfslave->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
+ if ((bus_setup & DSPI_CTAR_DBR) ||
+ (cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
bus_setup |= DSPI_CTAR_DBR;
dbr = 1;
}
- if (mode & SPI_CPOL)
- bus_setup |= DSPI_CTAR_CPOL;
- if (mode & SPI_CPHA)
- bus_setup |= DSPI_CTAR_CPHA;
- if (mode & SPI_LSB_FIRST)
- bus_setup |= DSPI_CTAR_LSBFE;
-
/* Overwrite default value set in platform configuration file */
- if (mode & SPI_MODE_MOD) {
-
- if ((mode & 0xF0000000) == 0)
- bus_setup |=
- dspi->ctar[cfslave->slave.bus] & 0x78000000;
- else
- bus_setup |= ((mode & 0xF0000000) >> 1);
-
+ if (cfspi->mode & SPI_MODE_MOD) {
/*
* Check to see if it is enabled by default in platform
* config, or manual setting passed by mode parameter
*/
- if (mode & SPI_DBLRATE) {
+ if (cfspi->mode & SPI_DBLRATE) {
bus_setup |= DSPI_CTAR_DBR;
dbr = 1;
}
- bus_setup |= (mode & 0x0FC00000) >> 4; /* PSCSCK, PASC, PDT */
- bus_setup |= (mode & 0x000FFF00) >> 4; /* CSSCK, ASC, DT */
- } else
- bus_setup |= (dspi->ctar[cfslave->slave.bus] & 0x78FCFFF0);
-
- cfslave->charbit =
- ((dspi->ctar[cfslave->slave.bus] & 0x78000000) ==
- 0x78000000) ? 16 : 8;
+ }
pbrcnt = sizeof(prescaler) / sizeof(int);
brcnt = sizeof(scaler) / sizeof(int);
@@ -259,10 +356,10 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
for (j = 0; j < brcnt; j++) {
tmp = (baud_speed / scaler[j]) * (1 + dbr);
- if (tmp > cfslave->baudrate)
- diff = tmp - cfslave->baudrate;
+ if (tmp > cfspi->baudrate)
+ diff = tmp - cfspi->baudrate;
else
- diff = cfslave->baudrate - tmp;
+ diff = cfspi->baudrate - tmp;
if (diff < bestmatch) {
bestmatch = diff;
@@ -271,65 +368,173 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
}
}
}
+
+ bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f));
bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
- dspi->ctar[cfslave->slave.bus] = bus_setup;
+ writel(bus_setup, &dspi->ctar[bus->seq]);
- return &cfslave->slave;
+ return 0;
}
-#endif /* CONFIG_CF_DSPI */
-#ifdef CONFIG_CMD_SPI
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+static int coldfire_spi_set_mode(struct udevice *bus, uint mode)
{
- if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8)))
- return 1;
- else
- return 0;
-}
+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+ struct dspi *dspi = cfspi->regs;
+ u32 bus_setup = 0;
-void spi_init(void)
-{
- cfspi_init();
-}
+ cfspi->mode = mode;
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct cf_spi_slave *cfslave;
+ if (cfspi->mode & SPI_CPOL)
+ bus_setup |= DSPI_CTAR_CPOL;
+ if (cfspi->mode & SPI_CPHA)
+ bus_setup |= DSPI_CTAR_CPHA;
+ if (cfspi->mode & SPI_LSB_FIRST)
+ bus_setup |= DSPI_CTAR_LSBFE;
+
+ /* Overwrite default value set in platform configuration file */
+ if (cfspi->mode & SPI_MODE_MOD) {
+ if ((cfspi->mode & 0xF0000000) == 0)
+ bus_setup |=
+ readl(&dspi->ctar[bus->seq]) & 0x78000000;
+ else
+ bus_setup |= ((cfspi->mode & 0xF0000000) >> 1);
- if (!spi_cs_is_valid(bus, cs))
- return NULL;
+ /* PSCSCK, PASC, PDT */
+ bus_setup |= (cfspi->mode & 0x0FC00000) >> 4;
+ /* CSSCK, ASC, DT */
+ bus_setup |= (cfspi->mode & 0x000FFF00) >> 4;
+ } else {
+ bus_setup |= (readl(&dspi->ctar[bus->seq]) & 0x78FCFFF0);
+ }
- cfslave = spi_alloc_slave(struct cf_spi_slave, bus, cs);
- if (!cfslave)
- return NULL;
+ cfspi->charbit =
+ ((readl(&dspi->ctar[bus->seq]) & 0x78000000) ==
+ 0x78000000) ? 16 : 8;
- cfslave->baudrate = max_hz;
+ setbits_be32(&dspi->ctar[bus->seq], bus_setup);
- /* specific setup */
- return cfspi_setup_slave(cfslave, mode);
+ return 0;
}
-void spi_free_slave(struct spi_slave *slave)
+static int coldfire_spi_probe(struct udevice *bus)
{
- struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
+ struct coldfire_spi_platdata *plat = dev_get_platdata(bus);
+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+ struct dspi *dspi = cfspi->regs;
+ int i;
- free(cfslave);
-}
+ cfspi->regs = (struct dspi *)plat->regs_addr;
+ cfspi->gpio_regs = (struct gpio *)MMAP_GPIO;
-int spi_claim_bus(struct spi_slave *slave)
-{
- return cfspi_claim_bus(slave->bus, slave->cs);
+ cfspi->baudrate = plat->speed_hz;
+ cfspi->mode = plat->mode;
+
+ for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) {
+ unsigned int ctar = 0;
+
+ if (plat->ctar[i][0] == 0)
+ break;
+
+ ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) |
+ DSPI_CTAR_PCSSCK(plat->ctar[i][1]) |
+ DSPI_CTAR_PASC(plat->ctar[i][2]) |
+ DSPI_CTAR_PDT(plat->ctar[i][3]) |
+ DSPI_CTAR_CSSCK(plat->ctar[i][4]) |
+ DSPI_CTAR_ASC(plat->ctar[i][5]) |
+ DSPI_CTAR_DT(plat->ctar[i][6]) |
+ DSPI_CTAR_BR(plat->ctar[i][7]);
+
+ writel(ctar, &cfspi->regs->ctar[i]);
+ }
+
+ /* Default CTARs */
+ for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++)
+ writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]);
+
+ dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
+ DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
+ DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
+ DSPI_MCR_CRXF | DSPI_MCR_CTXF;
+
+ return 0;
}
-void spi_release_bus(struct spi_slave *slave)
+void spi_init(void)
{
- cfspi_release_bus(slave->bus, slave->cs);
}
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+static int coldfire_dspi_ofdata_to_platdata(struct udevice *bus)
{
- return cfspi_xfer(slave, bitlen, dout, din, flags);
+ fdt_addr_t addr;
+ struct coldfire_spi_platdata *plat = bus->platdata;
+ const void *blob = gd->fdt_blob;
+ int node = dev_of_offset(bus);
+ int *ctar, len;
+
+ addr = devfdt_get_addr(bus);
+ if (addr == FDT_ADDR_T_NONE)
+ return -ENOMEM;
+
+ plat->regs_addr = addr;
+
+ plat->num_cs = fdtdec_get_int(blob, node, "num-cs",
+ MCF_DSPI_DEFAULT_MAX_CS);
+
+ plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
+ MCF_DSPI_DEFAULT_SCK_FREQ);
+
+ plat->mode = fdtdec_get_int(blob, node, "spi-mode",
+ MCF_DSPI_DEFAULT_MODE);
+
+ memset(plat->ctar, 0, sizeof(plat->ctar));
+
+ ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len);
+
+ if (ctar && len) {
+ int i, q, ctar_regs;
+
+ ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS;
+
+ if (ctar_regs > MAX_CTAR_REGS)
+ ctar_regs = MAX_CTAR_REGS;
+
+ for (i = 0; i < ctar_regs; i++) {
+ for (q = 0; q < MAX_CTAR_FIELDS; q++)
+ plat->ctar[i][q] = *ctar++;
+ }
+ }
+
+ debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n",
+ (void *)plat->regs_addr,
+ plat->speed_hz, plat->num_cs, plat->mode);
+
+ return 0;
}
-#endif /* CONFIG_CMD_SPI */
+
+static const struct udevice_id coldfire_spi_ids[] = {
+ { .compatible = "fsl,mcf-dspi" },
+ { }
+};
+#endif
+
+static const struct dm_spi_ops coldfire_spi_ops = {
+ .claim_bus = coldfire_spi_claim_bus,
+ .release_bus = coldfire_spi_release_bus,
+ .xfer = coldfire_spi_xfer,
+ .set_speed = coldfire_spi_set_speed,
+ .set_mode = coldfire_spi_set_mode,
+};
+
+U_BOOT_DRIVER(coldfire_spi) = {
+ .name = "spi_coldfire",
+ .id = UCLASS_SPI,
+ .probe = coldfire_spi_probe,
+ .ops = &coldfire_spi_ops,
+ .platdata_auto_alloc_size = sizeof(struct coldfire_spi_platdata),
+ .priv_auto_alloc_size = sizeof(struct coldfire_spi_priv),
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .of_match = coldfire_spi_ids,
+ .ofdata_to_platdata = coldfire_dspi_ofdata_to_platdata,
+#endif
+};
diff --git a/include/dm/platform_data/spi_coldfire.h b/include/dm/platform_data/spi_coldfire.h
new file mode 100644
index 0000000000..8ad8eaedfd
--- /dev/null
+++ b/include/dm/platform_data/spi_coldfire.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+#ifndef __spi_coldfire_h
+#define __spi_coldfire_h
+
+#define MAX_CTAR_REGS 8
+#define MAX_CTAR_FIELDS 8
+
+/*
+ * struct coldfire_spi_platdata - information about a coldfire spi module
+ *
+ * @regs_addr: base address for module registers
+ * @speed_hz: default SCK frequency
+ * @mode: default SPI mode
+ * @num_cs: number of DSPI chipselect signals
+ */
+struct coldfire_spi_platdata {
+ fdt_addr_t regs_addr;
+ uint speed_hz;
+ uint mode;
+ uint num_cs;
+ uint ctar[MAX_CTAR_REGS][MAX_CTAR_FIELDS];
+};
+
+#endif /* __spi_coldfire_h */
+
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v4 08/12] configs: add DM_SPI config option
2018-12-16 11:22 [U-Boot] [PATCH v4 01/12] m68k: add basic set of devicetrees Angelo Dureghello
` (5 preceding siblings ...)
2018-12-16 11:22 ` [U-Boot] [PATCH v4 07/12] drivers: spi: cf_spi: convert to driver model Angelo Dureghello
@ 2018-12-16 11:22 ` Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 09/12] drivers: serial: mcfuart: add DT support Angelo Dureghello
` (3 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Angelo Dureghello @ 2018-12-16 11:22 UTC (permalink / raw)
To: u-boot
This patch adds CONFIG_DM_SPI for all m68k boards using
the cf_spi.c driver (DSPI module).
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
---
Changes for v2:
- new patch
Changes for v3:
- none
Changes for v4:
- none
---
configs/M52277EVB_defconfig | 1 +
configs/M52277EVB_stmicro_defconfig | 1 +
configs/M54418TWR_defconfig | 1 +
configs/M54418TWR_nand_mii_defconfig | 1 +
configs/M54418TWR_nand_rmii_defconfig | 1 +
configs/M54418TWR_nand_rmii_lowfreq_defconfig | 1 +
configs/M54418TWR_serial_mii_defconfig | 1 +
configs/M54418TWR_serial_rmii_defconfig | 1 +
configs/M54451EVB_defconfig | 1 +
configs/M54451EVB_stmicro_defconfig | 1 +
configs/M54455EVB_a66_defconfig | 1 +
configs/M54455EVB_defconfig | 1 +
configs/M54455EVB_i66_defconfig | 1 +
configs/M54455EVB_intel_defconfig | 1 +
configs/M54455EVB_stm33_defconfig | 1 +
configs/stmark2_defconfig | 2 ++
16 files changed, 17 insertions(+)
diff --git a/configs/M52277EVB_defconfig b/configs/M52277EVB_defconfig
index 87d5e852f0..bc7b051239 100644
--- a/configs/M52277EVB_defconfig
+++ b/configs/M52277EVB_defconfig
@@ -26,4 +26,5 @@ CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
diff --git a/configs/M52277EVB_stmicro_defconfig b/configs/M52277EVB_stmicro_defconfig
index ed24d3e11d..c76ff5fb3a 100644
--- a/configs/M52277EVB_stmicro_defconfig
+++ b/configs/M52277EVB_stmicro_defconfig
@@ -25,4 +25,5 @@ CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
diff --git a/configs/M54418TWR_defconfig b/configs/M54418TWR_defconfig
index 3b35bcec4f..7713f266bb 100644
--- a/configs/M54418TWR_defconfig
+++ b/configs/M54418TWR_defconfig
@@ -26,3 +26,4 @@ CONFIG_SPI_FLASH_ATMEL=y
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_CF_SPI=y
+CONFIG_DM_SPI=y
diff --git a/configs/M54418TWR_nand_mii_defconfig b/configs/M54418TWR_nand_mii_defconfig
index c53c9d4512..1c2d337367 100644
--- a/configs/M54418TWR_nand_mii_defconfig
+++ b/configs/M54418TWR_nand_mii_defconfig
@@ -24,4 +24,5 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
diff --git a/configs/M54418TWR_nand_rmii_defconfig b/configs/M54418TWR_nand_rmii_defconfig
index 822d34928a..29d891b073 100644
--- a/configs/M54418TWR_nand_rmii_defconfig
+++ b/configs/M54418TWR_nand_rmii_defconfig
@@ -24,4 +24,5 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
diff --git a/configs/M54418TWR_nand_rmii_lowfreq_defconfig b/configs/M54418TWR_nand_rmii_lowfreq_defconfig
index dda2864e18..4881076757 100644
--- a/configs/M54418TWR_nand_rmii_lowfreq_defconfig
+++ b/configs/M54418TWR_nand_rmii_lowfreq_defconfig
@@ -24,4 +24,5 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
diff --git a/configs/M54418TWR_serial_mii_defconfig b/configs/M54418TWR_serial_mii_defconfig
index 25d8c4c72c..95949fec76 100644
--- a/configs/M54418TWR_serial_mii_defconfig
+++ b/configs/M54418TWR_serial_mii_defconfig
@@ -25,4 +25,5 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
diff --git a/configs/M54418TWR_serial_rmii_defconfig b/configs/M54418TWR_serial_rmii_defconfig
index 29490e2faa..229f1d45d3 100644
--- a/configs/M54418TWR_serial_rmii_defconfig
+++ b/configs/M54418TWR_serial_rmii_defconfig
@@ -25,4 +25,5 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
diff --git a/configs/M54451EVB_defconfig b/configs/M54451EVB_defconfig
index 067eaa1369..c85b476089 100644
--- a/configs/M54451EVB_defconfig
+++ b/configs/M54451EVB_defconfig
@@ -31,4 +31,5 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
diff --git a/configs/M54451EVB_stmicro_defconfig b/configs/M54451EVB_stmicro_defconfig
index 95b54612c9..36393c50fe 100644
--- a/configs/M54451EVB_stmicro_defconfig
+++ b/configs/M54451EVB_stmicro_defconfig
@@ -30,4 +30,5 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
diff --git a/configs/M54455EVB_a66_defconfig b/configs/M54455EVB_a66_defconfig
index e131460ca9..9cfd1f896c 100644
--- a/configs/M54455EVB_a66_defconfig
+++ b/configs/M54455EVB_a66_defconfig
@@ -35,4 +35,5 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
diff --git a/configs/M54455EVB_defconfig b/configs/M54455EVB_defconfig
index cda5702f07..8d0f9bf54f 100644
--- a/configs/M54455EVB_defconfig
+++ b/configs/M54455EVB_defconfig
@@ -36,4 +36,5 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
diff --git a/configs/M54455EVB_i66_defconfig b/configs/M54455EVB_i66_defconfig
index 701f746b15..d47a20a73a 100644
--- a/configs/M54455EVB_i66_defconfig
+++ b/configs/M54455EVB_i66_defconfig
@@ -35,4 +35,5 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
diff --git a/configs/M54455EVB_intel_defconfig b/configs/M54455EVB_intel_defconfig
index eaa46842b5..b90dad72c1 100644
--- a/configs/M54455EVB_intel_defconfig
+++ b/configs/M54455EVB_intel_defconfig
@@ -35,4 +35,5 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
diff --git a/configs/M54455EVB_stm33_defconfig b/configs/M54455EVB_stm33_defconfig
index 6e08f91894..333be173a8 100644
--- a/configs/M54455EVB_stm33_defconfig
+++ b/configs/M54455EVB_stm33_defconfig
@@ -35,4 +35,5 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig
index f69fe5bc86..e67136c745 100644
--- a/configs/stmark2_defconfig
+++ b/configs/stmark2_defconfig
@@ -33,5 +33,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_CF_SPI=y
CONFIG_REGEX=y
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v4 09/12] drivers: serial: mcfuart: add DT support
2018-12-16 11:22 [U-Boot] [PATCH v4 01/12] m68k: add basic set of devicetrees Angelo Dureghello
` (6 preceding siblings ...)
2018-12-16 11:22 ` [U-Boot] [PATCH v4 08/12] configs: add DM_SPI config option Angelo Dureghello
@ 2018-12-16 11:22 ` Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 10/12] configs: remove CONFIG_SYS_DSPI_XX references Angelo Dureghello
` (2 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Angelo Dureghello @ 2018-12-16 11:22 UTC (permalink / raw)
To: u-boot
This patch adds devicetree support to the mcfuart.c driver
and removes non DM code.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
---
Changes for v2:
- remove non DM code
Changes for v3:
- none
Changes for v4:
- none
---
drivers/serial/Kconfig | 8 +++
drivers/serial/mcfuart.c | 106 +++++++++++----------------------------
2 files changed, 36 insertions(+), 78 deletions(-)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 6252dd8c4b..bf2e345964 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -530,6 +530,14 @@ config MVEBU_A3700_UART
Choose this option to add support for UART driver on the Marvell
Armada 3700 SoC. The base address is configured via DT.
+config MCFUART
+ bool "Freescale ColdFire UART support"
+ help
+ Choose this option to add support for UART driver on the ColdFire
+ SoC's family. The serial communication channel provides a full-duplex
+ asynchronous/synchronous receiver and transmitter deriving an
+ operating frequency from the internal bus clock or an external clock.
+
config MXC_UART
bool "IMX serial port support"
depends on MX5 || MX6
diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c
index 1371049de2..066e5a18d8 100644
--- a/drivers/serial/mcfuart.c
+++ b/drivers/serial/mcfuart.c
@@ -5,6 +5,9 @@
*
* Modified to add device model (DM) support
* (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
+ *
+ * Modified to add DM and fdt support, removed non DM code
+ * (C) Copyright 2018 Angelo Dureghello <angelo@sysam.it>
*/
/*
@@ -78,83 +81,6 @@ static void mcf_serial_setbrg_common(uart_t *uart, int baudrate)
writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
}
-#ifndef CONFIG_DM_SERIAL
-
-static int mcf_serial_init(void)
-{
- uart_t *uart_base;
- int port_idx;
-
- uart_base = (uart_t *)CONFIG_SYS_UART_BASE;
- port_idx = CONFIG_SYS_UART_PORT;
-
- return mcf_serial_init_common(uart_base, port_idx, gd->baudrate);
-}
-
-static void mcf_serial_putc(const char c)
-{
- uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
-
- if (c == '\n')
- serial_putc('\r');
-
- /* Wait for last character to go. */
- while (!(readb(&uart->usr) & UART_USR_TXRDY))
- ;
-
- writeb(c, &uart->utb);
-}
-
-static int mcf_serial_getc(void)
-{
- uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
-
- /* Wait for a character to arrive. */
- while (!(readb(&uart->usr) & UART_USR_RXRDY))
- ;
-
- return readb(&uart->urb);
-}
-
-static void mcf_serial_setbrg(void)
-{
- uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
-
- mcf_serial_setbrg_common(uart, gd->baudrate);
-}
-
-static int mcf_serial_tstc(void)
-{
- uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
-
- return readb(&uart->usr) & UART_USR_RXRDY;
-}
-
-static struct serial_device mcf_serial_drv = {
- .name = "mcf_serial",
- .start = mcf_serial_init,
- .stop = NULL,
- .setbrg = mcf_serial_setbrg,
- .putc = mcf_serial_putc,
- .puts = default_serial_puts,
- .getc = mcf_serial_getc,
- .tstc = mcf_serial_tstc,
-};
-
-void mcf_serial_initialize(void)
-{
- serial_register(&mcf_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &mcf_serial_drv;
-}
-
-#endif
-
-#ifdef CONFIG_DM_SERIAL
-
static int coldfire_serial_probe(struct udevice *dev)
{
struct coldfire_serial_platdata *plat = dev->platdata;
@@ -212,6 +138,23 @@ static int coldfire_serial_pending(struct udevice *dev, bool input)
return 0;
}
+static int coldfire_ofdata_to_platdata(struct udevice *dev)
+{
+ struct coldfire_serial_platdata *plat = dev_get_platdata(dev);
+ fdt_addr_t addr_base;
+
+ addr_base = devfdt_get_addr(dev);
+ if (addr_base == FDT_ADDR_T_NONE)
+ return -ENODEV;
+
+ plat->base = (uint32_t)addr_base;
+
+ plat->port = dev->seq;
+ plat->baudrate = gd->baudrate;
+
+ return 0;
+}
+
static const struct dm_serial_ops coldfire_serial_ops = {
.putc = coldfire_serial_putc,
.pending = coldfire_serial_pending,
@@ -219,11 +162,18 @@ static const struct dm_serial_ops coldfire_serial_ops = {
.setbrg = coldfire_serial_setbrg,
};
+static const struct udevice_id coldfire_serial_ids[] = {
+ { .compatible = "fsl,mcf-uart" },
+ { }
+};
+
U_BOOT_DRIVER(serial_coldfire) = {
.name = "serial_coldfire",
.id = UCLASS_SERIAL,
+ .of_match = coldfire_serial_ids,
+ .ofdata_to_platdata = coldfire_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct coldfire_serial_platdata),
.probe = coldfire_serial_probe,
.ops = &coldfire_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
};
-#endif
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v4 10/12] configs: remove CONFIG_SYS_DSPI_XX references
2018-12-16 11:22 [U-Boot] [PATCH v4 01/12] m68k: add basic set of devicetrees Angelo Dureghello
` (7 preceding siblings ...)
2018-12-16 11:22 ` [U-Boot] [PATCH v4 09/12] drivers: serial: mcfuart: add DT support Angelo Dureghello
@ 2018-12-16 11:22 ` Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 11/12] m68k: add OF control support to m68k Angelo Dureghello
2018-12-16 11:23 ` [U-Boot] [PATCH v4 12/12] m68k: move dspi bus control functions into cf_spi.c driver Angelo Dureghello
10 siblings, 0 replies; 15+ messages in thread
From: Angelo Dureghello @ 2018-12-16 11:22 UTC (permalink / raw)
To: u-boot
This patch removes CONFIG_SYS_DSPI_XX options from
include/configs "m68k" .h board files, since CTAR
registers are now set with default values in the cf_spi
driver initialization, and configurable by devicetree.
Note, these options cannot be totally removed from the
whitelist, since still used from boards using fsl_dspi.c
(mostly arm-based boards).
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
---
Changes for v2:
- new patch
Changes for v3:
- none
Changes for v4:
- none
---
include/configs/M52277EVB.h | 11 -----------
include/configs/M54418TWR.h | 12 ------------
include/configs/M54451EVB.h | 12 ------------
include/configs/M54455EVB.h | 10 ----------
include/configs/stmark2.h | 11 -----------
5 files changed, 56 deletions(-)
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
index 83d774527a..b0e9a0f526 100644
--- a/include/configs/M52277EVB.h
+++ b/include/configs/M52277EVB.h
@@ -103,17 +103,6 @@
/* DSPI and Serial Flash */
#define CONFIG_CF_DSPI
#define CONFIG_SYS_SBFHDR_SIZE 0x7
-#ifdef CONFIG_CMD_SPI
-# define CONFIG_SYS_DSPI_CS2
-
-# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
- DSPI_CTAR_PCSSCK_1CLK | \
- DSPI_CTAR_PASC(0) | \
- DSPI_CTAR_PDT(0) | \
- DSPI_CTAR_CSSCK(0) | \
- DSPI_CTAR_ASC(0) | \
- DSPI_CTAR_DT(1))
-#endif
/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK
diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h
index 4b8ef38c0b..1426492c23 100644
--- a/include/configs/M54418TWR.h
+++ b/include/configs/M54418TWR.h
@@ -152,18 +152,6 @@
#define CONFIG_CF_DSPI
#define CONFIG_SERIAL_FLASH
#define CONFIG_SYS_SBFHDR_SIZE 0x7
-#ifdef CONFIG_CMD_SPI
-
-# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
- DSPI_CTAR_PCSSCK_1CLK | \
- DSPI_CTAR_PASC(0) | \
- DSPI_CTAR_PDT(0) | \
- DSPI_CTAR_CSSCK(0) | \
- DSPI_CTAR_ASC(0) | \
- DSPI_CTAR_DT(1))
-# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
-# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
-#endif
/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index 87cdbae1db..44fd8072fc 100644
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -117,18 +117,6 @@
#define CONFIG_CF_DSPI
#define CONFIG_SERIAL_FLASH
#define CONFIG_SYS_SBFHDR_SIZE 0x7
-#ifdef CONFIG_CMD_SPI
-
-# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
- DSPI_CTAR_PCSSCK_1CLK | \
- DSPI_CTAR_PASC(0) | \
- DSPI_CTAR_PDT(0) | \
- DSPI_CTAR_CSSCK(0) | \
- DSPI_CTAR_ASC(0) | \
- DSPI_CTAR_DT(1))
-# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
-# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
-#endif
/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index d41b7c4492..ea97188fe8 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -143,16 +143,6 @@
/* DSPI and Serial Flash */
#define CONFIG_CF_DSPI
#define CONFIG_SYS_SBFHDR_SIZE 0x13
-#ifdef CONFIG_CMD_SPI
-
-# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
- DSPI_CTAR_PCSSCK_1CLK | \
- DSPI_CTAR_PASC(0) | \
- DSPI_CTAR_PDT(0) | \
- DSPI_CTAR_CSSCK(0) | \
- DSPI_CTAR_ASC(0) | \
- DSPI_CTAR_DT(1))
-#endif
/* PCI */
#ifdef CONFIG_CMD_PCI
diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h
index f49e79c824..d16ed8f253 100644
--- a/include/configs/stmark2.h
+++ b/include/configs/stmark2.h
@@ -78,17 +78,6 @@
#define CONFIG_SYS_SBFHDR_SIZE 0x7
-#define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
- DSPI_CTAR_PCSSCK_1CLK | \
- DSPI_CTAR_PASC(0) | \
- DSPI_CTAR_PDT(0) | \
- DSPI_CTAR_CSSCK(0) | \
- DSPI_CTAR_ASC(0) | \
- DSPI_CTAR_DT(1) | \
- DSPI_CTAR_BR(6))
-#define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
-#define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
-
/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v4 11/12] m68k: add OF control support to m68k
2018-12-16 11:22 [U-Boot] [PATCH v4 01/12] m68k: add basic set of devicetrees Angelo Dureghello
` (8 preceding siblings ...)
2018-12-16 11:22 ` [U-Boot] [PATCH v4 10/12] configs: remove CONFIG_SYS_DSPI_XX references Angelo Dureghello
@ 2018-12-16 11:22 ` Angelo Dureghello
2018-12-16 11:23 ` [U-Boot] [PATCH v4 12/12] m68k: move dspi bus control functions into cf_spi.c driver Angelo Dureghello
10 siblings, 0 replies; 15+ messages in thread
From: Angelo Dureghello @ 2018-12-16 11:22 UTC (permalink / raw)
To: u-boot
Add SUPPORT_OF_CONTROL at this stage, to avoid to break build
bisectability.
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
---
Changes for v4:
- new patch
---
arch/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/Kconfig b/arch/Kconfig
index 35e2712fce..a8393b86e9 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -28,6 +28,7 @@ config M68K
select HAVE_PRIVATE_LIBGCC
select SYS_BOOT_GET_CMDLINE
select SYS_BOOT_GET_KBD
+ select SUPPORT_OF_CONTROL
config MICROBLAZE
bool "MicroBlaze architecture"
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v4 12/12] m68k: move dspi bus control functions into cf_spi.c driver
2018-12-16 11:22 [U-Boot] [PATCH v4 01/12] m68k: add basic set of devicetrees Angelo Dureghello
` (9 preceding siblings ...)
2018-12-16 11:22 ` [U-Boot] [PATCH v4 11/12] m68k: add OF control support to m68k Angelo Dureghello
@ 2018-12-16 11:23 ` Angelo Dureghello
10 siblings, 0 replies; 15+ messages in thread
From: Angelo Dureghello @ 2018-12-16 11:23 UTC (permalink / raw)
To: u-boot
This patches move dspi bus-related operations into more
proper location, to avoid the driver to declares them as externs.
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
---
Changes for v4:
- new patch
---
arch/m68k/cpu/mcf5227x/cpu_init.c | 65 +++-----------
arch/m68k/cpu/mcf5445x/cpu_init.c | 142 +++++++-----------------------
2 files changed, 41 insertions(+), 166 deletions(-)
diff --git a/arch/m68k/cpu/mcf5227x/cpu_init.c b/arch/m68k/cpu/mcf5227x/cpu_init.c
index 0d6a484a45..3bbc42f508 100644
--- a/arch/m68k/cpu/mcf5227x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5227x/cpu_init.c
@@ -16,6 +16,15 @@
#include <asm/rtc.h>
#include <linux/compiler.h>
+void cfspi_port_conf(void)
+{
+ gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
+ out_8(&gpio->par_dspi,
+ GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+ GPIO_PAR_DSPI_SCK_SCK);
+}
+
/*
* Breath some life into the CPU...
*
@@ -93,6 +102,8 @@ void cpu_init_f(void)
#endif
icache_enable();
+
+ cfspi_port_conf();
}
/*
@@ -137,57 +148,3 @@ void uart_port_conf(int port)
break;
}
}
-
-#ifdef CONFIG_CF_DSPI
-void cfspi_port_conf(void)
-{
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- out_8(&gpio->par_dspi,
- GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
- GPIO_PAR_DSPI_SCK_SCK);
-}
-
-int cfspi_claim_bus(uint bus, uint cs)
-{
- dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
- return -1;
-
- /* Clear FIFO and resume transfer */
- clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
-
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- break;
- case 2:
- clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
- setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
- break;
- }
-
- return 0;
-}
-
-void cfspi_release_bus(uint bus, uint cs)
-{
- dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- /* Clear FIFO */
- clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
-
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- break;
- case 2:
- clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
- break;
- }
-}
-#endif
diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c
index 7632d9262c..8f4991c1cb 100644
--- a/arch/m68k/cpu/mcf5445x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5445x/cpu_init.c
@@ -66,6 +66,32 @@ void init_fbcs(void)
#endif
}
+#ifdef CONFIG_CF_DSPI
+void cfspi_port_conf(void)
+{
+ gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
+#ifdef CONFIG_MCF5445x
+ out_8(&gpio->par_dspi,
+ GPIO_PAR_DSPI_SIN_SIN |
+ GPIO_PAR_DSPI_SOUT_SOUT |
+ GPIO_PAR_DSPI_SCK_SCK);
+#endif
+
+#ifdef CONFIG_MCF5441x
+ pm_t *pm = (pm_t *)MMAP_PM;
+
+ out_8(&gpio->par_dspi0,
+ GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
+ GPIO_PAR_DSPI0_SCK_DSPI0SCK);
+ out_8(&gpio->srcr_dspiow, 3);
+
+ /* DSPI0 */
+ out_8(&pm->pmcr0, 23);
+#endif
+}
+#endif
+
/*
* Breath some life into the CPU...
*
@@ -204,6 +230,10 @@ void cpu_init_f(void)
GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
+#ifdef CONFIG_CF_SPI
+ cfspi_port_conf();
+#endif
+
#ifdef CONFIG_SYS_FSL_I2C
out_be16(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
@@ -433,115 +463,3 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
}
#endif
-#ifdef CONFIG_CF_DSPI
-void cfspi_port_conf(void)
-{
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
-#ifdef CONFIG_MCF5445x
- out_8(&gpio->par_dspi,
- GPIO_PAR_DSPI_SIN_SIN |
- GPIO_PAR_DSPI_SOUT_SOUT |
- GPIO_PAR_DSPI_SCK_SCK);
-#endif
-
-#ifdef CONFIG_MCF5441x
- pm_t *pm = (pm_t *) MMAP_PM;
-
- out_8(&gpio->par_dspi0,
- GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
- GPIO_PAR_DSPI0_SCK_DSPI0SCK);
- out_8(&gpio->srcr_dspiow, 3);
-
- /* DSPI0 */
- out_8(&pm->pmcr0, 23);
-#endif
-}
-
-int cfspi_claim_bus(uint bus, uint cs)
-{
- dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
- return -1;
-
- /* Clear FIFO and resume transfer */
- clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
-
-#ifdef CONFIG_MCF5445x
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- break;
- case 1:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
- break;
- case 2:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
- break;
- case 3:
- clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
- setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
- break;
- case 5:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
- break;
- }
-#endif
-
-#ifdef CONFIG_MCF5441x
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi0, ~GPIO_PAR_DSPI0_PCS0_MASK);
- setbits_8(&gpio->par_dspi0, GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
- break;
- case 1:
- clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
- setbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
- break;
- }
-#endif
-
- return 0;
-}
-
-void cfspi_release_bus(uint bus, uint cs)
-{
- dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- /* Clear FIFO */
- clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
-
-#ifdef CONFIG_MCF5445x
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- break;
- case 1:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
- break;
- case 2:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
- break;
- case 3:
- clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
- break;
- case 5:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
- break;
- }
-#endif
-
-#ifdef CONFIG_MCF5441x
- if (cs == 1)
- clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
-#endif
-}
-
-#endif
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v4 07/12] drivers: spi: cf_spi: convert to driver model
2018-12-16 11:22 ` [U-Boot] [PATCH v4 07/12] drivers: spi: cf_spi: convert to driver model Angelo Dureghello
@ 2019-03-08 6:00 ` Jagan Teki
2019-03-10 16:17 ` Angelo Dureghello
0 siblings, 1 reply; 15+ messages in thread
From: Jagan Teki @ 2019-03-08 6:00 UTC (permalink / raw)
To: u-boot
On Mon, Dec 17, 2018 at 1:06 AM Angelo Dureghello <angelo@sysam.it> wrote:
>
> Converting to driver model and removes non-dm code.
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Signed-off-by: Angelo Dureghello <angelo@sysam.it>
> ---
> Changes for v2:
> - removed non DM code part
> - add default setup of CTAR registers
> - add DT CTAR register setup support
> Changes for v3:
> - changed commit head
> - removed spi_slave reference
> - add #ifdefs for the case OF_PLATDATA is used
> Changes for v4:
> - remove all internal static functions that are no more needed including
> their code in the standard driver methods
> - add helper macro for ctrl setup
> - fix wrong fifo level check on spi tx
> - move code inside same #if (avoid multiple #if on same option)
> - removed externals and moved bus control code here
> ---
> drivers/spi/cf_spi.c | 539 ++++++++++++++++--------
> include/dm/platform_data/spi_coldfire.h | 29 ++
> 2 files changed, 401 insertions(+), 167 deletions(-)
> create mode 100644 include/dm/platform_data/spi_coldfire.h
>
> diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c
> index 522631cbbf..3d02c87637 100644
> --- a/drivers/spi/cf_spi.c
> +++ b/drivers/spi/cf_spi.c
> @@ -6,23 +6,31 @@
> *
> * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
> * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
> + *
> + * Support for DM and DT, non-DM code removed.
> + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
> + *
> + * TODO: fsl_dspi.c should work as a driver for the DSPI module.
> */
>
> #include <common.h>
> +#include <dm.h>
> +#include <dm/platform_data/spi_coldfire.h>
> #include <spi.h>
> #include <malloc.h>
> +#include <wait_bit.h>
> +#include <asm/coldfire/dspi.h>
> #include <asm/immap.h>
> +#include <asm/io.h>
>
> -struct cf_spi_slave {
> - struct spi_slave slave;
> +struct coldfire_spi_priv {
> + struct dspi *regs;
> + struct gpio *gpio_regs;
> uint baudrate;
> + int mode;
> int charbit;
> };
>
> -extern void cfspi_port_conf(void);
> -extern int cfspi_claim_bus(uint bus, uint cs);
> -extern void cfspi_release_bus(uint bus, uint cs);
> -
> DECLARE_GLOBAL_DATA_PTR;
>
> #ifndef CONFIG_SPI_IDLE_VAL
> @@ -33,149 +41,267 @@ DECLARE_GLOBAL_DATA_PTR;
> #endif
> #endif
>
> -#if defined(CONFIG_CF_DSPI)
> /* DSPI specific mode */
> #define SPI_MODE_MOD 0x00200000
> #define SPI_DBLRATE 0x00100000
>
> -static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave)
> +#define MCF_DSPI_MAX_CTAR_REGS 8
> +
> +/* Default values */
> +#define MCF_DSPI_DEFAULT_SCK_FREQ 10000000
> +#define MCF_DSPI_DEFAULT_MAX_CS 4
> +#define MCF_DSPI_DEFAULT_MODE 0
> +
> +#define MCF_DSPI_DEFAULT_CTAR (DSPI_CTAR_TRSZ(7) | \
> + DSPI_CTAR_PCSSCK_1CLK | \
> + DSPI_CTAR_PASC(0) | \
> + DSPI_CTAR_PDT(0) | \
> + DSPI_CTAR_CSSCK(0) | \
> + DSPI_CTAR_ASC(0) | \
> + DSPI_CTAR_DT(1) | \
> + DSPI_CTAR_BR(6))
> +
> +#define setup_ctrl(ctrl, cs) ((ctrl & 0xFF000000) | ((1 << cs) << 16))
> +
> +static inline void cfspi_tx(struct coldfire_spi_priv *cfspi,
> + u32 ctrl, u16 data)
> {
> - return container_of(slave, struct cf_spi_slave, slave);
> + /*
> + * Need to check fifo level here
> + */
> + while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 0x4000)
> + ;
> +
> + writel(ctrl | data, &cfspi->regs->tfr);
> }
>
> -static void cfspi_init(void)
> +static inline u16 cfspi_rx(struct coldfire_spi_priv *cfspi)
> {
> - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
> -
> - cfspi_port_conf(); /* port configuration */
> + while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0)
> + ;
>
> - dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
> - DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
> - DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
> - DSPI_MCR_CRXF | DSPI_MCR_CTXF;
> + return readw(&cfspi->regs->rfr);
> +}
Look like you include wait header and forgot to implement
wait_for_bit_* logic which I commented before.
>
> - /* Default setting in platform configuration */
> -#ifdef CONFIG_SYS_DSPI_CTAR0
> - dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0;
> -#endif
> -#ifdef CONFIG_SYS_DSPI_CTAR1
> - dspi->ctar[1] = CONFIG_SYS_DSPI_CTAR1;
> -#endif
> -#ifdef CONFIG_SYS_DSPI_CTAR2
> - dspi->ctar[2] = CONFIG_SYS_DSPI_CTAR2;
> -#endif
> -#ifdef CONFIG_SYS_DSPI_CTAR3
> - dspi->ctar[3] = CONFIG_SYS_DSPI_CTAR3;
> -#endif
> -#ifdef CONFIG_SYS_DSPI_CTAR4
> - dspi->ctar[4] = CONFIG_SYS_DSPI_CTAR4;
> +static int coldfire_spi_claim_bus(struct udevice *dev)
> +{
> + struct udevice *bus = dev->parent;
> + struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
> + struct dspi *dspi = cfspi->regs;
> +#if defined(CONFIG_MCF5445x) || \
> + defined(CONFIG_MCF5441x) || defined(CONFIG_MCF5227x)
> + struct dm_spi_slave_platdata *slave_plat =
> + dev_get_parent_platdata(dev);
> + struct gpio *gpio = cfspi->gpio_regs;
> #endif
> -#ifdef CONFIG_SYS_DSPI_CTAR5
> - dspi->ctar[5] = CONFIG_SYS_DSPI_CTAR5;
> +
> + if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
> + return -1;
> +
> + /* Clear FIFO and resume transfer */
> + clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
> +
> +#ifdef CONFIG_MCF5445x
> + switch (slave_plat->cs) {
> + case 0:
> + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
> + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
> + break;
> + case 1:
> + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
> + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
> + break;
> + case 2:
> + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
> + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
> + break;
> + case 3:
> + clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
> + setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
> + break;
> + case 5:
> + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
> + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
> + break;
> + }
> #endif
> -#ifdef CONFIG_SYS_DSPI_CTAR6
> - dspi->ctar[6] = CONFIG_SYS_DSPI_CTAR6;
> +
> +#ifdef CONFIG_MCF5441x
> + switch (slave_plat->cs) {
> + case 0:
> + clrbits_8(&gpio->par_dspi0, ~GPIO_PAR_DSPI0_PCS0_MASK);
> + setbits_8(&gpio->par_dspi0, GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
> + break;
> + case 1:
> + clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
> + setbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
> + break;
> + }
> #endif
> -#ifdef CONFIG_SYS_DSPI_CTAR7
> - dspi->ctar[7] = CONFIG_SYS_DSPI_CTAR7;
> +
> +#ifdef CONFIG_MCF5227x
> + switch (slave_plat->cs) {
> + case 0:
> + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
> + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
> + break;
> + case 2:
> + clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
> + setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
> + break;
> + }
> #endif
> + return 0;
> }
>
> -static void cfspi_tx(u32 ctrl, u16 data)
> +static int coldfire_spi_release_bus(struct udevice *dev)
> {
> - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
> -
> - while ((dspi->sr & 0x0000F000) >= 4) ;
> -
> - dspi->tfr = (ctrl | data);
> -}
> + struct udevice *bus = dev->parent;
> + struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
> + struct dspi *dspi = cfspi->regs;
> +#if defined(CONFIG_MCF5445x) || \
> + defined(CONFIG_MCF5441x) || defined(CONFIG_MCF5227x)
> + struct dm_spi_slave_platdata *slave_plat =
> + dev_get_parent_platdata(dev);
> + struct gpio *gpio = cfspi->gpio_regs;
> +#endif
>
> -static u16 cfspi_rx(void)
> -{
> - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
> + /* Clear FIFO */
> + clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
> +
> +#ifdef CONFIG_MCF5445x
> + switch (slave_plat->cs) {
> + case 0:
> + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
> + break;
> + case 1:
> + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
> + break;
> + case 2:
> + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
> + break;
> + case 3:
> + clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
> + break;
> + case 5:
> + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
> + break;
> + }
> +#endif
>
> - while ((dspi->sr & 0x000000F0) == 0) ;
> +#ifdef CONFIG_MCF5441x
> + if (slave_plat->cs == 1)
> + clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
> +#endif
>
> - return (dspi->rfr & 0xFFFF);
> +#ifdef CONFIG_MCF5227x
Like this macro, along with above CONFIG_MCF5445x
Does it support separate compatible between these diff, if yes we can
handle these via driver data.
> + switch (slave_plat->cs) {
> + case 0:
> + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
> + break;
> + case 2:
> + clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
> + break;
> + }
> +#endif
> + return 0;
> }
>
> -static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
> - void *din, ulong flags)
> +static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
> + const void *dout, void *din,
> + unsigned long flags)
> {
> - struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
> + struct udevice *bus = dev_get_parent(dev);
> + struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
> + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
> u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
> u8 *spi_rd = NULL, *spi_wr = NULL;
> - static u32 ctrl = 0;
> + static u32 ctrl;
> uint len = bitlen >> 3;
>
> - if (cfslave->charbit == 16) {
> + if (cfspi->charbit == 16) {
> bitlen >>= 1;
> - spi_wr16 = (u16 *) dout;
> - spi_rd16 = (u16 *) din;
> + spi_wr16 = (u16 *)dout;
> + spi_rd16 = (u16 *)din;
> } else {
> - spi_wr = (u8 *) dout;
> - spi_rd = (u8 *) din;
> + spi_wr = (u8 *)dout;
> + spi_rd = (u8 *)din;
> }
>
> if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
> ctrl |= DSPI_TFR_CONT;
>
> - ctrl = (ctrl & 0xFF000000) | ((1 << slave->cs) << 16);
> + ctrl = setup_ctrl(ctrl, slave_plat->cs);
>
> if (len > 1) {
> int tmp_len = len - 1;
> +
> while (tmp_len--) {
> - if (dout != NULL) {
> - if (cfslave->charbit == 16)
> - cfspi_tx(ctrl, *spi_wr16++);
> + if (dout) {
> + if (cfspi->charbit == 16)
> + cfspi_tx(cfspi, ctrl, *spi_wr16++);
> else
> - cfspi_tx(ctrl, *spi_wr++);
> - cfspi_rx();
> + cfspi_tx(cfspi, ctrl, *spi_wr++);
> + cfspi_rx(cfspi);
> }
>
> - if (din != NULL) {
> - cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
> - if (cfslave->charbit == 16)
> - *spi_rd16++ = cfspi_rx();
> + if (din) {
> + cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
> + if (cfspi->charbit == 16)
> + *spi_rd16++ = cfspi_rx(cfspi);
> else
> - *spi_rd++ = cfspi_rx();
> + *spi_rd++ = cfspi_rx(cfspi);
> }
> }
>
> len = 1; /* remaining byte */
> }
>
> - if ((flags & SPI_XFER_END) == SPI_XFER_END)
> + if (flags & SPI_XFER_END)
> ctrl &= ~DSPI_TFR_CONT;
>
> if (len) {
> - if (dout != NULL) {
> - if (cfslave->charbit == 16)
> - cfspi_tx(ctrl, *spi_wr16);
> + if (dout) {
> + if (cfspi->charbit == 16)
> + cfspi_tx(cfspi, ctrl, *spi_wr16);
> else
> - cfspi_tx(ctrl, *spi_wr);
> - cfspi_rx();
> + cfspi_tx(cfspi, ctrl, *spi_wr);
> + cfspi_rx(cfspi);
> }
>
> - if (din != NULL) {
> - cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
> - if (cfslave->charbit == 16)
> - *spi_rd16 = cfspi_rx();
> + if (din) {
> + cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
> + if (cfspi->charbit == 16)
> + *spi_rd16 = cfspi_rx(cfspi);
> else
> - *spi_rd = cfspi_rx();
> + *spi_rd = cfspi_rx(cfspi);
> }
> } else {
> /* dummy read */
> - cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
> - cfspi_rx();
> + cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
> + cfspi_rx(cfspi);
> }
>
> return 0;
> }
>
> -static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
> - uint mode)
> +static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz)
> {
> + struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
> + struct dspi *dspi = cfspi->regs;
> + int prescaler[] = { 2, 3, 5, 7 };
> + int scaler[] = {
> + 2, 4, 6, 8,
> + 16, 32, 64, 128,
> + 256, 512, 1024, 2048,
> + 4096, 8192, 16384, 32768
> + };
> + int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
> + int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed;
bestmatch, replace with macro?
> + u32 bus_setup;
> +
> + cfspi->baudrate = max_hz;
> +
> /*
> * bit definition for mode:
> * bit 31 - 28: Transfer size 3 to 16 bits
> @@ -189,66 +315,37 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
> * 11 - 8: Delay after transfer scaler
> * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
> */
> - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
> - int prescaler[] = { 2, 3, 5, 7 };
> - int scaler[] = {
> - 2, 4, 6, 8,
> - 16, 32, 64, 128,
> - 256, 512, 1024, 2048,
> - 4096, 8192, 16384, 32768
> - };
> - int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
> - int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed;
> - u32 bus_setup = 0;
> +
> + /* Read current setup */
> + bus_setup = readl(&dspi->ctar[bus->seq]);
>
> tmp = (prescaler[3] * scaler[15]);
> /* Maximum and minimum baudrate it can handle */
> - if ((cfslave->baudrate > (gd->bus_clk >> 1)) ||
> - (cfslave->baudrate < (gd->bus_clk / tmp))) {
> + if ((cfspi->baudrate > (gd->bus_clk >> 1)) ||
> + (cfspi->baudrate < (gd->bus_clk / tmp))) {
> printf("Exceed baudrate limitation: Max %d - Min %d\n",
> (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
> - return NULL;
> + return -1;
> }
>
> /* Activate Double Baud when it exceed 1/4 the bus clk */
> - if ((CONFIG_SYS_DSPI_CTAR0 & DSPI_CTAR_DBR) ||
> - (cfslave->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
> + if ((bus_setup & DSPI_CTAR_DBR) ||
> + (cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
> bus_setup |= DSPI_CTAR_DBR;
> dbr = 1;
> }
>
> - if (mode & SPI_CPOL)
> - bus_setup |= DSPI_CTAR_CPOL;
> - if (mode & SPI_CPHA)
> - bus_setup |= DSPI_CTAR_CPHA;
> - if (mode & SPI_LSB_FIRST)
> - bus_setup |= DSPI_CTAR_LSBFE;
> -
> /* Overwrite default value set in platform configuration file */
> - if (mode & SPI_MODE_MOD) {
> -
> - if ((mode & 0xF0000000) == 0)
> - bus_setup |=
> - dspi->ctar[cfslave->slave.bus] & 0x78000000;
> - else
> - bus_setup |= ((mode & 0xF0000000) >> 1);
> -
> + if (cfspi->mode & SPI_MODE_MOD) {
> /*
> * Check to see if it is enabled by default in platform
> * config, or manual setting passed by mode parameter
> */
> - if (mode & SPI_DBLRATE) {
> + if (cfspi->mode & SPI_DBLRATE) {
> bus_setup |= DSPI_CTAR_DBR;
> dbr = 1;
> }
> - bus_setup |= (mode & 0x0FC00000) >> 4; /* PSCSCK, PASC, PDT */
> - bus_setup |= (mode & 0x000FFF00) >> 4; /* CSSCK, ASC, DT */
> - } else
> - bus_setup |= (dspi->ctar[cfslave->slave.bus] & 0x78FCFFF0);
> -
> - cfslave->charbit =
> - ((dspi->ctar[cfslave->slave.bus] & 0x78000000) ==
> - 0x78000000) ? 16 : 8;
> + }
>
> pbrcnt = sizeof(prescaler) / sizeof(int);
> brcnt = sizeof(scaler) / sizeof(int);
> @@ -259,10 +356,10 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
> for (j = 0; j < brcnt; j++) {
> tmp = (baud_speed / scaler[j]) * (1 + dbr);
>
> - if (tmp > cfslave->baudrate)
> - diff = tmp - cfslave->baudrate;
> + if (tmp > cfspi->baudrate)
> + diff = tmp - cfspi->baudrate;
> else
> - diff = cfslave->baudrate - tmp;
> + diff = cfspi->baudrate - tmp;
>
> if (diff < bestmatch) {
> bestmatch = diff;
> @@ -271,65 +368,173 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
> }
> }
> }
> +
> + bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f));
> bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
> - dspi->ctar[cfslave->slave.bus] = bus_setup;
> + writel(bus_setup, &dspi->ctar[bus->seq]);
>
> - return &cfslave->slave;
> + return 0;
> }
> -#endif /* CONFIG_CF_DSPI */
>
> -#ifdef CONFIG_CMD_SPI
> -int spi_cs_is_valid(unsigned int bus, unsigned int cs)
> +static int coldfire_spi_set_mode(struct udevice *bus, uint mode)
> {
> - if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8)))
> - return 1;
> - else
> - return 0;
> -}
> + struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
> + struct dspi *dspi = cfspi->regs;
> + u32 bus_setup = 0;
>
> -void spi_init(void)
> -{
> - cfspi_init();
> -}
> + cfspi->mode = mode;
>
> -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> - unsigned int max_hz, unsigned int mode)
> -{
> - struct cf_spi_slave *cfslave;
> + if (cfspi->mode & SPI_CPOL)
> + bus_setup |= DSPI_CTAR_CPOL;
> + if (cfspi->mode & SPI_CPHA)
> + bus_setup |= DSPI_CTAR_CPHA;
> + if (cfspi->mode & SPI_LSB_FIRST)
> + bus_setup |= DSPI_CTAR_LSBFE;
> +
> + /* Overwrite default value set in platform configuration file */
> + if (cfspi->mode & SPI_MODE_MOD) {
> + if ((cfspi->mode & 0xF0000000) == 0)
> + bus_setup |=
> + readl(&dspi->ctar[bus->seq]) & 0x78000000;
> + else
> + bus_setup |= ((cfspi->mode & 0xF0000000) >> 1);
>
> - if (!spi_cs_is_valid(bus, cs))
> - return NULL;
> + /* PSCSCK, PASC, PDT */
> + bus_setup |= (cfspi->mode & 0x0FC00000) >> 4;
> + /* CSSCK, ASC, DT */
> + bus_setup |= (cfspi->mode & 0x000FFF00) >> 4;
> + } else {
> + bus_setup |= (readl(&dspi->ctar[bus->seq]) & 0x78FCFFF0);
> + }
>
> - cfslave = spi_alloc_slave(struct cf_spi_slave, bus, cs);
> - if (!cfslave)
> - return NULL;
> + cfspi->charbit =
> + ((readl(&dspi->ctar[bus->seq]) & 0x78000000) ==
> + 0x78000000) ? 16 : 8;
Same here?
>
> - cfslave->baudrate = max_hz;
> + setbits_be32(&dspi->ctar[bus->seq], bus_setup);
>
> - /* specific setup */
> - return cfspi_setup_slave(cfslave, mode);
> + return 0;
> }
>
> -void spi_free_slave(struct spi_slave *slave)
> +static int coldfire_spi_probe(struct udevice *bus)
> {
> - struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
> + struct coldfire_spi_platdata *plat = dev_get_platdata(bus);
> + struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
> + struct dspi *dspi = cfspi->regs;
> + int i;
>
> - free(cfslave);
> -}
> + cfspi->regs = (struct dspi *)plat->regs_addr;
> + cfspi->gpio_regs = (struct gpio *)MMAP_GPIO;
>
> -int spi_claim_bus(struct spi_slave *slave)
> -{
> - return cfspi_claim_bus(slave->bus, slave->cs);
> + cfspi->baudrate = plat->speed_hz;
> + cfspi->mode = plat->mode;
> +
> + for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) {
> + unsigned int ctar = 0;
> +
> + if (plat->ctar[i][0] == 0)
> + break;
> +
> + ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) |
> + DSPI_CTAR_PCSSCK(plat->ctar[i][1]) |
> + DSPI_CTAR_PASC(plat->ctar[i][2]) |
> + DSPI_CTAR_PDT(plat->ctar[i][3]) |
> + DSPI_CTAR_CSSCK(plat->ctar[i][4]) |
> + DSPI_CTAR_ASC(plat->ctar[i][5]) |
> + DSPI_CTAR_DT(plat->ctar[i][6]) |
> + DSPI_CTAR_BR(plat->ctar[i][7]);
> +
> + writel(ctar, &cfspi->regs->ctar[i]);
> + }
> +
> + /* Default CTARs */
> + for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++)
> + writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]);
> +
> + dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
> + DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
> + DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
> + DSPI_MCR_CRXF | DSPI_MCR_CTXF;
> +
> + return 0;
> }
>
> -void spi_release_bus(struct spi_slave *slave)
> +void spi_init(void)
> {
> - cfspi_release_bus(slave->bus, slave->cs);
> }
>
> -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
> - void *din, unsigned long flags)
> +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
> +static int coldfire_dspi_ofdata_to_platdata(struct udevice *bus)
> {
> - return cfspi_xfer(slave, bitlen, dout, din, flags);
> + fdt_addr_t addr;
> + struct coldfire_spi_platdata *plat = bus->platdata;
> + const void *blob = gd->fdt_blob;
> + int node = dev_of_offset(bus);
> + int *ctar, len;
> +
> + addr = devfdt_get_addr(bus);
> + if (addr == FDT_ADDR_T_NONE)
> + return -ENOMEM;
> +
> + plat->regs_addr = addr;
> +
> + plat->num_cs = fdtdec_get_int(blob, node, "num-cs",
> + MCF_DSPI_DEFAULT_MAX_CS);
> +
> + plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
> + MCF_DSPI_DEFAULT_SCK_FREQ);
> +
> + plat->mode = fdtdec_get_int(blob, node, "spi-mode",
> + MCF_DSPI_DEFAULT_MODE);
> +
> + memset(plat->ctar, 0, sizeof(plat->ctar));
> +
> + ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len);
> +
> + if (ctar && len) {
> + int i, q, ctar_regs;
> +
> + ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS;
> +
> + if (ctar_regs > MAX_CTAR_REGS)
> + ctar_regs = MAX_CTAR_REGS;
> +
> + for (i = 0; i < ctar_regs; i++) {
> + for (q = 0; q < MAX_CTAR_FIELDS; q++)
> + plat->ctar[i][q] = *ctar++;
> + }
> + }
> +
> + debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n",
> + (void *)plat->regs_addr,
> + plat->speed_hz, plat->num_cs, plat->mode);
> +
> + return 0;
> }
> -#endif /* CONFIG_CMD_SPI */
> +
> +static const struct udevice_id coldfire_spi_ids[] = {
> + { .compatible = "fsl,mcf-dspi" },
> + { }
> +};
> +#endif
> +
> +static const struct dm_spi_ops coldfire_spi_ops = {
> + .claim_bus = coldfire_spi_claim_bus,
> + .release_bus = coldfire_spi_release_bus,
> + .xfer = coldfire_spi_xfer,
> + .set_speed = coldfire_spi_set_speed,
> + .set_mode = coldfire_spi_set_mode,
> +};
> +
> +U_BOOT_DRIVER(coldfire_spi) = {
> + .name = "spi_coldfire",
> + .id = UCLASS_SPI,
> + .probe = coldfire_spi_probe,
> + .ops = &coldfire_spi_ops,
> + .platdata_auto_alloc_size = sizeof(struct coldfire_spi_platdata),
> + .priv_auto_alloc_size = sizeof(struct coldfire_spi_priv),
> +#if !CONFIG_IS_ENABLED(OF_PLATDATA)
> + .of_match = coldfire_spi_ids,
> + .ofdata_to_platdata = coldfire_dspi_ofdata_to_platdata,
> +#endif
> +};
This has to be as below
U_BOOT_DRIVER(coldfire_spi) = {
.name = "spi_coldfire",
.id = UCLASS_SPI,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = coldfire_spi_ids,
.ofdata_to_platdata = coldfire_dspi_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct coldfire_spi_platdata),
#endif
.probe = coldfire_spi_probe,
.ops = &coldfire_spi_ops,
.priv_auto_alloc_size = sizeof(struct coldfire_spi_priv),
};
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v4 07/12] drivers: spi: cf_spi: convert to driver model
2019-03-08 6:00 ` Jagan Teki
@ 2019-03-10 16:17 ` Angelo Dureghello
2019-03-11 17:34 ` Jagan Teki
0 siblings, 1 reply; 15+ messages in thread
From: Angelo Dureghello @ 2019-03-10 16:17 UTC (permalink / raw)
To: u-boot
Hi Jagan,
thanks for your comments,
On Fri, Mar 08, 2019 at 11:30:56AM +0530, Jagan Teki wrote:
> On Mon, Dec 17, 2018 at 1:06 AM Angelo Dureghello <angelo@sysam.it> wrote:
> >
> > Converting to driver model and removes non-dm code.
> >
> > Reviewed-by: Simon Glass <sjg@chromium.org>
> > Signed-off-by: Angelo Dureghello <angelo@sysam.it>
> > ---
> > Changes for v2:
> > - removed non DM code part
> > - add default setup of CTAR registers
> > - add DT CTAR register setup support
> > Changes for v3:
> > - changed commit head
> > - removed spi_slave reference
> > - add #ifdefs for the case OF_PLATDATA is used
> > Changes for v4:
> > - remove all internal static functions that are no more needed including
> > their code in the standard driver methods
> > - add helper macro for ctrl setup
> > - fix wrong fifo level check on spi tx
> > - move code inside same #if (avoid multiple #if on same option)
> > - removed externals and moved bus control code here
> > ---
> > drivers/spi/cf_spi.c | 539 ++++++++++++++++--------
> > include/dm/platform_data/spi_coldfire.h | 29 ++
> > 2 files changed, 401 insertions(+), 167 deletions(-)
> > create mode 100644 include/dm/platform_data/spi_coldfire.h
> >
> > diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c
> > index 522631cbbf..3d02c87637 100644
> > --- a/drivers/spi/cf_spi.c
> > +++ b/drivers/spi/cf_spi.c
> > @@ -6,23 +6,31 @@
> > *
> > * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
> > * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
> > + *
> > + * Support for DM and DT, non-DM code removed.
> > + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
> > + *
> > + * TODO: fsl_dspi.c should work as a driver for the DSPI module.
> > */
> >
> > #include <common.h>
> > +#include <dm.h>
> > +#include <dm/platform_data/spi_coldfire.h>
> > #include <spi.h>
> > #include <malloc.h>
> > +#include <wait_bit.h>
> > +#include <asm/coldfire/dspi.h>
> > #include <asm/immap.h>
> > +#include <asm/io.h>
> >
> > -struct cf_spi_slave {
> > - struct spi_slave slave;
> > +struct coldfire_spi_priv {
> > + struct dspi *regs;
> > + struct gpio *gpio_regs;
> > uint baudrate;
> > + int mode;
> > int charbit;
> > };
> >
> > -extern void cfspi_port_conf(void);
> > -extern int cfspi_claim_bus(uint bus, uint cs);
> > -extern void cfspi_release_bus(uint bus, uint cs);
> > -
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > #ifndef CONFIG_SPI_IDLE_VAL
> > @@ -33,149 +41,267 @@ DECLARE_GLOBAL_DATA_PTR;
> > #endif
> > #endif
> >
> > -#if defined(CONFIG_CF_DSPI)
> > /* DSPI specific mode */
> > #define SPI_MODE_MOD 0x00200000
> > #define SPI_DBLRATE 0x00100000
> >
> > -static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave)
> > +#define MCF_DSPI_MAX_CTAR_REGS 8
> > +
> > +/* Default values */
> > +#define MCF_DSPI_DEFAULT_SCK_FREQ 10000000
> > +#define MCF_DSPI_DEFAULT_MAX_CS 4
> > +#define MCF_DSPI_DEFAULT_MODE 0
> > +
> > +#define MCF_DSPI_DEFAULT_CTAR (DSPI_CTAR_TRSZ(7) | \
> > + DSPI_CTAR_PCSSCK_1CLK | \
> > + DSPI_CTAR_PASC(0) | \
> > + DSPI_CTAR_PDT(0) | \
> > + DSPI_CTAR_CSSCK(0) | \
> > + DSPI_CTAR_ASC(0) | \
> > + DSPI_CTAR_DT(1) | \
> > + DSPI_CTAR_BR(6))
> > +
> > +#define setup_ctrl(ctrl, cs) ((ctrl & 0xFF000000) | ((1 << cs) << 16))
> > +
> > +static inline void cfspi_tx(struct coldfire_spi_priv *cfspi,
> > + u32 ctrl, u16 data)
> > {
> > - return container_of(slave, struct cf_spi_slave, slave);
> > + /*
> > + * Need to check fifo level here
> > + */
> > + while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 0x4000)
> > + ;
> > +
> > + writel(ctrl | data, &cfspi->regs->tfr);
> > }
> >
> > -static void cfspi_init(void)
> > +static inline u16 cfspi_rx(struct coldfire_spi_priv *cfspi)
> > {
> > - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
> > -
> > - cfspi_port_conf(); /* port configuration */
> > + while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0)
> > + ;
> >
> > - dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
> > - DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
> > - DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
> > - DSPI_MCR_CRXF | DSPI_MCR_CTXF;
> > + return readw(&cfspi->regs->rfr);
> > +}
>
> Look like you include wait header and forgot to implement
> wait_for_bit_* logic which I commented before.
>
I tried to use it, this is why i forgot the header.
The fact is that wait_for_bit_* logic wait for one or more bit(s),
but cannot wait for one "of" more bit(s), as in the above case.
So seems cannot apply here.
> >
> > - /* Default setting in platform configuration */
> > -#ifdef CONFIG_SYS_DSPI_CTAR0
> > - dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0;
> > -#endif
> > -#ifdef CONFIG_SYS_DSPI_CTAR1
> > - dspi->ctar[1] = CONFIG_SYS_DSPI_CTAR1;
> > -#endif
> > -#ifdef CONFIG_SYS_DSPI_CTAR2
> > - dspi->ctar[2] = CONFIG_SYS_DSPI_CTAR2;
> > -#endif
> > -#ifdef CONFIG_SYS_DSPI_CTAR3
> > - dspi->ctar[3] = CONFIG_SYS_DSPI_CTAR3;
> > -#endif
> > -#ifdef CONFIG_SYS_DSPI_CTAR4
> > - dspi->ctar[4] = CONFIG_SYS_DSPI_CTAR4;
> > +static int coldfire_spi_claim_bus(struct udevice *dev)
> > +{
> > + struct udevice *bus = dev->parent;
> > + struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
> > + struct dspi *dspi = cfspi->regs;
> > +#if defined(CONFIG_MCF5445x) || \
> > + defined(CONFIG_MCF5441x) || defined(CONFIG_MCF5227x)
> > + struct dm_spi_slave_platdata *slave_plat =
> > + dev_get_parent_platdata(dev);
> > + struct gpio *gpio = cfspi->gpio_regs;
> > #endif
> > -#ifdef CONFIG_SYS_DSPI_CTAR5
> > - dspi->ctar[5] = CONFIG_SYS_DSPI_CTAR5;
> > +
> > + if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
> > + return -1;
> > +
> > + /* Clear FIFO and resume transfer */
> > + clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
> > +
> > +#ifdef CONFIG_MCF5445x
> > + switch (slave_plat->cs) {
> > + case 0:
> > + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
> > + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
> > + break;
> > + case 1:
> > + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
> > + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
> > + break;
> > + case 2:
> > + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
> > + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
> > + break;
> > + case 3:
> > + clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
> > + setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
> > + break;
> > + case 5:
> > + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
> > + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
> > + break;
> > + }
> > #endif
> > -#ifdef CONFIG_SYS_DSPI_CTAR6
> > - dspi->ctar[6] = CONFIG_SYS_DSPI_CTAR6;
> > +
> > +#ifdef CONFIG_MCF5441x
> > + switch (slave_plat->cs) {
> > + case 0:
> > + clrbits_8(&gpio->par_dspi0, ~GPIO_PAR_DSPI0_PCS0_MASK);
> > + setbits_8(&gpio->par_dspi0, GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
> > + break;
> > + case 1:
> > + clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
> > + setbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
> > + break;
> > + }
> > #endif
> > -#ifdef CONFIG_SYS_DSPI_CTAR7
> > - dspi->ctar[7] = CONFIG_SYS_DSPI_CTAR7;
> > +
> > +#ifdef CONFIG_MCF5227x
> > + switch (slave_plat->cs) {
> > + case 0:
> > + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
> > + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
> > + break;
> > + case 2:
> > + clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
> > + setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
> > + break;
> > + }
> > #endif
> > + return 0;
> > }
> >
> > -static void cfspi_tx(u32 ctrl, u16 data)
> > +static int coldfire_spi_release_bus(struct udevice *dev)
> > {
> > - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
> > -
> > - while ((dspi->sr & 0x0000F000) >= 4) ;
> > -
> > - dspi->tfr = (ctrl | data);
> > -}
> > + struct udevice *bus = dev->parent;
> > + struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
> > + struct dspi *dspi = cfspi->regs;
> > +#if defined(CONFIG_MCF5445x) || \
> > + defined(CONFIG_MCF5441x) || defined(CONFIG_MCF5227x)
> > + struct dm_spi_slave_platdata *slave_plat =
> > + dev_get_parent_platdata(dev);
> > + struct gpio *gpio = cfspi->gpio_regs;
> > +#endif
> >
> > -static u16 cfspi_rx(void)
> > -{
> > - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
> > + /* Clear FIFO */
> > + clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
> > +
> > +#ifdef CONFIG_MCF5445x
> > + switch (slave_plat->cs) {
> > + case 0:
> > + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
> > + break;
> > + case 1:
> > + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
> > + break;
> > + case 2:
> > + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
> > + break;
> > + case 3:
> > + clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
> > + break;
> > + case 5:
> > + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
> > + break;
> > + }
> > +#endif
> >
> > - while ((dspi->sr & 0x000000F0) == 0) ;
> > +#ifdef CONFIG_MCF5441x
> > + if (slave_plat->cs == 1)
> > + clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
> > +#endif
> >
> > - return (dspi->rfr & 0xFFFF);
> > +#ifdef CONFIG_MCF5227x
>
> Like this macro, along with above CONFIG_MCF5445x
>
> Does it support separate compatible between these diff, if yes we can
> handle these via driver data.
>
Ok, fixing this, nearly done, should be able to avoid
all the config macroes probably.
> > + switch (slave_plat->cs) {
> > + case 0:
> > + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
> > + break;
> > + case 2:
> > + clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
> > + break;
> > + }
> > +#endif
> > + return 0;
> > }
> >
> > -static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
> > - void *din, ulong flags)
> > +static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
> > + const void *dout, void *din,
> > + unsigned long flags)
> > {
> > - struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
> > + struct udevice *bus = dev_get_parent(dev);
> > + struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
> > + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
> > u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
> > u8 *spi_rd = NULL, *spi_wr = NULL;
> > - static u32 ctrl = 0;
> > + static u32 ctrl;
> > uint len = bitlen >> 3;
> >
> > - if (cfslave->charbit == 16) {
> > + if (cfspi->charbit == 16) {
> > bitlen >>= 1;
> > - spi_wr16 = (u16 *) dout;
> > - spi_rd16 = (u16 *) din;
> > + spi_wr16 = (u16 *)dout;
> > + spi_rd16 = (u16 *)din;
> > } else {
> > - spi_wr = (u8 *) dout;
> > - spi_rd = (u8 *) din;
> > + spi_wr = (u8 *)dout;
> > + spi_rd = (u8 *)din;
> > }
> >
> > if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
> > ctrl |= DSPI_TFR_CONT;
> >
> > - ctrl = (ctrl & 0xFF000000) | ((1 << slave->cs) << 16);
> > + ctrl = setup_ctrl(ctrl, slave_plat->cs);
> >
> > if (len > 1) {
> > int tmp_len = len - 1;
> > +
> > while (tmp_len--) {
> > - if (dout != NULL) {
> > - if (cfslave->charbit == 16)
> > - cfspi_tx(ctrl, *spi_wr16++);
> > + if (dout) {
> > + if (cfspi->charbit == 16)
> > + cfspi_tx(cfspi, ctrl, *spi_wr16++);
> > else
> > - cfspi_tx(ctrl, *spi_wr++);
> > - cfspi_rx();
> > + cfspi_tx(cfspi, ctrl, *spi_wr++);
> > + cfspi_rx(cfspi);
> > }
> >
> > - if (din != NULL) {
> > - cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
> > - if (cfslave->charbit == 16)
> > - *spi_rd16++ = cfspi_rx();
> > + if (din) {
> > + cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
> > + if (cfspi->charbit == 16)
> > + *spi_rd16++ = cfspi_rx(cfspi);
> > else
> > - *spi_rd++ = cfspi_rx();
> > + *spi_rd++ = cfspi_rx(cfspi);
> > }
> > }
> >
> > len = 1; /* remaining byte */
> > }
> >
> > - if ((flags & SPI_XFER_END) == SPI_XFER_END)
> > + if (flags & SPI_XFER_END)
> > ctrl &= ~DSPI_TFR_CONT;
> >
> > if (len) {
> > - if (dout != NULL) {
> > - if (cfslave->charbit == 16)
> > - cfspi_tx(ctrl, *spi_wr16);
> > + if (dout) {
> > + if (cfspi->charbit == 16)
> > + cfspi_tx(cfspi, ctrl, *spi_wr16);
> > else
> > - cfspi_tx(ctrl, *spi_wr);
> > - cfspi_rx();
> > + cfspi_tx(cfspi, ctrl, *spi_wr);
> > + cfspi_rx(cfspi);
> > }
> >
> > - if (din != NULL) {
> > - cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
> > - if (cfslave->charbit == 16)
> > - *spi_rd16 = cfspi_rx();
> > + if (din) {
> > + cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
> > + if (cfspi->charbit == 16)
> > + *spi_rd16 = cfspi_rx(cfspi);
> > else
> > - *spi_rd = cfspi_rx();
> > + *spi_rd = cfspi_rx(cfspi);
> > }
> > } else {
> > /* dummy read */
> > - cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
> > - cfspi_rx();
> > + cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
> > + cfspi_rx(cfspi);
> > }
> >
> > return 0;
> > }
> >
> > -static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
> > - uint mode)
> > +static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz)
> > {
> > + struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
> > + struct dspi *dspi = cfspi->regs;
> > + int prescaler[] = { 2, 3, 5, 7 };
> > + int scaler[] = {
> > + 2, 4, 6, 8,
> > + 16, 32, 64, 128,
> > + 256, 512, 1024, 2048,
> > + 4096, 8192, 16384, 32768
> > + };
> > + int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
> > + int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed;
>
> bestmatch, replace with macro?
>
Ok, done.
> > + u32 bus_setup;
> > +
> > + cfspi->baudrate = max_hz;
> > +
> > /*
> > * bit definition for mode:
> > * bit 31 - 28: Transfer size 3 to 16 bits
> > @@ -189,66 +315,37 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
> > * 11 - 8: Delay after transfer scaler
> > * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
> > */
> > - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
> > - int prescaler[] = { 2, 3, 5, 7 };
> > - int scaler[] = {
> > - 2, 4, 6, 8,
> > - 16, 32, 64, 128,
> > - 256, 512, 1024, 2048,
> > - 4096, 8192, 16384, 32768
> > - };
> > - int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
> > - int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed;
> > - u32 bus_setup = 0;
> > +
> > + /* Read current setup */
> > + bus_setup = readl(&dspi->ctar[bus->seq]);
> >
> > tmp = (prescaler[3] * scaler[15]);
> > /* Maximum and minimum baudrate it can handle */
> > - if ((cfslave->baudrate > (gd->bus_clk >> 1)) ||
> > - (cfslave->baudrate < (gd->bus_clk / tmp))) {
> > + if ((cfspi->baudrate > (gd->bus_clk >> 1)) ||
> > + (cfspi->baudrate < (gd->bus_clk / tmp))) {
> > printf("Exceed baudrate limitation: Max %d - Min %d\n",
> > (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
> > - return NULL;
> > + return -1;
> > }
> >
> > /* Activate Double Baud when it exceed 1/4 the bus clk */
> > - if ((CONFIG_SYS_DSPI_CTAR0 & DSPI_CTAR_DBR) ||
> > - (cfslave->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
> > + if ((bus_setup & DSPI_CTAR_DBR) ||
> > + (cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
> > bus_setup |= DSPI_CTAR_DBR;
> > dbr = 1;
> > }
> >
> > - if (mode & SPI_CPOL)
> > - bus_setup |= DSPI_CTAR_CPOL;
> > - if (mode & SPI_CPHA)
> > - bus_setup |= DSPI_CTAR_CPHA;
> > - if (mode & SPI_LSB_FIRST)
> > - bus_setup |= DSPI_CTAR_LSBFE;
> > -
> > /* Overwrite default value set in platform configuration file */
> > - if (mode & SPI_MODE_MOD) {
> > -
> > - if ((mode & 0xF0000000) == 0)
> > - bus_setup |=
> > - dspi->ctar[cfslave->slave.bus] & 0x78000000;
> > - else
> > - bus_setup |= ((mode & 0xF0000000) >> 1);
> > -
> > + if (cfspi->mode & SPI_MODE_MOD) {
> > /*
> > * Check to see if it is enabled by default in platform
> > * config, or manual setting passed by mode parameter
> > */
> > - if (mode & SPI_DBLRATE) {
> > + if (cfspi->mode & SPI_DBLRATE) {
> > bus_setup |= DSPI_CTAR_DBR;
> > dbr = 1;
> > }
> > - bus_setup |= (mode & 0x0FC00000) >> 4; /* PSCSCK, PASC, PDT */
> > - bus_setup |= (mode & 0x000FFF00) >> 4; /* CSSCK, ASC, DT */
> > - } else
> > - bus_setup |= (dspi->ctar[cfslave->slave.bus] & 0x78FCFFF0);
> > -
> > - cfslave->charbit =
> > - ((dspi->ctar[cfslave->slave.bus] & 0x78000000) ==
> > - 0x78000000) ? 16 : 8;
> > + }
> >
> > pbrcnt = sizeof(prescaler) / sizeof(int);
> > brcnt = sizeof(scaler) / sizeof(int);
> > @@ -259,10 +356,10 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
> > for (j = 0; j < brcnt; j++) {
> > tmp = (baud_speed / scaler[j]) * (1 + dbr);
> >
> > - if (tmp > cfslave->baudrate)
> > - diff = tmp - cfslave->baudrate;
> > + if (tmp > cfspi->baudrate)
> > + diff = tmp - cfspi->baudrate;
> > else
> > - diff = cfslave->baudrate - tmp;
> > + diff = cfspi->baudrate - tmp;
> >
> > if (diff < bestmatch) {
> > bestmatch = diff;
> > @@ -271,65 +368,173 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
> > }
> > }
> > }
> > +
> > + bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f));
> > bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
> > - dspi->ctar[cfslave->slave.bus] = bus_setup;
> > + writel(bus_setup, &dspi->ctar[bus->seq]);
> >
> > - return &cfslave->slave;
> > + return 0;
> > }
> > -#endif /* CONFIG_CF_DSPI */
> >
> > -#ifdef CONFIG_CMD_SPI
> > -int spi_cs_is_valid(unsigned int bus, unsigned int cs)
> > +static int coldfire_spi_set_mode(struct udevice *bus, uint mode)
> > {
> > - if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8)))
> > - return 1;
> > - else
> > - return 0;
> > -}
> > + struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
> > + struct dspi *dspi = cfspi->regs;
> > + u32 bus_setup = 0;
> >
> > -void spi_init(void)
> > -{
> > - cfspi_init();
> > -}
> > + cfspi->mode = mode;
> >
> > -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> > - unsigned int max_hz, unsigned int mode)
> > -{
> > - struct cf_spi_slave *cfslave;
> > + if (cfspi->mode & SPI_CPOL)
> > + bus_setup |= DSPI_CTAR_CPOL;
> > + if (cfspi->mode & SPI_CPHA)
> > + bus_setup |= DSPI_CTAR_CPHA;
> > + if (cfspi->mode & SPI_LSB_FIRST)
> > + bus_setup |= DSPI_CTAR_LSBFE;
> > +
> > + /* Overwrite default value set in platform configuration file */
> > + if (cfspi->mode & SPI_MODE_MOD) {
> > + if ((cfspi->mode & 0xF0000000) == 0)
> > + bus_setup |=
> > + readl(&dspi->ctar[bus->seq]) & 0x78000000;
> > + else
> > + bus_setup |= ((cfspi->mode & 0xF0000000) >> 1);
> >
> > - if (!spi_cs_is_valid(bus, cs))
> > - return NULL;
> > + /* PSCSCK, PASC, PDT */
> > + bus_setup |= (cfspi->mode & 0x0FC00000) >> 4;
> > + /* CSSCK, ASC, DT */
> > + bus_setup |= (cfspi->mode & 0x000FFF00) >> 4;
> > + } else {
> > + bus_setup |= (readl(&dspi->ctar[bus->seq]) & 0x78FCFFF0);
> > + }
> >
> > - cfslave = spi_alloc_slave(struct cf_spi_slave, bus, cs);
> > - if (!cfslave)
> > - return NULL;
> > + cfspi->charbit =
> > + ((readl(&dspi->ctar[bus->seq]) & 0x78000000) ==
> > + 0x78000000) ? 16 : 8;
>
> Same here?
>
Ok, done.
> >
> > - cfslave->baudrate = max_hz;
> > + setbits_be32(&dspi->ctar[bus->seq], bus_setup);
> >
> > - /* specific setup */
> > - return cfspi_setup_slave(cfslave, mode);
> > + return 0;
> > }
> >
> > -void spi_free_slave(struct spi_slave *slave)
> > +static int coldfire_spi_probe(struct udevice *bus)
> > {
> > - struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
> > + struct coldfire_spi_platdata *plat = dev_get_platdata(bus);
> > + struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
> > + struct dspi *dspi = cfspi->regs;
> > + int i;
> >
> > - free(cfslave);
> > -}
> > + cfspi->regs = (struct dspi *)plat->regs_addr;
> > + cfspi->gpio_regs = (struct gpio *)MMAP_GPIO;
> >
> > -int spi_claim_bus(struct spi_slave *slave)
> > -{
> > - return cfspi_claim_bus(slave->bus, slave->cs);
> > + cfspi->baudrate = plat->speed_hz;
> > + cfspi->mode = plat->mode;
> > +
> > + for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) {
> > + unsigned int ctar = 0;
> > +
> > + if (plat->ctar[i][0] == 0)
> > + break;
> > +
> > + ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) |
> > + DSPI_CTAR_PCSSCK(plat->ctar[i][1]) |
> > + DSPI_CTAR_PASC(plat->ctar[i][2]) |
> > + DSPI_CTAR_PDT(plat->ctar[i][3]) |
> > + DSPI_CTAR_CSSCK(plat->ctar[i][4]) |
> > + DSPI_CTAR_ASC(plat->ctar[i][5]) |
> > + DSPI_CTAR_DT(plat->ctar[i][6]) |
> > + DSPI_CTAR_BR(plat->ctar[i][7]);
> > +
> > + writel(ctar, &cfspi->regs->ctar[i]);
> > + }
> > +
> > + /* Default CTARs */
> > + for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++)
> > + writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]);
> > +
> > + dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
> > + DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
> > + DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
> > + DSPI_MCR_CRXF | DSPI_MCR_CTXF;
> > +
> > + return 0;
> > }
> >
> > -void spi_release_bus(struct spi_slave *slave)
> > +void spi_init(void)
> > {
> > - cfspi_release_bus(slave->bus, slave->cs);
> > }
> >
> > -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
> > - void *din, unsigned long flags)
> > +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
> > +static int coldfire_dspi_ofdata_to_platdata(struct udevice *bus)
> > {
> > - return cfspi_xfer(slave, bitlen, dout, din, flags);
> > + fdt_addr_t addr;
> > + struct coldfire_spi_platdata *plat = bus->platdata;
> > + const void *blob = gd->fdt_blob;
> > + int node = dev_of_offset(bus);
> > + int *ctar, len;
> > +
> > + addr = devfdt_get_addr(bus);
> > + if (addr == FDT_ADDR_T_NONE)
> > + return -ENOMEM;
> > +
> > + plat->regs_addr = addr;
> > +
> > + plat->num_cs = fdtdec_get_int(blob, node, "num-cs",
> > + MCF_DSPI_DEFAULT_MAX_CS);
> > +
> > + plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
> > + MCF_DSPI_DEFAULT_SCK_FREQ);
> > +
> > + plat->mode = fdtdec_get_int(blob, node, "spi-mode",
> > + MCF_DSPI_DEFAULT_MODE);
> > +
> > + memset(plat->ctar, 0, sizeof(plat->ctar));
> > +
> > + ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len);
> > +
> > + if (ctar && len) {
> > + int i, q, ctar_regs;
> > +
> > + ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS;
> > +
> > + if (ctar_regs > MAX_CTAR_REGS)
> > + ctar_regs = MAX_CTAR_REGS;
> > +
> > + for (i = 0; i < ctar_regs; i++) {
> > + for (q = 0; q < MAX_CTAR_FIELDS; q++)
> > + plat->ctar[i][q] = *ctar++;
> > + }
> > + }
> > +
> > + debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n",
> > + (void *)plat->regs_addr,
> > + plat->speed_hz, plat->num_cs, plat->mode);
> > +
> > + return 0;
> > }
> > -#endif /* CONFIG_CMD_SPI */
> > +
> > +static const struct udevice_id coldfire_spi_ids[] = {
> > + { .compatible = "fsl,mcf-dspi" },
> > + { }
> > +};
> > +#endif
> > +
> > +static const struct dm_spi_ops coldfire_spi_ops = {
> > + .claim_bus = coldfire_spi_claim_bus,
> > + .release_bus = coldfire_spi_release_bus,
> > + .xfer = coldfire_spi_xfer,
> > + .set_speed = coldfire_spi_set_speed,
> > + .set_mode = coldfire_spi_set_mode,
> > +};
> > +
> > +U_BOOT_DRIVER(coldfire_spi) = {
> > + .name = "spi_coldfire",
> > + .id = UCLASS_SPI,
> > + .probe = coldfire_spi_probe,
> > + .ops = &coldfire_spi_ops,
> > + .platdata_auto_alloc_size = sizeof(struct coldfire_spi_platdata),
> > + .priv_auto_alloc_size = sizeof(struct coldfire_spi_priv),
> > +#if !CONFIG_IS_ENABLED(OF_PLATDATA)
> > + .of_match = coldfire_spi_ids,
> > + .ofdata_to_platdata = coldfire_dspi_ofdata_to_platdata,
> > +#endif
> > +};
>
> This has to be as below
>
> U_BOOT_DRIVER(coldfire_spi) = {
> .name = "spi_coldfire",
> .id = UCLASS_SPI,
> #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
> .of_match = coldfire_spi_ids,
> .ofdata_to_platdata = coldfire_dspi_ofdata_to_platdata,
> .platdata_auto_alloc_size = sizeof(struct coldfire_spi_platdata),
> #endif
> .probe = coldfire_spi_probe,
> .ops = &coldfire_spi_ops,
> .priv_auto_alloc_size = sizeof(struct coldfire_spi_priv),
> };
Ok, done.
If there are no other points from you, will provide a new version in
short.
Regards,
Angelo
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v4 07/12] drivers: spi: cf_spi: convert to driver model
2019-03-10 16:17 ` Angelo Dureghello
@ 2019-03-11 17:34 ` Jagan Teki
0 siblings, 0 replies; 15+ messages in thread
From: Jagan Teki @ 2019-03-11 17:34 UTC (permalink / raw)
To: u-boot
On Sun, Mar 10, 2019 at 9:47 PM Angelo Dureghello <angelo@sysam.it> wrote:
>
> Hi Jagan,
>
> thanks for your comments,
>
> On Fri, Mar 08, 2019 at 11:30:56AM +0530, Jagan Teki wrote:
> > On Mon, Dec 17, 2018 at 1:06 AM Angelo Dureghello <angelo@sysam.it> wrote:
> > >
> > > Converting to driver model and removes non-dm code.
> > >
> > > Reviewed-by: Simon Glass <sjg@chromium.org>
> > > Signed-off-by: Angelo Dureghello <angelo@sysam.it>
> > > ---
> > > Changes for v2:
> > > - removed non DM code part
> > > - add default setup of CTAR registers
> > > - add DT CTAR register setup support
> > > Changes for v3:
> > > - changed commit head
> > > - removed spi_slave reference
> > > - add #ifdefs for the case OF_PLATDATA is used
> > > Changes for v4:
> > > - remove all internal static functions that are no more needed including
> > > their code in the standard driver methods
> > > - add helper macro for ctrl setup
> > > - fix wrong fifo level check on spi tx
> > > - move code inside same #if (avoid multiple #if on same option)
> > > - removed externals and moved bus control code here
> > > ---
> > > drivers/spi/cf_spi.c | 539 ++++++++++++++++--------
> > > include/dm/platform_data/spi_coldfire.h | 29 ++
> > > 2 files changed, 401 insertions(+), 167 deletions(-)
> > > create mode 100644 include/dm/platform_data/spi_coldfire.h
> > >
> > > diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c
> > > index 522631cbbf..3d02c87637 100644
> > > --- a/drivers/spi/cf_spi.c
> > > +++ b/drivers/spi/cf_spi.c
> > > @@ -6,23 +6,31 @@
> > > *
> > > * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
> > > * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
> > > + *
> > > + * Support for DM and DT, non-DM code removed.
> > > + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
> > > + *
> > > + * TODO: fsl_dspi.c should work as a driver for the DSPI module.
> > > */
> > >
> > > #include <common.h>
> > > +#include <dm.h>
> > > +#include <dm/platform_data/spi_coldfire.h>
> > > #include <spi.h>
> > > #include <malloc.h>
> > > +#include <wait_bit.h>
> > > +#include <asm/coldfire/dspi.h>
> > > #include <asm/immap.h>
> > > +#include <asm/io.h>
> > >
> > > -struct cf_spi_slave {
> > > - struct spi_slave slave;
> > > +struct coldfire_spi_priv {
> > > + struct dspi *regs;
> > > + struct gpio *gpio_regs;
> > > uint baudrate;
> > > + int mode;
> > > int charbit;
> > > };
> > >
> > > -extern void cfspi_port_conf(void);
> > > -extern int cfspi_claim_bus(uint bus, uint cs);
> > > -extern void cfspi_release_bus(uint bus, uint cs);
> > > -
> > > DECLARE_GLOBAL_DATA_PTR;
> > >
> > > #ifndef CONFIG_SPI_IDLE_VAL
> > > @@ -33,149 +41,267 @@ DECLARE_GLOBAL_DATA_PTR;
> > > #endif
> > > #endif
> > >
> > > -#if defined(CONFIG_CF_DSPI)
> > > /* DSPI specific mode */
> > > #define SPI_MODE_MOD 0x00200000
> > > #define SPI_DBLRATE 0x00100000
> > >
> > > -static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave)
> > > +#define MCF_DSPI_MAX_CTAR_REGS 8
> > > +
> > > +/* Default values */
> > > +#define MCF_DSPI_DEFAULT_SCK_FREQ 10000000
> > > +#define MCF_DSPI_DEFAULT_MAX_CS 4
> > > +#define MCF_DSPI_DEFAULT_MODE 0
> > > +
> > > +#define MCF_DSPI_DEFAULT_CTAR (DSPI_CTAR_TRSZ(7) | \
> > > + DSPI_CTAR_PCSSCK_1CLK | \
> > > + DSPI_CTAR_PASC(0) | \
> > > + DSPI_CTAR_PDT(0) | \
> > > + DSPI_CTAR_CSSCK(0) | \
> > > + DSPI_CTAR_ASC(0) | \
> > > + DSPI_CTAR_DT(1) | \
> > > + DSPI_CTAR_BR(6))
> > > +
> > > +#define setup_ctrl(ctrl, cs) ((ctrl & 0xFF000000) | ((1 << cs) << 16))
> > > +
> > > +static inline void cfspi_tx(struct coldfire_spi_priv *cfspi,
> > > + u32 ctrl, u16 data)
> > > {
> > > - return container_of(slave, struct cf_spi_slave, slave);
> > > + /*
> > > + * Need to check fifo level here
> > > + */
> > > + while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 0x4000)
> > > + ;
> > > +
> > > + writel(ctrl | data, &cfspi->regs->tfr);
> > > }
> > >
> > > -static void cfspi_init(void)
> > > +static inline u16 cfspi_rx(struct coldfire_spi_priv *cfspi)
> > > {
> > > - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
> > > -
> > > - cfspi_port_conf(); /* port configuration */
> > > + while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0)
> > > + ;
> > >
> > > - dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
> > > - DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
> > > - DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
> > > - DSPI_MCR_CRXF | DSPI_MCR_CTXF;
> > > + return readw(&cfspi->regs->rfr);
> > > +}
> >
> > Look like you include wait header and forgot to implement
> > wait_for_bit_* logic which I commented before.
> >
>
> I tried to use it, this is why i forgot the header.
> The fact is that wait_for_bit_* logic wait for one or more bit(s),
> but cannot wait for one "of" more bit(s), as in the above case.
> So seems cannot apply here.
>
> > >
> > > - /* Default setting in platform configuration */
> > > -#ifdef CONFIG_SYS_DSPI_CTAR0
> > > - dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0;
> > > -#endif
> > > -#ifdef CONFIG_SYS_DSPI_CTAR1
> > > - dspi->ctar[1] = CONFIG_SYS_DSPI_CTAR1;
> > > -#endif
> > > -#ifdef CONFIG_SYS_DSPI_CTAR2
> > > - dspi->ctar[2] = CONFIG_SYS_DSPI_CTAR2;
> > > -#endif
> > > -#ifdef CONFIG_SYS_DSPI_CTAR3
> > > - dspi->ctar[3] = CONFIG_SYS_DSPI_CTAR3;
> > > -#endif
> > > -#ifdef CONFIG_SYS_DSPI_CTAR4
> > > - dspi->ctar[4] = CONFIG_SYS_DSPI_CTAR4;
> > > +static int coldfire_spi_claim_bus(struct udevice *dev)
> > > +{
> > > + struct udevice *bus = dev->parent;
> > > + struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
> > > + struct dspi *dspi = cfspi->regs;
> > > +#if defined(CONFIG_MCF5445x) || \
> > > + defined(CONFIG_MCF5441x) || defined(CONFIG_MCF5227x)
> > > + struct dm_spi_slave_platdata *slave_plat =
> > > + dev_get_parent_platdata(dev);
> > > + struct gpio *gpio = cfspi->gpio_regs;
> > > #endif
> > > -#ifdef CONFIG_SYS_DSPI_CTAR5
> > > - dspi->ctar[5] = CONFIG_SYS_DSPI_CTAR5;
> > > +
> > > + if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
> > > + return -1;
> > > +
> > > + /* Clear FIFO and resume transfer */
> > > + clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
> > > +
> > > +#ifdef CONFIG_MCF5445x
> > > + switch (slave_plat->cs) {
> > > + case 0:
> > > + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
> > > + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
> > > + break;
> > > + case 1:
> > > + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
> > > + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
> > > + break;
> > > + case 2:
> > > + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
> > > + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
> > > + break;
> > > + case 3:
> > > + clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
> > > + setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
> > > + break;
> > > + case 5:
> > > + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
> > > + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
> > > + break;
> > > + }
> > > #endif
> > > -#ifdef CONFIG_SYS_DSPI_CTAR6
> > > - dspi->ctar[6] = CONFIG_SYS_DSPI_CTAR6;
> > > +
> > > +#ifdef CONFIG_MCF5441x
> > > + switch (slave_plat->cs) {
> > > + case 0:
> > > + clrbits_8(&gpio->par_dspi0, ~GPIO_PAR_DSPI0_PCS0_MASK);
> > > + setbits_8(&gpio->par_dspi0, GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
> > > + break;
> > > + case 1:
> > > + clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
> > > + setbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
> > > + break;
> > > + }
> > > #endif
> > > -#ifdef CONFIG_SYS_DSPI_CTAR7
> > > - dspi->ctar[7] = CONFIG_SYS_DSPI_CTAR7;
> > > +
> > > +#ifdef CONFIG_MCF5227x
> > > + switch (slave_plat->cs) {
> > > + case 0:
> > > + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
> > > + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
> > > + break;
> > > + case 2:
> > > + clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
> > > + setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
> > > + break;
> > > + }
> > > #endif
> > > + return 0;
> > > }
> > >
> > > -static void cfspi_tx(u32 ctrl, u16 data)
> > > +static int coldfire_spi_release_bus(struct udevice *dev)
> > > {
> > > - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
> > > -
> > > - while ((dspi->sr & 0x0000F000) >= 4) ;
> > > -
> > > - dspi->tfr = (ctrl | data);
> > > -}
> > > + struct udevice *bus = dev->parent;
> > > + struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
> > > + struct dspi *dspi = cfspi->regs;
> > > +#if defined(CONFIG_MCF5445x) || \
> > > + defined(CONFIG_MCF5441x) || defined(CONFIG_MCF5227x)
> > > + struct dm_spi_slave_platdata *slave_plat =
> > > + dev_get_parent_platdata(dev);
> > > + struct gpio *gpio = cfspi->gpio_regs;
> > > +#endif
> > >
> > > -static u16 cfspi_rx(void)
> > > -{
> > > - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
> > > + /* Clear FIFO */
> > > + clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
> > > +
> > > +#ifdef CONFIG_MCF5445x
> > > + switch (slave_plat->cs) {
> > > + case 0:
> > > + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
> > > + break;
> > > + case 1:
> > > + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
> > > + break;
> > > + case 2:
> > > + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
> > > + break;
> > > + case 3:
> > > + clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
> > > + break;
> > > + case 5:
> > > + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
> > > + break;
> > > + }
> > > +#endif
> > >
> > > - while ((dspi->sr & 0x000000F0) == 0) ;
> > > +#ifdef CONFIG_MCF5441x
> > > + if (slave_plat->cs == 1)
> > > + clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
> > > +#endif
> > >
> > > - return (dspi->rfr & 0xFFFF);
> > > +#ifdef CONFIG_MCF5227x
> >
> > Like this macro, along with above CONFIG_MCF5445x
> >
> > Does it support separate compatible between these diff, if yes we can
> > handle these via driver data.
> >
> Ok, fixing this, nearly done, should be able to avoid
> all the config macroes probably.
>
> > > + switch (slave_plat->cs) {
> > > + case 0:
> > > + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
> > > + break;
> > > + case 2:
> > > + clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
> > > + break;
> > > + }
> > > +#endif
> > > + return 0;
> > > }
> > >
> > > -static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
> > > - void *din, ulong flags)
> > > +static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
> > > + const void *dout, void *din,
> > > + unsigned long flags)
> > > {
> > > - struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
> > > + struct udevice *bus = dev_get_parent(dev);
> > > + struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
> > > + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
> > > u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
> > > u8 *spi_rd = NULL, *spi_wr = NULL;
> > > - static u32 ctrl = 0;
> > > + static u32 ctrl;
> > > uint len = bitlen >> 3;
> > >
> > > - if (cfslave->charbit == 16) {
> > > + if (cfspi->charbit == 16) {
> > > bitlen >>= 1;
> > > - spi_wr16 = (u16 *) dout;
> > > - spi_rd16 = (u16 *) din;
> > > + spi_wr16 = (u16 *)dout;
> > > + spi_rd16 = (u16 *)din;
> > > } else {
> > > - spi_wr = (u8 *) dout;
> > > - spi_rd = (u8 *) din;
> > > + spi_wr = (u8 *)dout;
> > > + spi_rd = (u8 *)din;
> > > }
> > >
> > > if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
> > > ctrl |= DSPI_TFR_CONT;
> > >
> > > - ctrl = (ctrl & 0xFF000000) | ((1 << slave->cs) << 16);
> > > + ctrl = setup_ctrl(ctrl, slave_plat->cs);
> > >
> > > if (len > 1) {
> > > int tmp_len = len - 1;
> > > +
> > > while (tmp_len--) {
> > > - if (dout != NULL) {
> > > - if (cfslave->charbit == 16)
> > > - cfspi_tx(ctrl, *spi_wr16++);
> > > + if (dout) {
> > > + if (cfspi->charbit == 16)
> > > + cfspi_tx(cfspi, ctrl, *spi_wr16++);
> > > else
> > > - cfspi_tx(ctrl, *spi_wr++);
> > > - cfspi_rx();
> > > + cfspi_tx(cfspi, ctrl, *spi_wr++);
> > > + cfspi_rx(cfspi);
> > > }
> > >
> > > - if (din != NULL) {
> > > - cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
> > > - if (cfslave->charbit == 16)
> > > - *spi_rd16++ = cfspi_rx();
> > > + if (din) {
> > > + cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
> > > + if (cfspi->charbit == 16)
> > > + *spi_rd16++ = cfspi_rx(cfspi);
> > > else
> > > - *spi_rd++ = cfspi_rx();
> > > + *spi_rd++ = cfspi_rx(cfspi);
> > > }
> > > }
> > >
> > > len = 1; /* remaining byte */
> > > }
> > >
> > > - if ((flags & SPI_XFER_END) == SPI_XFER_END)
> > > + if (flags & SPI_XFER_END)
> > > ctrl &= ~DSPI_TFR_CONT;
> > >
> > > if (len) {
> > > - if (dout != NULL) {
> > > - if (cfslave->charbit == 16)
> > > - cfspi_tx(ctrl, *spi_wr16);
> > > + if (dout) {
> > > + if (cfspi->charbit == 16)
> > > + cfspi_tx(cfspi, ctrl, *spi_wr16);
> > > else
> > > - cfspi_tx(ctrl, *spi_wr);
> > > - cfspi_rx();
> > > + cfspi_tx(cfspi, ctrl, *spi_wr);
> > > + cfspi_rx(cfspi);
> > > }
> > >
> > > - if (din != NULL) {
> > > - cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
> > > - if (cfslave->charbit == 16)
> > > - *spi_rd16 = cfspi_rx();
> > > + if (din) {
> > > + cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
> > > + if (cfspi->charbit == 16)
> > > + *spi_rd16 = cfspi_rx(cfspi);
> > > else
> > > - *spi_rd = cfspi_rx();
> > > + *spi_rd = cfspi_rx(cfspi);
> > > }
> > > } else {
> > > /* dummy read */
> > > - cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
> > > - cfspi_rx();
> > > + cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
> > > + cfspi_rx(cfspi);
> > > }
> > >
> > > return 0;
> > > }
> > >
> > > -static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
> > > - uint mode)
> > > +static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz)
> > > {
> > > + struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
> > > + struct dspi *dspi = cfspi->regs;
> > > + int prescaler[] = { 2, 3, 5, 7 };
> > > + int scaler[] = {
> > > + 2, 4, 6, 8,
> > > + 16, 32, 64, 128,
> > > + 256, 512, 1024, 2048,
> > > + 4096, 8192, 16384, 32768
> > > + };
> > > + int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
> > > + int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed;
> >
> > bestmatch, replace with macro?
> >
>
> Ok, done.
>
> > > + u32 bus_setup;
> > > +
> > > + cfspi->baudrate = max_hz;
> > > +
> > > /*
> > > * bit definition for mode:
> > > * bit 31 - 28: Transfer size 3 to 16 bits
> > > @@ -189,66 +315,37 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
> > > * 11 - 8: Delay after transfer scaler
> > > * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
> > > */
> > > - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
> > > - int prescaler[] = { 2, 3, 5, 7 };
> > > - int scaler[] = {
> > > - 2, 4, 6, 8,
> > > - 16, 32, 64, 128,
> > > - 256, 512, 1024, 2048,
> > > - 4096, 8192, 16384, 32768
> > > - };
> > > - int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
> > > - int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed;
> > > - u32 bus_setup = 0;
> > > +
> > > + /* Read current setup */
> > > + bus_setup = readl(&dspi->ctar[bus->seq]);
> > >
> > > tmp = (prescaler[3] * scaler[15]);
> > > /* Maximum and minimum baudrate it can handle */
> > > - if ((cfslave->baudrate > (gd->bus_clk >> 1)) ||
> > > - (cfslave->baudrate < (gd->bus_clk / tmp))) {
> > > + if ((cfspi->baudrate > (gd->bus_clk >> 1)) ||
> > > + (cfspi->baudrate < (gd->bus_clk / tmp))) {
> > > printf("Exceed baudrate limitation: Max %d - Min %d\n",
> > > (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
> > > - return NULL;
> > > + return -1;
> > > }
> > >
> > > /* Activate Double Baud when it exceed 1/4 the bus clk */
> > > - if ((CONFIG_SYS_DSPI_CTAR0 & DSPI_CTAR_DBR) ||
> > > - (cfslave->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
> > > + if ((bus_setup & DSPI_CTAR_DBR) ||
> > > + (cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
> > > bus_setup |= DSPI_CTAR_DBR;
> > > dbr = 1;
> > > }
> > >
> > > - if (mode & SPI_CPOL)
> > > - bus_setup |= DSPI_CTAR_CPOL;
> > > - if (mode & SPI_CPHA)
> > > - bus_setup |= DSPI_CTAR_CPHA;
> > > - if (mode & SPI_LSB_FIRST)
> > > - bus_setup |= DSPI_CTAR_LSBFE;
> > > -
> > > /* Overwrite default value set in platform configuration file */
> > > - if (mode & SPI_MODE_MOD) {
> > > -
> > > - if ((mode & 0xF0000000) == 0)
> > > - bus_setup |=
> > > - dspi->ctar[cfslave->slave.bus] & 0x78000000;
> > > - else
> > > - bus_setup |= ((mode & 0xF0000000) >> 1);
> > > -
> > > + if (cfspi->mode & SPI_MODE_MOD) {
> > > /*
> > > * Check to see if it is enabled by default in platform
> > > * config, or manual setting passed by mode parameter
> > > */
> > > - if (mode & SPI_DBLRATE) {
> > > + if (cfspi->mode & SPI_DBLRATE) {
> > > bus_setup |= DSPI_CTAR_DBR;
> > > dbr = 1;
> > > }
> > > - bus_setup |= (mode & 0x0FC00000) >> 4; /* PSCSCK, PASC, PDT */
> > > - bus_setup |= (mode & 0x000FFF00) >> 4; /* CSSCK, ASC, DT */
> > > - } else
> > > - bus_setup |= (dspi->ctar[cfslave->slave.bus] & 0x78FCFFF0);
> > > -
> > > - cfslave->charbit =
> > > - ((dspi->ctar[cfslave->slave.bus] & 0x78000000) ==
> > > - 0x78000000) ? 16 : 8;
> > > + }
> > >
> > > pbrcnt = sizeof(prescaler) / sizeof(int);
> > > brcnt = sizeof(scaler) / sizeof(int);
> > > @@ -259,10 +356,10 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
> > > for (j = 0; j < brcnt; j++) {
> > > tmp = (baud_speed / scaler[j]) * (1 + dbr);
> > >
> > > - if (tmp > cfslave->baudrate)
> > > - diff = tmp - cfslave->baudrate;
> > > + if (tmp > cfspi->baudrate)
> > > + diff = tmp - cfspi->baudrate;
> > > else
> > > - diff = cfslave->baudrate - tmp;
> > > + diff = cfspi->baudrate - tmp;
> > >
> > > if (diff < bestmatch) {
> > > bestmatch = diff;
> > > @@ -271,65 +368,173 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
> > > }
> > > }
> > > }
> > > +
> > > + bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f));
> > > bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
> > > - dspi->ctar[cfslave->slave.bus] = bus_setup;
> > > + writel(bus_setup, &dspi->ctar[bus->seq]);
> > >
> > > - return &cfslave->slave;
> > > + return 0;
> > > }
> > > -#endif /* CONFIG_CF_DSPI */
> > >
> > > -#ifdef CONFIG_CMD_SPI
> > > -int spi_cs_is_valid(unsigned int bus, unsigned int cs)
> > > +static int coldfire_spi_set_mode(struct udevice *bus, uint mode)
> > > {
> > > - if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8)))
> > > - return 1;
> > > - else
> > > - return 0;
> > > -}
> > > + struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
> > > + struct dspi *dspi = cfspi->regs;
> > > + u32 bus_setup = 0;
> > >
> > > -void spi_init(void)
> > > -{
> > > - cfspi_init();
> > > -}
> > > + cfspi->mode = mode;
> > >
> > > -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> > > - unsigned int max_hz, unsigned int mode)
> > > -{
> > > - struct cf_spi_slave *cfslave;
> > > + if (cfspi->mode & SPI_CPOL)
> > > + bus_setup |= DSPI_CTAR_CPOL;
> > > + if (cfspi->mode & SPI_CPHA)
> > > + bus_setup |= DSPI_CTAR_CPHA;
> > > + if (cfspi->mode & SPI_LSB_FIRST)
> > > + bus_setup |= DSPI_CTAR_LSBFE;
> > > +
> > > + /* Overwrite default value set in platform configuration file */
> > > + if (cfspi->mode & SPI_MODE_MOD) {
> > > + if ((cfspi->mode & 0xF0000000) == 0)
> > > + bus_setup |=
> > > + readl(&dspi->ctar[bus->seq]) & 0x78000000;
> > > + else
> > > + bus_setup |= ((cfspi->mode & 0xF0000000) >> 1);
> > >
> > > - if (!spi_cs_is_valid(bus, cs))
> > > - return NULL;
> > > + /* PSCSCK, PASC, PDT */
> > > + bus_setup |= (cfspi->mode & 0x0FC00000) >> 4;
> > > + /* CSSCK, ASC, DT */
> > > + bus_setup |= (cfspi->mode & 0x000FFF00) >> 4;
> > > + } else {
> > > + bus_setup |= (readl(&dspi->ctar[bus->seq]) & 0x78FCFFF0);
> > > + }
> > >
> > > - cfslave = spi_alloc_slave(struct cf_spi_slave, bus, cs);
> > > - if (!cfslave)
> > > - return NULL;
> > > + cfspi->charbit =
> > > + ((readl(&dspi->ctar[bus->seq]) & 0x78000000) ==
> > > + 0x78000000) ? 16 : 8;
> >
> > Same here?
> >
>
> Ok, done.
>
> > >
> > > - cfslave->baudrate = max_hz;
> > > + setbits_be32(&dspi->ctar[bus->seq], bus_setup);
> > >
> > > - /* specific setup */
> > > - return cfspi_setup_slave(cfslave, mode);
> > > + return 0;
> > > }
> > >
> > > -void spi_free_slave(struct spi_slave *slave)
> > > +static int coldfire_spi_probe(struct udevice *bus)
> > > {
> > > - struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
> > > + struct coldfire_spi_platdata *plat = dev_get_platdata(bus);
> > > + struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
> > > + struct dspi *dspi = cfspi->regs;
> > > + int i;
> > >
> > > - free(cfslave);
> > > -}
> > > + cfspi->regs = (struct dspi *)plat->regs_addr;
> > > + cfspi->gpio_regs = (struct gpio *)MMAP_GPIO;
> > >
> > > -int spi_claim_bus(struct spi_slave *slave)
> > > -{
> > > - return cfspi_claim_bus(slave->bus, slave->cs);
> > > + cfspi->baudrate = plat->speed_hz;
> > > + cfspi->mode = plat->mode;
> > > +
> > > + for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) {
> > > + unsigned int ctar = 0;
> > > +
> > > + if (plat->ctar[i][0] == 0)
> > > + break;
> > > +
> > > + ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) |
> > > + DSPI_CTAR_PCSSCK(plat->ctar[i][1]) |
> > > + DSPI_CTAR_PASC(plat->ctar[i][2]) |
> > > + DSPI_CTAR_PDT(plat->ctar[i][3]) |
> > > + DSPI_CTAR_CSSCK(plat->ctar[i][4]) |
> > > + DSPI_CTAR_ASC(plat->ctar[i][5]) |
> > > + DSPI_CTAR_DT(plat->ctar[i][6]) |
> > > + DSPI_CTAR_BR(plat->ctar[i][7]);
> > > +
> > > + writel(ctar, &cfspi->regs->ctar[i]);
> > > + }
> > > +
> > > + /* Default CTARs */
> > > + for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++)
> > > + writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]);
> > > +
> > > + dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
> > > + DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
> > > + DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
> > > + DSPI_MCR_CRXF | DSPI_MCR_CTXF;
> > > +
> > > + return 0;
> > > }
> > >
> > > -void spi_release_bus(struct spi_slave *slave)
> > > +void spi_init(void)
> > > {
> > > - cfspi_release_bus(slave->bus, slave->cs);
> > > }
> > >
> > > -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
> > > - void *din, unsigned long flags)
> > > +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
> > > +static int coldfire_dspi_ofdata_to_platdata(struct udevice *bus)
> > > {
> > > - return cfspi_xfer(slave, bitlen, dout, din, flags);
> > > + fdt_addr_t addr;
> > > + struct coldfire_spi_platdata *plat = bus->platdata;
> > > + const void *blob = gd->fdt_blob;
> > > + int node = dev_of_offset(bus);
> > > + int *ctar, len;
> > > +
> > > + addr = devfdt_get_addr(bus);
> > > + if (addr == FDT_ADDR_T_NONE)
> > > + return -ENOMEM;
> > > +
> > > + plat->regs_addr = addr;
> > > +
> > > + plat->num_cs = fdtdec_get_int(blob, node, "num-cs",
> > > + MCF_DSPI_DEFAULT_MAX_CS);
> > > +
> > > + plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
> > > + MCF_DSPI_DEFAULT_SCK_FREQ);
> > > +
> > > + plat->mode = fdtdec_get_int(blob, node, "spi-mode",
> > > + MCF_DSPI_DEFAULT_MODE);
> > > +
> > > + memset(plat->ctar, 0, sizeof(plat->ctar));
> > > +
> > > + ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len);
> > > +
> > > + if (ctar && len) {
> > > + int i, q, ctar_regs;
> > > +
> > > + ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS;
> > > +
> > > + if (ctar_regs > MAX_CTAR_REGS)
> > > + ctar_regs = MAX_CTAR_REGS;
> > > +
> > > + for (i = 0; i < ctar_regs; i++) {
> > > + for (q = 0; q < MAX_CTAR_FIELDS; q++)
> > > + plat->ctar[i][q] = *ctar++;
> > > + }
> > > + }
> > > +
> > > + debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n",
> > > + (void *)plat->regs_addr,
> > > + plat->speed_hz, plat->num_cs, plat->mode);
> > > +
> > > + return 0;
> > > }
> > > -#endif /* CONFIG_CMD_SPI */
> > > +
> > > +static const struct udevice_id coldfire_spi_ids[] = {
> > > + { .compatible = "fsl,mcf-dspi" },
> > > + { }
> > > +};
> > > +#endif
> > > +
> > > +static const struct dm_spi_ops coldfire_spi_ops = {
> > > + .claim_bus = coldfire_spi_claim_bus,
> > > + .release_bus = coldfire_spi_release_bus,
> > > + .xfer = coldfire_spi_xfer,
> > > + .set_speed = coldfire_spi_set_speed,
> > > + .set_mode = coldfire_spi_set_mode,
> > > +};
> > > +
> > > +U_BOOT_DRIVER(coldfire_spi) = {
> > > + .name = "spi_coldfire",
> > > + .id = UCLASS_SPI,
> > > + .probe = coldfire_spi_probe,
> > > + .ops = &coldfire_spi_ops,
> > > + .platdata_auto_alloc_size = sizeof(struct coldfire_spi_platdata),
> > > + .priv_auto_alloc_size = sizeof(struct coldfire_spi_priv),
> > > +#if !CONFIG_IS_ENABLED(OF_PLATDATA)
> > > + .of_match = coldfire_spi_ids,
> > > + .ofdata_to_platdata = coldfire_dspi_ofdata_to_platdata,
> > > +#endif
> > > +};
> >
> > This has to be as below
> >
> > U_BOOT_DRIVER(coldfire_spi) = {
> > .name = "spi_coldfire",
> > .id = UCLASS_SPI,
> > #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
> > .of_match = coldfire_spi_ids,
> > .ofdata_to_platdata = coldfire_dspi_ofdata_to_platdata,
> > .platdata_auto_alloc_size = sizeof(struct coldfire_spi_platdata),
> > #endif
> > .probe = coldfire_spi_probe,
> > .ops = &coldfire_spi_ops,
> > .priv_auto_alloc_size = sizeof(struct coldfire_spi_priv),
> > };
>
> Ok, done.
>
> If there are no other points from you, will provide a new version in
> short.
Just send next version, meanwhile I will look for wait_for_bit will
combine while applying.
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2019-03-11 17:34 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-12-16 11:22 [U-Boot] [PATCH v4 01/12] m68k: add basic set of devicetrees Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 02/12] m68k: architecture changes to support fdt Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 03/12] m68k: add initial dts files for all m68k boards Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 04/12] m68k: enabling long jumps on mcf54x5 SoCs Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 05/12] configs: enable use of DT for all m68k boards Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 06/12] drivers: spi: cf_spi: add Kconfig option Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 07/12] drivers: spi: cf_spi: convert to driver model Angelo Dureghello
2019-03-08 6:00 ` Jagan Teki
2019-03-10 16:17 ` Angelo Dureghello
2019-03-11 17:34 ` Jagan Teki
2018-12-16 11:22 ` [U-Boot] [PATCH v4 08/12] configs: add DM_SPI config option Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 09/12] drivers: serial: mcfuart: add DT support Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 10/12] configs: remove CONFIG_SYS_DSPI_XX references Angelo Dureghello
2018-12-16 11:22 ` [U-Boot] [PATCH v4 11/12] m68k: add OF control support to m68k Angelo Dureghello
2018-12-16 11:23 ` [U-Boot] [PATCH v4 12/12] m68k: move dspi bus control functions into cf_spi.c driver Angelo Dureghello
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.