* [PATCH 0/3] clk: renesas: r8a779g0: Add clocks for video capture
@ 2023-02-11 14:36 Niklas Söderlund
2023-02-11 14:36 ` [PATCH 1/3] clk: renesas: r8a779g0: Add CSI-2 clocks Niklas Söderlund
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Niklas Söderlund @ 2023-02-11 14:36 UTC (permalink / raw)
To: Geert Uytterhoeven, linux-clk; +Cc: linux-renesas-soc, Niklas Söderlund
Hi Geert,
This series adds all clocks needed to capture video on V4H.
Niklas Söderlund (3):
clk: renesas: r8a779g0: Add CSI-2 clocks
clk: renesas: r8a779g0: Add ISPCS clocks
clk: renesas: r8a779g0: Add VIN clocks
drivers/clk/renesas/r8a779g0-cpg-mssr.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
--
2.39.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/3] clk: renesas: r8a779g0: Add CSI-2 clocks
2023-02-11 14:36 [PATCH 0/3] clk: renesas: r8a779g0: Add clocks for video capture Niklas Söderlund
@ 2023-02-11 14:36 ` Niklas Söderlund
2023-02-13 16:18 ` Geert Uytterhoeven
2023-02-11 14:36 ` [PATCH 2/3] clk: renesas: r8a779g0: Add ISPCS clocks Niklas Söderlund
2023-02-11 14:36 ` [PATCH 3/3] clk: renesas: r8a779g0: Add VIN clocks Niklas Söderlund
2 siblings, 1 reply; 7+ messages in thread
From: Niklas Söderlund @ 2023-02-11 14:36 UTC (permalink / raw)
To: Geert Uytterhoeven, linux-clk; +Cc: linux-renesas-soc, Niklas Söderlund
Add the CSI core clock and the CSI40 and CSI41 module clocks, which are
used by the CSI-2 Interfaces on the Renesas R-Car V4H (R8A779G0) SoC.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
---
drivers/clk/renesas/r8a779g0-cpg-mssr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 7fca11204f74..baed1b8601bf 100644
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -146,6 +146,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1),
DEF_DIV6P1("canfd", R8A779G0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
+ DEF_DIV6P1("csi", R8A779G0_CLK_CSI, CLK_PLL5_DIV4, 0x880),
DEF_FIXED("dsiref", R8A779G0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1),
DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884),
@@ -164,7 +165,9 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC),
DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC),
DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC),
+ DEF_MOD("csi40", 331, R8A779G0_CLK_CSI),
DEF_MOD("canfd0", 328, R8A779G0_CLK_SASYNCPERD2),
+ DEF_MOD("csi41", 400, R8A779G0_CLK_CSI),
DEF_MOD("dis0", 411, R8A779G0_CLK_VIOBUSD2),
DEF_MOD("dsitxlink0", 415, R8A779G0_CLK_VIOBUSD2),
DEF_MOD("dsitxlink1", 416, R8A779G0_CLK_VIOBUSD2),
--
2.39.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/3] clk: renesas: r8a779g0: Add ISPCS clocks
2023-02-11 14:36 [PATCH 0/3] clk: renesas: r8a779g0: Add clocks for video capture Niklas Söderlund
2023-02-11 14:36 ` [PATCH 1/3] clk: renesas: r8a779g0: Add CSI-2 clocks Niklas Söderlund
@ 2023-02-11 14:36 ` Niklas Söderlund
2023-02-13 16:32 ` Geert Uytterhoeven
2023-02-11 14:36 ` [PATCH 3/3] clk: renesas: r8a779g0: Add VIN clocks Niklas Söderlund
2 siblings, 1 reply; 7+ messages in thread
From: Niklas Söderlund @ 2023-02-11 14:36 UTC (permalink / raw)
To: Geert Uytterhoeven, linux-clk; +Cc: linux-renesas-soc, Niklas Söderlund
Add the ISPCS0 and ISPCS1 module clocks, which are used by the ISPCS
modules on the Renesas R-Car V4H (R8A779G0) SoC.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
---
drivers/clk/renesas/r8a779g0-cpg-mssr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index baed1b8601bf..0ae3c7f43ce7 100644
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -184,6 +184,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
DEF_MOD("i2c4", 522, R8A779G0_CLK_S0D6_PER),
DEF_MOD("i2c5", 523, R8A779G0_CLK_S0D6_PER),
DEF_MOD("irqc", 611, R8A779G0_CLK_CL16M),
+ DEF_MOD("ispcs0", 612, R8A779G0_CLK_S0D2_VIO),
+ DEF_MOD("ispcs1", 613, R8A779G0_CLK_S0D2_VIO),
DEF_MOD("msi0", 618, R8A779G0_CLK_MSO),
DEF_MOD("msi1", 619, R8A779G0_CLK_MSO),
DEF_MOD("msi2", 620, R8A779G0_CLK_MSO),
--
2.39.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/3] clk: renesas: r8a779g0: Add VIN clocks
2023-02-11 14:36 [PATCH 0/3] clk: renesas: r8a779g0: Add clocks for video capture Niklas Söderlund
2023-02-11 14:36 ` [PATCH 1/3] clk: renesas: r8a779g0: Add CSI-2 clocks Niklas Söderlund
2023-02-11 14:36 ` [PATCH 2/3] clk: renesas: r8a779g0: Add ISPCS clocks Niklas Söderlund
@ 2023-02-11 14:36 ` Niklas Söderlund
2023-02-13 16:39 ` Geert Uytterhoeven
2 siblings, 1 reply; 7+ messages in thread
From: Niklas Söderlund @ 2023-02-11 14:36 UTC (permalink / raw)
To: Geert Uytterhoeven, linux-clk; +Cc: linux-renesas-soc, Niklas Söderlund
Add the VIN module clocks, which are used by the VIN modules on the
Renesas R-Car V4H (R8A779G0) SoC.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
---
drivers/clk/renesas/r8a779g0-cpg-mssr.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 0ae3c7f43ce7..dedbe1a6767c 100644
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -207,6 +207,22 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
DEF_MOD("tmu3", 716, R8A779G0_CLK_SASYNCPERD2),
DEF_MOD("tmu4", 717, R8A779G0_CLK_SASYNCPERD2),
DEF_MOD("tpu0", 718, R8A779G0_CLK_SASYNCPERD4),
+ DEF_MOD("vin00", 730, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin01", 731, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin02", 800, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin03", 801, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin04", 802, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin05", 803, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin06", 804, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin07", 805, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin10", 806, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin11", 807, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin12", 808, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin13", 809, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin14", 810, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin15", 811, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin16", 812, R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin17", 813, R8A779G0_CLK_S0D4_VIO),
DEF_MOD("vspd0", 830, R8A779G0_CLK_VIOBUSD2),
DEF_MOD("vspd1", 831, R8A779G0_CLK_VIOBUSD2),
DEF_MOD("wdt1:wdt0", 907, R8A779G0_CLK_R),
--
2.39.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/3] clk: renesas: r8a779g0: Add CSI-2 clocks
2023-02-11 14:36 ` [PATCH 1/3] clk: renesas: r8a779g0: Add CSI-2 clocks Niklas Söderlund
@ 2023-02-13 16:18 ` Geert Uytterhoeven
0 siblings, 0 replies; 7+ messages in thread
From: Geert Uytterhoeven @ 2023-02-13 16:18 UTC (permalink / raw)
To: Niklas Söderlund; +Cc: linux-clk, linux-renesas-soc
Hi Niklas,
On Sat, Feb 11, 2023 at 3:37 PM Niklas Söderlund
<niklas.soderlund+renesas@ragnatech.se> wrote:
> Add the CSI core clock and the CSI40 and CSI41 module clocks, which are
> used by the CSI-2 Interfaces on the Renesas R-Car V4H (R8A779G0) SoC.
>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Thanks for your patch!
> --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> @@ -146,6 +146,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
> DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
> DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1),
> DEF_DIV6P1("canfd", R8A779G0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
> + DEF_DIV6P1("csi", R8A779G0_CLK_CSI, CLK_PLL5_DIV4, 0x880),
> DEF_FIXED("dsiref", R8A779G0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1),
> DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884),
>
> @@ -164,7 +165,9 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
> DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC),
> DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC),
> DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC),
> + DEF_MOD("csi40", 331, R8A779G0_CLK_CSI),
I will move this one one line down while applying, to preserve sort order.
> DEF_MOD("canfd0", 328, R8A779G0_CLK_SASYNCPERD2),
> + DEF_MOD("csi41", 400, R8A779G0_CLK_CSI),
> DEF_MOD("dis0", 411, R8A779G0_CLK_VIOBUSD2),
> DEF_MOD("dsitxlink0", 415, R8A779G0_CLK_VIOBUSD2),
> DEF_MOD("dsitxlink1", 416, R8A779G0_CLK_VIOBUSD2),
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v6.4.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/3] clk: renesas: r8a779g0: Add ISPCS clocks
2023-02-11 14:36 ` [PATCH 2/3] clk: renesas: r8a779g0: Add ISPCS clocks Niklas Söderlund
@ 2023-02-13 16:32 ` Geert Uytterhoeven
0 siblings, 0 replies; 7+ messages in thread
From: Geert Uytterhoeven @ 2023-02-13 16:32 UTC (permalink / raw)
To: Niklas Söderlund; +Cc: linux-clk, linux-renesas-soc
On Sat, Feb 11, 2023 at 3:37 PM Niklas Söderlund
<niklas.soderlund+renesas@ragnatech.se> wrote:
> Add the ISPCS0 and ISPCS1 module clocks, which are used by the ISPCS
> modules on the Renesas R-Car V4H (R8A779G0) SoC.
>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v6.4.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 3/3] clk: renesas: r8a779g0: Add VIN clocks
2023-02-11 14:36 ` [PATCH 3/3] clk: renesas: r8a779g0: Add VIN clocks Niklas Söderlund
@ 2023-02-13 16:39 ` Geert Uytterhoeven
0 siblings, 0 replies; 7+ messages in thread
From: Geert Uytterhoeven @ 2023-02-13 16:39 UTC (permalink / raw)
To: Niklas Söderlund; +Cc: linux-clk, linux-renesas-soc
On Sat, Feb 11, 2023 at 3:37 PM Niklas Söderlund
<niklas.soderlund+renesas@ragnatech.se> wrote:
> Add the VIN module clocks, which are used by the VIN modules on the
> Renesas R-Car V4H (R8A779G0) SoC.
>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v6.4.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-02-13 16:39 UTC | newest]
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2023-02-11 14:36 [PATCH 0/3] clk: renesas: r8a779g0: Add clocks for video capture Niklas Söderlund
2023-02-11 14:36 ` [PATCH 1/3] clk: renesas: r8a779g0: Add CSI-2 clocks Niklas Söderlund
2023-02-13 16:18 ` Geert Uytterhoeven
2023-02-11 14:36 ` [PATCH 2/3] clk: renesas: r8a779g0: Add ISPCS clocks Niklas Söderlund
2023-02-13 16:32 ` Geert Uytterhoeven
2023-02-11 14:36 ` [PATCH 3/3] clk: renesas: r8a779g0: Add VIN clocks Niklas Söderlund
2023-02-13 16:39 ` Geert Uytterhoeven
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