[PATCH 0/6] Optimize pinctrl image size for RZ/G SoC's

[PATCH 0/6] Optimize pinctrl image size for RZ/G SoC's

[Biju Das]

This patch series aims to optimize pinctrl image size of RZ/G[1|2] SoC's
when the corresponding RCar SoC is disabled from the config.

Before applying this patch
--------------------------
$ size drivers/pinctrl/renesas/*.o
   text	   data	    bss	    dec	    hex	filename
  52048	      0	      0	  52048	   cb50	drivers/pinctrl/renesas/pfc-r8a77951.o
  51848	      0	      0	  51848	   ca88	drivers/pinctrl/renesas/pfc-r8a77965.o
  51816	      0	      0	  51816	   ca68	drivers/pinctrl/renesas/pfc-r8a7796.o
  39947	      0	      0	  39947	   9c0b	drivers/pinctrl/renesas/pfc-r8a77990.o

$ size drivers/pinctrl/renesas/*.o
   text	   data	    bss	    dec	    hex	filename
  35083	      0	      0	  35083	   890b	drivers/pinctrl/renesas/pfc-r8a7790.o
  37531	      0	      0	  37531	   929b	drivers/pinctrl/renesas/pfc-r8a7791.o

After applying this patch
---------------------------
$ size drivers/pinctrl/renesas/*.o
   text	   data	    bss	    dec	    hex	filename
  49584	      0	      0	  49584	   c1b0	drivers/pinctrl/renesas/pfc-r8a77951.o
  49384	      0	      0	  49384	   c0e8	drivers/pinctrl/renesas/pfc-r8a77965.o
  49176	      0	      0	  49176	   c018	drivers/pinctrl/renesas/pfc-r8a7796.o
  38131	      0	      0	  38131	   94f3	drivers/pinctrl/renesas/pfc-r8a77990.o


$ size drivers/pinctrl/renesas/*.o
   text	   data	    bss	    dec	    hex	filena
  34909	      0	      0	  34909	   885d	drivers/pinctrl/renesas/pfc-r8a7790.o
  36884	      0	      0	  36884	   9014	drivers/pinctrl/renesas/pfc-r8a7791.o

This patch series is based on renesas-drivers.

Biju Das (6):
  pinctrl: renesas: r8a77951: Optimize pinctrl image size for R8A774E1
  pinctrl: renesas: r8a7796: Optimize pinctrl image size for R8A774A1
  pinctrl: renesas: r8a77965: Optimize pinctrl image size for R8A774B1
  pinctrl: renesas: r8a77990: Optimize pinctrl image size for R8A774C0
  pinctrl: renesas: r8a7790: Optimize pinctrl image size for R8A7742
  pinctrl: renesas: r8a7791: Optimize pinctrl image size for R8A774[3|4]

 drivers/pinctrl/renesas/pfc-r8a7790.c  | 12 ++++++++++++
 drivers/pinctrl/renesas/pfc-r8a7791.c  | 17 ++++++++++++++++-
 drivers/pinctrl/renesas/pfc-r8a77951.c | 14 ++++++++++++--
 drivers/pinctrl/renesas/pfc-r8a7796.c  | 12 ++++++++++++
 drivers/pinctrl/renesas/pfc-r8a77965.c | 12 ++++++++++++
 drivers/pinctrl/renesas/pfc-r8a77990.c | 12 ++++++++++++
 6 files changed, 76 insertions(+), 3 deletions(-)

-- 
2.17.1

[PATCH 1/6] pinctrl: renesas: r8a77951: Optimize pinctrl image size for R8A774E1

[Biju Das]

This driver supports both RZ/G2H and R-Car H3(R8A77951) SoC's.
Optimize pinctrl image size for RZ/G2H, when R-Car H3(R8A77951) SoC is
disabled in the defconfig.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/pinctrl/renesas/pfc-r8a77951.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c
index a94ebe0bf5d0..c4011c57453d 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77951.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77951.c
@@ -1827,6 +1827,7 @@ static const unsigned int canfd1_data_mux[] = {
 	CANFD1_TX_MARK,         CANFD1_RX_MARK,
 };
 
+#ifdef CONFIG_PINCTRL_PFC_R8A77951
 /* - DRIF0 --------------------------------------------------------------- */
 static const unsigned int drif0_ctrl_a_pins[] = {
 	/* CLK, SYNC */
@@ -2041,6 +2042,7 @@ static const unsigned int drif3_data1_b_pins[] = {
 static const unsigned int drif3_data1_b_mux[] = {
 	RIF3_D1_B_MARK,
 };
+#endif
 
 /* - DU --------------------------------------------------------------------- */
 static const unsigned int du_rgb666_pins[] = {
@@ -4159,7 +4161,9 @@ static const unsigned int vin5_clk_mux[] = {
 
 static const struct {
 	struct sh_pfc_pin_group common[320];
+#ifdef CONFIG_PINCTRL_PFC_R8A77951
 	struct sh_pfc_pin_group automotive[30];
+#endif
 } pinmux_groups = {
 	.common = {
 		SH_PFC_PIN_GROUP(audio_clk_a_a),
@@ -4483,6 +4487,7 @@ static const struct {
 		SH_PFC_PIN_GROUP(vin5_clkenb),
 		SH_PFC_PIN_GROUP(vin5_clk),
 	},
+#ifdef CONFIG_PINCTRL_PFC_R8A77951
 	.automotive = {
 		SH_PFC_PIN_GROUP(drif0_ctrl_a),
 		SH_PFC_PIN_GROUP(drif0_data0_a),
@@ -4515,7 +4520,7 @@ static const struct {
 		SH_PFC_PIN_GROUP(drif3_data0_b),
 		SH_PFC_PIN_GROUP(drif3_data1_b),
 	}
-
+#endif
 };
 
 static const char * const audio_clk_groups[] = {
@@ -4574,6 +4579,7 @@ static const char * const canfd1_groups[] = {
 	"canfd1_data",
 };
 
+#ifdef CONFIG_PINCTRL_PFC_R8A77951
 static const char * const drif0_groups[] = {
 	"drif0_ctrl_a",
 	"drif0_data0_a",
@@ -4615,6 +4621,7 @@ static const char * const drif3_groups[] = {
 	"drif3_data0_b",
 	"drif3_data1_b",
 };
+#endif
 
 static const char * const du_groups[] = {
 	"du_rgb666",
@@ -5041,7 +5048,9 @@ static const char * const vin5_groups[] = {
 
 static const struct {
 	struct sh_pfc_function common[53];
+#ifdef CONFIG_PINCTRL_PFC_R8A77951
 	struct sh_pfc_function automotive[4];
+#endif
 } pinmux_functions = {
 	.common = {
 		SH_PFC_FUNCTION(audio_clk),
@@ -5098,13 +5107,14 @@ static const struct {
 		SH_PFC_FUNCTION(vin4),
 		SH_PFC_FUNCTION(vin5),
 	},
+#ifdef CONFIG_PINCTRL_PFC_R8A77951
 	.automotive = {
 		SH_PFC_FUNCTION(drif0),
 		SH_PFC_FUNCTION(drif1),
 		SH_PFC_FUNCTION(drif2),
 		SH_PFC_FUNCTION(drif3),
 	}
-
+#endif
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-- 
2.17.1

[PATCH 2/6] pinctrl: renesas: r8a7796: Optimize pinctrl image size for R8A774A1

[Biju Das]

This driver supports both RZ/G2M and R-Car M3-W/W+(R8A7796[0|1]) SoC's.
Optimize pinctrl image size for RZ/G2M, when R-Car M3-W/W+(R8A7796[0|1])
SoC's are disabled in the defconfig.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/pinctrl/renesas/pfc-r8a7796.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c
index 55f0344a3d3e..65bb8b3c62d4 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7796.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7796.c
@@ -1831,6 +1831,7 @@ static const unsigned int canfd1_data_mux[] = {
 	CANFD1_TX_MARK,         CANFD1_RX_MARK,
 };
 
+#ifdef CONFIG_PINCTRL_PFC_R8A77961
 /* - DRIF0 --------------------------------------------------------------- */
 static const unsigned int drif0_ctrl_a_pins[] = {
 	/* CLK, SYNC */
@@ -2045,6 +2046,7 @@ static const unsigned int drif3_data1_b_pins[] = {
 static const unsigned int drif3_data1_b_mux[] = {
 	RIF3_D1_B_MARK,
 };
+#endif
 
 /* - DU --------------------------------------------------------------------- */
 static const unsigned int du_rgb666_pins[] = {
@@ -4133,7 +4135,9 @@ static const unsigned int vin5_clk_mux[] = {
 
 static const struct {
 	struct sh_pfc_pin_group common[316];
+#ifdef CONFIG_PINCTRL_PFC_R8A77961
 	struct sh_pfc_pin_group automotive[30];
+#endif
 } pinmux_groups = {
 	.common = {
 		SH_PFC_PIN_GROUP(audio_clk_a_a),
@@ -4453,6 +4457,7 @@ static const struct {
 		SH_PFC_PIN_GROUP(vin5_clkenb),
 		SH_PFC_PIN_GROUP(vin5_clk),
 	},
+#ifdef CONFIG_PINCTRL_PFC_R8A77961
 	.automotive = {
 		SH_PFC_PIN_GROUP(drif0_ctrl_a),
 		SH_PFC_PIN_GROUP(drif0_data0_a),
@@ -4485,6 +4490,7 @@ static const struct {
 		SH_PFC_PIN_GROUP(drif3_data0_b),
 		SH_PFC_PIN_GROUP(drif3_data1_b),
 	}
+#endif
 };
 
 static const char * const audio_clk_groups[] = {
@@ -4543,6 +4549,7 @@ static const char * const canfd1_groups[] = {
 	"canfd1_data",
 };
 
+#ifdef CONFIG_PINCTRL_PFC_R8A77961
 static const char * const drif0_groups[] = {
 	"drif0_ctrl_a",
 	"drif0_data0_a",
@@ -4584,6 +4591,7 @@ static const char * const drif3_groups[] = {
 	"drif3_data0_b",
 	"drif3_data1_b",
 };
+#endif
 
 static const char * const du_groups[] = {
 	"du_rgb666",
@@ -4997,7 +5005,9 @@ static const char * const vin5_groups[] = {
 
 static const struct {
 	struct sh_pfc_function common[50];
+#ifdef CONFIG_PINCTRL_PFC_R8A77961
 	struct sh_pfc_function automotive[4];
+#endif
 } pinmux_functions = {
 	.common = {
 		SH_PFC_FUNCTION(audio_clk),
@@ -5051,12 +5061,14 @@ static const struct {
 		SH_PFC_FUNCTION(vin4),
 		SH_PFC_FUNCTION(vin5),
 	},
+#ifdef CONFIG_PINCTRL_PFC_R8A77961
 	.automotive = {
 		SH_PFC_FUNCTION(drif0),
 		SH_PFC_FUNCTION(drif1),
 		SH_PFC_FUNCTION(drif2),
 		SH_PFC_FUNCTION(drif3),
 	}
+#endif
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-- 
2.17.1

[PATCH 3/6] pinctrl: renesas: r8a77965: Optimize pinctrl image size for R8A774B1

[Biju Das]

This driver supports both RZ/G2N and R-Car M3-N(R8A77965) SoC's.
Optimize pinctrl image size for RZ/G2N, when R-Car M3-N(R8A77965) SoC is
disabled in the defconfig.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/pinctrl/renesas/pfc-r8a77965.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c
index 7a50b9b69a7d..85fce3dae7a5 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77965.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77965.c
@@ -1847,6 +1847,7 @@ static const unsigned int canfd1_data_mux[] = {
 	CANFD1_TX_MARK,         CANFD1_RX_MARK,
 };
 
+#ifdef CONFIG_PINCTRL_PFC_R8A77965
 /* - DRIF0 --------------------------------------------------------------- */
 static const unsigned int drif0_ctrl_a_pins[] = {
 	/* CLK, SYNC */
@@ -2120,6 +2121,7 @@ static const unsigned int drif3_data1_b_pins[] = {
 static const unsigned int drif3_data1_b_mux[] = {
 	RIF3_D1_B_MARK,
 };
+#endif
 
 /* - DU --------------------------------------------------------------------- */
 static const unsigned int du_rgb666_pins[] = {
@@ -4380,7 +4382,9 @@ static const unsigned int vin5_clk_mux[] = {
 
 static const struct {
 	struct sh_pfc_pin_group common[318];
+#ifdef CONFIG_PINCTRL_PFC_R8A77965
 	struct sh_pfc_pin_group automotive[30];
+#endif
 } pinmux_groups = {
 	.common = {
 		SH_PFC_PIN_GROUP(audio_clk_a_a),
@@ -4702,6 +4706,7 @@ static const struct {
 		SH_PFC_PIN_GROUP(vin5_clkenb),
 		SH_PFC_PIN_GROUP(vin5_clk),
 	},
+#ifdef CONFIG_PINCTRL_PFC_R8A77965
 	.automotive = {
 		SH_PFC_PIN_GROUP(drif0_ctrl_a),
 		SH_PFC_PIN_GROUP(drif0_data0_a),
@@ -4734,6 +4739,7 @@ static const struct {
 		SH_PFC_PIN_GROUP(drif3_data0_b),
 		SH_PFC_PIN_GROUP(drif3_data1_b),
 	}
+#endif
 };
 
 static const char * const audio_clk_groups[] = {
@@ -4792,6 +4798,7 @@ static const char * const canfd1_groups[] = {
 	"canfd1_data",
 };
 
+#ifdef CONFIG_PINCTRL_PFC_R8A77965
 static const char * const drif0_groups[] = {
 	"drif0_ctrl_a",
 	"drif0_data0_a",
@@ -4833,6 +4840,7 @@ static const char * const drif3_groups[] = {
 	"drif3_data0_b",
 	"drif3_data1_b",
 };
+#endif
 
 static const char * const du_groups[] = {
 	"du_rgb666",
@@ -5250,7 +5258,9 @@ static const char * const vin5_groups[] = {
 
 static const struct {
 	struct sh_pfc_function common[51];
+#ifdef CONFIG_PINCTRL_PFC_R8A77965
 	struct sh_pfc_function automotive[4];
+#endif
 } pinmux_functions = {
 	.common = {
 		SH_PFC_FUNCTION(audio_clk),
@@ -5305,12 +5315,14 @@ static const struct {
 		SH_PFC_FUNCTION(vin4),
 		SH_PFC_FUNCTION(vin5),
 	},
+#ifdef CONFIG_PINCTRL_PFC_R8A77965
 	.automotive = {
 		SH_PFC_FUNCTION(drif0),
 		SH_PFC_FUNCTION(drif1),
 		SH_PFC_FUNCTION(drif2),
 		SH_PFC_FUNCTION(drif3),
 	}
+#endif
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-- 
2.17.1

[PATCH 4/6] pinctrl: renesas: r8a77990: Optimize pinctrl image size for R8A774C0

[Biju Das]

This driver supports both RZ/G2E and R-Car E3(R8A774C0) SoC's.
Optimize pinctrl image size for RZ/G2E, when R-Car E3(R8A774C0) SoC is
disabled in the defconfig.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/pinctrl/renesas/pfc-r8a77990.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c
index aed04a4c6116..47d57cf88011 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77990.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
@@ -1593,6 +1593,7 @@ static const unsigned int canfd1_data_mux[] = {
 	CANFD1_TX_MARK, CANFD1_RX_MARK,
 };
 
+#ifdef CONFIG_PINCTRL_PFC_R8A77990
 /* - DRIF0 --------------------------------------------------------------- */
 static const unsigned int drif0_ctrl_a_pins[] = {
 	/* CLK, SYNC */
@@ -1785,6 +1786,7 @@ static const unsigned int drif3_data1_b_pins[] = {
 static const unsigned int drif3_data1_b_mux[] = {
 	RIF3_D1_B_MARK,
 };
+#endif
 
 /* - DU --------------------------------------------------------------------- */
 static const unsigned int du_rgb666_pins[] = {
@@ -3761,7 +3763,9 @@ static const unsigned int vin5_clk_b_mux[] = {
 
 static const struct {
 	struct sh_pfc_pin_group common[247];
+#ifdef CONFIG_PINCTRL_PFC_R8A77990
 	struct sh_pfc_pin_group automotive[21];
+#endif
 } pinmux_groups = {
 	.common = {
 		SH_PFC_PIN_GROUP(audio_clk_a),
@@ -4012,6 +4016,7 @@ static const struct {
 		SH_PFC_PIN_GROUP(vin5_clk_a),
 		SH_PFC_PIN_GROUP(vin5_clk_b),
 	},
+#ifdef CONFIG_PINCTRL_PFC_R8A77990
 	.automotive = {
 		SH_PFC_PIN_GROUP(drif0_ctrl_a),
 		SH_PFC_PIN_GROUP(drif0_data0_a),
@@ -4035,6 +4040,7 @@ static const struct {
 		SH_PFC_PIN_GROUP(drif3_data0_b),
 		SH_PFC_PIN_GROUP(drif3_data1_b),
 	}
+#endif
 };
 
 static const char * const audio_clk_groups[] = {
@@ -4088,6 +4094,7 @@ static const char * const canfd1_groups[] = {
 	"canfd1_data",
 };
 
+#ifdef CONFIG_PINCTRL_PFC_R8A77990
 static const char * const drif0_groups[] = {
 	"drif0_ctrl_a",
 	"drif0_data0_a",
@@ -4120,6 +4127,7 @@ static const char * const drif3_groups[] = {
 	"drif3_data0_b",
 	"drif3_data1_b",
 };
+#endif
 
 static const char * const du_groups[] = {
 	"du_rgb666",
@@ -4460,7 +4468,9 @@ static const char * const vin5_groups[] = {
 
 static const struct {
 	struct sh_pfc_function common[47];
+#ifdef CONFIG_PINCTRL_PFC_R8A77990
 	struct sh_pfc_function automotive[4];
+#endif
 } pinmux_functions = {
 	.common = {
 		SH_PFC_FUNCTION(audio_clk),
@@ -4511,12 +4521,14 @@ static const struct {
 		SH_PFC_FUNCTION(vin4),
 		SH_PFC_FUNCTION(vin5),
 	},
+#ifdef CONFIG_PINCTRL_PFC_R8A77990
 	.automotive = {
 		SH_PFC_FUNCTION(drif0),
 		SH_PFC_FUNCTION(drif1),
 		SH_PFC_FUNCTION(drif2),
 		SH_PFC_FUNCTION(drif3),
 	}
+#endif
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-- 
2.17.1

[PATCH 5/6] pinctrl: renesas: r8a7790: Optimize pinctrl image size for R8A7742

[Biju Das]

This driver supports both RZ/G1H and R-Car H2(R8A7790) SoC's.
Optimize pinctrl image size for RZ/G1H, when R-Car H2(R8A7790) SoC is
disabled in the shmobile_defconfig.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/pinctrl/renesas/pfc-r8a7790.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c
index 3f48d3d879f7..8943ca695ff0 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7790.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7790.c
@@ -2393,6 +2393,7 @@ static const unsigned int intc_irq3_pins[] = {
 static const unsigned int intc_irq3_mux[] = {
 	IRQ3_MARK,
 };
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
 /* - MLB+ ------------------------------------------------------------------- */
 static const unsigned int mlb_3pin_pins[] = {
 	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
@@ -2400,6 +2401,7 @@ static const unsigned int mlb_3pin_pins[] = {
 static const unsigned int mlb_3pin_mux[] = {
 	MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
 };
+#endif
 /* - MMCIF0 ----------------------------------------------------------------- */
 static const unsigned int mmc0_data1_pins[] = {
 	/* D[0] */
@@ -4131,7 +4133,9 @@ static const unsigned int vin3_clk_mux[] = {
 
 static const struct {
 	struct sh_pfc_pin_group common[311];
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
 	struct sh_pfc_pin_group automotive[1];
+#endif
 } pinmux_groups = {
 	.common = {
 		SH_PFC_PIN_GROUP(audio_clk_a),
@@ -4446,9 +4450,11 @@ static const struct {
 		SH_PFC_PIN_GROUP(vin3_clkenb),
 		SH_PFC_PIN_GROUP(vin3_clk),
 	},
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
 	.automotive = {
 		SH_PFC_PIN_GROUP(mlb_3pin),
 	}
+#endif
 };
 
 static const char * const audio_clk_groups[] = {
@@ -4592,9 +4598,11 @@ static const char * const intc_groups[] = {
 	"intc_irq3",
 };
 
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
 static const char * const mlb_groups[] = {
 	"mlb_3pin",
 };
+#endif
 
 static const char * const mmc0_groups[] = {
 	"mmc0_data1",
@@ -4942,7 +4950,9 @@ static const char * const vin3_groups[] = {
 
 static const struct {
 	struct sh_pfc_function common[58];
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
 	struct sh_pfc_function automotive[1];
+#endif
 } pinmux_functions = {
 	.common = {
 		SH_PFC_FUNCTION(audio_clk),
@@ -5004,9 +5014,11 @@ static const struct {
 		SH_PFC_FUNCTION(vin2),
 		SH_PFC_FUNCTION(vin3),
 	},
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
 	.automotive = {
 		SH_PFC_FUNCTION(mlb),
 	}
+#endif
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-- 
2.17.1

[PATCH 6/6] pinctrl: renesas: r8a7791: Optimize pinctrl image size for R8A774[3|4]

[Biju Das]

This driver supports both RZ/G1[M|N] and R-Car M2-W/M2-N(R8A779[1|3])
SoC's. Optimize pinctrl image size for RZ/G1[M|N], when R-Car M2-W/M2-N
(R8A779[1|3]) SoC's are disabled in the shmobile_defconfig.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/pinctrl/renesas/pfc-r8a7791.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c
index bc9caf812fc1..f16004e9f263 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7791.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7791.c
@@ -1700,6 +1700,7 @@ static const struct sh_pfc_pin pinmux_pins[] = {
 	PINMUX_GPIO_GP_ALL(),
 };
 
+#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
 /* - ADI -------------------------------------------------------------------- */
 static const unsigned int adi_common_pins[] = {
 	/* ADIDATA, ADICS/SAMP, ADICLK */
@@ -1765,7 +1766,7 @@ static const unsigned int adi_chsel2_b_mux[] = {
 	/* ADICHS B 2 */
 	ADICHS2_B_MARK,
 };
-
+#endif
 /* - Audio Clock ------------------------------------------------------------ */
 static const unsigned int audio_clk_a_pins[] = {
 	/* CLK */
@@ -2553,6 +2554,7 @@ static const unsigned int intc_irq3_pins[] = {
 static const unsigned int intc_irq3_mux[] = {
 	IRQ3_MARK,
 };
+#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
 /* - MLB+ ------------------------------------------------------------------- */
 static const unsigned int mlb_3pin_pins[] = {
 	RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
@@ -2560,6 +2562,7 @@ static const unsigned int mlb_3pin_pins[] = {
 static const unsigned int mlb_3pin_mux[] = {
 	MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
 };
+#endif
 /* - MMCIF ------------------------------------------------------------------ */
 static const unsigned int mmc_data1_pins[] = {
 	/* D[0] */
@@ -4452,7 +4455,9 @@ static const unsigned int vin2_clk_mux[] = {
 
 static const struct {
 	struct sh_pfc_pin_group common[346];
+#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
 	struct sh_pfc_pin_group automotive[9];
+#endif
 } pinmux_groups = {
 	.common = {
 		SH_PFC_PIN_GROUP(audio_clk_a),
@@ -4802,6 +4807,7 @@ static const struct {
 		SH_PFC_PIN_GROUP(vin2_clkenb),
 		SH_PFC_PIN_GROUP(vin2_clk),
 	},
+#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
 	.automotive = {
 		SH_PFC_PIN_GROUP(adi_common),
 		SH_PFC_PIN_GROUP(adi_chsel0),
@@ -4813,8 +4819,10 @@ static const struct {
 		SH_PFC_PIN_GROUP(adi_chsel2_b),
 		SH_PFC_PIN_GROUP(mlb_3pin),
 	}
+#endif
 };
 
+#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
 static const char * const adi_groups[] = {
 	"adi_common",
 	"adi_chsel0",
@@ -4825,6 +4833,7 @@ static const char * const adi_groups[] = {
 	"adi_chsel1_b",
 	"adi_chsel2_b",
 };
+#endif
 
 static const char * const audio_clk_groups[] = {
 	"audio_clk_a",
@@ -5002,9 +5011,11 @@ static const char * const intc_groups[] = {
 	"intc_irq3",
 };
 
+#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
 static const char * const mlb_groups[] = {
 	"mlb_3pin",
 };
+#endif
 
 static const char * const mmc_groups[] = {
 	"mmc_data1",
@@ -5359,7 +5370,9 @@ static const char * const vin2_groups[] = {
 
 static const struct {
 	struct sh_pfc_function common[58];
+#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
 	struct sh_pfc_function automotive[2];
+#endif
 } pinmux_functions = {
 	.common = {
 		SH_PFC_FUNCTION(audio_clk),
@@ -5421,10 +5434,12 @@ static const struct {
 		SH_PFC_FUNCTION(vin1),
 		SH_PFC_FUNCTION(vin2),
 	},
+#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
 	.automotive = {
 		SH_PFC_FUNCTION(adi),
 		SH_PFC_FUNCTION(mlb),
 	}
+#endif
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-- 
2.17.1

RE: [PATCH 2/6] pinctrl: renesas: r8a7796: Optimize pinctrl image size for R8A774A1

[Biju Das]

Hi All,

Please drop this patch, Will send V2 for this. I have missed adding CONFIG_PINCTRL_PFC_R8A77960  for automotive parts.
Sorry for the inconvenience.

Regards,
Biju

> -----Original Message-----
> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: 19 October 2020 13:43
> To: Linus Walleij <linus.walleij@linaro.org>
> Cc: Biju Das <biju.das.jz@bp.renesas.com>; Geert Uytterhoeven
> <geert+renesas@glider.be>; linux-renesas-soc@vger.kernel.org; linux-
> gpio@vger.kernel.org; Chris Paterson <Chris.Paterson2@renesas.com>; Biju
> Das <biju.das@bp.renesas.com>; Prabhakar Mahadev Lad
> <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Subject: [PATCH 2/6] pinctrl: renesas: r8a7796: Optimize pinctrl image size for
> R8A774A1
> 
> This driver supports both RZ/G2M and R-Car M3-W/W+(R8A7796[0|1]) SoC's.
> Optimize pinctrl image size for RZ/G2M, when R-Car M3-
> W/W+(R8A7796[0|1]) SoC's are disabled in the defconfig.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  drivers/pinctrl/renesas/pfc-r8a7796.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c
> b/drivers/pinctrl/renesas/pfc-r8a7796.c
> index 55f0344a3d3e..65bb8b3c62d4 100644
> --- a/drivers/pinctrl/renesas/pfc-r8a7796.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c
> @@ -1831,6 +1831,7 @@ static const unsigned int canfd1_data_mux[] = {
>  	CANFD1_TX_MARK,         CANFD1_RX_MARK,
>  };
> 
> +#ifdef CONFIG_PINCTRL_PFC_R8A77961
>  /* - DRIF0 --------------------------------------------------------------- */  static
> const unsigned int drif0_ctrl_a_pins[] = {
>  	/* CLK, SYNC */
> @@ -2045,6 +2046,7 @@ static const unsigned int drif3_data1_b_pins[] = {
> static const unsigned int drif3_data1_b_mux[] = {
>  	RIF3_D1_B_MARK,
>  };
> +#endif
> 
>  /* - DU --------------------------------------------------------------------- */  static
> const unsigned int du_rgb666_pins[] = { @@ -4133,7 +4135,9 @@ static const
> unsigned int vin5_clk_mux[] = {
> 
>  static const struct {
>  	struct sh_pfc_pin_group common[316];
> +#ifdef CONFIG_PINCTRL_PFC_R8A77961
>  	struct sh_pfc_pin_group automotive[30];
> +#endif
>  } pinmux_groups = {
>  	.common = {
>  		SH_PFC_PIN_GROUP(audio_clk_a_a),
> @@ -4453,6 +4457,7 @@ static const struct {
>  		SH_PFC_PIN_GROUP(vin5_clkenb),
>  		SH_PFC_PIN_GROUP(vin5_clk),
>  	},
> +#ifdef CONFIG_PINCTRL_PFC_R8A77961
>  	.automotive = {
>  		SH_PFC_PIN_GROUP(drif0_ctrl_a),
>  		SH_PFC_PIN_GROUP(drif0_data0_a),
> @@ -4485,6 +4490,7 @@ static const struct {
>  		SH_PFC_PIN_GROUP(drif3_data0_b),
>  		SH_PFC_PIN_GROUP(drif3_data1_b),
>  	}
> +#endif
>  };
> 
>  static const char * const audio_clk_groups[] = { @@ -4543,6 +4549,7 @@
> static const char * const canfd1_groups[] = {
>  	"canfd1_data",
>  };
> 
> +#ifdef CONFIG_PINCTRL_PFC_R8A77961
>  static const char * const drif0_groups[] = {
>  	"drif0_ctrl_a",
>  	"drif0_data0_a",
> @@ -4584,6 +4591,7 @@ static const char * const drif3_groups[] = {
>  	"drif3_data0_b",
>  	"drif3_data1_b",
>  };
> +#endif
> 
>  static const char * const du_groups[] = {
>  	"du_rgb666",
> @@ -4997,7 +5005,9 @@ static const char * const vin5_groups[] = {
> 
>  static const struct {
>  	struct sh_pfc_function common[50];
> +#ifdef CONFIG_PINCTRL_PFC_R8A77961
>  	struct sh_pfc_function automotive[4];
> +#endif
>  } pinmux_functions = {
>  	.common = {
>  		SH_PFC_FUNCTION(audio_clk),
> @@ -5051,12 +5061,14 @@ static const struct {
>  		SH_PFC_FUNCTION(vin4),
>  		SH_PFC_FUNCTION(vin5),
>  	},
> +#ifdef CONFIG_PINCTRL_PFC_R8A77961
>  	.automotive = {
>  		SH_PFC_FUNCTION(drif0),
>  		SH_PFC_FUNCTION(drif1),
>  		SH_PFC_FUNCTION(drif2),
>  		SH_PFC_FUNCTION(drif3),
>  	}
> +#endif
>  };
> 
>  static const struct pinmux_cfg_reg pinmux_config_regs[] = {
> --
> 2.17.1

Re: [PATCH 1/6] pinctrl: renesas: r8a77951: Optimize pinctrl image size for R8A774E1

[Geert Uytterhoeven]

Hi Biju,

On Mon, Oct 19, 2020 at 2:43 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> This driver supports both RZ/G2H and R-Car H3(R8A77951) SoC's.
> Optimize pinctrl image size for RZ/G2H, when R-Car H3(R8A77951) SoC is
> disabled in the defconfig.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

> --- a/drivers/pinctrl/renesas/pfc-r8a77951.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a77951.c
> @@ -1827,6 +1827,7 @@ static const unsigned int canfd1_data_mux[] = {
>         CANFD1_TX_MARK,         CANFD1_RX_MARK,
>  };
>
> +#ifdef CONFIG_PINCTRL_PFC_R8A77951
>  /* - DRIF0 --------------------------------------------------------------- */
>  static const unsigned int drif0_ctrl_a_pins[] = {
>         /* CLK, SYNC */
> @@ -2041,6 +2042,7 @@ static const unsigned int drif3_data1_b_pins[] = {
>  static const unsigned int drif3_data1_b_mux[] = {
>         RIF3_D1_B_MARK,
>  };
> +#endif

For long #ifdef blocks, where you cannot see both the #ifdef and #endif
in your editor window, it is recommended to add comments to the #endif.
No worries, I'll fix that myself while applying.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-pinctrl-for-v5.11, with comments added to
the #endifs where appropriate.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/6] pinctrl: renesas: r8a77965: Optimize pinctrl image size for R8A774B1

[Geert Uytterhoeven]

On Mon, Oct 19, 2020 at 2:43 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> This driver supports both RZ/G2N and R-Car M3-N(R8A77965) SoC's.
> Optimize pinctrl image size for RZ/G2N, when R-Car M3-N(R8A77965) SoC is
> disabled in the defconfig.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-pinctrl-for-v5.11, with comments added to
the #endifs where appropriate.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 4/6] pinctrl: renesas: r8a77990: Optimize pinctrl image size for R8A774C0

[Geert Uytterhoeven]

On Mon, Oct 19, 2020 at 2:43 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> This driver supports both RZ/G2E and R-Car E3(R8A774C0) SoC's.
> Optimize pinctrl image size for RZ/G2E, when R-Car E3(R8A774C0) SoC is
> disabled in the defconfig.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-pinctrl-for-v5.11, with comments added to
the #endifs where appropriate.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 4/6] pinctrl: renesas: r8a77990: Optimize pinctrl image size for R8A774C0

[Geert Uytterhoeven]

On Thu, Oct 22, 2020 at 2:04 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Mon, Oct 19, 2020 at 2:43 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > This driver supports both RZ/G2E and R-Car E3(R8A774C0) SoC's.
> > Optimize pinctrl image size for RZ/G2E, when R-Car E3(R8A774C0) SoC is

Ooops, R8A77990, twice. Will fix while applying.

> > disabled in the defconfig.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 5/6] pinctrl: renesas: r8a7790: Optimize pinctrl image size for R8A7742

[Geert Uytterhoeven]

On Mon, Oct 19, 2020 at 2:43 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> This driver supports both RZ/G1H and R-Car H2(R8A7790) SoC's.
> Optimize pinctrl image size for RZ/G1H, when R-Car H2(R8A7790) SoC is
> disabled in the shmobile_defconfig.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-pinctrl-for-v5.11, with comments added to
the #endifs where appropriate.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 6/6] pinctrl: renesas: r8a7791: Optimize pinctrl image size for R8A774[3|4]

[Geert Uytterhoeven]

On Mon, Oct 19, 2020 at 2:43 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> This driver supports both RZ/G1[M|N] and R-Car M2-W/M2-N(R8A779[1|3])
> SoC's. Optimize pinctrl image size for RZ/G1[M|N], when R-Car M2-W/M2-N
> (R8A779[1|3]) SoC's are disabled in the shmobile_defconfig.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-pinctrl-for-v5.11, with comments added to
the #endifs where appropriate.

> --- a/drivers/pinctrl/renesas/pfc-r8a7791.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a7791.c
> @@ -1700,6 +1700,7 @@ static const struct sh_pfc_pin pinmux_pins[] = {
>         PINMUX_GPIO_GP_ALL(),
>  };
>
> +#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
>  /* - ADI -------------------------------------------------------------------- */
>  static const unsigned int adi_common_pins[] = {
>         /* ADIDATA, ADICS/SAMP, ADICLK */
> @@ -1765,7 +1766,7 @@ static const unsigned int adi_chsel2_b_mux[] = {
>         /* ADICHS B 2 */
>         ADICHS2_B_MARK,
>  };
> -
> +#endif
>  /* - Audio Clock ------------------------------------------------------------ */
>  static const unsigned int audio_clk_a_pins[] = {
>         /* CLK */
> @@ -2553,6 +2554,7 @@ static const unsigned int intc_irq3_pins[] = {
>  static const unsigned int intc_irq3_mux[] = {
>         IRQ3_MARK,
>  };
> +#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)

BTW, if we get more of these automotive-only pin groups, we may consider
moving them together, to reduce the number of #ifdefs.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 1/6] pinctrl: renesas: r8a77951: Optimize pinctrl image size for R8A774E1

[Biju Das]

Hi Geert,

> Subject: Re: [PATCH 1/6] pinctrl: renesas: r8a77951: Optimize pinctrl image
> size for R8A774E1
> 
> Hi Biju,
> 
> On Mon, Oct 19, 2020 at 2:43 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > This driver supports both RZ/G2H and R-Car H3(R8A77951) SoC's.
> > Optimize pinctrl image size for RZ/G2H, when R-Car H3(R8A77951) SoC is
> > disabled in the defconfig.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Thanks for your patch!
> 
> > --- a/drivers/pinctrl/renesas/pfc-r8a77951.c
> > +++ b/drivers/pinctrl/renesas/pfc-r8a77951.c
> > @@ -1827,6 +1827,7 @@ static const unsigned int canfd1_data_mux[] = {
> >         CANFD1_TX_MARK,         CANFD1_RX_MARK,
> >  };
> >
> > +#ifdef CONFIG_PINCTRL_PFC_R8A77951
> >  /* - DRIF0
> > --------------------------------------------------------------- */  static const
> unsigned int drif0_ctrl_a_pins[] = {
> >         /* CLK, SYNC */
> > @@ -2041,6 +2042,7 @@ static const unsigned int drif3_data1_b_pins[] =
> > {  static const unsigned int drif3_data1_b_mux[] = {
> >         RIF3_D1_B_MARK,
> >  };
> > +#endif
> 
> For long #ifdef blocks, where you cannot see both the #ifdef and #endif in
> your editor window, it is recommended to add comments to the #endif.
> No worries, I'll fix that myself while applying.

Thank you.

Regards,
Biju

> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will
> queue in renesas-pinctrl-for-v5.11, with comments added to the #endifs
> where appropriate.
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

RE: [PATCH 4/6] pinctrl: renesas: r8a77990: Optimize pinctrl image size for R8A774C0

[Biju Das]

Hi Geert,

> Subject: Re: [PATCH 4/6] pinctrl: renesas: r8a77990: Optimize pinctrl image
> size for R8A774C0
> 
> On Thu, Oct 22, 2020 at 2:04 PM Geert Uytterhoeven <geert@linux-
> m68k.org> wrote:
> > On Mon, Oct 19, 2020 at 2:43 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > > This driver supports both RZ/G2E and R-Car E3(R8A774C0) SoC's.
> > > Optimize pinctrl image size for RZ/G2E, when R-Car E3(R8A774C0) SoC
> > > is
> 
> Ooops, R8A77990, twice. Will fix while applying.

Thanks,  I didn't spot this.

Regards,
Biju

> > > disabled in the defconfig.
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds