* [PATCH 0/7] Add support for iWave G20D-Q7 board based on RZ/G1N
@ 2018-11-22 9:14 Biju Das
2018-11-22 9:14 ` [PATCH 1/7] ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N Qseven SOM Biju Das
` (6 more replies)
0 siblings, 7 replies; 28+ messages in thread
From: Biju Das @ 2018-11-22 9:14 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Biju Das, Simon Horman, Magnus Damm, linux-renesas-soc,
devicetree, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
This patch series aims to add support for iWave G20D-Q7 board based on RZ/G1N.
This patch series is tested against renesas-dev
Biju Das (7):
ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N Qseven SOM
ARM: dts: r8a7744: Initial SoC device tree
ARM: dts: r8a7744-iwg20d-q7: Add support for iWave G20D-Q7 board based
on RZ/G1N
ARM: dts: r8a7744: Add SYS-DMAC support
ARM: dts: r8a7744: Add GPIO support
ARM: dts: r8a7744: Add Ethernet AVB support
ARM: dts: r8a7744: Add SMP support
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/r8a7744-iwg20d-q7.dts | 15 +
arch/arm/boot/dts/r8a7744-iwg20m.dtsi | 31 ++
arch/arm/boot/dts/r8a7744.dtsi | 561 ++++++++++++++++++++++++++++++++
4 files changed, 608 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7744-iwg20d-q7.dts
create mode 100644 arch/arm/boot/dts/r8a7744-iwg20m.dtsi
create mode 100644 arch/arm/boot/dts/r8a7744.dtsi
--
2.7.4
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 1/7] ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N Qseven SOM
2018-11-22 9:14 [PATCH 0/7] Add support for iWave G20D-Q7 board based on RZ/G1N Biju Das
@ 2018-11-22 9:14 ` Biju Das
2018-11-29 12:50 ` Simon Horman
2018-11-30 9:44 ` Geert Uytterhoeven
2018-11-22 9:14 ` [PATCH 2/7] ARM: dts: r8a7744: Initial SoC device tree Biju Das
` (5 subsequent siblings)
6 siblings, 2 replies; 28+ messages in thread
From: Biju Das @ 2018-11-22 9:14 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Biju Das, Simon Horman, Magnus Damm, linux-renesas-soc,
devicetree, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
Add support for iWave RZ/G1N Qseven System On Module.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
arch/arm/boot/dts/r8a7744-iwg20m.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7744-iwg20m.dtsi
diff --git a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
new file mode 100644
index 0000000..6166ae0
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the iWave RZ/G1N Qseven SOM
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+#include "r8a7744.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "iwave,g20m", "renesas,r8a7744";
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+
+ reg_3p3v: 3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 2/7] ARM: dts: r8a7744: Initial SoC device tree
2018-11-22 9:14 [PATCH 0/7] Add support for iWave G20D-Q7 board based on RZ/G1N Biju Das
2018-11-22 9:14 ` [PATCH 1/7] ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N Qseven SOM Biju Das
@ 2018-11-22 9:14 ` Biju Das
2018-11-29 12:50 ` Simon Horman
` (2 more replies)
2018-11-22 9:14 ` [PATCH 3/7] ARM: dts: r8a7744-iwg20d-q7: Add support for iWave G20D-Q7 board based on RZ/G1N Biju Das
` (4 subsequent siblings)
6 siblings, 3 replies; 28+ messages in thread
From: Biju Das @ 2018-11-22 9:14 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Biju Das, Simon Horman, Magnus Damm, linux-renesas-soc,
devicetree, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
Basic support for the RZ/G1N (R8A7744) SoC. Added placeholders
to avoid compilation error with the common platform code.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
arch/arm/boot/dts/r8a7744.dtsi | 369 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 369 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7744.dtsi
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
new file mode 100644
index 0000000..cf02bf7
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -0,0 +1,369 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the r8a7744 SoC
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r8a7744-cpg-mssr.h>
+#include <dt-bindings/power/r8a7744-sysc.h>
+
+/ {
+ compatible = "renesas,r8a7744";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /*
+ * The external audio clocks are configured as 0 Hz fixed frequency
+ * clocks by default.
+ * Boards that provide audio clocks should override them.
+ */
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_c: audio_clk_c {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External CAN clock */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <1500000000>;
+ clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
+ clock-latency = <300000>; /* 300 us */
+ power-domains = <&sysc R8A7744_PD_CA15_CPU0>;
+ next-level-cache = <&L2_CA15>;
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <1500000 1000000>,
+ <1312500 1000000>,
+ <1125000 1000000>,
+ < 937500 1000000>,
+ < 750000 1000000>,
+ < 375000 1000000>;
+ };
+
+ L2_CA15: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ power-domains = <&sysc R8A7744_PD_CA15_SCU>;
+ };
+ };
+
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a15-pmu";
+ interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>;
+ };
+
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@e6050000 {
+ reg = <0 0xe6050000 0 0x50>;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ /* placeholder */
+ };
+
+ gpio1: gpio@e6051000 {
+ reg = <0 0xe6051000 0 0x50>;
+ #gpio-cells = <2>;
+ /* placeholder */
+ };
+
+ gpio2: gpio@e6052000 {
+ reg = <0 0xe6052000 0 0x50>;
+ #gpio-cells = <2>;
+ /* placeholder */
+ };
+
+ gpio6: gpio@e6055400 {
+ reg = <0 0xe6055400 0 0x50>;
+ #gpio-cells = <2>;
+ /* placeholder */
+ };
+
+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a7744";
+ reg = <0 0xe6060000 0 0x164>;
+ };
+
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a7744-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&usb_extal_clk>;
+ clock-names = "extal", "usb_extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
+
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a7744-rst";
+ reg = <0 0xe6160000 0 0x100>;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a7744-sysc";
+ reg = <0 0xe6180000 0 0x200>;
+ #power-domain-cells = <1>;
+ };
+
+ icram0: sram@e63a0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63a0000 0 0x12000>;
+ };
+
+ icram1: sram@e63c0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63c0000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63c0000 0x1000>;
+
+ smp-sram@0 {
+ compatible = "renesas,smp-sram";
+ reg = <0 0x100>;
+ };
+ };
+
+ icram2: sram@e6300000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe6300000 0 0x40000>;
+ };
+
+ i2c2: i2c@e6530000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0xe6530000 0 0x40>;
+ /* placeholder */
+ };
+
+ i2c5: i2c@e6528000 {
+ /* doesn't need pinmux */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0xe6528000 0 0x40>;
+ /* placeholder */
+ };
+
+ hsusb: usb@e6590000 {
+ reg = <0 0xe6590000 0 0x100>;
+ /* placeholder */
+ };
+
+ usbphy: usb-phy@e6590100 {
+ reg = <0 0xe6590100 0 0x100>;
+ /* placeholder */
+ };
+
+ avb: ethernet@e6800000 {
+ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* placeholder */
+ };
+
+ scifb1: serial@e6c30000 {
+ reg = <0 0xe6c30000 0 0x100>;
+ /* placeholder */
+ };
+
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a7744",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e60000 0 0x40>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 721>,
+ <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+ resets = <&cpg 721>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ reg = <0 0xe6e68000 0 0x40>;
+ /* placeholder */
+ };
+
+ hscif1: serial@e62c8000 {
+ reg = <0 0xe62c8000 0 0x60>;
+ /* placeholder */
+ };
+
+ can0: can@e6e80000 {
+ reg = <0 0xe6e80000 0 0x1000>;
+ /* placeholder */
+ };
+
+ can1: can@e6e88000 {
+ reg = <0 0xe6e88000 0 0x1000>;
+ /* placeholder */
+ };
+
+ rcar_sound: sound@ec500000 {
+ reg = <0 0xec500000 0 0x1000>;
+
+ rcar_sound,dvc {
+ dvc0: dvc-0 {};
+ dvc1: dvc-1 {};
+ };
+
+ rcar_sound,src {
+ src2: src-2 {};
+ src3: src-3 {};
+ };
+
+ rcar_sound,ssi {
+ ssi0: ssi-0 {};
+ ssi1: ssi-1 {};
+ };
+ /* placeholder */
+ };
+
+ pci0: pci@ee090000 {
+ reg = <0 0xee090000 0 0xc00>;
+
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ /* placeholder */
+ };
+
+ pci1: pci@ee0d0000 {
+ reg = <0 0xee0d0000 0 0xc00>;
+
+ bus-range = <1 1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ /* placeholder */
+ };
+
+ sdhi1: sd@ee140000 {
+ reg = <0 0xee140000 0 0x100>;
+ /* placeholder */
+ };
+
+ sdhi2: sd@ee160000 {
+ reg = <0 0xee160000 0 0x100>;
+ /* placeholder */
+ };
+
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
+ <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&cpg CPG_MOD 408>;
+ clock-names = "clk";
+ power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+ resets = <&cpg 408>;
+ };
+
+ du: display@feb00000 {
+ reg = <0 0xfeb00000 0 0x40000>,
+ <0 0xfeb90000 0 0x1c>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_rgb: endpoint {
+ };
+ };
+ port@1 {
+ reg = <1>;
+ du_out_lvds0: endpoint {
+ };
+ };
+ };
+ /* placeholder */
+ };
+
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ /* External USB clock - can be overridden by the board */
+ usb_extal_clk: usb_extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 3/7] ARM: dts: r8a7744-iwg20d-q7: Add support for iWave G20D-Q7 board based on RZ/G1N
2018-11-22 9:14 [PATCH 0/7] Add support for iWave G20D-Q7 board based on RZ/G1N Biju Das
2018-11-22 9:14 ` [PATCH 1/7] ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N Qseven SOM Biju Das
2018-11-22 9:14 ` [PATCH 2/7] ARM: dts: r8a7744: Initial SoC device tree Biju Das
@ 2018-11-22 9:14 ` Biju Das
2018-11-29 12:50 ` Simon Horman
2018-11-30 9:46 ` Geert Uytterhoeven
2018-11-22 9:14 ` [PATCH 4/7] ARM: dts: r8a7744: Add SYS-DMAC support Biju Das
` (3 subsequent siblings)
6 siblings, 2 replies; 28+ messages in thread
From: Biju Das @ 2018-11-22 9:14 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Biju Das, Simon Horman, Magnus Damm, linux-renesas-soc,
devicetree, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
Add support for iWave RainboW-G20D-Qseven board based on RZ/G1N.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/r8a7744-iwg20d-q7.dts | 15 +++++++++++++++
2 files changed, 16 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7744-iwg20d-q7.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b0e966d..aba5a25 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -829,6 +829,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r8a7743-iwg20d-q7.dtb \
r8a7743-iwg20d-q7-dbcm-ca.dtb \
r8a7743-sk-rzg1m.dtb \
+ r8a7744-iwg20d-q7.dtb \
r8a7745-iwg22d-sodimm.dtb \
r8a7745-iwg22d-sodimm-dbhd-ca.dtb \
r8a7745-sk-rzg1e.dtb \
diff --git a/arch/arm/boot/dts/r8a7744-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7744-iwg20d-q7.dts
new file mode 100644
index 0000000..1fdac52
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7744-iwg20d-q7.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the iWave-RZ/G1N Qseven board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a7744-iwg20m.dtsi"
+#include "iwg20d-q7-common.dtsi"
+
+/ {
+ model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1N";
+ compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744";
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 4/7] ARM: dts: r8a7744: Add SYS-DMAC support
2018-11-22 9:14 [PATCH 0/7] Add support for iWave G20D-Q7 board based on RZ/G1N Biju Das
` (2 preceding siblings ...)
2018-11-22 9:14 ` [PATCH 3/7] ARM: dts: r8a7744-iwg20d-q7: Add support for iWave G20D-Q7 board based on RZ/G1N Biju Das
@ 2018-11-22 9:14 ` Biju Das
2018-11-29 12:50 ` Simon Horman
2018-11-30 8:49 ` Geert Uytterhoeven
2018-11-22 9:14 ` [PATCH 5/7] ARM: dts: r8a7744: Add GPIO support Biju Das
` (2 subsequent siblings)
6 siblings, 2 replies; 28+ messages in thread
From: Biju Das @ 2018-11-22 9:14 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Biju Das, Simon Horman, Magnus Damm, linux-renesas-soc,
devicetree, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
Describe SYS-DMAC0/1 in the R8A7744 device tree.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
arch/arm/boot/dts/r8a7744.dtsi | 66 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 66 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index cf02bf7..a9ebd09 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -215,6 +215,72 @@
/* placeholder */
};
+ dmac0: dma-controller@e6700000 {
+ compatible = "renesas,dmac-r8a7744",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x20000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+ resets = <&cpg 219>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ dmac1: dma-controller@e6720000 {
+ compatible = "renesas,dmac-r8a7744",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6720000 0 0x20000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+ resets = <&cpg 218>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
avb: ethernet@e6800000 {
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
#address-cells = <1>;
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 5/7] ARM: dts: r8a7744: Add GPIO support
2018-11-22 9:14 [PATCH 0/7] Add support for iWave G20D-Q7 board based on RZ/G1N Biju Das
` (3 preceding siblings ...)
2018-11-22 9:14 ` [PATCH 4/7] ARM: dts: r8a7744: Add SYS-DMAC support Biju Das
@ 2018-11-22 9:14 ` Biju Das
2018-11-29 12:51 ` Simon Horman
2018-11-30 8:49 ` Geert Uytterhoeven
2018-11-22 9:14 ` [PATCH 6/7] ARM: dts: r8a7744: Add Ethernet AVB support Biju Das
2018-11-22 9:14 ` [PATCH 7/7] ARM: dts: r8a7744: Add SMP support Biju Das
6 siblings, 2 replies; 28+ messages in thread
From: Biju Das @ 2018-11-22 9:14 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Biju Das, Simon Horman, Magnus Damm, linux-renesas-soc,
devicetree, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
Describe GPIO blocks in the R8A7744 device tree.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
arch/arm/boot/dts/r8a7744.dtsi | 102 +++++++++++++++++++++++++++++++++++++++--
1 file changed, 98 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index a9ebd09..114642a 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -116,29 +116,123 @@
ranges;
gpio0: gpio@e6050000 {
+ compatible = "renesas,gpio-r8a7744",
+ "renesas,rcar-gen2-gpio";
reg = <0 0xe6050000 0 0x50>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 0 32>;
#interrupt-cells = <2>;
interrupt-controller;
- /* placeholder */
+ clocks = <&cpg CPG_MOD 912>;
+ power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+ resets = <&cpg 912>;
};
gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a7744",
+ "renesas,rcar-gen2-gpio";
reg = <0 0xe6051000 0 0x50>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
- /* placeholder */
+ gpio-controller;
+ gpio-ranges = <&pfc 0 32 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 911>;
+ power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+ resets = <&cpg 911>;
};
gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a7744",
+ "renesas,rcar-gen2-gpio";
reg = <0 0xe6052000 0 0x50>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
- /* placeholder */
+ gpio-controller;
+ gpio-ranges = <&pfc 0 64 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 910>;
+ power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+ resets = <&cpg 910>;
+ };
+
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a7744",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 96 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 909>;
+ power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+ resets = <&cpg 909>;
+ };
+
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a7744",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 128 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 908>;
+ power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+ resets = <&cpg 908>;
+ };
+
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a7744",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 160 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 907>;
+ power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+ resets = <&cpg 907>;
};
gpio6: gpio@e6055400 {
+ compatible = "renesas,gpio-r8a7744",
+ "renesas,rcar-gen2-gpio";
reg = <0 0xe6055400 0 0x50>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
- /* placeholder */
+ gpio-controller;
+ gpio-ranges = <&pfc 0 192 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 905>;
+ power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+ resets = <&cpg 905>;
+ };
+
+ gpio7: gpio@e6055800 {
+ compatible = "renesas,gpio-r8a7744",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055800 0 0x50>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 224 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 904>;
+ power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+ resets = <&cpg 904>;
};
pfc: pin-controller@e6060000 {
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 6/7] ARM: dts: r8a7744: Add Ethernet AVB support
2018-11-22 9:14 [PATCH 0/7] Add support for iWave G20D-Q7 board based on RZ/G1N Biju Das
` (4 preceding siblings ...)
2018-11-22 9:14 ` [PATCH 5/7] ARM: dts: r8a7744: Add GPIO support Biju Das
@ 2018-11-22 9:14 ` Biju Das
2018-11-29 12:51 ` Simon Horman
2018-11-30 8:50 ` Geert Uytterhoeven
2018-11-22 9:14 ` [PATCH 7/7] ARM: dts: r8a7744: Add SMP support Biju Das
6 siblings, 2 replies; 28+ messages in thread
From: Biju Das @ 2018-11-22 9:14 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Biju Das, Simon Horman, Magnus Damm, linux-renesas-soc,
devicetree, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
Add Ethernet AVB support for R8A7744 SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
arch/arm/boot/dts/r8a7744.dtsi | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 114642a..046ed94 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -376,10 +376,16 @@
};
avb: ethernet@e6800000 {
+ compatible = "renesas,etheravb-r8a7744",
+ "renesas,etheravb-rcar-gen2";
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+ resets = <&cpg 812>;
#address-cells = <1>;
#size-cells = <0>;
- /* placeholder */
+ status = "disabled";
};
scifb1: serial@e6c30000 {
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 7/7] ARM: dts: r8a7744: Add SMP support
2018-11-22 9:14 [PATCH 0/7] Add support for iWave G20D-Q7 board based on RZ/G1N Biju Das
` (5 preceding siblings ...)
2018-11-22 9:14 ` [PATCH 6/7] ARM: dts: r8a7744: Add Ethernet AVB support Biju Das
@ 2018-11-22 9:14 ` Biju Das
2018-11-29 12:49 ` Simon Horman
2018-11-30 8:54 ` Geert Uytterhoeven
6 siblings, 2 replies; 28+ messages in thread
From: Biju Das @ 2018-11-22 9:14 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Biju Das, Simon Horman, Magnus Damm, linux-renesas-soc,
devicetree, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
Add DT node for the Advanced Power Management Unit (APMU), add the
second CPU core, and use "renesas,apmu" as "enable-method".
Also add cpu1 phandle node to the PMU interrupt-affinity property.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
arch/arm/boot/dts/r8a7744.dtsi | 28 +++++++++++++++++++++++++++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 046ed94..79e75e7 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -49,6 +49,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -69,6 +70,25 @@
< 375000 1000000>;
};
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ clock-frequency = <1500000000>;
+ clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
+ clock-latency = <300000>; /* 300 us */
+ power-domains = <&sysc R8A7744_PD_CA15_CPU1>;
+ next-level-cache = <&L2_CA15>;
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <1500000 1000000>,
+ <1312500 1000000>,
+ <1125000 1000000>,
+ < 937500 1000000>,
+ < 750000 1000000>,
+ < 375000 1000000>;
+ };
+
L2_CA15: cache-controller-0 {
compatible = "cache";
cache-unified;
@@ -96,7 +116,7 @@
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
};
/* External SCIF clock */
@@ -250,6 +270,12 @@
#reset-cells = <1>;
};
+ apmu@e6152000 {
+ compatible = "renesas,r8a7744-apmu", "renesas,apmu";
+ reg = <0 0xe6152000 0 0x188>;
+ cpus = <&cpu0 &cpu1>;
+ };
+
rst: reset-controller@e6160000 {
compatible = "renesas,r8a7744-rst";
reg = <0 0xe6160000 0 0x100>;
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH 7/7] ARM: dts: r8a7744: Add SMP support
2018-11-22 9:14 ` [PATCH 7/7] ARM: dts: r8a7744: Add SMP support Biju Das
@ 2018-11-29 12:49 ` Simon Horman
2018-11-29 13:31 ` Biju Das
2018-11-30 8:54 ` Geert Uytterhoeven
1 sibling, 1 reply; 28+ messages in thread
From: Simon Horman @ 2018-11-29 12:49 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Magnus Damm, linux-renesas-soc,
devicetree, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
On Thu, Nov 22, 2018 at 09:14:35AM +0000, Biju Das wrote:
> Add DT node for the Advanced Power Management Unit (APMU), add the
> second CPU core, and use "renesas,apmu" as "enable-method".
>
> Also add cpu1 phandle node to the PMU interrupt-affinity property.
Hi Biju,
Could you comment on how well this has been tested with respect
to CPU hotplug and suspend to RAM?
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> ---
> arch/arm/boot/dts/r8a7744.dtsi | 28 +++++++++++++++++++++++++++-
> 1 file changed, 27 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
> index 046ed94..79e75e7 100644
> --- a/arch/arm/boot/dts/r8a7744.dtsi
> +++ b/arch/arm/boot/dts/r8a7744.dtsi
> @@ -49,6 +49,7 @@
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> + enable-method = "renesas,apmu";
>
> cpu0: cpu@0 {
> device_type = "cpu";
> @@ -69,6 +70,25 @@
> < 375000 1000000>;
> };
>
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <1>;
> + clock-frequency = <1500000000>;
> + clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
> + clock-latency = <300000>; /* 300 us */
> + power-domains = <&sysc R8A7744_PD_CA15_CPU1>;
> + next-level-cache = <&L2_CA15>;
> +
> + /* kHz - uV - OPPs unknown yet */
> + operating-points = <1500000 1000000>,
> + <1312500 1000000>,
> + <1125000 1000000>,
> + < 937500 1000000>,
> + < 750000 1000000>,
> + < 375000 1000000>;
> + };
> +
> L2_CA15: cache-controller-0 {
> compatible = "cache";
> cache-unified;
> @@ -96,7 +116,7 @@
> compatible = "arm,cortex-a15-pmu";
> interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
> <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-affinity = <&cpu0>;
> + interrupt-affinity = <&cpu0>, <&cpu1>;
> };
>
> /* External SCIF clock */
> @@ -250,6 +270,12 @@
> #reset-cells = <1>;
> };
>
> + apmu@e6152000 {
> + compatible = "renesas,r8a7744-apmu", "renesas,apmu";
> + reg = <0 0xe6152000 0 0x188>;
> + cpus = <&cpu0 &cpu1>;
> + };
> +
> rst: reset-controller@e6160000 {
> compatible = "renesas,r8a7744-rst";
> reg = <0 0xe6160000 0 0x100>;
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/7] ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N Qseven SOM
2018-11-22 9:14 ` [PATCH 1/7] ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N Qseven SOM Biju Das
@ 2018-11-29 12:50 ` Simon Horman
2018-11-30 9:44 ` Geert Uytterhoeven
1 sibling, 0 replies; 28+ messages in thread
From: Simon Horman @ 2018-11-29 12:50 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Magnus Damm, linux-renesas-soc,
devicetree, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
On Thu, Nov 22, 2018 at 09:14:29AM +0000, Biju Das wrote:
> Add support for iWave RZ/G1N Qseven System On Module.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Thanks,
This looks fine to me but I will wait to see if there are other reviews
before applying.
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 2/7] ARM: dts: r8a7744: Initial SoC device tree
2018-11-22 9:14 ` [PATCH 2/7] ARM: dts: r8a7744: Initial SoC device tree Biju Das
@ 2018-11-29 12:50 ` Simon Horman
2018-11-30 8:48 ` Geert Uytterhoeven
2018-11-30 8:53 ` Geert Uytterhoeven
2 siblings, 0 replies; 28+ messages in thread
From: Simon Horman @ 2018-11-29 12:50 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Magnus Damm, linux-renesas-soc,
devicetree, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
On Thu, Nov 22, 2018 at 09:14:30AM +0000, Biju Das wrote:
> Basic support for the RZ/G1N (R8A7744) SoC. Added placeholders
> to avoid compilation error with the common platform code.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Thanks,
This looks fine to me but I will wait to see if there are other reviews
before applying.
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 3/7] ARM: dts: r8a7744-iwg20d-q7: Add support for iWave G20D-Q7 board based on RZ/G1N
2018-11-22 9:14 ` [PATCH 3/7] ARM: dts: r8a7744-iwg20d-q7: Add support for iWave G20D-Q7 board based on RZ/G1N Biju Das
@ 2018-11-29 12:50 ` Simon Horman
2018-11-30 9:46 ` Geert Uytterhoeven
1 sibling, 0 replies; 28+ messages in thread
From: Simon Horman @ 2018-11-29 12:50 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Magnus Damm, linux-renesas-soc,
devicetree, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
On Thu, Nov 22, 2018 at 09:14:31AM +0000, Biju Das wrote:
> Add support for iWave RainboW-G20D-Qseven board based on RZ/G1N.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Thanks,
This looks fine to me but I will wait to see if there are other reviews
before applying.
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 4/7] ARM: dts: r8a7744: Add SYS-DMAC support
2018-11-22 9:14 ` [PATCH 4/7] ARM: dts: r8a7744: Add SYS-DMAC support Biju Das
@ 2018-11-29 12:50 ` Simon Horman
2018-11-30 8:49 ` Geert Uytterhoeven
1 sibling, 0 replies; 28+ messages in thread
From: Simon Horman @ 2018-11-29 12:50 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Magnus Damm, linux-renesas-soc,
devicetree, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
On Thu, Nov 22, 2018 at 09:14:32AM +0000, Biju Das wrote:
> Describe SYS-DMAC0/1 in the R8A7744 device tree.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Thanks,
This looks fine to me but I will wait to see if there are other reviews
before applying.
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 5/7] ARM: dts: r8a7744: Add GPIO support
2018-11-22 9:14 ` [PATCH 5/7] ARM: dts: r8a7744: Add GPIO support Biju Das
@ 2018-11-29 12:51 ` Simon Horman
2018-11-30 8:49 ` Geert Uytterhoeven
1 sibling, 0 replies; 28+ messages in thread
From: Simon Horman @ 2018-11-29 12:51 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Magnus Damm, linux-renesas-soc,
devicetree, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
On Thu, Nov 22, 2018 at 09:14:33AM +0000, Biju Das wrote:
> Describe GPIO blocks in the R8A7744 device tree.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Thanks,
This looks fine to me but I will wait to see if there are other reviews
before applying.
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 6/7] ARM: dts: r8a7744: Add Ethernet AVB support
2018-11-22 9:14 ` [PATCH 6/7] ARM: dts: r8a7744: Add Ethernet AVB support Biju Das
@ 2018-11-29 12:51 ` Simon Horman
2018-11-30 8:50 ` Geert Uytterhoeven
1 sibling, 0 replies; 28+ messages in thread
From: Simon Horman @ 2018-11-29 12:51 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Magnus Damm, linux-renesas-soc,
devicetree, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
On Thu, Nov 22, 2018 at 09:14:34AM +0000, Biju Das wrote:
> Add Ethernet AVB support for R8A7744 SoC.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Thanks,
This looks fine to me but I will wait to see if there are other reviews
before applying.
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH 7/7] ARM: dts: r8a7744: Add SMP support
2018-11-29 12:49 ` Simon Horman
@ 2018-11-29 13:31 ` Biju Das
0 siblings, 0 replies; 28+ messages in thread
From: Biju Das @ 2018-11-29 13:31 UTC (permalink / raw)
To: Simon Horman
Cc: Rob Herring, Mark Rutland, Magnus Damm, linux-renesas-soc,
devicetree, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
Hi Simon,
Thanks for the feedback.
> -----Original Message-----
> From: linux-renesas-soc-owner@vger.kernel.org <linux-renesas-soc-
> owner@vger.kernel.org> On Behalf Of Simon Horman
> Sent: 29 November 2018 12:49
> To: Biju Das <biju.das@bp.renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>; Mark Rutland
> <mark.rutland@arm.com>; Magnus Damm <magnus.damm@gmail.com>;
> linux-renesas-soc@vger.kernel.org; devicetree@vger.kernel.org; Geert
> Uytterhoeven <geert+renesas@glider.be>; Chris Paterson
> <Chris.Paterson2@renesas.com>; Fabrizio Castro
> <fabrizio.castro@bp.renesas.com>
> Subject: Re: [PATCH 7/7] ARM: dts: r8a7744: Add SMP support
>
> On Thu, Nov 22, 2018 at 09:14:35AM +0000, Biju Das wrote:
> > Add DT node for the Advanced Power Management Unit (APMU), add the
> > second CPU core, and use "renesas,apmu" as "enable-method".
> >
> > Also add cpu1 phandle node to the PMU interrupt-affinity property.
>
> Hi Biju,
>
> Could you comment on how well this has been tested with respect to CPU
> hotplug and suspend to RAM?
Please find the snippet from test script. It will details the tests related to CPU hot plug and STR.
For cpu hotplug
-----------------
SCRIPTS_DIRECTORY="$(cd "$(dirname "$0")"; pwd)"
source "${SCRIPTS_DIRECTORY}"/identity.sh
PROCESSORS=$(cat /test-data/apmu_t_001-rzg1${RZG1_VARIANT}.txt | grep -c ^processor)
for CURRENT_PROCESSOR in $(seq ${PROCESSORS}); do
echo "*** Testing CPU hotplug for processor ${CURRENT_PROCESSOR} ***"
echo 0 > /sys/devices/system/cpu/cpu$((CURRENT_PROCESSOR - 1))/online
CURRENT_PROCESSORS=$(cat /proc/cpuinfo | grep -c ^processor)
if [ ${CURRENT_PROCESSORS} -eq ${PROCESSORS} ]; then
echo "FAILED: Can't take processor ${CURRENT_PROCESSOR} offline"
exit 1
fi
echo 1 > /sys/devices/system/cpu/cpu$((CURRENT_PROCESSOR - 1))/online
CURRENT_PROCESSORS=$(cat /proc/cpuinfo | grep -c ^processor)
if [ ${CURRENT_PROCESSORS} -ne ${PROCESSORS} ]; then
echo "FAILED: Can't take processor ${CURRENT_PROCESSOR} online"
exit 1
fi
done
For STR
---------
PROCESSORS=$(cat /test-data/apmu_t_001-rzg1${RZG1_VARIANT}.txt | grep -c ^processor)
PROCESSORS_COMBINATIONS=$(power_of_two ${PROCESSORS})
PROCESSORS_COMBINATIONS=$((PROCESSORS_COMBINATIONS - 1))
for CURRENT_PROCESSORS in $(seq ${PROCESSORS_COMBINATIONS}); do
echo "***********************************************************"
echo "* Testing suspend-to-RAM with the following configuration *"
echo "***********************************************************"
enable_all_cpus
disable_cpus ${CURRENT_PROCESSORS}
sleep 1
print_cpus_status
echo
echo
dmesg -c > /dev/null
echo enabled > /sys/class/tty/${DEBUG_CONSOLE}/power/wakeup
echo N > /sys/module/printk/parameters/console_suspend
echo mem > /sys/power/state
dmesg | grep -F "Restarting tasks ... done." > /dev/null
if [ $? -ne 0 ]; then
echo "FAILED: Something went wrong either when going to sleep or when waking up"
exit 1
fi
done
regards,
Biju
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > ---
> > arch/arm/boot/dts/r8a7744.dtsi | 28 +++++++++++++++++++++++++++-
> > 1 file changed, 27 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/boot/dts/r8a7744.dtsi
> > b/arch/arm/boot/dts/r8a7744.dtsi index 046ed94..79e75e7 100644
> > --- a/arch/arm/boot/dts/r8a7744.dtsi
> > +++ b/arch/arm/boot/dts/r8a7744.dtsi
> > @@ -49,6 +49,7 @@
> > cpus {
> > #address-cells = <1>;
> > #size-cells = <0>;
> > +enable-method = "renesas,apmu";
> >
> > cpu0: cpu@0 {
> > device_type = "cpu";
> > @@ -69,6 +70,25 @@
> > < 375000 1000000>;
> > };
> >
> > +cpu1: cpu@1 {
> > +device_type = "cpu";
> > +compatible = "arm,cortex-a15";
> > +reg = <1>;
> > +clock-frequency = <1500000000>;
> > +clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
> > +clock-latency = <300000>; /* 300 us */
> > +power-domains = <&sysc R8A7744_PD_CA15_CPU1>;
> > +next-level-cache = <&L2_CA15>;
> > +
> > +/* kHz - uV - OPPs unknown yet */
> > +operating-points = <1500000 1000000>,
> > + <1312500 1000000>,
> > + <1125000 1000000>,
> > + < 937500 1000000>,
> > + < 750000 1000000>,
> > + < 375000 1000000>;
> > +};
> > +
> > L2_CA15: cache-controller-0 {
> > compatible = "cache";
> > cache-unified;
> > @@ -96,7 +116,7 @@
> > compatible = "arm,cortex-a15-pmu";
> > interrupts-extended = <&gic GIC_SPI 72
> IRQ_TYPE_LEVEL_HIGH>,
> > <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> > -interrupt-affinity = <&cpu0>;
> > +interrupt-affinity = <&cpu0>, <&cpu1>;
> > };
> >
> > /* External SCIF clock */
> > @@ -250,6 +270,12 @@
> > #reset-cells = <1>;
> > };
> >
> > +apmu@e6152000 {
> > +compatible = "renesas,r8a7744-apmu",
> "renesas,apmu";
> > +reg = <0 0xe6152000 0 0x188>;
> > +cpus = <&cpu0 &cpu1>;
> > +};
> > +
> > rst: reset-controller@e6160000 {
> > compatible = "renesas,r8a7744-rst";
> > reg = <0 0xe6160000 0 0x100>;
> > --
> > 2.7.4
> >
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 2/7] ARM: dts: r8a7744: Initial SoC device tree
2018-11-22 9:14 ` [PATCH 2/7] ARM: dts: r8a7744: Initial SoC device tree Biju Das
2018-11-29 12:50 ` Simon Horman
@ 2018-11-30 8:48 ` Geert Uytterhoeven
2018-11-30 9:15 ` Biju Das
2018-11-30 8:53 ` Geert Uytterhoeven
2 siblings, 1 reply; 28+ messages in thread
From: Geert Uytterhoeven @ 2018-11-30 8:48 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
Hi Biju,
On Thu, Nov 22, 2018 at 10:23 AM Biju Das <biju.das@bp.renesas.com> wrote:
> Basic support for the RZ/G1N (R8A7744) SoC. Added placeholders
> to avoid compilation error with the common platform code.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Thanks for your patch!
> --- /dev/null
> +++ b/arch/arm/boot/dts/r8a7744.dtsi
> + soc {
> + pfc: pin-controller@e6060000 {
> + compatible = "renesas,pfc-r8a7744";
> + reg = <0 0xe6060000 0 0x164>;
Given the datasheet mentions (reserved) registers up to offset 0x24c,
you may want to use 0x250 for the register block length.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 4/7] ARM: dts: r8a7744: Add SYS-DMAC support
2018-11-22 9:14 ` [PATCH 4/7] ARM: dts: r8a7744: Add SYS-DMAC support Biju Das
2018-11-29 12:50 ` Simon Horman
@ 2018-11-30 8:49 ` Geert Uytterhoeven
1 sibling, 0 replies; 28+ messages in thread
From: Geert Uytterhoeven @ 2018-11-30 8:49 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
On Thu, Nov 22, 2018 at 10:23 AM Biju Das <biju.das@bp.renesas.com> wrote:
> Describe SYS-DMAC0/1 in the R8A7744 device tree.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 5/7] ARM: dts: r8a7744: Add GPIO support
2018-11-22 9:14 ` [PATCH 5/7] ARM: dts: r8a7744: Add GPIO support Biju Das
2018-11-29 12:51 ` Simon Horman
@ 2018-11-30 8:49 ` Geert Uytterhoeven
1 sibling, 0 replies; 28+ messages in thread
From: Geert Uytterhoeven @ 2018-11-30 8:49 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
On Thu, Nov 22, 2018 at 10:23 AM Biju Das <biju.das@bp.renesas.com> wrote:
> Describe GPIO blocks in the R8A7744 device tree.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 6/7] ARM: dts: r8a7744: Add Ethernet AVB support
2018-11-22 9:14 ` [PATCH 6/7] ARM: dts: r8a7744: Add Ethernet AVB support Biju Das
2018-11-29 12:51 ` Simon Horman
@ 2018-11-30 8:50 ` Geert Uytterhoeven
1 sibling, 0 replies; 28+ messages in thread
From: Geert Uytterhoeven @ 2018-11-30 8:50 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
On Thu, Nov 22, 2018 at 10:23 AM Biju Das <biju.das@bp.renesas.com> wrote:
> Add Ethernet AVB support for R8A7744 SoC.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 2/7] ARM: dts: r8a7744: Initial SoC device tree
2018-11-22 9:14 ` [PATCH 2/7] ARM: dts: r8a7744: Initial SoC device tree Biju Das
2018-11-29 12:50 ` Simon Horman
2018-11-30 8:48 ` Geert Uytterhoeven
@ 2018-11-30 8:53 ` Geert Uytterhoeven
2 siblings, 0 replies; 28+ messages in thread
From: Geert Uytterhoeven @ 2018-11-30 8:53 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
Hi Biju,
On Thu, Nov 22, 2018 at 10:23 AM Biju Das <biju.das@bp.renesas.com> wrote:
> Basic support for the RZ/G1N (R8A7744) SoC. Added placeholders
> to avoid compilation error with the common platform code.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> --- /dev/null
> +++ b/arch/arm/boot/dts/r8a7744.dtsi
> @@ -0,0 +1,369 @@
> + soc {
> + gic: interrupt-controller@f1001000 {
> + compatible = "arm,gic-400";
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> + interrupt-controller;
> + reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
> + <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
Tehcnically, this mask should be GIC_CPU_MASK_SIMPLE(1)
until you add the second CPU node.
> + timer {
> + compatible = "arm,armv7-timer";
> + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
Likewise.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 7/7] ARM: dts: r8a7744: Add SMP support
2018-11-22 9:14 ` [PATCH 7/7] ARM: dts: r8a7744: Add SMP support Biju Das
2018-11-29 12:49 ` Simon Horman
@ 2018-11-30 8:54 ` Geert Uytterhoeven
2018-11-30 9:22 ` Biju Das
1 sibling, 1 reply; 28+ messages in thread
From: Geert Uytterhoeven @ 2018-11-30 8:54 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
On Thu, Nov 22, 2018 at 10:23 AM Biju Das <biju.das@bp.renesas.com> wrote:
> Add DT node for the Advanced Power Management Unit (APMU), add the
> second CPU core, and use "renesas,apmu" as "enable-method".
>
> Also add cpu1 phandle node to the PMU interrupt-affinity property.
Please change GIC_CPU_MASK_SIMPLE() from 1 to 2 in this patch, too.
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH 2/7] ARM: dts: r8a7744: Initial SoC device tree
2018-11-30 8:48 ` Geert Uytterhoeven
@ 2018-11-30 9:15 ` Biju Das
0 siblings, 0 replies; 28+ messages in thread
From: Biju Das @ 2018-11-30 9:15 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
Hi Geert,
Thanks for the feedback.
> -----Original Message-----
> From: linux-renesas-soc-owner@vger.kernel.org <linux-renesas-soc-
> owner@vger.kernel.org> On Behalf Of Geert Uytterhoeven
> Sent: 30 November 2018 08:49
> To: Biju Das <biju.das@bp.renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>; Mark Rutland
> <mark.rutland@arm.com>; Simon Horman <horms@verge.net.au>; Magnus
> Damm <magnus.damm@gmail.com>; Linux-Renesas <linux-renesas-
> soc@vger.kernel.org>; open list:OPEN FIRMWARE AND FLATTENED DEVICE
> TREE BINDINGS <devicetree@vger.kernel.org>; Geert Uytterhoeven
> <geert+renesas@glider.be>; Chris Paterson
> <Chris.Paterson2@renesas.com>; Fabrizio Castro
> <fabrizio.castro@bp.renesas.com>
> Subject: Re: [PATCH 2/7] ARM: dts: r8a7744: Initial SoC device tree
>
> Hi Biju,
>
> On Thu, Nov 22, 2018 at 10:23 AM Biju Das <biju.das@bp.renesas.com>
> wrote:
> > Basic support for the RZ/G1N (R8A7744) SoC. Added placeholders to
> > avoid compilation error with the common platform code.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/r8a7744.dtsi
>
> > + soc {
>
> > + pfc: pin-controller@e6060000 {
> > + compatible = "renesas,pfc-r8a7744";
> > + reg = <0 0xe6060000 0 0x164>;
>
> Given the datasheet mentions (reserved) registers up to offset 0x24c, you
> may want to use 0x250 for the register block length.
>
Ok will send V2 for this.
I was in confusion to set the size as 0x164 or 0x250, since the Data sheet mention that setting prohibited for 0x240-0x24c and is reserved.
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Gr{oetje,eeting}s,
>
> Geert
Regards,
Biju
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH 7/7] ARM: dts: r8a7744: Add SMP support
2018-11-30 8:54 ` Geert Uytterhoeven
@ 2018-11-30 9:22 ` Biju Das
0 siblings, 0 replies; 28+ messages in thread
From: Biju Das @ 2018-11-30 9:22 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
Hi Geert,
Thanks for the feedback.
> -----Original Message-----
> From: linux-renesas-soc-owner@vger.kernel.org <linux-renesas-soc-
> owner@vger.kernel.org> On Behalf Of Geert Uytterhoeven
> Sent: 30 November 2018 08:54
> To: Biju Das <biju.das@bp.renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>; Mark Rutland
> <mark.rutland@arm.com>; Simon Horman <horms@verge.net.au>; Magnus
> Damm <magnus.damm@gmail.com>; Linux-Renesas <linux-renesas-
> soc@vger.kernel.org>; open list:OPEN FIRMWARE AND FLATTENED DEVICE
> TREE BINDINGS <devicetree@vger.kernel.org>; Geert Uytterhoeven
> <geert+renesas@glider.be>; Chris Paterson
> <Chris.Paterson2@renesas.com>; Fabrizio Castro
> <fabrizio.castro@bp.renesas.com>
> Subject: Re: [PATCH 7/7] ARM: dts: r8a7744: Add SMP support
>
> On Thu, Nov 22, 2018 at 10:23 AM Biju Das <biju.das@bp.renesas.com>
> wrote:
> > Add DT node for the Advanced Power Management Unit (APMU), add the
> > second CPU core, and use "renesas,apmu" as "enable-method".
> >
> > Also add cpu1 phandle node to the PMU interrupt-affinity property.
>
> Please change GIC_CPU_MASK_SIMPLE() from 1 to 2 in this patch, too.
OK, Will send V2 for this.
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Gr{oetje,eeting}s,
>
> Geert
>
Regards,
Biju
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/7] ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N Qseven SOM
2018-11-22 9:14 ` [PATCH 1/7] ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N Qseven SOM Biju Das
2018-11-29 12:50 ` Simon Horman
@ 2018-11-30 9:44 ` Geert Uytterhoeven
2018-11-30 10:04 ` Biju Das
1 sibling, 1 reply; 28+ messages in thread
From: Geert Uytterhoeven @ 2018-11-30 9:44 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
Hi Biju,
On Thu, Nov 22, 2018 at 10:22 AM Biju Das <biju.das@bp.renesas.com> wrote:
> Add support for iWave RZ/G1N Qseven System On Module.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> --- /dev/null
> +++ b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
> @@ -0,0 +1,31 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the iWave RZ/G1N Qseven SOM
> + *
> + * Copyright (C) 2018 Renesas Electronics Corp.
> + */
> +
> +#include "r8a7744.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + compatible = "iwave,g20m", "renesas,r8a7744";
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0 0x40000000 0 0x40000000>;
> + };
I could not verify the memory configuration, but I assume it's correct ;-)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 3/7] ARM: dts: r8a7744-iwg20d-q7: Add support for iWave G20D-Q7 board based on RZ/G1N
2018-11-22 9:14 ` [PATCH 3/7] ARM: dts: r8a7744-iwg20d-q7: Add support for iWave G20D-Q7 board based on RZ/G1N Biju Das
2018-11-29 12:50 ` Simon Horman
@ 2018-11-30 9:46 ` Geert Uytterhoeven
1 sibling, 0 replies; 28+ messages in thread
From: Geert Uytterhoeven @ 2018-11-30 9:46 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
On Thu, Nov 22, 2018 at 10:23 AM Biju Das <biju.das@bp.renesas.com> wrote:
> Add support for iWave RainboW-G20D-Qseven board based on RZ/G1N.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH 1/7] ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N Qseven SOM
2018-11-30 9:44 ` Geert Uytterhoeven
@ 2018-11-30 10:04 ` Biju Das
0 siblings, 0 replies; 28+ messages in thread
From: Biju Das @ 2018-11-30 10:04 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
<devicetree@vger.kernel.org>,
Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
Hello Geert,
Thanks for the feedback.
> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 30 November 2018 09:45
> To: Biju Das <biju.das@bp.renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>; Mark Rutland
> <mark.rutland@arm.com>; Simon Horman <horms@verge.net.au>; Magnus
> Damm <magnus.damm@gmail.com>; Linux-Renesas <linux-renesas-
> soc@vger.kernel.org>; open list:OPEN FIRMWARE AND FLATTENED DEVICE
> TREE BINDINGS <devicetree@vger.kernel.org>; Geert Uytterhoeven
> <geert+renesas@glider.be>; Chris Paterson
> <Chris.Paterson2@renesas.com>; Fabrizio Castro
> <fabrizio.castro@bp.renesas.com>
> Subject: Re: [PATCH 1/7] ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N
> Qseven SOM
>
> Hi Biju,
>
> On Thu, Nov 22, 2018 at 10:22 AM Biju Das <biju.das@bp.renesas.com>
> wrote:
> > Add support for iWave RZ/G1N Qseven System On Module.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
> > @@ -0,0 +1,31 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Device Tree Source for the iWave RZ/G1N Qseven SOM
> > + *
> > + * Copyright (C) 2018 Renesas Electronics Corp.
> > + */
> > +
> > +#include "r8a7744.dtsi"
> > +#include <dt-bindings/gpio/gpio.h>
> > +
> > +/ {
> > + compatible = "iwave,g20m", "renesas,r8a7744";
> > +
> > + memory@40000000 {
> > + device_type = "memory";
> > + reg = <0 0x40000000 0 0x40000000>;
> > + };
>
> I could not verify the memory configuration, but I assume it's correct ;-)
Yes it is correct, 1GB memory populated on this board.
Regards,
Biju
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH 1/7] ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N Qseven SOM
@ 2018-11-30 10:04 ` Biju Das
0 siblings, 0 replies; 28+ messages in thread
From: Biju Das @ 2018-11-30 10:04 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
Hello Geert,
Thanks for the feedback.
> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 30 November 2018 09:45
> To: Biju Das <biju.das@bp.renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>; Mark Rutland
> <mark.rutland@arm.com>; Simon Horman <horms@verge.net.au>; Magnus
> Damm <magnus.damm@gmail.com>; Linux-Renesas <linux-renesas-
> soc@vger.kernel.org>; open list:OPEN FIRMWARE AND FLATTENED DEVICE
> TREE BINDINGS <devicetree@vger.kernel.org>; Geert Uytterhoeven
> <geert+renesas@glider.be>; Chris Paterson
> <Chris.Paterson2@renesas.com>; Fabrizio Castro
> <fabrizio.castro@bp.renesas.com>
> Subject: Re: [PATCH 1/7] ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N
> Qseven SOM
>
> Hi Biju,
>
> On Thu, Nov 22, 2018 at 10:22 AM Biju Das <biju.das@bp.renesas.com>
> wrote:
> > Add support for iWave RZ/G1N Qseven System On Module.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
> > @@ -0,0 +1,31 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Device Tree Source for the iWave RZ/G1N Qseven SOM
> > + *
> > + * Copyright (C) 2018 Renesas Electronics Corp.
> > + */
> > +
> > +#include "r8a7744.dtsi"
> > +#include <dt-bindings/gpio/gpio.h>
> > +
> > +/ {
> > + compatible = "iwave,g20m", "renesas,r8a7744";
> > +
> > + memory@40000000 {
> > + device_type = "memory";
> > + reg = <0 0x40000000 0 0x40000000>;
> > + };
>
> I could not verify the memory configuration, but I assume it's correct ;-)
Yes it is correct, 1GB memory populated on this board.
Regards,
Biju
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2018-11-30 21:13 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-11-22 9:14 [PATCH 0/7] Add support for iWave G20D-Q7 board based on RZ/G1N Biju Das
2018-11-22 9:14 ` [PATCH 1/7] ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N Qseven SOM Biju Das
2018-11-29 12:50 ` Simon Horman
2018-11-30 9:44 ` Geert Uytterhoeven
2018-11-30 10:04 ` Biju Das
2018-11-30 10:04 ` Biju Das
2018-11-22 9:14 ` [PATCH 2/7] ARM: dts: r8a7744: Initial SoC device tree Biju Das
2018-11-29 12:50 ` Simon Horman
2018-11-30 8:48 ` Geert Uytterhoeven
2018-11-30 9:15 ` Biju Das
2018-11-30 8:53 ` Geert Uytterhoeven
2018-11-22 9:14 ` [PATCH 3/7] ARM: dts: r8a7744-iwg20d-q7: Add support for iWave G20D-Q7 board based on RZ/G1N Biju Das
2018-11-29 12:50 ` Simon Horman
2018-11-30 9:46 ` Geert Uytterhoeven
2018-11-22 9:14 ` [PATCH 4/7] ARM: dts: r8a7744: Add SYS-DMAC support Biju Das
2018-11-29 12:50 ` Simon Horman
2018-11-30 8:49 ` Geert Uytterhoeven
2018-11-22 9:14 ` [PATCH 5/7] ARM: dts: r8a7744: Add GPIO support Biju Das
2018-11-29 12:51 ` Simon Horman
2018-11-30 8:49 ` Geert Uytterhoeven
2018-11-22 9:14 ` [PATCH 6/7] ARM: dts: r8a7744: Add Ethernet AVB support Biju Das
2018-11-29 12:51 ` Simon Horman
2018-11-30 8:50 ` Geert Uytterhoeven
2018-11-22 9:14 ` [PATCH 7/7] ARM: dts: r8a7744: Add SMP support Biju Das
2018-11-29 12:49 ` Simon Horman
2018-11-29 13:31 ` Biju Das
2018-11-30 8:54 ` Geert Uytterhoeven
2018-11-30 9:22 ` Biju Das
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.