* [PATCH 00/16] treewide: Initial support for R-Car S4-8
@ 2021-11-16 7:41 Yoshihiro Shimoda
2021-11-16 7:41 ` [PATCH 01/16] dt-bindings: arm: renesas: Document R-Car S4-8 SoC DT bindings Yoshihiro Shimoda
` (15 more replies)
0 siblings, 16 replies; 47+ messages in thread
From: Yoshihiro Shimoda @ 2021-11-16 7:41 UTC (permalink / raw)
To: geert+renesas, magnus.damm, robh+dt, gregkh, jirislaby
Cc: linux-renesas-soc, devicetree, linux-serial, Yoshihiro Shimoda
This patch series adds initial support for the Renesas R-Car S4-8
(r8a779f0) SoC.
Yoshihiro Shimoda (16):
dt-bindings: arm: renesas: Document R-Car S4-8 SoC DT bindings
dt-bindings: arm: renesas: Document Renesas Spider boards
dt-bindings: reset: renesas,rst: Document r8a779f0 reset module
dt-bindings: power: renesas,rcar-sysc: Document r8a779f0 SYSC bindings
dt-bindings: power: Add r8a779f0 SYSC power domain definitions
dt-bindings: clock: renesas,cpg-mssr: Document r8a779f0
dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions
dt-bindings: serial: renesas,scif: Document r8a779f0 bindings
soc: renesas: Identify R-Car S4-8
soc: renesas: r8a779f0-sysc: Add r8a779f0 support
soc: renesas: rcar-rst: Add support for R-Car S4-8
clk: renesas: cpg-mssr: Add support for R-Car S4-8
tty: serial: sh-sci: Add support for R-Car Gen4
arm64: dts: renesas: Add Renesas R8A779F0 SoC support
arm64: dts: renesas: Add Renesas Spider boards support
arm64: defconfig: Enable R-Car S4-8
.../devicetree/bindings/arm/renesas.yaml | 12 +
.../bindings/clock/renesas,cpg-mssr.yaml | 1 +
.../bindings/power/renesas,rcar-sysc.yaml | 1 +
.../bindings/reset/renesas,rst.yaml | 1 +
.../bindings/serial/renesas,scif.yaml | 6 +
arch/arm64/boot/dts/renesas/Makefile | 2 +
.../boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 36 ++
.../boot/dts/renesas/r8a779f0-spider.dts | 22 +
arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 121 ++++++
arch/arm64/configs/defconfig | 1 +
drivers/clk/renesas/Kconfig | 10 +
drivers/clk/renesas/Makefile | 2 +
drivers/clk/renesas/r8a779a0-cpg-mssr.c | 2 +-
drivers/clk/renesas/r8a779f0-cpg-mssr.c | 188 +++++++++
drivers/clk/renesas/rcar-gen4-cpg.c | 141 +++++++
drivers/clk/renesas/rcar-gen4-cpg.h | 76 ++++
drivers/clk/renesas/renesas-cpg-mssr.c | 42 +-
drivers/clk/renesas/renesas-cpg-mssr.h | 3 +-
drivers/soc/renesas/Kconfig | 10 +
drivers/soc/renesas/Makefile | 3 +-
drivers/soc/renesas/r8a779a0-sysc.c | 380 +-----------------
drivers/soc/renesas/r8a779f0-sysc.c | 47 +++
drivers/soc/renesas/rcar-gen4-sysc.c | 376 +++++++++++++++++
drivers/soc/renesas/rcar-gen4-sysc.h | 43 ++
drivers/soc/renesas/rcar-rst.c | 14 +-
drivers/soc/renesas/renesas-soc.c | 13 +
drivers/tty/serial/sh-sci.c | 3 +
include/dt-bindings/clock/r8a779f0-cpg-mssr.h | 65 +++
include/dt-bindings/power/r8a779f0-sysc.h | 30 ++
29 files changed, 1251 insertions(+), 400 deletions(-)
create mode 100644 arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r8a779f0-spider.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a779f0.dtsi
create mode 100644 drivers/clk/renesas/r8a779f0-cpg-mssr.c
create mode 100644 drivers/clk/renesas/rcar-gen4-cpg.c
create mode 100644 drivers/clk/renesas/rcar-gen4-cpg.h
create mode 100644 drivers/soc/renesas/r8a779f0-sysc.c
create mode 100644 drivers/soc/renesas/rcar-gen4-sysc.c
create mode 100644 drivers/soc/renesas/rcar-gen4-sysc.h
create mode 100644 include/dt-bindings/clock/r8a779f0-cpg-mssr.h
create mode 100644 include/dt-bindings/power/r8a779f0-sysc.h
--
2.25.1
^ permalink raw reply [flat|nested] 47+ messages in thread* [PATCH 01/16] dt-bindings: arm: renesas: Document R-Car S4-8 SoC DT bindings 2021-11-16 7:41 [PATCH 00/16] treewide: Initial support for R-Car S4-8 Yoshihiro Shimoda @ 2021-11-16 7:41 ` Yoshihiro Shimoda 2021-11-18 17:50 ` Geert Uytterhoeven 2021-11-16 7:41 ` [PATCH 02/16] dt-bindings: arm: renesas: Document Renesas Spider boards Yoshihiro Shimoda ` (14 subsequent siblings) 15 siblings, 1 reply; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-11-16 7:41 UTC (permalink / raw) To: geert+renesas, magnus.damm, robh+dt, gregkh, jirislaby Cc: linux-renesas-soc, devicetree, linux-serial, Yoshihiro Shimoda Add device tree bindings documentation for Renesas R-Car S4-8 (r8a779f0). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- Documentation/devicetree/bindings/arm/renesas.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 517206507801..36197f53b310 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -315,6 +315,10 @@ properties: - const: renesas,falcon-cpu - const: renesas,r8a779a0 + - description: R-Car S4-8 (R8A779F0) + items: + - const: renesas,r8a779f0 + - description: R-Car H3e (R8A779M0) items: - enum: -- 2.25.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH 01/16] dt-bindings: arm: renesas: Document R-Car S4-8 SoC DT bindings 2021-11-16 7:41 ` [PATCH 01/16] dt-bindings: arm: renesas: Document R-Car S4-8 SoC DT bindings Yoshihiro Shimoda @ 2021-11-18 17:50 ` Geert Uytterhoeven 0 siblings, 0 replies; 47+ messages in thread From: Geert Uytterhoeven @ 2021-11-18 17:50 UTC (permalink / raw) To: Yoshihiro Shimoda Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > Add device tree bindings documentation for Renesas R-Car S4-8 > (r8a779f0). > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v5.17. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH 02/16] dt-bindings: arm: renesas: Document Renesas Spider boards 2021-11-16 7:41 [PATCH 00/16] treewide: Initial support for R-Car S4-8 Yoshihiro Shimoda 2021-11-16 7:41 ` [PATCH 01/16] dt-bindings: arm: renesas: Document R-Car S4-8 SoC DT bindings Yoshihiro Shimoda @ 2021-11-16 7:41 ` Yoshihiro Shimoda 2021-11-16 14:02 ` Rob Herring 2021-11-18 17:53 ` Geert Uytterhoeven 2021-11-16 7:41 ` [PATCH 03/16] dt-bindings: reset: renesas,rst: Document r8a779f0 reset module Yoshihiro Shimoda ` (13 subsequent siblings) 15 siblings, 2 replies; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-11-16 7:41 UTC (permalink / raw) To: geert+renesas, magnus.damm, robh+dt, gregkh, jirislaby Cc: linux-renesas-soc, devicetree, linux-serial, Yoshihiro Shimoda Add device tree bindings documentation for Renesas R-Car S4-8 Spider CPU and BreakOut boards. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- Documentation/devicetree/bindings/arm/renesas.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 36197f53b310..41f3de8ddc76 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -317,6 +317,14 @@ properties: - description: R-Car S4-8 (R8A779F0) items: + - enum: + - renesas,spider-cpu # Spider CPU board (RTP8A779FASKB0SC2S) + - const: renesas,r8a779f0 + + items: + - enum: + - renesas,spider-breakout # Spider BreakOut board (RTP8A779F0ASKB0SB0S) + - const: renesas,spider-cpu - const: renesas,r8a779f0 - description: R-Car H3e (R8A779M0) -- 2.25.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH 02/16] dt-bindings: arm: renesas: Document Renesas Spider boards 2021-11-16 7:41 ` [PATCH 02/16] dt-bindings: arm: renesas: Document Renesas Spider boards Yoshihiro Shimoda @ 2021-11-16 14:02 ` Rob Herring 2021-11-18 17:53 ` Geert Uytterhoeven 1 sibling, 0 replies; 47+ messages in thread From: Rob Herring @ 2021-11-16 14:02 UTC (permalink / raw) To: Yoshihiro Shimoda Cc: gregkh, magnus.damm, jirislaby, geert+renesas, robh+dt, linux-renesas-soc, devicetree, linux-serial On Tue, 16 Nov 2021 16:41:16 +0900, Yoshihiro Shimoda wrote: > Add device tree bindings documentation for Renesas R-Car S4-8 > Spider CPU and BreakOut boards. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > --- > Documentation/devicetree/bindings/arm/renesas.yaml | 8 ++++++++ > 1 file changed, 8 insertions(+) > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: ./Documentation/devicetree/bindings/arm/renesas.yaml:324:9: [error] duplication of key "items" in mapping (key-duplicates) dtschema/dtc warnings/errors: make[1]: *** Deleting file 'Documentation/devicetree/bindings/arm/renesas.example.dts' Traceback (most recent call last): File "/usr/local/bin/dt-extract-example", line 45, in <module> binding = yaml.load(open(args.yamlfile, encoding='utf-8').read()) File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/main.py", line 434, in load return constructor.get_single_data() File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 121, in get_single_data return self.construct_document(node) File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 131, in construct_document for _dummy in generator: File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 674, in construct_yaml_map value = self.construct_mapping(node) File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 445, in construct_mapping return BaseConstructor.construct_mapping(self, node, deep=deep) File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 263, in construct_mapping if self.check_mapping_key(node, key_node, mapping, key, value): File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 294, in check_mapping_key raise DuplicateKeyError(*args) ruamel.yaml.constructor.DuplicateKeyError: while constructing a mapping in "<unicode string>", line 318, column 9 found duplicate key "items" with value "[]" (original value: "[]") in "<unicode string>", line 324, column 9 To suppress this check see: http://yaml.readthedocs.io/en/latest/api.html#duplicate-keys make[1]: *** [Documentation/devicetree/bindings/Makefile:25: Documentation/devicetree/bindings/arm/renesas.example.dts] Error 1 make[1]: *** Waiting for unfinished jobs.... Traceback (most recent call last): File "/usr/local/bin/dt-doc-validate", line 25, in check_doc testtree = dtschema.load(filename, line_number=line_number) File "/usr/local/lib/python3.8/dist-packages/dtschema/lib.py", line 656, in load return yaml.load(f.read()) File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/main.py", line 434, in load return constructor.get_single_data() File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 121, in get_single_data return self.construct_document(node) File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 131, in construct_document for _dummy in generator: File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 674, in construct_yaml_map value = self.construct_mapping(node) File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 445, in construct_mapping return BaseConstructor.construct_mapping(self, node, deep=deep) File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 263, in construct_mapping if self.check_mapping_key(node, key_node, mapping, key, value): File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 294, in check_mapping_key raise DuplicateKeyError(*args) ruamel.yaml.constructor.DuplicateKeyError: while constructing a mapping in "<unicode string>", line 318, column 9 found duplicate key "items" with value "[]" (original value: "[]") in "<unicode string>", line 324, column 9 To suppress this check see: http://yaml.readthedocs.io/en/latest/api.html#duplicate-keys During handling of the above exception, another exception occurred: Traceback (most recent call last): File "/usr/local/bin/dt-doc-validate", line 67, in <module> ret = check_doc(f) File "/usr/local/bin/dt-doc-validate", line 30, in check_doc print(filename + ":", exc.path[-1], exc.message, file=sys.stderr) AttributeError: 'DuplicateKeyError' object has no attribute 'path' /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/arm/renesas.yaml: ignoring, error parsing file warning: no schema found in file: ./Documentation/devicetree/bindings/arm/renesas.yaml make: *** [Makefile:1413: dt_binding_check] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/1555677 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit. ^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 02/16] dt-bindings: arm: renesas: Document Renesas Spider boards 2021-11-16 7:41 ` [PATCH 02/16] dt-bindings: arm: renesas: Document Renesas Spider boards Yoshihiro Shimoda 2021-11-16 14:02 ` Rob Herring @ 2021-11-18 17:53 ` Geert Uytterhoeven 2021-11-19 2:14 ` Yoshihiro Shimoda 1 sibling, 1 reply; 47+ messages in thread From: Geert Uytterhoeven @ 2021-11-18 17:53 UTC (permalink / raw) To: Yoshihiro Shimoda Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS Hi Shimoda-san, On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > Add device tree bindings documentation for Renesas R-Car S4-8 > Spider CPU and BreakOut boards. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Thanks for your patch! > --- a/Documentation/devicetree/bindings/arm/renesas.yaml > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml > @@ -317,6 +317,14 @@ properties: > > - description: R-Car S4-8 (R8A779F0) > items: > + - enum: > + - renesas,spider-cpu # Spider CPU board (RTP8A779FASKB0SC2S) > + - const: renesas,r8a779f0 > + > + items: Missing "-" in front of "items:". > + - enum: > + - renesas,spider-breakout # Spider BreakOut board (RTP8A779F0ASKB0SB0S) > + - const: renesas,spider-cpu > - const: renesas,r8a779f0 > > - description: R-Car H3e (R8A779M0) The rest LGTM. Reading[1], I assume "RTP8A779F0ASKB0SP2S" is the part number of the full kit? [1] https://www.renesas.com/us/en/products/automotive-products/automotive-system-chips-socs/rtp8a779f0askb0sp2s-r-car-s4-reference-boardspider Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 47+ messages in thread
* RE: [PATCH 02/16] dt-bindings: arm: renesas: Document Renesas Spider boards 2021-11-18 17:53 ` Geert Uytterhoeven @ 2021-11-19 2:14 ` Yoshihiro Shimoda 0 siblings, 0 replies; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-11-19 2:14 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS Hi Geert-san, Thank you for your review! > From: Geert Uytterhoeven, Sent: Friday, November 19, 2021 2:54 AM > > On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda > <yoshihiro.shimoda.uh@renesas.com> wrote: > > Add device tree bindings documentation for Renesas R-Car S4-8 > > Spider CPU and BreakOut boards. > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > > Thanks for your patch! > > > --- a/Documentation/devicetree/bindings/arm/renesas.yaml > > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml > > @@ -317,6 +317,14 @@ properties: > > > > - description: R-Car S4-8 (R8A779F0) > > items: > > + - enum: > > + - renesas,spider-cpu # Spider CPU board (RTP8A779FASKB0SC2S) I realized that the part number should be RTP8A779F0ASKB0SC2S. ~ I'll fix it in v2. > > + - const: renesas,r8a779f0 > > + > > + items: > > Missing "-" in front of "items:". Oops. I'll fix it. > > + - enum: > > + - renesas,spider-breakout # Spider BreakOut board (RTP8A779F0ASKB0SB0S) > > + - const: renesas,spider-cpu > > - const: renesas,r8a779f0 > > > > - description: R-Car H3e (R8A779M0) > > The rest LGTM. > Reading[1], I assume "RTP8A779F0ASKB0SP2S" is the part number of the > full kit? Yes, your assumption is correct. Best regards, Yoshihiro Shimoda ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH 03/16] dt-bindings: reset: renesas,rst: Document r8a779f0 reset module 2021-11-16 7:41 [PATCH 00/16] treewide: Initial support for R-Car S4-8 Yoshihiro Shimoda 2021-11-16 7:41 ` [PATCH 01/16] dt-bindings: arm: renesas: Document R-Car S4-8 SoC DT bindings Yoshihiro Shimoda 2021-11-16 7:41 ` [PATCH 02/16] dt-bindings: arm: renesas: Document Renesas Spider boards Yoshihiro Shimoda @ 2021-11-16 7:41 ` Yoshihiro Shimoda 2021-11-18 18:19 ` Geert Uytterhoeven 2021-11-16 7:41 ` [PATCH 04/16] dt-bindings: power: renesas,rcar-sysc: Document r8a779f0 SYSC bindings Yoshihiro Shimoda ` (12 subsequent siblings) 15 siblings, 1 reply; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-11-16 7:41 UTC (permalink / raw) To: geert+renesas, magnus.damm, robh+dt, gregkh, jirislaby Cc: linux-renesas-soc, devicetree, linux-serial, Yoshihiro Shimoda Document bindings for the R-Car S4-8 (R8A779F0) reset module. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- Documentation/devicetree/bindings/reset/renesas,rst.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.yaml b/Documentation/devicetree/bindings/reset/renesas,rst.yaml index 620cd0538bbe..bbe313bf1796 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rst.yaml +++ b/Documentation/devicetree/bindings/reset/renesas,rst.yaml @@ -48,6 +48,7 @@ properties: - renesas,r8a77990-rst # R-Car E3 - renesas,r8a77995-rst # R-Car D3 - renesas,r8a779a0-rst # R-Car V3U + - renesas,r8a779f0-rst # R-Car S4-8 reg: maxItems: 1 -- 2.25.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH 03/16] dt-bindings: reset: renesas,rst: Document r8a779f0 reset module 2021-11-16 7:41 ` [PATCH 03/16] dt-bindings: reset: renesas,rst: Document r8a779f0 reset module Yoshihiro Shimoda @ 2021-11-18 18:19 ` Geert Uytterhoeven 0 siblings, 0 replies; 47+ messages in thread From: Geert Uytterhoeven @ 2021-11-18 18:19 UTC (permalink / raw) To: Yoshihiro Shimoda Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > Document bindings for the R-Car S4-8 (R8A779F0) reset module. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v5.17. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH 04/16] dt-bindings: power: renesas,rcar-sysc: Document r8a779f0 SYSC bindings 2021-11-16 7:41 [PATCH 00/16] treewide: Initial support for R-Car S4-8 Yoshihiro Shimoda ` (2 preceding siblings ...) 2021-11-16 7:41 ` [PATCH 03/16] dt-bindings: reset: renesas,rst: Document r8a779f0 reset module Yoshihiro Shimoda @ 2021-11-16 7:41 ` Yoshihiro Shimoda 2021-11-18 18:38 ` Geert Uytterhoeven 2021-11-16 7:41 ` [PATCH 05/16] dt-bindings: power: Add r8a779f0 SYSC power domain definitions Yoshihiro Shimoda ` (11 subsequent siblings) 15 siblings, 1 reply; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-11-16 7:41 UTC (permalink / raw) To: geert+renesas, magnus.damm, robh+dt, gregkh, jirislaby Cc: linux-renesas-soc, devicetree, linux-serial, Yoshihiro Shimoda Document bindings for the R-Car S4-8 (aka R8A779F0) SYSC block. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml index 99e8042ac111..62a49ca319ec 100644 --- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml +++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml @@ -41,6 +41,7 @@ properties: - renesas,r8a77990-sysc # R-Car E3 - renesas,r8a77995-sysc # R-Car D3 - renesas,r8a779a0-sysc # R-Car V3U + - renesas,r8a779f0-sysc # R-Car S4-8 reg: maxItems: 1 -- 2.25.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH 04/16] dt-bindings: power: renesas,rcar-sysc: Document r8a779f0 SYSC bindings 2021-11-16 7:41 ` [PATCH 04/16] dt-bindings: power: renesas,rcar-sysc: Document r8a779f0 SYSC bindings Yoshihiro Shimoda @ 2021-11-18 18:38 ` Geert Uytterhoeven 0 siblings, 0 replies; 47+ messages in thread From: Geert Uytterhoeven @ 2021-11-18 18:38 UTC (permalink / raw) To: Yoshihiro Shimoda Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > Document bindings for the R-Car S4-8 (aka R8A779F0) SYSC block. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v5.17. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH 05/16] dt-bindings: power: Add r8a779f0 SYSC power domain definitions 2021-11-16 7:41 [PATCH 00/16] treewide: Initial support for R-Car S4-8 Yoshihiro Shimoda ` (3 preceding siblings ...) 2021-11-16 7:41 ` [PATCH 04/16] dt-bindings: power: renesas,rcar-sysc: Document r8a779f0 SYSC bindings Yoshihiro Shimoda @ 2021-11-16 7:41 ` Yoshihiro Shimoda 2021-11-18 18:42 ` Geert Uytterhoeven 2021-11-16 7:41 ` [PATCH 06/16] dt-bindings: clock: renesas,cpg-mssr: Document r8a779f0 Yoshihiro Shimoda ` (10 subsequent siblings) 15 siblings, 1 reply; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-11-16 7:41 UTC (permalink / raw) To: geert+renesas, magnus.damm, robh+dt, gregkh, jirislaby Cc: linux-renesas-soc, devicetree, linux-serial, Yoshihiro Shimoda Add power domain indices for R-Car S4-8 (r8a779f0). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- include/dt-bindings/power/r8a779f0-sysc.h | 30 +++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 include/dt-bindings/power/r8a779f0-sysc.h diff --git a/include/dt-bindings/power/r8a779f0-sysc.h b/include/dt-bindings/power/r8a779f0-sysc.h new file mode 100644 index 000000000000..97e6ed5c16d5 --- /dev/null +++ b/include/dt-bindings/power/r8a779f0-sysc.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ +/* + * Copyright (C) 2021 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A779F0_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A779F0_SYSC_H__ + +/* + * These power domain indices match the Power Domain Register Numbers (PDR) + */ + +#define R8A779F0_PD_A1E0D0C0 0 +#define R8A779F0_PD_A1E0D0C1 1 +#define R8A779F0_PD_A1E0D1C0 2 +#define R8A779F0_PD_A1E0D1C1 3 +#define R8A779F0_PD_A1E1D0C0 4 +#define R8A779F0_PD_A1E1D0C1 5 +#define R8A779F0_PD_A1E1D1C0 6 +#define R8A779F0_PD_A1E1D1C1 7 +#define R8A779F0_PD_A2E0D0 16 +#define R8A779F0_PD_A2E0D1 17 +#define R8A779F0_PD_A2E1D0 18 +#define R8A779F0_PD_A2E1D1 19 +#define R8A779F0_PD_A3E0 20 +#define R8A779F0_PD_A3E1 21 + +/* Always-on power area */ +#define R8A779F0_PD_ALWAYS_ON 22 + +#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__*/ -- 2.25.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH 05/16] dt-bindings: power: Add r8a779f0 SYSC power domain definitions 2021-11-16 7:41 ` [PATCH 05/16] dt-bindings: power: Add r8a779f0 SYSC power domain definitions Yoshihiro Shimoda @ 2021-11-18 18:42 ` Geert Uytterhoeven 2021-11-19 2:16 ` Yoshihiro Shimoda 0 siblings, 1 reply; 47+ messages in thread From: Geert Uytterhoeven @ 2021-11-18 18:42 UTC (permalink / raw) To: Yoshihiro Shimoda Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS Hi Shimoda-san, On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > Add power domain indices for R-Car S4-8 (r8a779f0). > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Thanks for your patch! > --- /dev/null > +++ b/include/dt-bindings/power/r8a779f0-sysc.h > @@ -0,0 +1,30 @@ > +/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ > +/* > + * Copyright (C) 2021 Renesas Electronics Corp. > + */ > +#ifndef __DT_BINDINGS_POWER_R8A779F0_SYSC_H__ > +#define __DT_BINDINGS_POWER_R8A779F0_SYSC_H__ > + > +/* > + * These power domain indices match the Power Domain Register Numbers (PDR) > + */ > + > +#define R8A779F0_PD_A1E0D0C0 0 > +#define R8A779F0_PD_A1E0D0C1 1 > +#define R8A779F0_PD_A1E0D1C0 2 > +#define R8A779F0_PD_A1E0D1C1 3 > +#define R8A779F0_PD_A1E1D0C0 4 > +#define R8A779F0_PD_A1E1D0C1 5 > +#define R8A779F0_PD_A1E1D1C0 6 > +#define R8A779F0_PD_A1E1D1C1 7 > +#define R8A779F0_PD_A2E0D0 16 > +#define R8A779F0_PD_A2E0D1 17 > +#define R8A779F0_PD_A2E1D0 18 > +#define R8A779F0_PD_A2E1D1 19 > +#define R8A779F0_PD_A3E0 20 > +#define R8A779F0_PD_A3E1 21 The above are fine. > + > +/* Always-on power area */ > +#define R8A779F0_PD_ALWAYS_ON 22 This should be 64 (i.e. beyond the range supported by the hardware block). > + > +#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__*/ Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 47+ messages in thread
* RE: [PATCH 05/16] dt-bindings: power: Add r8a779f0 SYSC power domain definitions 2021-11-18 18:42 ` Geert Uytterhoeven @ 2021-11-19 2:16 ` Yoshihiro Shimoda 0 siblings, 0 replies; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-11-19 2:16 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS Hi Geert-san, Thank you for your review! > From: Geert Uytterhoeven, Sent: Friday, November 19, 2021 3:42 AM > > On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda > <yoshihiro.shimoda.uh@renesas.com> wrote: > > Add power domain indices for R-Car S4-8 (r8a779f0). > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > > Thanks for your patch! > > > --- /dev/null > > +++ b/include/dt-bindings/power/r8a779f0-sysc.h > > @@ -0,0 +1,30 @@ <snip> > > + > > +/* Always-on power area */ > > +#define R8A779F0_PD_ALWAYS_ON 22 > > This should be 64 (i.e. beyond the range supported by the hardware > block). I got it. I'll fix it in v2. Best regards, Yoshihiro Shimoda ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH 06/16] dt-bindings: clock: renesas,cpg-mssr: Document r8a779f0 2021-11-16 7:41 [PATCH 00/16] treewide: Initial support for R-Car S4-8 Yoshihiro Shimoda ` (4 preceding siblings ...) 2021-11-16 7:41 ` [PATCH 05/16] dt-bindings: power: Add r8a779f0 SYSC power domain definitions Yoshihiro Shimoda @ 2021-11-16 7:41 ` Yoshihiro Shimoda 2021-11-18 18:43 ` Geert Uytterhoeven 2021-11-16 7:41 ` [PATCH 07/16] dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions Yoshihiro Shimoda ` (9 subsequent siblings) 15 siblings, 1 reply; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-11-16 7:41 UTC (permalink / raw) To: geert+renesas, magnus.damm, robh+dt, gregkh, jirislaby Cc: linux-renesas-soc, devicetree, linux-serial, Yoshihiro Shimoda Add binding documentation for the R-Car S4-8 (R8A779F0) Clock Pulse Generator. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml index 9b414fbde6d7..e0b86214f0f5 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml @@ -48,6 +48,7 @@ properties: - renesas,r8a77990-cpg-mssr # R-Car E3 - renesas,r8a77995-cpg-mssr # R-Car D3 - renesas,r8a779a0-cpg-mssr # R-Car V3U + - renesas,r8a779f0-cpg-mssr # R-Car S4-8 reg: maxItems: 1 -- 2.25.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH 06/16] dt-bindings: clock: renesas,cpg-mssr: Document r8a779f0 2021-11-16 7:41 ` [PATCH 06/16] dt-bindings: clock: renesas,cpg-mssr: Document r8a779f0 Yoshihiro Shimoda @ 2021-11-18 18:43 ` Geert Uytterhoeven 0 siblings, 0 replies; 47+ messages in thread From: Geert Uytterhoeven @ 2021-11-18 18:43 UTC (permalink / raw) To: Yoshihiro Shimoda Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > Add binding documentation for the R-Car S4-8 (R8A779F0) Clock Pulse > Generator. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk-for-v5.17. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH 07/16] dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions 2021-11-16 7:41 [PATCH 00/16] treewide: Initial support for R-Car S4-8 Yoshihiro Shimoda ` (5 preceding siblings ...) 2021-11-16 7:41 ` [PATCH 06/16] dt-bindings: clock: renesas,cpg-mssr: Document r8a779f0 Yoshihiro Shimoda @ 2021-11-16 7:41 ` Yoshihiro Shimoda 2021-11-18 18:53 ` Geert Uytterhoeven 2021-11-16 7:41 ` [PATCH 08/16] dt-bindings: serial: renesas,scif: Document r8a779f0 bindings Yoshihiro Shimoda ` (8 subsequent siblings) 15 siblings, 1 reply; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-11-16 7:41 UTC (permalink / raw) To: geert+renesas, magnus.damm, robh+dt, gregkh, jirislaby Cc: linux-renesas-soc, devicetree, linux-serial, Yoshihiro Shimoda Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car S4-8 (R8A779F0) SoC. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- include/dt-bindings/clock/r8a779f0-cpg-mssr.h | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 include/dt-bindings/clock/r8a779f0-cpg-mssr.h diff --git a/include/dt-bindings/clock/r8a779f0-cpg-mssr.h b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h new file mode 100644 index 000000000000..cb0d4593a7bd --- /dev/null +++ b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ +/* + * Copyright (C) 2021 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a779f0 CPG Core Clocks */ + +#define R8A779F0_CLK_ZX 0 +#define R8A779F0_CLK_ZS 1 +#define R8A779F0_CLK_ZT 2 +#define R8A779F0_CLK_ZTR 3 +#define R8A779F0_CLK_S0D2 4 +#define R8A779F0_CLK_S0D3 5 +#define R8A779F0_CLK_S0D4 6 +#define R8A779F0_CLK_S0D2_MM 7 +#define R8A779F0_CLK_S0D3_MM 8 +#define R8A779F0_CLK_S0D4_MM 9 +#define R8A779F0_CLK_S0D2_RT 10 +#define R8A779F0_CLK_S0D3_RT 11 +#define R8A779F0_CLK_S0D4_RT 12 +#define R8A779F0_CLK_S0D6_RT 13 +#define R8A779F0_CLK_S0D3_PER 14 +#define R8A779F0_CLK_S0D6_PER 15 +#define R8A779F0_CLK_S0D12_PER 16 +#define R8A779F0_CLK_S0D24_PER 17 +#define R8A779F0_CLK_S0D2_HSC 18 +#define R8A779F0_CLK_S0D3_HSC 19 +#define R8A779F0_CLK_S0D4_HSC 20 +#define R8A779F0_CLK_S0D6_HSC 21 +#define R8A779F0_CLK_S0D12_HSC 22 +#define R8A779F0_CLK_S0D2_CC 23 +#define R8A779F0_CLK_CL 24 +#define R8A779F0_CLK_CL16M 25 +#define R8A779F0_CLK_CL16M_MM 26 +#define R8A779F0_CLK_CL16M_RT 27 +#define R8A779F0_CLK_CL16M_PER 28 +#define R8A779F0_CLK_CL16M_HSC 29 +#define R8A779F0_CLK_Z0 30 +#define R8A779F0_CLK_Z1 31 +#define R8A779F0_CLK_ZB3 32 +#define R8A779F0_CLK_ZB3D2 33 +#define R8A779F0_CLK_ZB3D4 34 +#define R8A779F0_CLK_SDSRC 35 +#define R8A779F0_CLK_SD0H 36 +#define R8A779F0_CLK_SD0 37 +#define R8A779F0_CLK_RPC 38 +#define R8A779F0_CLK_RPCD2 39 +#define R8A779F0_CLK_MSO 40 +#define R8A779F0_CLK_SASYNCRT 41 +#define R8A779F0_CLK_SASYNCPERD1 42 +#define R8A779F0_CLK_SASYNCPERD2 43 +#define R8A779F0_CLK_SASYNCPERD4 44 +#define R8A779F0_CLK_DBGSOC_HSC 45 +#define R8A779F0_CLK_RSW2 46 +#define R8A779F0_CLK_OSC 47 +#define R8A779F0_CLK_ZR 48 +#define R8A779F0_CLK_CPEX 49 +#define R8A779F0_CLK_CBFUSA 50 +#define R8A779F0_CLK_R 51 + +#endif /* __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ */ -- 2.25.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH 07/16] dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions 2021-11-16 7:41 ` [PATCH 07/16] dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions Yoshihiro Shimoda @ 2021-11-18 18:53 ` Geert Uytterhoeven 2021-11-19 2:21 ` Yoshihiro Shimoda 0 siblings, 1 reply; 47+ messages in thread From: Geert Uytterhoeven @ 2021-11-18 18:53 UTC (permalink / raw) To: Yoshihiro Shimoda Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS Hi Shimoda-san, On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > Add all Clock Pulse Generator Core Clock Outputs for the Renesas > R-Car S4-8 (R8A779F0) SoC. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Thanks for your patch! > --- /dev/null > +++ b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h > @@ -0,0 +1,65 @@ > +/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ > +/* > + * Copyright (C) 2021 Renesas Electronics Corp. > + */ > +#ifndef __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ > +#define __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ > + > +#include <dt-bindings/clock/renesas-cpg-mssr.h> > + > +/* r8a779f0 CPG Core Clocks */ > + > +#define R8A779F0_CLK_ZX 0 > +#define R8A779F0_CLK_ZS 1 > +#define R8A779F0_CLK_ZT 2 > +#define R8A779F0_CLK_ZTR 3 > +#define R8A779F0_CLK_S0D2 4 > +#define R8A779F0_CLK_S0D3 5 > +#define R8A779F0_CLK_S0D4 6 > +#define R8A779F0_CLK_S0D2_MM 7 > +#define R8A779F0_CLK_S0D3_MM 8 > +#define R8A779F0_CLK_S0D4_MM 9 > +#define R8A779F0_CLK_S0D2_RT 10 > +#define R8A779F0_CLK_S0D3_RT 11 > +#define R8A779F0_CLK_S0D4_RT 12 > +#define R8A779F0_CLK_S0D6_RT 13 > +#define R8A779F0_CLK_S0D3_PER 14 > +#define R8A779F0_CLK_S0D6_PER 15 > +#define R8A779F0_CLK_S0D12_PER 16 > +#define R8A779F0_CLK_S0D24_PER 17 > +#define R8A779F0_CLK_S0D2_HSC 18 > +#define R8A779F0_CLK_S0D3_HSC 19 > +#define R8A779F0_CLK_S0D4_HSC 20 > +#define R8A779F0_CLK_S0D6_HSC 21 > +#define R8A779F0_CLK_S0D12_HSC 22 > +#define R8A779F0_CLK_S0D2_CC 23 > +#define R8A779F0_CLK_CL 24 > +#define R8A779F0_CLK_CL16M 25 > +#define R8A779F0_CLK_CL16M_MM 26 > +#define R8A779F0_CLK_CL16M_RT 27 > +#define R8A779F0_CLK_CL16M_PER 28 > +#define R8A779F0_CLK_CL16M_HSC 29 > +#define R8A779F0_CLK_Z0 30 > +#define R8A779F0_CLK_Z1 31 > +#define R8A779F0_CLK_ZB3 32 > +#define R8A779F0_CLK_ZB3D2 33 > +#define R8A779F0_CLK_ZB3D4 34 > +#define R8A779F0_CLK_SDSRC 35 I think we can leave out SDSRC, like on the other SoCs, as it's an internal clock. > +#define R8A779F0_CLK_SD0H 36 > +#define R8A779F0_CLK_SD0 37 > +#define R8A779F0_CLK_RPC 38 > +#define R8A779F0_CLK_RPCD2 39 > +#define R8A779F0_CLK_MSO 40 > +#define R8A779F0_CLK_SASYNCRT 41 > +#define R8A779F0_CLK_SASYNCPERD1 42 > +#define R8A779F0_CLK_SASYNCPERD2 43 > +#define R8A779F0_CLK_SASYNCPERD4 44 > +#define R8A779F0_CLK_DBGSOC_HSC 45 > +#define R8A779F0_CLK_RSW2 46 > +#define R8A779F0_CLK_OSC 47 > +#define R8A779F0_CLK_ZR 48 > +#define R8A779F0_CLK_CPEX 49 > +#define R8A779F0_CLK_CBFUSA 50 > +#define R8A779F0_CLK_R 51 The rest looks good to me. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 47+ messages in thread
* RE: [PATCH 07/16] dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions 2021-11-18 18:53 ` Geert Uytterhoeven @ 2021-11-19 2:21 ` Yoshihiro Shimoda 0 siblings, 0 replies; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-11-19 2:21 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS Hi Geert-san, Thank you for your review! > From: Geert Uytterhoeven, Sent: Friday, November 19, 2021 3:53 AM > > Hi Shimoda-san, > > On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda > <yoshihiro.shimoda.uh@renesas.com> wrote: > > Add all Clock Pulse Generator Core Clock Outputs for the Renesas > > R-Car S4-8 (R8A779F0) SoC. > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > > Thanks for your patch! > > > --- /dev/null > > +++ b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h > > @@ -0,0 +1,65 @@ <snip> > > +#define R8A779F0_CLK_SDSRC 35 > > I think we can leave out SDSRC, like on the other SoCs, as it's an > internal clock. I got it. I'll fix it in v2. Best regards, Yoshihiro Shimoda ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH 08/16] dt-bindings: serial: renesas,scif: Document r8a779f0 bindings 2021-11-16 7:41 [PATCH 00/16] treewide: Initial support for R-Car S4-8 Yoshihiro Shimoda ` (6 preceding siblings ...) 2021-11-16 7:41 ` [PATCH 07/16] dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions Yoshihiro Shimoda @ 2021-11-16 7:41 ` Yoshihiro Shimoda 2021-11-18 18:56 ` Geert Uytterhoeven 2021-11-16 7:41 ` [PATCH 09/16] soc: renesas: Identify R-Car S4-8 Yoshihiro Shimoda ` (7 subsequent siblings) 15 siblings, 1 reply; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-11-16 7:41 UTC (permalink / raw) To: geert+renesas, magnus.damm, robh+dt, gregkh, jirislaby Cc: linux-renesas-soc, devicetree, linux-serial, Yoshihiro Shimoda R-Car S4-8 (R8A779F0) SoC has the R-Car Gen4 compatible SCIF ports, so document the SoC specific bindings. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- Documentation/devicetree/bindings/serial/renesas,scif.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml index 6b8731f7f2fb..14602b720cc0 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml @@ -64,6 +64,12 @@ properties: - const: renesas,rcar-gen3-scif # R-Car Gen3 and RZ/G2 - const: renesas,scif # generic SCIF compatible UART + - items: + - enum: + - renesas,scif-r8a779f0 # R-Car S4-8 + - const: renesas,rcar-gen4-scif # R-Car Gen4 + - const: renesas,scif # generic SCIF compatible UART + - items: - enum: - renesas,scif-r9a07g044 # RZ/G2{L,LC} -- 2.25.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH 08/16] dt-bindings: serial: renesas,scif: Document r8a779f0 bindings 2021-11-16 7:41 ` [PATCH 08/16] dt-bindings: serial: renesas,scif: Document r8a779f0 bindings Yoshihiro Shimoda @ 2021-11-18 18:56 ` Geert Uytterhoeven 2021-11-19 2:24 ` Yoshihiro Shimoda 0 siblings, 1 reply; 47+ messages in thread From: Geert Uytterhoeven @ 2021-11-18 18:56 UTC (permalink / raw) To: Yoshihiro Shimoda Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS Hi Shimoda-san, On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > R-Car S4-8 (R8A779F0) SoC has the R-Car Gen4 compatible SCIF ports, > so document the SoC specific bindings. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Thanks for your patch! > --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml > +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml > @@ -64,6 +64,12 @@ properties: > - const: renesas,rcar-gen3-scif # R-Car Gen3 and RZ/G2 > - const: renesas,scif # generic SCIF compatible UART > > + - items: > + - enum: > + - renesas,scif-r8a779f0 # R-Car S4-8 > + - const: renesas,rcar-gen4-scif # R-Car Gen4 > + - const: renesas,scif # generic SCIF compatible UART > + OK. > - items: > - enum: > - renesas,scif-r9a07g044 # RZ/G2{L,LC} Please add "renesas,rcar-gen4-scif" to the block that requires resets. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 47+ messages in thread
* RE: [PATCH 08/16] dt-bindings: serial: renesas,scif: Document r8a779f0 bindings 2021-11-18 18:56 ` Geert Uytterhoeven @ 2021-11-19 2:24 ` Yoshihiro Shimoda 0 siblings, 0 replies; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-11-19 2:24 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS Hi Geert-san, Thank you for your review! > From: Geert Uytterhoeven, Sent: Friday, November 19, 2021 3:56 AM > > Hi Shimoda-san, > > On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda > <yoshihiro.shimoda.uh@renesas.com> wrote: > > R-Car S4-8 (R8A779F0) SoC has the R-Car Gen4 compatible SCIF ports, > > so document the SoC specific bindings. > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > > Thanks for your patch! > > > --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml > > +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml <snip> > > - items: > > - enum: > > - renesas,scif-r9a07g044 # RZ/G2{L,LC} > > Please add "renesas,rcar-gen4-scif" to the block that requires resets. Oops. I got it. I'll add it in v2. Best regards, Yoshihiro Shimoda ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH 09/16] soc: renesas: Identify R-Car S4-8 2021-11-16 7:41 [PATCH 00/16] treewide: Initial support for R-Car S4-8 Yoshihiro Shimoda ` (7 preceding siblings ...) 2021-11-16 7:41 ` [PATCH 08/16] dt-bindings: serial: renesas,scif: Document r8a779f0 bindings Yoshihiro Shimoda @ 2021-11-16 7:41 ` Yoshihiro Shimoda 2021-11-18 19:03 ` Geert Uytterhoeven 2021-11-18 19:04 ` Geert Uytterhoeven 2021-11-16 7:41 ` [PATCH 10/16] soc: renesas: r8a779f0-sysc: Add r8a779f0 support Yoshihiro Shimoda ` (6 subsequent siblings) 15 siblings, 2 replies; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-11-16 7:41 UTC (permalink / raw) To: geert+renesas, magnus.damm, robh+dt, gregkh, jirislaby Cc: linux-renesas-soc, devicetree, linux-serial, Yoshihiro Shimoda Add support for identifying the R-Car S4-8 (R8A779F0) SoC. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- drivers/soc/renesas/Kconfig | 7 +++++++ drivers/soc/renesas/renesas-soc.c | 13 +++++++++++++ 2 files changed, 20 insertions(+) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index ce16ef5c939c..9915b953e9a0 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -256,6 +256,13 @@ config ARCH_R8A779A0 help This enables support for the Renesas R-Car V3U SoC. +config ARCH_R8A779F0 + bool "ARM64 Platform support for R-Car S4-8" + select ARCH_RCAR_GEN3 + select SYSC_R8A779F0 + help + This enables support for the Renesas R-Car S4-8 SoC. + config ARCH_R8A774C0 bool "ARM64 Platform support for RZ/G2E" select ARCH_RCAR_GEN3 diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index 7961b0be1850..857a42a82747 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -33,6 +33,11 @@ static const struct renesas_family fam_rcar_gen3 __initconst __maybe_unused = { .reg = 0xfff00044, /* PRR (Product Register) */ }; +static const struct renesas_family fam_rcar_gen4 __initconst __maybe_unused = { + .name = "R-Car Gen4", + .reg = 0xfff00044, /* PRR (Product Register) */ +}; + static const struct renesas_family fam_rmobile __initconst __maybe_unused = { .name = "R-Mobile", .reg = 0xe600101c, /* CCCR (Common Chip Code Register) */ @@ -214,6 +219,11 @@ static const struct renesas_soc soc_rcar_v3u __initconst __maybe_unused = { .id = 0x59, }; +static const struct renesas_soc soc_rcar_s4 __initconst __maybe_unused = { + .family = &fam_rcar_gen4, + .id = 0x5a, +}; + static const struct renesas_soc soc_shmobile_ag5 __initconst __maybe_unused = { .family = &fam_shmobile, .id = 0x37, @@ -319,6 +329,9 @@ static const struct of_device_id renesas_socs[] __initconst = { #ifdef CONFIG_ARCH_R8A779A0 { .compatible = "renesas,r8a779a0", .data = &soc_rcar_v3u }, #endif +#ifdef CONFIG_ARCH_R8A779F0 + { .compatible = "renesas,r8a779f0", .data = &soc_rcar_s4 }, +#endif #if defined(CONFIG_ARCH_R9A07G044) { .compatible = "renesas,r9a07g044", .data = &soc_rz_g2l }, #endif -- 2.25.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH 09/16] soc: renesas: Identify R-Car S4-8 2021-11-16 7:41 ` [PATCH 09/16] soc: renesas: Identify R-Car S4-8 Yoshihiro Shimoda @ 2021-11-18 19:03 ` Geert Uytterhoeven 2021-11-19 2:27 ` Yoshihiro Shimoda 2021-11-18 19:04 ` Geert Uytterhoeven 1 sibling, 1 reply; 47+ messages in thread From: Geert Uytterhoeven @ 2021-11-18 19:03 UTC (permalink / raw) To: Yoshihiro Shimoda Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS Hi Shimoda-san, On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > Add support for identifying the R-Car S4-8 (R8A779F0) SoC. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Thanks for your patch! > --- a/drivers/soc/renesas/Kconfig > +++ b/drivers/soc/renesas/Kconfig > @@ -256,6 +256,13 @@ config ARCH_R8A779A0 > help > This enables support for the Renesas R-Car V3U SoC. > > +config ARCH_R8A779F0 > + bool "ARM64 Platform support for R-Car S4-8" > + select ARCH_RCAR_GEN3 > + select SYSC_R8A779F0 > + help > + This enables support for the Renesas R-Car S4-8 SoC. > + Please keep sort order (alphabetical, not by part number). > config ARCH_R8A774C0 > bool "ARM64 Platform support for RZ/G2E" > select ARCH_RCAR_GEN3 > diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c > index 7961b0be1850..857a42a82747 100644 > --- a/drivers/soc/renesas/renesas-soc.c > +++ b/drivers/soc/renesas/renesas-soc.c > @@ -33,6 +33,11 @@ static const struct renesas_family fam_rcar_gen3 __initconst __maybe_unused = { > .reg = 0xfff00044, /* PRR (Product Register) */ > }; > > +static const struct renesas_family fam_rcar_gen4 __initconst __maybe_unused = { > + .name = "R-Car Gen4", > + .reg = 0xfff00044, /* PRR (Product Register) */ Please drop ".reg", which is only meant for existing SoCs. For new SoCs, we rely on the presence of a "renesas,prr" node in DT. > +}; The rest looks good to me. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 47+ messages in thread
* RE: [PATCH 09/16] soc: renesas: Identify R-Car S4-8 2021-11-18 19:03 ` Geert Uytterhoeven @ 2021-11-19 2:27 ` Yoshihiro Shimoda 0 siblings, 0 replies; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-11-19 2:27 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS Hi Geert-san, Thank you for your review1 > From: Geert Uytterhoeven, Sent: Friday, November 19, 2021 4:04 AM > > Hi Shimoda-san, > > On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda > <yoshihiro.shimoda.uh@renesas.com> wrote: > > Add support for identifying the R-Car S4-8 (R8A779F0) SoC. > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > > Thanks for your patch! > > > --- a/drivers/soc/renesas/Kconfig > > +++ b/drivers/soc/renesas/Kconfig > > @@ -256,6 +256,13 @@ config ARCH_R8A779A0 > > help > > This enables support for the Renesas R-Car V3U SoC. > > > > +config ARCH_R8A779F0 > > + bool "ARM64 Platform support for R-Car S4-8" > > + select ARCH_RCAR_GEN3 > > + select SYSC_R8A779F0 > > + help > > + This enables support for the Renesas R-Car S4-8 SoC. > > + > > Please keep sort order (alphabetical, not by part number). I'm sorry. I didn't realized that. I'll fix it in v2. > > config ARCH_R8A774C0 > > bool "ARM64 Platform support for RZ/G2E" > > select ARCH_RCAR_GEN3 > > diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c > > index 7961b0be1850..857a42a82747 100644 > > --- a/drivers/soc/renesas/renesas-soc.c > > +++ b/drivers/soc/renesas/renesas-soc.c > > @@ -33,6 +33,11 @@ static const struct renesas_family fam_rcar_gen3 __initconst __maybe_unused = { > > .reg = 0xfff00044, /* PRR (Product Register) */ > > }; > > > > +static const struct renesas_family fam_rcar_gen4 __initconst __maybe_unused = { > > + .name = "R-Car Gen4", > > + .reg = 0xfff00044, /* PRR (Product Register) */ > > Please drop ".reg", which is only meant for existing SoCs. > For new SoCs, we rely on the presence of a "renesas,prr" node in DT. I got it. I'll fix it in v2. Best regards, Yoshihiro Shimoda ^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 09/16] soc: renesas: Identify R-Car S4-8 2021-11-16 7:41 ` [PATCH 09/16] soc: renesas: Identify R-Car S4-8 Yoshihiro Shimoda 2021-11-18 19:03 ` Geert Uytterhoeven @ 2021-11-18 19:04 ` Geert Uytterhoeven 2021-11-19 2:32 ` Yoshihiro Shimoda 1 sibling, 1 reply; 47+ messages in thread From: Geert Uytterhoeven @ 2021-11-18 19:04 UTC (permalink / raw) To: Yoshihiro Shimoda Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS Hi Shimoda-san, On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > Add support for identifying the R-Car S4-8 (R8A779F0) SoC. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Thanks for your patch! > --- a/drivers/soc/renesas/Kconfig > +++ b/drivers/soc/renesas/Kconfig > @@ -256,6 +256,13 @@ config ARCH_R8A779A0 > help > This enables support for the Renesas R-Car V3U SoC. > > +config ARCH_R8A779F0 > + bool "ARM64 Platform support for R-Car S4-8" > + select ARCH_RCAR_GEN3 > + select SYSC_R8A779F0 "SYSC_R8A779F0" is only defined in [PATCH 10/16], so you may want to reorder your series. Or I will while applying later ;-) > + help > + This enables support for the Renesas R-Car S4-8 SoC. > + > config ARCH_R8A774C0 > bool "ARM64 Platform support for RZ/G2E" > select ARCH_RCAR_GEN3 > diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c > index 7961b0be1850..857a42a82747 100644 > --- a/drivers/soc/renesas/renesas-soc.c > +++ b/drivers/soc/renesas/renesas-soc.c > @@ -33,6 +33,11 @@ static const struct renesas_family fam_rcar_gen3 __initconst __maybe_unused = { > .reg = 0xfff00044, /* PRR (Product Register) */ > }; > > +static const struct renesas_family fam_rcar_gen4 __initconst __maybe_unused = { > + .name = "R-Car Gen4", > + .reg = 0xfff00044, /* PRR (Product Register) */ > +}; > + > static const struct renesas_family fam_rmobile __initconst __maybe_unused = { > .name = "R-Mobile", > .reg = 0xe600101c, /* CCCR (Common Chip Code Register) */ > @@ -214,6 +219,11 @@ static const struct renesas_soc soc_rcar_v3u __initconst __maybe_unused = { > .id = 0x59, > }; > > +static const struct renesas_soc soc_rcar_s4 __initconst __maybe_unused = { > + .family = &fam_rcar_gen4, > + .id = 0x5a, > +}; > + > static const struct renesas_soc soc_shmobile_ag5 __initconst __maybe_unused = { > .family = &fam_shmobile, > .id = 0x37, > @@ -319,6 +329,9 @@ static const struct of_device_id renesas_socs[] __initconst = { > #ifdef CONFIG_ARCH_R8A779A0 > { .compatible = "renesas,r8a779a0", .data = &soc_rcar_v3u }, > #endif > +#ifdef CONFIG_ARCH_R8A779F0 > + { .compatible = "renesas,r8a779f0", .data = &soc_rcar_s4 }, > +#endif > #if defined(CONFIG_ARCH_R9A07G044) > { .compatible = "renesas,r9a07g044", .data = &soc_rz_g2l }, > #endif > -- > 2.25.1 > -- Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 47+ messages in thread
* RE: [PATCH 09/16] soc: renesas: Identify R-Car S4-8 2021-11-18 19:04 ` Geert Uytterhoeven @ 2021-11-19 2:32 ` Yoshihiro Shimoda 0 siblings, 0 replies; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-11-19 2:32 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS Hi Geert-san, Thank you for your review! > From: Geert Uytterhoeven, Sent: Friday, November 19, 2021 4:05 AM > > Hi Shimoda-san, > > On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda > <yoshihiro.shimoda.uh@renesas.com> wrote: > > Add support for identifying the R-Car S4-8 (R8A779F0) SoC. > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > > Thanks for your patch! > > > --- a/drivers/soc/renesas/Kconfig > > +++ b/drivers/soc/renesas/Kconfig > > @@ -256,6 +256,13 @@ config ARCH_R8A779A0 > > help > > This enables support for the Renesas R-Car V3U SoC. > > > > +config ARCH_R8A779F0 > > + bool "ARM64 Platform support for R-Car S4-8" > > + select ARCH_RCAR_GEN3 > > + select SYSC_R8A779F0 > > "SYSC_R8A779F0" is only defined in [PATCH 10/16], so you may want to > reorder your series. Or I will while applying later ;-) Oops. Thank you for pointed it out. I'll reorder my series on v2. Best regards, Yoshihiro Shimoda ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH 10/16] soc: renesas: r8a779f0-sysc: Add r8a779f0 support 2021-11-16 7:41 [PATCH 00/16] treewide: Initial support for R-Car S4-8 Yoshihiro Shimoda ` (8 preceding siblings ...) 2021-11-16 7:41 ` [PATCH 09/16] soc: renesas: Identify R-Car S4-8 Yoshihiro Shimoda @ 2021-11-16 7:41 ` Yoshihiro Shimoda 2021-11-23 16:18 ` Geert Uytterhoeven 2021-11-16 7:41 ` [PATCH 11/16] soc: renesas: rcar-rst: Add support for R-Car S4-8 Yoshihiro Shimoda ` (5 subsequent siblings) 15 siblings, 1 reply; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-11-16 7:41 UTC (permalink / raw) To: geert+renesas, magnus.damm, robh+dt, gregkh, jirislaby Cc: linux-renesas-soc, devicetree, linux-serial, Yoshihiro Shimoda Add support for R-Car S4-8 (R8A779F0) SoC power areas and register access. This register specification is similar with R-Car V3U. So, introduces rcar-gen4-sysc.c for both V3U and S4-8. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- drivers/soc/renesas/Kconfig | 3 + drivers/soc/renesas/Makefile | 3 +- drivers/soc/renesas/r8a779a0-sysc.c | 380 +-------------------------- drivers/soc/renesas/r8a779f0-sysc.c | 47 ++++ drivers/soc/renesas/rcar-gen4-sysc.c | 376 ++++++++++++++++++++++++++ drivers/soc/renesas/rcar-gen4-sysc.h | 43 +++ 6 files changed, 474 insertions(+), 378 deletions(-) create mode 100644 drivers/soc/renesas/r8a779f0-sysc.c create mode 100644 drivers/soc/renesas/rcar-gen4-sysc.c create mode 100644 drivers/soc/renesas/rcar-gen4-sysc.h diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 9915b953e9a0..b5919ea08a84 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -359,6 +359,9 @@ config SYSC_R8A77970 config SYSC_R8A779A0 bool "System Controller support for R-Car V3U" if COMPILE_TEST +config SYSC_R8A779F0 + bool "System Controller support for R-Car S4-8" if COMPILE_TEST + config SYSC_RMOBILE bool "System Controller support for R-Mobile" if COMPILE_TEST diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index 9b29bed2a597..f6c5f8c3818c 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -25,11 +25,12 @@ obj-$(CONFIG_SYSC_R8A77980) += r8a77980-sysc.o obj-$(CONFIG_SYSC_R8A77990) += r8a77990-sysc.o obj-$(CONFIG_SYSC_R8A77995) += r8a77995-sysc.o obj-$(CONFIG_SYSC_R8A779A0) += r8a779a0-sysc.o +obj-$(CONFIG_SYSC_R8A779F0) += r8a779f0-sysc.o ifdef CONFIG_SMP obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o endif # Family obj-$(CONFIG_RST_RCAR) += rcar-rst.o -obj-$(CONFIG_SYSC_RCAR) += rcar-sysc.o +obj-$(CONFIG_SYSC_RCAR) += rcar-sysc.o rcar-gen4-sysc.o obj-$(CONFIG_SYSC_RMOBILE) += rmobile-sysc.o diff --git a/drivers/soc/renesas/r8a779a0-sysc.c b/drivers/soc/renesas/r8a779a0-sysc.c index 7410b9fa9846..fdfc857df334 100644 --- a/drivers/soc/renesas/r8a779a0-sysc.c +++ b/drivers/soc/renesas/r8a779a0-sysc.c @@ -21,35 +21,9 @@ #include <dt-bindings/power/r8a779a0-sysc.h> -/* - * Power Domain flags - */ -#define PD_CPU BIT(0) /* Area contains main CPU core */ -#define PD_SCU BIT(1) /* Area contains SCU and L2 cache */ -#define PD_NO_CR BIT(2) /* Area lacks PWR{ON,OFF}CR registers */ - -#define PD_CPU_NOCR PD_CPU | PD_NO_CR /* CPU area lacks CR */ -#define PD_ALWAYS_ON PD_NO_CR /* Always-on area */ - -/* - * Description of a Power Area - */ -struct r8a779a0_sysc_area { - const char *name; - u8 pdr; /* PDRn */ - int parent; /* -1 if none */ - unsigned int flags; /* See PD_* */ -}; - -/* - * SoC-specific Power Area Description - */ -struct r8a779a0_sysc_info { - const struct r8a779a0_sysc_area *areas; - unsigned int num_areas; -}; +#include "rcar-gen4-sysc.h" -static struct r8a779a0_sysc_area r8a779a0_areas[] __initdata = { +static struct rcar_gen4_sysc_area r8a779a0_areas[] __initdata = { { "always-on", R8A779A0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, { "a3e0", R8A779A0_PD_A3E0, R8A779A0_PD_ALWAYS_ON, PD_SCU }, { "a3e1", R8A779A0_PD_A3E1, R8A779A0_PD_ALWAYS_ON, PD_SCU }, @@ -96,355 +70,7 @@ static struct r8a779a0_sysc_area r8a779a0_areas[] __initdata = { { "a1dsp1", R8A779A0_PD_A1DSP1, R8A779A0_PD_A2CN1 }, }; -static const struct r8a779a0_sysc_info r8a779a0_sysc_info __initconst = { +const struct rcar_gen4_sysc_info r8a779a0_sysc_info __initconst = { .areas = r8a779a0_areas, .num_areas = ARRAY_SIZE(r8a779a0_areas), }; - -/* SYSC Common */ -#define SYSCSR 0x000 /* SYSC Status Register */ -#define SYSCPONSR(x) (0x800 + ((x) * 0x4)) /* Power-ON Status Register 0 */ -#define SYSCPOFFSR(x) (0x808 + ((x) * 0x4)) /* Power-OFF Status Register */ -#define SYSCISCR(x) (0x810 + ((x) * 0x4)) /* Interrupt Status/Clear Register */ -#define SYSCIER(x) (0x820 + ((x) * 0x4)) /* Interrupt Enable Register */ -#define SYSCIMR(x) (0x830 + ((x) * 0x4)) /* Interrupt Mask Register */ - -/* Power Domain Registers */ -#define PDRSR(n) (0x1000 + ((n) * 0x40)) -#define PDRONCR(n) (0x1004 + ((n) * 0x40)) -#define PDROFFCR(n) (0x1008 + ((n) * 0x40)) -#define PDRESR(n) (0x100C + ((n) * 0x40)) - -/* PWRON/PWROFF */ -#define PWRON_PWROFF BIT(0) /* Power-ON/OFF request */ - -/* PDRESR */ -#define PDRESR_ERR BIT(0) - -/* PDRSR */ -#define PDRSR_OFF BIT(0) /* Power-OFF state */ -#define PDRSR_ON BIT(4) /* Power-ON state */ -#define PDRSR_OFF_STATE BIT(8) /* Processing Power-OFF sequence */ -#define PDRSR_ON_STATE BIT(12) /* Processing Power-ON sequence */ - -#define SYSCSR_BUSY GENMASK(1, 0) /* All bit sets is not busy */ - -#define SYSCSR_TIMEOUT 10000 -#define SYSCSR_DELAY_US 10 - -#define PDRESR_RETRIES 1000 -#define PDRESR_DELAY_US 10 - -#define SYSCISR_TIMEOUT 10000 -#define SYSCISR_DELAY_US 10 - -#define NUM_DOMAINS_EACH_REG BITS_PER_TYPE(u32) - -static void __iomem *r8a779a0_sysc_base; -static DEFINE_SPINLOCK(r8a779a0_sysc_lock); /* SMP CPUs + I/O devices */ - -static int r8a779a0_sysc_pwr_on_off(u8 pdr, bool on) -{ - unsigned int reg_offs; - u32 val; - int ret; - - if (on) - reg_offs = PDRONCR(pdr); - else - reg_offs = PDROFFCR(pdr); - - /* Wait until SYSC is ready to accept a power request */ - ret = readl_poll_timeout_atomic(r8a779a0_sysc_base + SYSCSR, val, - (val & SYSCSR_BUSY) == SYSCSR_BUSY, - SYSCSR_DELAY_US, SYSCSR_TIMEOUT); - if (ret < 0) - return -EAGAIN; - - /* Submit power shutoff or power resume request */ - iowrite32(PWRON_PWROFF, r8a779a0_sysc_base + reg_offs); - - return 0; -} - -static int clear_irq_flags(unsigned int reg_idx, unsigned int isr_mask) -{ - u32 val; - int ret; - - iowrite32(isr_mask, r8a779a0_sysc_base + SYSCISCR(reg_idx)); - - ret = readl_poll_timeout_atomic(r8a779a0_sysc_base + SYSCISCR(reg_idx), - val, !(val & isr_mask), - SYSCISR_DELAY_US, SYSCISR_TIMEOUT); - if (ret < 0) { - pr_err("\n %s : Can not clear IRQ flags in SYSCISCR", __func__); - return -EIO; - } - - return 0; -} - -static int r8a779a0_sysc_power(u8 pdr, bool on) -{ - unsigned int isr_mask; - unsigned int reg_idx, bit_idx; - unsigned int status; - unsigned long flags; - int ret = 0; - u32 val; - int k; - - spin_lock_irqsave(&r8a779a0_sysc_lock, flags); - - reg_idx = pdr / NUM_DOMAINS_EACH_REG; - bit_idx = pdr % NUM_DOMAINS_EACH_REG; - - isr_mask = BIT(bit_idx); - - /* - * The interrupt source needs to be enabled, but masked, to prevent the - * CPU from receiving it. - */ - iowrite32(ioread32(r8a779a0_sysc_base + SYSCIER(reg_idx)) | isr_mask, - r8a779a0_sysc_base + SYSCIER(reg_idx)); - iowrite32(ioread32(r8a779a0_sysc_base + SYSCIMR(reg_idx)) | isr_mask, - r8a779a0_sysc_base + SYSCIMR(reg_idx)); - - ret = clear_irq_flags(reg_idx, isr_mask); - if (ret) - goto out; - - /* Submit power shutoff or resume request until it was accepted */ - for (k = 0; k < PDRESR_RETRIES; k++) { - ret = r8a779a0_sysc_pwr_on_off(pdr, on); - if (ret) - goto out; - - status = ioread32(r8a779a0_sysc_base + PDRESR(pdr)); - if (!(status & PDRESR_ERR)) - break; - - udelay(PDRESR_DELAY_US); - } - - if (k == PDRESR_RETRIES) { - ret = -EIO; - goto out; - } - - /* Wait until the power shutoff or resume request has completed * */ - ret = readl_poll_timeout_atomic(r8a779a0_sysc_base + SYSCISCR(reg_idx), - val, (val & isr_mask), - SYSCISR_DELAY_US, SYSCISR_TIMEOUT); - if (ret < 0) { - ret = -EIO; - goto out; - } - - /* Clear interrupt flags */ - ret = clear_irq_flags(reg_idx, isr_mask); - if (ret) - goto out; - - out: - spin_unlock_irqrestore(&r8a779a0_sysc_lock, flags); - - pr_debug("sysc power %s domain %d: %08x -> %d\n", on ? "on" : "off", - pdr, ioread32(r8a779a0_sysc_base + SYSCISCR(reg_idx)), ret); - return ret; -} - -static bool r8a779a0_sysc_power_is_off(u8 pdr) -{ - unsigned int st; - - st = ioread32(r8a779a0_sysc_base + PDRSR(pdr)); - - if (st & PDRSR_OFF) - return true; - - return false; -} - -struct r8a779a0_sysc_pd { - struct generic_pm_domain genpd; - u8 pdr; - unsigned int flags; - char name[]; -}; - -static inline struct r8a779a0_sysc_pd *to_r8a779a0_pd(struct generic_pm_domain *d) -{ - return container_of(d, struct r8a779a0_sysc_pd, genpd); -} - -static int r8a779a0_sysc_pd_power_off(struct generic_pm_domain *genpd) -{ - struct r8a779a0_sysc_pd *pd = to_r8a779a0_pd(genpd); - - pr_debug("%s: %s\n", __func__, genpd->name); - return r8a779a0_sysc_power(pd->pdr, false); -} - -static int r8a779a0_sysc_pd_power_on(struct generic_pm_domain *genpd) -{ - struct r8a779a0_sysc_pd *pd = to_r8a779a0_pd(genpd); - - pr_debug("%s: %s\n", __func__, genpd->name); - return r8a779a0_sysc_power(pd->pdr, true); -} - -static int __init r8a779a0_sysc_pd_setup(struct r8a779a0_sysc_pd *pd) -{ - struct generic_pm_domain *genpd = &pd->genpd; - const char *name = pd->genpd.name; - int error; - - if (pd->flags & PD_CPU) { - /* - * This domain contains a CPU core and therefore it should - * only be turned off if the CPU is not in use. - */ - pr_debug("PM domain %s contains %s\n", name, "CPU"); - genpd->flags |= GENPD_FLAG_ALWAYS_ON; - } else if (pd->flags & PD_SCU) { - /* - * This domain contains an SCU and cache-controller, and - * therefore it should only be turned off if the CPU cores are - * not in use. - */ - pr_debug("PM domain %s contains %s\n", name, "SCU"); - genpd->flags |= GENPD_FLAG_ALWAYS_ON; - } else if (pd->flags & PD_NO_CR) { - /* - * This domain cannot be turned off. - */ - genpd->flags |= GENPD_FLAG_ALWAYS_ON; - } - - if (!(pd->flags & (PD_CPU | PD_SCU))) { - /* Enable Clock Domain for I/O devices */ - genpd->flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP; - genpd->attach_dev = cpg_mssr_attach_dev; - genpd->detach_dev = cpg_mssr_detach_dev; - } - - genpd->power_off = r8a779a0_sysc_pd_power_off; - genpd->power_on = r8a779a0_sysc_pd_power_on; - - if (pd->flags & (PD_CPU | PD_NO_CR)) { - /* Skip CPUs (handled by SMP code) and areas without control */ - pr_debug("%s: Not touching %s\n", __func__, genpd->name); - goto finalize; - } - - if (!r8a779a0_sysc_power_is_off(pd->pdr)) { - pr_debug("%s: %s is already powered\n", __func__, genpd->name); - goto finalize; - } - - r8a779a0_sysc_power(pd->pdr, true); - -finalize: - error = pm_genpd_init(genpd, &simple_qos_governor, false); - if (error) - pr_err("Failed to init PM domain %s: %d\n", name, error); - - return error; -} - -static const struct of_device_id r8a779a0_sysc_matches[] __initconst = { - { .compatible = "renesas,r8a779a0-sysc", .data = &r8a779a0_sysc_info }, - { /* sentinel */ } -}; - -struct r8a779a0_pm_domains { - struct genpd_onecell_data onecell_data; - struct generic_pm_domain *domains[R8A779A0_PD_ALWAYS_ON + 1]; -}; - -static struct genpd_onecell_data *r8a779a0_sysc_onecell_data; - -static int __init r8a779a0_sysc_pd_init(void) -{ - const struct r8a779a0_sysc_info *info; - const struct of_device_id *match; - struct r8a779a0_pm_domains *domains; - struct device_node *np; - void __iomem *base; - unsigned int i; - int error; - - np = of_find_matching_node_and_match(NULL, r8a779a0_sysc_matches, &match); - if (!np) - return -ENODEV; - - info = match->data; - - base = of_iomap(np, 0); - if (!base) { - pr_warn("%pOF: Cannot map regs\n", np); - error = -ENOMEM; - goto out_put; - } - - r8a779a0_sysc_base = base; - - domains = kzalloc(sizeof(*domains), GFP_KERNEL); - if (!domains) { - error = -ENOMEM; - goto out_put; - } - - domains->onecell_data.domains = domains->domains; - domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains); - r8a779a0_sysc_onecell_data = &domains->onecell_data; - - for (i = 0; i < info->num_areas; i++) { - const struct r8a779a0_sysc_area *area = &info->areas[i]; - struct r8a779a0_sysc_pd *pd; - size_t n; - - if (!area->name) { - /* Skip NULLified area */ - continue; - } - - n = strlen(area->name) + 1; - pd = kzalloc(sizeof(*pd) + n, GFP_KERNEL); - if (!pd) { - error = -ENOMEM; - goto out_put; - } - - memcpy(pd->name, area->name, n); - pd->genpd.name = pd->name; - pd->pdr = area->pdr; - pd->flags = area->flags; - - error = r8a779a0_sysc_pd_setup(pd); - if (error) - goto out_put; - - domains->domains[area->pdr] = &pd->genpd; - - if (area->parent < 0) - continue; - - error = pm_genpd_add_subdomain(domains->domains[area->parent], - &pd->genpd); - if (error) { - pr_warn("Failed to add PM subdomain %s to parent %u\n", - area->name, area->parent); - goto out_put; - } - } - - error = of_genpd_add_provider_onecell(np, &domains->onecell_data); - -out_put: - of_node_put(np); - return error; -} -early_initcall(r8a779a0_sysc_pd_init); diff --git a/drivers/soc/renesas/r8a779f0-sysc.c b/drivers/soc/renesas/r8a779f0-sysc.c new file mode 100644 index 000000000000..5602aa6bd7ed --- /dev/null +++ b/drivers/soc/renesas/r8a779f0-sysc.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas R-Car S4-8 System Controller + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include <linux/bits.h> +#include <linux/clk/renesas.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/of_address.h> +#include <linux/pm_domain.h> +#include <linux/slab.h> +#include <linux/spinlock.h> +#include <linux/types.h> + +#include <dt-bindings/power/r8a779f0-sysc.h> + +#include "rcar-gen4-sysc.h" + +static struct rcar_gen4_sysc_area r8a779f0_areas[] __initdata = { + { "always-on", R8A779F0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, + { "a3e0", R8A779F0_PD_A3E0, R8A779F0_PD_ALWAYS_ON, PD_SCU }, + { "a3e1", R8A779F0_PD_A3E1, R8A779F0_PD_ALWAYS_ON, PD_SCU }, + { "a2e0d0", R8A779F0_PD_A2E0D0, R8A779F0_PD_A3E0, PD_SCU }, + { "a2e0d1", R8A779F0_PD_A2E0D1, R8A779F0_PD_A3E0, PD_SCU }, + { "a2e1d0", R8A779F0_PD_A2E1D0, R8A779F0_PD_A3E1, PD_SCU }, + { "a2e1d1", R8A779F0_PD_A2E1D1, R8A779F0_PD_A3E1, PD_SCU }, + { "a1e0d0c0", R8A779F0_PD_A1E0D0C0, R8A779F0_PD_A2E0D0, PD_CPU_NOCR }, + { "a1e0d0c1", R8A779F0_PD_A1E0D0C1, R8A779F0_PD_A2E0D0, PD_CPU_NOCR }, + { "a1e0d1c0", R8A779F0_PD_A1E0D1C0, R8A779F0_PD_A2E0D1, PD_CPU_NOCR }, + { "a1e0d1c1", R8A779F0_PD_A1E0D1C1, R8A779F0_PD_A2E0D1, PD_CPU_NOCR }, + { "a1e1d0c0", R8A779F0_PD_A1E1D0C0, R8A779F0_PD_A2E1D0, PD_CPU_NOCR }, + { "a1e1d0c1", R8A779F0_PD_A1E1D0C1, R8A779F0_PD_A2E1D0, PD_CPU_NOCR }, + { "a1e1d1c0", R8A779F0_PD_A1E1D1C0, R8A779F0_PD_A2E1D1, PD_CPU_NOCR }, + { "a1e1d1c1", R8A779F0_PD_A1E1D1C1, R8A779F0_PD_A2E1D1, PD_CPU_NOCR }, +}; + +const struct rcar_gen4_sysc_info r8a779f0_sysc_info __initconst = { + .areas = r8a779f0_areas, + .num_areas = ARRAY_SIZE(r8a779f0_areas), +}; diff --git a/drivers/soc/renesas/rcar-gen4-sysc.c b/drivers/soc/renesas/rcar-gen4-sysc.c new file mode 100644 index 000000000000..831162a57f9a --- /dev/null +++ b/drivers/soc/renesas/rcar-gen4-sysc.c @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * R-Car Gen4 SYSC Power management support + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include <linux/bits.h> +#include <linux/clk/renesas.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/of_address.h> +#include <linux/pm_domain.h> +#include <linux/slab.h> +#include <linux/spinlock.h> +#include <linux/types.h> + +#include "rcar-gen4-sysc.h" + +/* SYSC Common */ +#define SYSCSR 0x000 /* SYSC Status Register */ +#define SYSCPONSR(x) (0x800 + ((x) * 0x4)) /* Power-ON Status Register 0 */ +#define SYSCPOFFSR(x) (0x808 + ((x) * 0x4)) /* Power-OFF Status Register */ +#define SYSCISCR(x) (0x810 + ((x) * 0x4)) /* Interrupt Status/Clear Register */ +#define SYSCIER(x) (0x820 + ((x) * 0x4)) /* Interrupt Enable Register */ +#define SYSCIMR(x) (0x830 + ((x) * 0x4)) /* Interrupt Mask Register */ + +/* Power Domain Registers */ +#define PDRSR(n) (0x1000 + ((n) * 0x40)) +#define PDRONCR(n) (0x1004 + ((n) * 0x40)) +#define PDROFFCR(n) (0x1008 + ((n) * 0x40)) +#define PDRESR(n) (0x100C + ((n) * 0x40)) + +/* PWRON/PWROFF */ +#define PWRON_PWROFF BIT(0) /* Power-ON/OFF request */ + +/* PDRESR */ +#define PDRESR_ERR BIT(0) + +/* PDRSR */ +#define PDRSR_OFF BIT(0) /* Power-OFF state */ +#define PDRSR_ON BIT(4) /* Power-ON state */ +#define PDRSR_OFF_STATE BIT(8) /* Processing Power-OFF sequence */ +#define PDRSR_ON_STATE BIT(12) /* Processing Power-ON sequence */ + +#define SYSCSR_BUSY GENMASK(1, 0) /* All bit sets is not busy */ + +#define SYSCSR_TIMEOUT 10000 +#define SYSCSR_DELAY_US 10 + +#define PDRESR_RETRIES 1000 +#define PDRESR_DELAY_US 10 + +#define SYSCISR_TIMEOUT 10000 +#define SYSCISR_DELAY_US 10 + +#define RCAR_GEN4_PD_ALWAYS_ON 64 +#define NUM_DOMAINS_EACH_REG BITS_PER_TYPE(u32) + +static void __iomem *rcar_gen4_sysc_base; +static DEFINE_SPINLOCK(rcar_gen4_sysc_lock); /* SMP CPUs + I/O devices */ + +static int rcar_gen4_sysc_pwr_on_off(u8 pdr, bool on) +{ + unsigned int reg_offs; + u32 val; + int ret; + + if (on) + reg_offs = PDRONCR(pdr); + else + reg_offs = PDROFFCR(pdr); + + /* Wait until SYSC is ready to accept a power request */ + ret = readl_poll_timeout_atomic(rcar_gen4_sysc_base + SYSCSR, val, + (val & SYSCSR_BUSY) == SYSCSR_BUSY, + SYSCSR_DELAY_US, SYSCSR_TIMEOUT); + if (ret < 0) + return -EAGAIN; + + /* Submit power shutoff or power resume request */ + iowrite32(PWRON_PWROFF, rcar_gen4_sysc_base + reg_offs); + + return 0; +} + +static int clear_irq_flags(unsigned int reg_idx, unsigned int isr_mask) +{ + u32 val; + int ret; + + iowrite32(isr_mask, rcar_gen4_sysc_base + SYSCISCR(reg_idx)); + + ret = readl_poll_timeout_atomic(rcar_gen4_sysc_base + SYSCISCR(reg_idx), + val, !(val & isr_mask), + SYSCISR_DELAY_US, SYSCISR_TIMEOUT); + if (ret < 0) { + pr_err("\n %s : Can not clear IRQ flags in SYSCISCR", __func__); + return -EIO; + } + + return 0; +} + +static int rcar_gen4_sysc_power(u8 pdr, bool on) +{ + unsigned int isr_mask; + unsigned int reg_idx, bit_idx; + unsigned int status; + unsigned long flags; + int ret = 0; + u32 val; + int k; + + spin_lock_irqsave(&rcar_gen4_sysc_lock, flags); + + reg_idx = pdr / NUM_DOMAINS_EACH_REG; + bit_idx = pdr % NUM_DOMAINS_EACH_REG; + + isr_mask = BIT(bit_idx); + + /* + * The interrupt source needs to be enabled, but masked, to prevent the + * CPU from receiving it. + */ + iowrite32(ioread32(rcar_gen4_sysc_base + SYSCIER(reg_idx)) | isr_mask, + rcar_gen4_sysc_base + SYSCIER(reg_idx)); + iowrite32(ioread32(rcar_gen4_sysc_base + SYSCIMR(reg_idx)) | isr_mask, + rcar_gen4_sysc_base + SYSCIMR(reg_idx)); + + ret = clear_irq_flags(reg_idx, isr_mask); + if (ret) + goto out; + + /* Submit power shutoff or resume request until it was accepted */ + for (k = 0; k < PDRESR_RETRIES; k++) { + ret = rcar_gen4_sysc_pwr_on_off(pdr, on); + if (ret) + goto out; + + status = ioread32(rcar_gen4_sysc_base + PDRESR(pdr)); + if (!(status & PDRESR_ERR)) + break; + + udelay(PDRESR_DELAY_US); + } + + if (k == PDRESR_RETRIES) { + ret = -EIO; + goto out; + } + + /* Wait until the power shutoff or resume request has completed * */ + ret = readl_poll_timeout_atomic(rcar_gen4_sysc_base + SYSCISCR(reg_idx), + val, (val & isr_mask), + SYSCISR_DELAY_US, SYSCISR_TIMEOUT); + if (ret < 0) { + ret = -EIO; + goto out; + } + + /* Clear interrupt flags */ + ret = clear_irq_flags(reg_idx, isr_mask); + if (ret) + goto out; + + out: + spin_unlock_irqrestore(&rcar_gen4_sysc_lock, flags); + + pr_debug("sysc power %s domain %d: %08x -> %d\n", on ? "on" : "off", + pdr, ioread32(rcar_gen4_sysc_base + SYSCISCR(reg_idx)), ret); + return ret; +} + +static bool rcar_gen4_sysc_power_is_off(u8 pdr) +{ + unsigned int st; + + st = ioread32(rcar_gen4_sysc_base + PDRSR(pdr)); + + if (st & PDRSR_OFF) + return true; + + return false; +} + +struct rcar_gen4_sysc_pd { + struct generic_pm_domain genpd; + u8 pdr; + unsigned int flags; + char name[]; +}; + +static inline struct rcar_gen4_sysc_pd *to_rcar_gen4_pd(struct generic_pm_domain *d) +{ + return container_of(d, struct rcar_gen4_sysc_pd, genpd); +} + +static int rcar_gen4_sysc_pd_power_off(struct generic_pm_domain *genpd) +{ + struct rcar_gen4_sysc_pd *pd = to_rcar_gen4_pd(genpd); + + pr_debug("%s: %s\n", __func__, genpd->name); + return rcar_gen4_sysc_power(pd->pdr, false); +} + +static int rcar_gen4_sysc_pd_power_on(struct generic_pm_domain *genpd) +{ + struct rcar_gen4_sysc_pd *pd = to_rcar_gen4_pd(genpd); + + pr_debug("%s: %s\n", __func__, genpd->name); + return rcar_gen4_sysc_power(pd->pdr, true); +} + +static int __init rcar_gen4_sysc_pd_setup(struct rcar_gen4_sysc_pd *pd) +{ + struct generic_pm_domain *genpd = &pd->genpd; + const char *name = pd->genpd.name; + int error; + + if (pd->flags & PD_CPU) { + /* + * This domain contains a CPU core and therefore it should + * only be turned off if the CPU is not in use. + */ + pr_debug("PM domain %s contains %s\n", name, "CPU"); + genpd->flags |= GENPD_FLAG_ALWAYS_ON; + } else if (pd->flags & PD_SCU) { + /* + * This domain contains an SCU and cache-controller, and + * therefore it should only be turned off if the CPU cores are + * not in use. + */ + pr_debug("PM domain %s contains %s\n", name, "SCU"); + genpd->flags |= GENPD_FLAG_ALWAYS_ON; + } else if (pd->flags & PD_NO_CR) { + /* + * This domain cannot be turned off. + */ + genpd->flags |= GENPD_FLAG_ALWAYS_ON; + } + + if (!(pd->flags & (PD_CPU | PD_SCU))) { + /* Enable Clock Domain for I/O devices */ + genpd->flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP; + genpd->attach_dev = cpg_mssr_attach_dev; + genpd->detach_dev = cpg_mssr_detach_dev; + } + + genpd->power_off = rcar_gen4_sysc_pd_power_off; + genpd->power_on = rcar_gen4_sysc_pd_power_on; + + if (pd->flags & (PD_CPU | PD_NO_CR)) { + /* Skip CPUs (handled by SMP code) and areas without control */ + pr_debug("%s: Not touching %s\n", __func__, genpd->name); + goto finalize; + } + + if (!rcar_gen4_sysc_power_is_off(pd->pdr)) { + pr_debug("%s: %s is already powered\n", __func__, genpd->name); + goto finalize; + } + + rcar_gen4_sysc_power(pd->pdr, true); + +finalize: + error = pm_genpd_init(genpd, &simple_qos_governor, false); + if (error) + pr_err("Failed to init PM domain %s: %d\n", name, error); + + return error; +} + +static const struct of_device_id rcar_gen4_sysc_matches[] __initconst = { +#ifdef CONFIG_SYSC_R8A779A0 + { .compatible = "renesas,r8a779a0-sysc", .data = &r8a779a0_sysc_info }, +#endif +#ifdef CONFIG_SYSC_R8A779F0 + { .compatible = "renesas,r8a779f0-sysc", .data = &r8a779f0_sysc_info }, +#endif + { /* sentinel */ } +}; + +struct rcar_gen4_pm_domains { + struct genpd_onecell_data onecell_data; + struct generic_pm_domain *domains[RCAR_GEN4_PD_ALWAYS_ON + 1]; +}; + +static struct genpd_onecell_data *rcar_gen4_sysc_onecell_data; + +static int __init rcar_gen4_sysc_pd_init(void) +{ + const struct rcar_gen4_sysc_info *info; + const struct of_device_id *match; + struct rcar_gen4_pm_domains *domains; + struct device_node *np; + void __iomem *base; + unsigned int i; + int error; + + np = of_find_matching_node_and_match(NULL, rcar_gen4_sysc_matches, &match); + if (!np) + return -ENODEV; + + info = match->data; + + base = of_iomap(np, 0); + if (!base) { + pr_warn("%pOF: Cannot map regs\n", np); + error = -ENOMEM; + goto out_put; + } + + rcar_gen4_sysc_base = base; + + domains = kzalloc(sizeof(*domains), GFP_KERNEL); + if (!domains) { + error = -ENOMEM; + goto out_put; + } + + domains->onecell_data.domains = domains->domains; + domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains); + rcar_gen4_sysc_onecell_data = &domains->onecell_data; + + for (i = 0; i < info->num_areas; i++) { + const struct rcar_gen4_sysc_area *area = &info->areas[i]; + struct rcar_gen4_sysc_pd *pd; + size_t n; + + if (!area->name) { + /* Skip NULLified area */ + continue; + } + + n = strlen(area->name) + 1; + pd = kzalloc(sizeof(*pd) + n, GFP_KERNEL); + if (!pd) { + error = -ENOMEM; + goto out_put; + } + + memcpy(pd->name, area->name, n); + pd->genpd.name = pd->name; + pd->pdr = area->pdr; + pd->flags = area->flags; + + error = rcar_gen4_sysc_pd_setup(pd); + if (error) + goto out_put; + + domains->domains[area->pdr] = &pd->genpd; + + if (area->parent < 0) + continue; + + error = pm_genpd_add_subdomain(domains->domains[area->parent], + &pd->genpd); + if (error) { + pr_warn("Failed to add PM subdomain %s to parent %u\n", + area->name, area->parent); + goto out_put; + } + } + + error = of_genpd_add_provider_onecell(np, &domains->onecell_data); + +out_put: + of_node_put(np); + return error; +} +early_initcall(rcar_gen4_sysc_pd_init); diff --git a/drivers/soc/renesas/rcar-gen4-sysc.h b/drivers/soc/renesas/rcar-gen4-sysc.h new file mode 100644 index 000000000000..0e0bd102b1f9 --- /dev/null +++ b/drivers/soc/renesas/rcar-gen4-sysc.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * R-Car Gen4 System Controller + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ +#ifndef __SOC_RENESAS_RCAR_GEN4_SYSC_H__ +#define __SOC_RENESAS_RCAR_GEN4_SYSC_H__ + +#include <linux/types.h> + +/* + * Power Domain flags + */ +#define PD_CPU BIT(0) /* Area contains main CPU core */ +#define PD_SCU BIT(1) /* Area contains SCU and L2 cache */ +#define PD_NO_CR BIT(2) /* Area lacks PWR{ON,OFF}CR registers */ + +#define PD_CPU_NOCR (PD_CPU | PD_NO_CR) /* CPU area lacks CR */ +#define PD_ALWAYS_ON PD_NO_CR /* Always-on area */ + +/* + * Description of a Power Area + */ +struct rcar_gen4_sysc_area { + const char *name; + u8 pdr; /* PDRn */ + int parent; /* -1 if none */ + unsigned int flags; /* See PD_* */ +}; + +/* + * SoC-specific Power Area Description + */ +struct rcar_gen4_sysc_info { + const struct rcar_gen4_sysc_area *areas; + unsigned int num_areas; +}; + +extern const struct rcar_gen4_sysc_info r8a779a0_sysc_info; +extern const struct rcar_gen4_sysc_info r8a779f0_sysc_info; + +#endif /* __SOC_RENESAS_RCAR_GEN4_SYSC_H__ */ -- 2.25.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH 10/16] soc: renesas: r8a779f0-sysc: Add r8a779f0 support 2021-11-16 7:41 ` [PATCH 10/16] soc: renesas: r8a779f0-sysc: Add r8a779f0 support Yoshihiro Shimoda @ 2021-11-23 16:18 ` Geert Uytterhoeven 2021-11-24 6:49 ` Yoshihiro Shimoda 0 siblings, 1 reply; 47+ messages in thread From: Geert Uytterhoeven @ 2021-11-23 16:18 UTC (permalink / raw) To: Yoshihiro Shimoda Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS Hi Shimoda-san, Thanks for your patch! On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > Add support for R-Car S4-8 (R8A779F0) SoC power areas and register > access. This register specification is similar with R-Car V3U. similar to > So, introduces rcar-gen4-sysc.c for both V3U and S4-8. introduce. That makes perfect sense, as "the R-Car V3U SoC is based on the R-Car Gen 4 architecture". (https://www.renesas.com/us/en/products/automotive-products/automotive-system-chips-socs/r-car-v3u-best-class-r-car-v3u-asil-d-system-chip-automated-driving) > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > --- a/drivers/soc/renesas/Kconfig > +++ b/drivers/soc/renesas/Kconfig > @@ -359,6 +359,9 @@ config SYSC_R8A77970 > config SYSC_R8A779A0 > bool "System Controller support for R-Car V3U" if COMPILE_TEST > > +config SYSC_R8A779F0 > + bool "System Controller support for R-Car S4-8" if COMPILE_TEST > + Please retain sort order (alphabetically). > config SYSC_RMOBILE > bool "System Controller support for R-Mobile" if COMPILE_TEST > > diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile > index 9b29bed2a597..f6c5f8c3818c 100644 > --- a/drivers/soc/renesas/Makefile > +++ b/drivers/soc/renesas/Makefile > @@ -25,11 +25,12 @@ obj-$(CONFIG_SYSC_R8A77980) += r8a77980-sysc.o > obj-$(CONFIG_SYSC_R8A77990) += r8a77990-sysc.o > obj-$(CONFIG_SYSC_R8A77995) += r8a77995-sysc.o > obj-$(CONFIG_SYSC_R8A779A0) += r8a779a0-sysc.o > +obj-$(CONFIG_SYSC_R8A779F0) += r8a779f0-sysc.o > ifdef CONFIG_SMP > obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o > endif > > # Family > obj-$(CONFIG_RST_RCAR) += rcar-rst.o > -obj-$(CONFIG_SYSC_RCAR) += rcar-sysc.o > +obj-$(CONFIG_SYSC_RCAR) += rcar-sysc.o rcar-gen4-sysc.o This means all R-Car kernels will always include support for both R-Car Gen1/2/3 and R-Car Gen4. I think this should be split. The rest looks good to me, but I think it wouldn't hurt to split this patch in two parts: one patch to generalize r8a779a0-sysc.c for R-Car Gen4, and a second patch to introduce support for R-Car S4-8. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 47+ messages in thread
* RE: [PATCH 10/16] soc: renesas: r8a779f0-sysc: Add r8a779f0 support 2021-11-23 16:18 ` Geert Uytterhoeven @ 2021-11-24 6:49 ` Yoshihiro Shimoda 0 siblings, 0 replies; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-11-24 6:49 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS Hi Geert-san, > From: Geert Uytterhoeven, Sent: Wednesday, November 24, 2021 1:18 AM > > Hi Shimoda-san, > > Thanks for your patch! > > On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda > <yoshihiro.shimoda.uh@renesas.com> wrote: > > Add support for R-Car S4-8 (R8A779F0) SoC power areas and register > > access. This register specification is similar with R-Car V3U. > > similar to > > > So, introduces rcar-gen4-sysc.c for both V3U and S4-8. > > introduce. I'll fix these works. > That makes perfect sense, as "the R-Car V3U SoC is based on the R-Car > Gen 4 architecture". > (https://www.renesas.com/us/en/products/automotive-products/automotive-system-chips-socs/r-car-v3u-best-class-r-car- > v3u-asil-d-system-chip-automated-driving) I got it. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > > > --- a/drivers/soc/renesas/Kconfig > > +++ b/drivers/soc/renesas/Kconfig > > @@ -359,6 +359,9 @@ config SYSC_R8A77970 > > config SYSC_R8A779A0 > > bool "System Controller support for R-Car V3U" if COMPILE_TEST > > > > +config SYSC_R8A779F0 > > + bool "System Controller support for R-Car S4-8" if COMPILE_TEST > > + > > Please retain sort order (alphabetically). Oops. I'll fix it on v2. > > config SYSC_RMOBILE > > bool "System Controller support for R-Mobile" if COMPILE_TEST > > > > diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile > > index 9b29bed2a597..f6c5f8c3818c 100644 > > --- a/drivers/soc/renesas/Makefile > > +++ b/drivers/soc/renesas/Makefile > > @@ -25,11 +25,12 @@ obj-$(CONFIG_SYSC_R8A77980) += r8a77980-sysc.o > > obj-$(CONFIG_SYSC_R8A77990) += r8a77990-sysc.o > > obj-$(CONFIG_SYSC_R8A77995) += r8a77995-sysc.o > > obj-$(CONFIG_SYSC_R8A779A0) += r8a779a0-sysc.o > > +obj-$(CONFIG_SYSC_R8A779F0) += r8a779f0-sysc.o > > ifdef CONFIG_SMP > > obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o > > endif > > > > # Family > > obj-$(CONFIG_RST_RCAR) += rcar-rst.o > > -obj-$(CONFIG_SYSC_RCAR) += rcar-sysc.o > > +obj-$(CONFIG_SYSC_RCAR) += rcar-sysc.o rcar-gen4-sysc.o > > This means all R-Car kernels will always include support for both > R-Car Gen1/2/3 and R-Car Gen4. > I think this should be split. > > The rest looks good to me, but I think it wouldn't hurt to split this > patch in two parts: one patch to generalize r8a779a0-sysc.c for R-Car > Gen4, and a second patch to introduce support for R-Car S4-8. I got it. I'll split this patch in two parts in v2. Best regards, Yoshihiro Shimoda ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH 11/16] soc: renesas: rcar-rst: Add support for R-Car S4-8 2021-11-16 7:41 [PATCH 00/16] treewide: Initial support for R-Car S4-8 Yoshihiro Shimoda ` (9 preceding siblings ...) 2021-11-16 7:41 ` [PATCH 10/16] soc: renesas: r8a779f0-sysc: Add r8a779f0 support Yoshihiro Shimoda @ 2021-11-16 7:41 ` Yoshihiro Shimoda 2021-11-18 19:10 ` Geert Uytterhoeven 2021-11-16 7:41 ` [PATCH 12/16] clk: renesas: cpg-mssr: " Yoshihiro Shimoda ` (4 subsequent siblings) 15 siblings, 1 reply; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-11-16 7:41 UTC (permalink / raw) To: geert+renesas, magnus.damm, robh+dt, gregkh, jirislaby Cc: linux-renesas-soc, devicetree, linux-serial, Yoshihiro Shimoda Add support for R-Car S4-8 (R8A779F0) to the R-Car RST driver. The register map of R-Car S4-8 is the same as R-Car V3U so that renames "V3U" and "r8a779a0" with "Gen4". Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- drivers/soc/renesas/rcar-rst.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c index 24c7466de9f2..c9f2232a1b42 100644 --- a/drivers/soc/renesas/rcar-rst.c +++ b/drivers/soc/renesas/rcar-rst.c @@ -12,7 +12,7 @@ #define WDTRSTCR_RESET 0xA55A0002 #define WDTRSTCR 0x0054 -#define V3U_WDTRSTCR 0x0010 +#define GEN4_WDTRSTCR 0x0010 #define CR7BAR 0x0070 #define CR7BAREN BIT(4) @@ -28,9 +28,9 @@ static int rcar_rst_enable_wdt_reset(void __iomem *base) return 0; } -static int v3u_rst_enable_wdt_reset(void __iomem *base) +static int rcar_rst_gen4_enable_wdt_reset(void __iomem *base) { - iowrite32(WDTRSTCR_RESET, base + V3U_WDTRSTCR); + iowrite32(WDTRSTCR_RESET, base + GEN4_WDTRSTCR); return 0; } @@ -73,9 +73,9 @@ static const struct rst_config rcar_rst_gen3 __initconst = { .set_rproc_boot_addr = rcar_rst_set_gen3_rproc_boot_addr, }; -static const struct rst_config rcar_rst_r8a779a0 __initconst = { +static const struct rst_config rcar_rst_gen4 __initconst = { .modemr = 0x00, /* MODEMR0 and it has CPG related bits */ - .configure = v3u_rst_enable_wdt_reset, + .configure = rcar_rst_gen4_enable_wdt_reset, }; static const struct of_device_id rcar_rst_matches[] __initconst = { @@ -109,7 +109,9 @@ static const struct of_device_id rcar_rst_matches[] __initconst = { { .compatible = "renesas,r8a77990-rst", .data = &rcar_rst_gen3 }, { .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen3 }, /* R-Car V3U */ - { .compatible = "renesas,r8a779a0-rst", .data = &rcar_rst_r8a779a0 }, + { .compatible = "renesas,r8a779a0-rst", .data = &rcar_rst_gen4 }, + /* R-Car Gen4 */ + { .compatible = "renesas,r8a779f0-rst", .data = &rcar_rst_gen4 }, { /* sentinel */ } }; -- 2.25.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH 11/16] soc: renesas: rcar-rst: Add support for R-Car S4-8 2021-11-16 7:41 ` [PATCH 11/16] soc: renesas: rcar-rst: Add support for R-Car S4-8 Yoshihiro Shimoda @ 2021-11-18 19:10 ` Geert Uytterhoeven 2021-11-19 2:35 ` Yoshihiro Shimoda 0 siblings, 1 reply; 47+ messages in thread From: Geert Uytterhoeven @ 2021-11-18 19:10 UTC (permalink / raw) To: Yoshihiro Shimoda Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS Hi Shimoda-san, On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > Add support for R-Car S4-8 (R8A779F0) to the R-Car RST driver. > The register map of R-Car S4-8 is the same as R-Car V3U so that > renames "V3U" and "r8a779a0" with "Gen4". > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Thanks for your patch! > --- a/drivers/soc/renesas/rcar-rst.c > +++ b/drivers/soc/renesas/rcar-rst.c > @@ -12,7 +12,7 @@ > > #define WDTRSTCR_RESET 0xA55A0002 > #define WDTRSTCR 0x0054 > -#define V3U_WDTRSTCR 0x0010 > +#define GEN4_WDTRSTCR 0x0010 V3U_WDTRSTCR handling is not present upstream, as it should be handled by the boot loader (ATF?), like on other R-Car Gen3 SoCs. Likewise, GEN4_WDTRSTCR should not become present upstream. So please split this in two patches: 1. A patch against upstream, just adding basic R-Car S4-8 support, 2. An optional second patch to enable GEN4_WDTRSTCR in renesas-drivers, to serve as an interim solution until the bootloader is fixed. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 47+ messages in thread
* RE: [PATCH 11/16] soc: renesas: rcar-rst: Add support for R-Car S4-8 2021-11-18 19:10 ` Geert Uytterhoeven @ 2021-11-19 2:35 ` Yoshihiro Shimoda 0 siblings, 0 replies; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-11-19 2:35 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS Hi Geert-san, Thank you for your review! > From: Geert Uytterhoeven, Sent: Friday, November 19, 2021 4:11 AM > > Hi Shimoda-san, > > On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda > <yoshihiro.shimoda.uh@renesas.com> wrote: > > Add support for R-Car S4-8 (R8A779F0) to the R-Car RST driver. > > The register map of R-Car S4-8 is the same as R-Car V3U so that > > renames "V3U" and "r8a779a0" with "Gen4". > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > > Thanks for your patch! > > > --- a/drivers/soc/renesas/rcar-rst.c > > +++ b/drivers/soc/renesas/rcar-rst.c > > @@ -12,7 +12,7 @@ > > > > #define WDTRSTCR_RESET 0xA55A0002 > > #define WDTRSTCR 0x0054 > > -#define V3U_WDTRSTCR 0x0010 > > +#define GEN4_WDTRSTCR 0x0010 > > V3U_WDTRSTCR handling is not present upstream, as it should be > handled by the boot loader (ATF?), like on other R-Car Gen3 SoCs. > Likewise, GEN4_WDTRSTCR should not become present upstream. I'm sorry. I made this patch on renesas-driver and I didn't realized this V3U_WDTRSTCR handling is not present upstream. > So please split this in two patches: > 1. A patch against upstream, just adding basic R-Car S4-8 support, > 2. An optional second patch to enable GEN4_WDTRSTCR in > renesas-drivers, to serve as an interim solution until the > bootloader is fixed. I got it. I'll make the 1. patch in v2 at this time. Best regards, Yoshihiro Shimoda ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH 12/16] clk: renesas: cpg-mssr: Add support for R-Car S4-8 2021-11-16 7:41 [PATCH 00/16] treewide: Initial support for R-Car S4-8 Yoshihiro Shimoda ` (10 preceding siblings ...) 2021-11-16 7:41 ` [PATCH 11/16] soc: renesas: rcar-rst: Add support for R-Car S4-8 Yoshihiro Shimoda @ 2021-11-16 7:41 ` Yoshihiro Shimoda 2021-11-24 13:48 ` Geert Uytterhoeven 2021-11-16 7:41 ` [PATCH 13/16] tty: serial: sh-sci: Add support for R-Car Gen4 Yoshihiro Shimoda ` (3 subsequent siblings) 15 siblings, 1 reply; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-11-16 7:41 UTC (permalink / raw) To: geert+renesas, magnus.damm, robh+dt, gregkh, jirislaby Cc: linux-renesas-soc, devicetree, linux-serial, Yoshihiro Shimoda Initial support for R-Car S4-8 (r8a779f0), including core, module clocks, resets, and register access, because register specification differs from R-Car Gen2/3. The register layout of V3U is a similar with R-Car S4-8 so that renames CLK_REG_LAYOUT_RCAR_V3U as CLK_REG_LAYOUT_RCAR_GEN4. However, PLL names differ between V3U and S4-8. Inspired by patches in the BSP by LUU HOAI. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- drivers/clk/renesas/Kconfig | 10 ++ drivers/clk/renesas/Makefile | 2 + drivers/clk/renesas/r8a779a0-cpg-mssr.c | 2 +- drivers/clk/renesas/r8a779f0-cpg-mssr.c | 188 ++++++++++++++++++++++++ drivers/clk/renesas/rcar-gen4-cpg.c | 141 ++++++++++++++++++ drivers/clk/renesas/rcar-gen4-cpg.h | 76 ++++++++++ drivers/clk/renesas/renesas-cpg-mssr.c | 42 ++++-- drivers/clk/renesas/renesas-cpg-mssr.h | 3 +- 8 files changed, 448 insertions(+), 16 deletions(-) create mode 100644 drivers/clk/renesas/r8a779f0-cpg-mssr.c create mode 100644 drivers/clk/renesas/rcar-gen4-cpg.c create mode 100644 drivers/clk/renesas/rcar-gen4-cpg.h diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 6d0280751bb1..0927fa963ca6 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -31,6 +31,7 @@ config CLK_RENESAS select CLK_R8A77990 if ARCH_R8A77990 select CLK_R8A77995 if ARCH_R8A77995 select CLK_R8A779A0 if ARCH_R8A779A0 + select CLK_R8A779F0 if ARCH_R8A779F0 select CLK_R9A06G032 if ARCH_R9A06G032 select CLK_R9A07G044 if ARCH_R9A07G044 select CLK_SH73A0 if ARCH_SH73A0 @@ -152,6 +153,10 @@ config CLK_R8A779A0 select CLK_RCAR_CPG_LIB select CLK_RENESAS_CPG_MSSR +config CLK_R8A779F0 + bool "R-Car S4-8 clock support" if COMPILE_TEST + select CLK_RCAR_GEN4_CPG + config CLK_R9A06G032 bool "RZ/N1D clock support" if COMPILE_TEST @@ -178,6 +183,11 @@ config CLK_RCAR_GEN3_CPG select CLK_RCAR_CPG_LIB select CLK_RENESAS_CPG_MSSR +config CLK_RCAR_GEN4_CPG + bool "R-Car Gen4 clock support" if COMPILE_TEST + select CLK_RCAR_CPG_LIB + select CLK_RENESAS_CPG_MSSR + config CLK_RCAR_USB2_CLOCK_SEL bool "Renesas R-Car USB2 clock selector support" depends on ARCH_RENESAS || COMPILE_TEST diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 7d018700d08b..1cd461b8fa7b 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o +obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o @@ -36,6 +37,7 @@ obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o obj-$(CONFIG_CLK_RCAR_GEN2_CPG) += rcar-gen2-cpg.o obj-$(CONFIG_CLK_RCAR_GEN3_CPG) += rcar-gen3-cpg.o +obj-$(CONFIG_CLK_RCAR_GEN4_CPG) += rcar-gen4-cpg.o obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL) += rcar-usb2-clock-sel.o obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index fbd7454f2beb..8aab3957c23d 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -583,5 +583,5 @@ const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = { .init = r8a779a0_cpg_mssr_init, .cpg_clk_register = rcar_r8a779a0_cpg_clk_register, - .reg_layout = CLK_REG_LAYOUT_RCAR_V3U, + .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4, }; diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c new file mode 100644 index 000000000000..ebec32008bc6 --- /dev/null +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * r8a779f0 Clock Pulse Generator / Module Standby and Software Reset + * + * Copyright (C) 2021 Renesas Electronics Corp. + * + * Based on r8a779a0-cpg-mssr.c + */ + +#include <linux/bug.h> +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/pm.h> +#include <linux/slab.h> +#include <linux/soc/renesas/rcar-rst.h> + +#include <dt-bindings/clock/r8a779f0-cpg-mssr.h> + +#include "renesas-cpg-mssr.h" +#include "rcar-gen4-cpg.h" + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R8A779F0_CLK_R, + + /* External Input Clocks */ + CLK_EXTAL, + CLK_EXTALR, + + /* Internal Core Clocks */ + CLK_MAIN, + CLK_PLL1, + CLK_PLL2, + CLK_PLL3, + CLK_PLL5, + CLK_PLL6, + CLK_PLL1_DIV2, + CLK_PLL2_DIV2, + CLK_PLL3_DIV2, + CLK_PLL5_DIV2, + CLK_PLL5_DIV4, + CLK_PLL6_DIV2, + CLK_S0, + CLK_SDSRC, + CLK_RPCSRC, + CLK_OCO, + + /* Module Clocks */ + MOD_CLK_BASE +}; + +static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + DEF_INPUT("extalr", CLK_EXTALR), + + /* Internal Core Clocks */ + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL), + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN), + DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN), + DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN), + DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN), + DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN), + + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), + DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1), + DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1), + DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1), + DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1), + DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1), + DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL5_DIV2, 2, 1), + DEF_RATE(".oco", CLK_OCO, 32768), + + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5), + DEF_BASE(".rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A779F0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC), + + /* Core Clock Outputs */ + DEF_FIXED("s0d2", R8A779F0_CLK_S0D2, CLK_S0, 2, 1), + DEF_FIXED("s0d3", R8A779F0_CLK_S0D3, CLK_S0, 3, 1), + DEF_FIXED("s0d4", R8A779F0_CLK_S0D4, CLK_S0, 4, 1), + DEF_FIXED("cl16m", R8A779F0_CLK_CL16M, CLK_S0, 48, 1), + DEF_FIXED("s0d2_mm", R8A779F0_CLK_S0D2_MM, CLK_S0, 2, 1), + DEF_FIXED("s0d3_mm", R8A779F0_CLK_S0D3_MM, CLK_S0, 3, 1), + DEF_FIXED("s0d4_mm", R8A779F0_CLK_S0D4_MM, CLK_S0, 4, 1), + DEF_FIXED("cl16m_mm", R8A779F0_CLK_CL16M_MM, CLK_S0, 48, 1), + DEF_FIXED("s0d2_rt", R8A779F0_CLK_S0D2_RT, CLK_S0, 2, 1), + DEF_FIXED("s0d3_rt", R8A779F0_CLK_S0D3_RT, CLK_S0, 3, 1), + DEF_FIXED("s0d4_rt", R8A779F0_CLK_S0D4_RT, CLK_S0, 4, 1), + DEF_FIXED("s0d6_rt", R8A779F0_CLK_S0D6_RT, CLK_S0, 6, 1), + DEF_FIXED("cl16m_rt", R8A779F0_CLK_CL16M_RT, CLK_S0, 48, 1), + DEF_FIXED("s0d3_per", R8A779F0_CLK_S0D3_PER, CLK_S0, 3, 1), + DEF_FIXED("s0d6_per", R8A779F0_CLK_S0D6_PER, CLK_S0, 6, 1), + DEF_FIXED("s0d12_per", R8A779F0_CLK_S0D12_PER, CLK_S0, 12, 1), + DEF_FIXED("s0d24_per", R8A779F0_CLK_S0D24_PER, CLK_S0, 24, 1), + DEF_FIXED("cl16m_per", R8A779F0_CLK_CL16M_PER, CLK_S0, 48, 1), + DEF_FIXED("s0d2_hsc", R8A779F0_CLK_S0D2_HSC, CLK_S0, 2, 1), + DEF_FIXED("s0d3_hsc", R8A779F0_CLK_S0D3_HSC, CLK_S0, 3, 1), + DEF_FIXED("s0d4_hsc", R8A779F0_CLK_S0D4_HSC, CLK_S0, 4, 1), + DEF_FIXED("s0d6_hsc", R8A779F0_CLK_S0D6_HSC, CLK_S0, 6, 1), + DEF_FIXED("s0d12_hsc", R8A779F0_CLK_S0D12_HSC, CLK_S0, 12, 1), + DEF_FIXED("cl16m_hsc", R8A779F0_CLK_CL16M_HSC, CLK_S0, 48, 1), + DEF_FIXED("s0d2_cc", R8A779F0_CLK_S0D2_CC, CLK_S0, 2, 1), + DEF_FIXED("rsw", R8A779F0_CLK_RSW2, CLK_PLL5, 2, 1), + DEF_FIXED("cbfusa", R8A779F0_CLK_CBFUSA, CLK_EXTAL, 2, 1), + DEF_FIXED("cpex", R8A779F0_CLK_CPEX, CLK_EXTAL, 2, 1), + + DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, CLK_SDSRC, 0x870), + DEF_DIV6P1("mso", R8A779F0_CLK_MSO, CLK_PLL5_DIV4, 0x087C), + + DEF_GEN4_OSC("osc", R8A779F0_CLK_OSC, CLK_EXTAL, 8), + DEF_GEN4_MDSEL("r", R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), +}; + +static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { + DEF_MOD("scif0", 702, R8A779F0_CLK_S0D12_PER), + DEF_MOD("scif1", 703, R8A779F0_CLK_S0D12_PER), + DEF_MOD("scif3", 704, R8A779F0_CLK_S0D12_PER), + DEF_MOD("scif4", 705, R8A779F0_CLK_S0D12_PER), +}; + +/* + * CPG Clock Data + */ +/* + * MD EXTAL PLL1 PLL2 PLL3 PLL5 PLL6 OSC + * 14 13 (MHz) + * ---------------------------------------------------------------- + * 0 0 16.66 / 1 x200 x150 x200 x200 x134 /15 + * 0 1 20 / 1 x160 x120 x160 x160 x106 /19 + * 1 0 Prohibited setting + * 1 1 40 / 2 x160 x120 x160 x160 x106 /38 + */ +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ + (((md) & BIT(13)) >> 13)) + +static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = { + /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */ + { 1, 200, 1, 150, 1, 200, 1, 200, 1, 134, 1, 16, }, + { 1, 160, 1, 120, 1, 160, 1, 160, 1, 106, 1, 19, }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + { 2, 160, 1, 120, 1, 160, 1, 160, 1, 106, 1, 38, }, +}; + +static int __init r8a779f0_cpg_mssr_init(struct device *dev) +{ + const struct rcar_gen4_cpg_pll_config *cpg_pll_config; + u32 cpg_mode; + int error; + + error = rcar_rst_read_mode_pins(&cpg_mode); + if (error) + return error; + + cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; + if (!cpg_pll_config->extal_div) { + dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); + return -EINVAL; + } + + return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); +} + +const struct cpg_mssr_info r8a779f0_cpg_mssr_info __initconst = { + /* Core Clocks */ + .core_clks = r8a779f0_core_clks, + .num_core_clks = ARRAY_SIZE(r8a779f0_core_clks), + .last_dt_core_clk = LAST_DT_CORE_CLK, + .num_total_core_clks = MOD_CLK_BASE, + + /* Module Clocks */ + .mod_clks = r8a779f0_mod_clks, + .num_mod_clks = ARRAY_SIZE(r8a779f0_mod_clks), + .num_hw_mod_clks = 28 * 32, + + /* Callbacks */ + .init = r8a779f0_cpg_mssr_init, + .cpg_clk_register = rcar_gen4_cpg_clk_register, + + .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4, +}; diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c new file mode 100644 index 000000000000..930ac767c1d5 --- /dev/null +++ b/drivers/clk/renesas/rcar-gen4-cpg.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * R-Car Gen4 Clock Pulse Generator + * + * Copyright (C) 2021 Renesas Electronics Corp. + * + * Based on rcar-gen3-cpg.c + * + * Copyright (C) 2015-2018 Glider bvba + * Copyright (C) 2019 Renesas Electronics Corp. + */ + +#include <linux/bug.h> +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/pm.h> +#include <linux/slab.h> +#include <linux/sys_soc.h> + +#include "renesas-cpg-mssr.h" +#include "rcar-gen4-cpg.h" +#include "rcar-cpg-lib.h" + +static const struct clk_div_table cpg_rpcsrc_div_table[] = { + { 2, 5 }, { 3, 6 }, { 0, 0 }, +}; + +static const struct rcar_gen4_cpg_pll_config *cpg_pll_config __initconst; +static unsigned int cpg_clk_extalr __initdata; +static u32 cpg_mode __initdata; + +struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev, + const struct cpg_core_clk *core, const struct cpg_mssr_info *info, + struct clk **clks, void __iomem *base, + struct raw_notifier_head *notifiers) +{ + const struct clk *parent; + unsigned int mult = 1; + unsigned int div = 1; + + parent = clks[core->parent & 0xffff]; /* some types use high bits */ + if (IS_ERR(parent)) + return ERR_CAST(parent); + + switch (core->type) { + case CLK_TYPE_GEN4_MAIN: + div = cpg_pll_config->extal_div; + break; + + case CLK_TYPE_GEN4_PLL1: + mult = cpg_pll_config->pll1_mult; + div = cpg_pll_config->pll1_div; + break; + + case CLK_TYPE_GEN4_PLL2: + mult = cpg_pll_config->pll2_mult; + div = cpg_pll_config->pll2_div; + break; + + case CLK_TYPE_GEN4_PLL3: + mult = cpg_pll_config->pll3_mult; + div = cpg_pll_config->pll3_div; + break; + + case CLK_TYPE_GEN4_PLL5: + mult = cpg_pll_config->pll5_mult; + div = cpg_pll_config->pll5_div; + break; + + case CLK_TYPE_GEN4_PLL6: + mult = cpg_pll_config->pll6_mult; + div = cpg_pll_config->pll6_div; + break; + + case CLK_TYPE_GEN4_MDSEL: + /* + * Clock selectable between two parents and two fixed dividers + * using a mode pin + */ + if (cpg_mode & BIT(core->offset)) { + div = core->div & 0xffff; + } else { + parent = clks[core->parent >> 16]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + div = core->div >> 16; + } + mult = 1; + break; + + case CLK_TYPE_GEN4_OSC: + /* + * Clock combining OSC EXTAL predivider and a fixed divider + */ + div = cpg_pll_config->osc_prediv * core->div; + break; + + case CLK_TYPE_GEN4_RPCSRC: + return clk_register_divider_table(NULL, core->name, + __clk_get_name(parent), 0, + base + CPG_RPCCKCR, 3, 2, 0, + cpg_rpcsrc_div_table, + &cpg_lock); + + case CLK_TYPE_GEN4_RPC: + return cpg_rpc_clk_register(core->name, base + CPG_RPCCKCR, + __clk_get_name(parent), notifiers); + + case CLK_TYPE_GEN4_RPCD2: + return cpg_rpcd2_clk_register(core->name, base + CPG_RPCCKCR, + __clk_get_name(parent)); + + case CLK_TYPE_GEN4_SD: + return cpg_sd_clk_register(core->name, base, core->offset, + __clk_get_name(parent), notifiers, + 0); + + default: + return ERR_PTR(-EINVAL); + } + + return clk_register_fixed_factor(NULL, core->name, + __clk_get_name(parent), 0, mult, div); +} + +int __init rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config, + unsigned int clk_extalr, u32 mode) +{ + cpg_pll_config = config; + cpg_clk_extalr = clk_extalr; + cpg_mode = mode; + + spin_lock_init(&cpg_lock); + + return 0; +} diff --git a/drivers/clk/renesas/rcar-gen4-cpg.h b/drivers/clk/renesas/rcar-gen4-cpg.h new file mode 100644 index 000000000000..d6e40b51743b --- /dev/null +++ b/drivers/clk/renesas/rcar-gen4-cpg.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * R-Car Gen4 Clock Pulse Generator + * + * Copyright (C) 2021 Renesas Electronics Corp. + * + */ + +#ifndef __CLK_RENESAS_RCAR_GEN4_CPG_H__ +#define __CLK_RENESAS_RCAR_GEN4_CPG_H__ + +enum rcar_gen4_clk_types { + CLK_TYPE_GEN4_MAIN = CLK_TYPE_CUSTOM, + CLK_TYPE_GEN4_PLL1, + CLK_TYPE_GEN4_PLL2, + CLK_TYPE_GEN4_PLL3, + CLK_TYPE_GEN4_PLL5, + CLK_TYPE_GEN4_PLL6, + CLK_TYPE_GEN4_SD, + CLK_TYPE_GEN4_R, + CLK_TYPE_GEN4_MDSEL, /* Select parent/divider using mode pin */ + CLK_TYPE_GEN4_Z, + CLK_TYPE_GEN4_ZG, + CLK_TYPE_GEN4_OSC, /* OSC EXTAL predivider and fixed divider */ + CLK_TYPE_GEN4_RPCSRC, + CLK_TYPE_GEN4_RPC, + CLK_TYPE_GEN4_RPCD2, + + /* SoC specific definitions start here */ + CLK_TYPE_GEN4_SOC_BASE, +}; + +#define DEF_GEN4_SD(_name, _id, _parent, _offset) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset) + +#define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL, \ + (_parent0) << 16 | (_parent1), \ + .div = (_div0) << 16 | (_div1), .offset = _md) + +#define DEF_GEN4_PE(_name, _id, _parent_clean, _div_clean, _parent_sscg, \ + _div_sscg) \ + DEF_GEN4_MDSEL(_name, _id, 12, _parent_clean, _div_clean, \ + _parent_sscg, _div_sscg) + +#define DEF_GEN4_OSC(_name, _id, _parent, _div) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div) + +#define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \ + DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset) + +struct rcar_gen4_cpg_pll_config { + u8 extal_div; + u8 pll1_mult; + u8 pll1_div; + u8 pll2_mult; + u8 pll2_div; + u8 pll3_mult; + u8 pll3_div; + u8 pll5_mult; + u8 pll5_div; + u8 pll6_mult; + u8 pll6_div; + u8 osc_prediv; +}; + +#define CPG_RPCCKCR 0x874 + +struct clk *rcar_gen4_cpg_clk_register(struct device *dev, + const struct cpg_core_clk *core, const struct cpg_mssr_info *info, + struct clk **clks, void __iomem *base, + struct raw_notifier_head *notifiers); +int rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config, + unsigned int clk_extalr, u32 mode); + +#endif diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index 21f762aa2131..ccde338b9fed 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -57,9 +57,11 @@ static const u16 mstpsr[] = { 0x9A0, 0x9A4, 0x9A8, 0x9AC, }; -static const u16 mstpsr_for_v3u[] = { +static const u16 mstpsr_for_gen4[] = { 0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C, - 0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38, + 0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38, 0x2E3C, + 0x2E40, 0x2E44, 0x2E48, 0x2E4C, 0x2E50, 0x2E54, 0x2E58, 0x2E5C, + 0x2E60, 0x2E64, 0x2E68, 0x2E6C, }; /* @@ -71,9 +73,11 @@ static const u16 smstpcr[] = { 0x990, 0x994, 0x998, 0x99C, }; -static const u16 mstpcr_for_v3u[] = { +static const u16 mstpcr_for_gen4[] = { 0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C, - 0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38, + 0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38, 0x2D3C, + 0x2D40, 0x2D44, 0x2D48, 0x2D4C, 0x2D50, 0x2D54, 0x2D58, 0x2D5C, + 0x2D60, 0x2D64, 0x2D68, 0x2D6C, }; /* @@ -95,9 +99,11 @@ static const u16 srcr[] = { 0x920, 0x924, 0x928, 0x92C, }; -static const u16 srcr_for_v3u[] = { +static const u16 srcr_for_gen4[] = { 0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C, - 0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38, + 0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38, 0x2C3C, + 0x2C40, 0x2C44, 0x2C48, 0x2C4C, 0x2C50, 0x2C54, 0x2C58, 0x2C5C, + 0x2C60, 0x2C64, 0x2C68, 0x2C6C, }; /* @@ -109,9 +115,11 @@ static const u16 srstclr[] = { 0x960, 0x964, 0x968, 0x96C, }; -static const u16 srstclr_for_v3u[] = { +static const u16 srstclr_for_gen4[] = { 0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C, - 0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8, + 0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8, 0x2CBC, + 0x2CC0, 0x2CC4, 0x2CC8, 0x2CCC, 0x2CD0, 0x2CD4, 0x2CD8, 0x2CDC, + 0x2CE0, 0x2CE4, 0x2CE8, 0x2CEC, }; /** @@ -158,7 +166,7 @@ struct cpg_mssr_priv { struct { u32 mask; u32 val; - } smstpcr_saved[ARRAY_SIZE(mstpsr_for_v3u)]; + } smstpcr_saved[ARRAY_SIZE(mstpsr_for_gen4)]; struct clk *clks[]; }; @@ -827,6 +835,12 @@ static const struct of_device_id cpg_mssr_match[] = { .compatible = "renesas,r8a779a0-cpg-mssr", .data = &r8a779a0_cpg_mssr_info, }, +#endif +#ifdef CONFIG_CLK_R8A779F0 + { + .compatible = "renesas,r8a779f0-cpg-mssr", + .data = &r8a779f0_cpg_mssr_info, + }, #endif { /* sentinel */ } }; @@ -970,11 +984,11 @@ static int __init cpg_mssr_common_init(struct device *dev, priv->reset_clear_regs = srstclr; } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { priv->control_regs = stbcr; - } else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) { - priv->status_regs = mstpsr_for_v3u; - priv->control_regs = mstpcr_for_v3u; - priv->reset_regs = srcr_for_v3u; - priv->reset_clear_regs = srstclr_for_v3u; + } else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) { + priv->status_regs = mstpsr_for_gen4; + priv->control_regs = mstpcr_for_gen4; + priv->reset_regs = srcr_for_gen4; + priv->reset_clear_regs = srstclr_for_gen4; } else { error = -EINVAL; goto out_err; diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index 6b2a0ade482e..16810dd4e6ac 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -88,7 +88,7 @@ struct device_node; enum clk_reg_layout { CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0, CLK_REG_LAYOUT_RZ_A, - CLK_REG_LAYOUT_RCAR_V3U, + CLK_REG_LAYOUT_RCAR_GEN4, }; /** @@ -178,6 +178,7 @@ extern const struct cpg_mssr_info r8a77980_cpg_mssr_info; extern const struct cpg_mssr_info r8a77990_cpg_mssr_info; extern const struct cpg_mssr_info r8a77995_cpg_mssr_info; extern const struct cpg_mssr_info r8a779a0_cpg_mssr_info; +extern const struct cpg_mssr_info r8a779f0_cpg_mssr_info; void __init cpg_mssr_early_init(struct device_node *np, const struct cpg_mssr_info *info); -- 2.25.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH 12/16] clk: renesas: cpg-mssr: Add support for R-Car S4-8 2021-11-16 7:41 ` [PATCH 12/16] clk: renesas: cpg-mssr: " Yoshihiro Shimoda @ 2021-11-24 13:48 ` Geert Uytterhoeven 2021-11-29 8:35 ` Yoshihiro Shimoda 0 siblings, 1 reply; 47+ messages in thread From: Geert Uytterhoeven @ 2021-11-24 13:48 UTC (permalink / raw) To: Yoshihiro Shimoda Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS Hi Shimoda-san, Thanks for your patch! On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > Initial support for R-Car S4-8 (r8a779f0), including core, module > clocks, resets, and register access, because register specification > differs from R-Car Gen2/3. The register layout of V3U is a similar > with R-Car S4-8 so that renames CLK_REG_LAYOUT_RCAR_V3U as > CLK_REG_LAYOUT_RCAR_GEN4. However, PLL names differ between V3U > and S4-8. This is a small difference, so I think more code can be shared between R-Car V3U and S4-8 (see below). > Inspired by patches in the BSP by LUU HOAI. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > drivers/clk/renesas/Kconfig | 10 ++ > drivers/clk/renesas/Makefile | 2 + > drivers/clk/renesas/r8a779a0-cpg-mssr.c | 2 +- > drivers/clk/renesas/r8a779f0-cpg-mssr.c | 188 ++++++++++++++++++++++++ > drivers/clk/renesas/rcar-gen4-cpg.c | 141 ++++++++++++++++++ > drivers/clk/renesas/rcar-gen4-cpg.h | 76 ++++++++++ > drivers/clk/renesas/renesas-cpg-mssr.c | 42 ++++-- > drivers/clk/renesas/renesas-cpg-mssr.h | 3 +- > 8 files changed, 448 insertions(+), 16 deletions(-) > create mode 100644 drivers/clk/renesas/r8a779f0-cpg-mssr.c > create mode 100644 drivers/clk/renesas/rcar-gen4-cpg.c > create mode 100644 drivers/clk/renesas/rcar-gen4-cpg.h Just like for the SYSC driver, I think it wouldn't hurt to split this patch in two parts: one patch to generalize r8a779a0-cpg-mssr.c for R-Car Gen4, and a second patch to introduce support for R-Car S4-8. > +static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { > + /* External Clock Inputs */ > + DEF_INPUT("extal", CLK_EXTAL), > + DEF_INPUT("extalr", CLK_EXTALR), > + > + /* Internal Core Clocks */ > + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL), > + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN), > + DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN), > + DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN), > + DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN), > + DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN), Please sort PLLn by index. > + > + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), > + DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1), > + DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1), > + DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1), > + DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1), > + DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1), > + DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), > + DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL5_DIV2, 2, 1), This relies on the default setting of the SD-IF0 Clock Frequency Control Register 1 (SD0CKCR1)? > + DEF_RATE(".oco", CLK_OCO, 32768), > + > + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5), > + DEF_BASE(".rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), > + DEF_BASE("rpcd2", R8A779F0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC), > + > + /* Core Clock Outputs */ > + DEF_FIXED("s0d2", R8A779F0_CLK_S0D2, CLK_S0, 2, 1), > + DEF_FIXED("s0d3", R8A779F0_CLK_S0D3, CLK_S0, 3, 1), > + DEF_FIXED("s0d4", R8A779F0_CLK_S0D4, CLK_S0, 4, 1), > + DEF_FIXED("cl16m", R8A779F0_CLK_CL16M, CLK_S0, 48, 1), > + DEF_FIXED("s0d2_mm", R8A779F0_CLK_S0D2_MM, CLK_S0, 2, 1), > + DEF_FIXED("s0d3_mm", R8A779F0_CLK_S0D3_MM, CLK_S0, 3, 1), > + DEF_FIXED("s0d4_mm", R8A779F0_CLK_S0D4_MM, CLK_S0, 4, 1), > + DEF_FIXED("cl16m_mm", R8A779F0_CLK_CL16M_MM, CLK_S0, 48, 1), > + DEF_FIXED("s0d2_rt", R8A779F0_CLK_S0D2_RT, CLK_S0, 2, 1), > + DEF_FIXED("s0d3_rt", R8A779F0_CLK_S0D3_RT, CLK_S0, 3, 1), > + DEF_FIXED("s0d4_rt", R8A779F0_CLK_S0D4_RT, CLK_S0, 4, 1), > + DEF_FIXED("s0d6_rt", R8A779F0_CLK_S0D6_RT, CLK_S0, 6, 1), > + DEF_FIXED("cl16m_rt", R8A779F0_CLK_CL16M_RT, CLK_S0, 48, 1), > + DEF_FIXED("s0d3_per", R8A779F0_CLK_S0D3_PER, CLK_S0, 3, 1), > + DEF_FIXED("s0d6_per", R8A779F0_CLK_S0D6_PER, CLK_S0, 6, 1), > + DEF_FIXED("s0d12_per", R8A779F0_CLK_S0D12_PER, CLK_S0, 12, 1), > + DEF_FIXED("s0d24_per", R8A779F0_CLK_S0D24_PER, CLK_S0, 24, 1), > + DEF_FIXED("cl16m_per", R8A779F0_CLK_CL16M_PER, CLK_S0, 48, 1), > + DEF_FIXED("s0d2_hsc", R8A779F0_CLK_S0D2_HSC, CLK_S0, 2, 1), > + DEF_FIXED("s0d3_hsc", R8A779F0_CLK_S0D3_HSC, CLK_S0, 3, 1), > + DEF_FIXED("s0d4_hsc", R8A779F0_CLK_S0D4_HSC, CLK_S0, 4, 1), > + DEF_FIXED("s0d6_hsc", R8A779F0_CLK_S0D6_HSC, CLK_S0, 6, 1), > + DEF_FIXED("s0d12_hsc", R8A779F0_CLK_S0D12_HSC, CLK_S0, 12, 1), > + DEF_FIXED("cl16m_hsc", R8A779F0_CLK_CL16M_HSC, CLK_S0, 48, 1), > + DEF_FIXED("s0d2_cc", R8A779F0_CLK_S0D2_CC, CLK_S0, 2, 1), > + DEF_FIXED("rsw", R8A779F0_CLK_RSW2, CLK_PLL5, 2, 1), "rsw2"? > + DEF_FIXED("cbfusa", R8A779F0_CLK_CBFUSA, CLK_EXTAL, 2, 1), > + DEF_FIXED("cpex", R8A779F0_CLK_CPEX, CLK_EXTAL, 2, 1), > + > + DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, CLK_SDSRC, 0x870), > + DEF_DIV6P1("mso", R8A779F0_CLK_MSO, CLK_PLL5_DIV4, 0x087C), 0x87c > + > + DEF_GEN4_OSC("osc", R8A779F0_CLK_OSC, CLK_EXTAL, 8), > + DEF_GEN4_MDSEL("r", R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), > +}; > + > +static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { > + DEF_MOD("scif0", 702, R8A779F0_CLK_S0D12_PER), > + DEF_MOD("scif1", 703, R8A779F0_CLK_S0D12_PER), > + DEF_MOD("scif3", 704, R8A779F0_CLK_S0D12_PER), > + DEF_MOD("scif4", 705, R8A779F0_CLK_S0D12_PER), > +}; > + > +/* > + * CPG Clock Data > + */ > +/* > + * MD EXTAL PLL1 PLL2 PLL3 PLL5 PLL6 OSC > + * 14 13 (MHz) > + * ---------------------------------------------------------------- > + * 0 0 16.66 / 1 x200 x150 x200 x200 x134 /15 EXTAL is 16 MHz? > + * 0 1 20 / 1 x160 x120 x160 x160 x106 /19 > + * 1 0 Prohibited setting > + * 1 1 40 / 2 x160 x120 x160 x160 x106 /38 > + */ > +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ > + (((md) & BIT(13)) >> 13)) > + > +static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = { > + /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */ > + { 1, 200, 1, 150, 1, 200, 1, 200, 1, 134, 1, 16, }, OSC prediv is 15? > + { 1, 160, 1, 120, 1, 160, 1, 160, 1, 106, 1, 19, }, > + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, > + { 2, 160, 1, 120, 1, 160, 1, 160, 1, 106, 1, 38, }, > +}; > --- /dev/null > +++ b/drivers/clk/renesas/rcar-gen4-cpg.c > @@ -0,0 +1,141 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * R-Car Gen4 Clock Pulse Generator > + * > + * Copyright (C) 2021 Renesas Electronics Corp. > + * > + * Based on rcar-gen3-cpg.c > + * > + * Copyright (C) 2015-2018 Glider bvba > + * Copyright (C) 2019 Renesas Electronics Corp. > + */ > + > +#include <linux/bug.h> > +#include <linux/bitfield.h> > +#include <linux/clk.h> > +#include <linux/clk-provider.h> > +#include <linux/device.h> > +#include <linux/err.h> > +#include <linux/init.h> > +#include <linux/io.h> > +#include <linux/pm.h> > +#include <linux/slab.h> > +#include <linux/sys_soc.h> Several of these includes are not needed. > + > +#include "renesas-cpg-mssr.h" > +#include "rcar-gen4-cpg.h" > +#include "rcar-cpg-lib.h" > + > +static const struct clk_div_table cpg_rpcsrc_div_table[] = { > + { 2, 5 }, { 3, 6 }, { 0, 0 }, The datasheet says { 0, 4 } and { 1, 6} are also supported, just like on R-Car V3U. > +}; > +struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev, > + const struct cpg_core_clk *core, const struct cpg_mssr_info *info, > + struct clk **clks, void __iomem *base, > + struct raw_notifier_head *notifiers) > +{ > + const struct clk *parent; > + unsigned int mult = 1; > + unsigned int div = 1; > + > + parent = clks[core->parent & 0xffff]; /* some types use high bits */ > + if (IS_ERR(parent)) > + return ERR_CAST(parent); > + > + switch (core->type) { > + case CLK_TYPE_GEN4_MAIN: > + div = cpg_pll_config->extal_div; > + break; > + > + case CLK_TYPE_GEN4_PLL1: > + mult = cpg_pll_config->pll1_mult; > + div = cpg_pll_config->pll1_div; > + break; > + > + case CLK_TYPE_GEN4_PLL2: > + mult = cpg_pll_config->pll2_mult; > + div = cpg_pll_config->pll2_div; > + break; > + > + case CLK_TYPE_GEN4_PLL3: > + mult = cpg_pll_config->pll3_mult; > + div = cpg_pll_config->pll3_div; > + break; > + > + case CLK_TYPE_GEN4_PLL5: > + mult = cpg_pll_config->pll5_mult; > + div = cpg_pll_config->pll5_div; > + break; > + > + case CLK_TYPE_GEN4_PLL6: > + mult = cpg_pll_config->pll6_mult; > + div = cpg_pll_config->pll6_div; > + break; The Z clock handling for R-Car S4-8 seems to be the same as for R-Car V3U, so you can move that here, too. That leaves us with the different PLLn handling: 1. I think you can just move the PLL2X_3C clock type for R-Car V3U here, too. It's only 4 lines of code. Then rcar-gen4-cpg.c can be shared by R-Car V3U and R-Car S4-8. 2. Future full PLLn handling for R-Car S4-8 (using the PLLnCR1 registers) will need switching from CLK_TYPE_GEN4_PLLn to a new clock type anyway. > + case CLK_TYPE_GEN4_SD: > + return cpg_sd_clk_register(core->name, base, core->offset, > + __clk_get_name(parent), notifiers, > + 0); This should be changed to: return cpg_sd_clk_register(core->name, base + core->offset, __clk_get_name(parent)); due to the recent changes in renesas-clk to handle the SDH clock. > + > + default: > + return ERR_PTR(-EINVAL); > + } > + > + return clk_register_fixed_factor(NULL, core->name, > + __clk_get_name(parent), 0, mult, div); > +} > --- /dev/null > +++ b/drivers/clk/renesas/rcar-gen4-cpg.h > @@ -0,0 +1,76 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * R-Car Gen4 Clock Pulse Generator > + * > + * Copyright (C) 2021 Renesas Electronics Corp. > + * > + */ > + > +#ifndef __CLK_RENESAS_RCAR_GEN4_CPG_H__ > +#define __CLK_RENESAS_RCAR_GEN4_CPG_H__ > + > +enum rcar_gen4_clk_types { > + CLK_TYPE_GEN4_MAIN = CLK_TYPE_CUSTOM, > + CLK_TYPE_GEN4_PLL1, > + CLK_TYPE_GEN4_PLL2, > + CLK_TYPE_GEN4_PLL3, > + CLK_TYPE_GEN4_PLL5, > + CLK_TYPE_GEN4_PLL6, > + CLK_TYPE_GEN4_SD, > + CLK_TYPE_GEN4_R, So far unused. > + CLK_TYPE_GEN4_MDSEL, /* Select parent/divider using mode pin */ > + CLK_TYPE_GEN4_Z, > + CLK_TYPE_GEN4_ZG, Both unused. > + CLK_TYPE_GEN4_OSC, /* OSC EXTAL predivider and fixed divider */ > + CLK_TYPE_GEN4_RPCSRC, > + CLK_TYPE_GEN4_RPC, > + CLK_TYPE_GEN4_RPCD2, > + > + /* SoC specific definitions start here */ > + CLK_TYPE_GEN4_SOC_BASE, > +}; > + > +#define DEF_GEN4_SD(_name, _id, _parent, _offset) \ > + DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset) > + > +#define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ > + DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL, \ > + (_parent0) << 16 | (_parent1), \ > + .div = (_div0) << 16 | (_div1), .offset = _md) > + > +#define DEF_GEN4_PE(_name, _id, _parent_clean, _div_clean, _parent_sscg, \ > + _div_sscg) \ > + DEF_GEN4_MDSEL(_name, _id, 12, _parent_clean, _div_clean, \ > + _parent_sscg, _div_sscg) R-Car S4 does not have a PE clock, so please drop this. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 47+ messages in thread
* RE: [PATCH 12/16] clk: renesas: cpg-mssr: Add support for R-Car S4-8 2021-11-24 13:48 ` Geert Uytterhoeven @ 2021-11-29 8:35 ` Yoshihiro Shimoda 2021-11-29 8:47 ` Geert Uytterhoeven 0 siblings, 1 reply; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-11-29 8:35 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS Hi Geert-san, Thank you for your review! > From: Geert Uytterhoeven, Sent: Wednesday, November 24, 2021 10:48 PM > > Hi Shimoda-san, > > Thanks for your patch! > > On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda > <yoshihiro.shimoda.uh@renesas.com> wrote: > > Initial support for R-Car S4-8 (r8a779f0), including core, module > > clocks, resets, and register access, because register specification > > differs from R-Car Gen2/3. The register layout of V3U is a similar > > with R-Car S4-8 so that renames CLK_REG_LAYOUT_RCAR_V3U as > > CLK_REG_LAYOUT_RCAR_GEN4. However, PLL names differ between V3U > > and S4-8. > > This is a small difference, so I think more code can be shared between > R-Car V3U and S4-8 (see below). I got it. > > Inspired by patches in the BSP by LUU HOAI. > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > > > drivers/clk/renesas/Kconfig | 10 ++ > > drivers/clk/renesas/Makefile | 2 + > > drivers/clk/renesas/r8a779a0-cpg-mssr.c | 2 +- > > drivers/clk/renesas/r8a779f0-cpg-mssr.c | 188 ++++++++++++++++++++++++ > > drivers/clk/renesas/rcar-gen4-cpg.c | 141 ++++++++++++++++++ > > drivers/clk/renesas/rcar-gen4-cpg.h | 76 ++++++++++ > > drivers/clk/renesas/renesas-cpg-mssr.c | 42 ++++-- > > drivers/clk/renesas/renesas-cpg-mssr.h | 3 +- > > 8 files changed, 448 insertions(+), 16 deletions(-) > > create mode 100644 drivers/clk/renesas/r8a779f0-cpg-mssr.c > > create mode 100644 drivers/clk/renesas/rcar-gen4-cpg.c > > create mode 100644 drivers/clk/renesas/rcar-gen4-cpg.h > > Just like for the SYSC driver, I think it wouldn't hurt to split this > patch in two parts: one patch to generalize r8a779a0-cpg-mssr.c for > R-Car Gen4, and a second patch to introduce support for R-Car S4-8. I got it. I'll split this patch in two parts in v2. > > +static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { > > + /* External Clock Inputs */ > > + DEF_INPUT("extal", CLK_EXTAL), > > + DEF_INPUT("extalr", CLK_EXTALR), > > + > > + /* Internal Core Clocks */ > > + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL), > > + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN), > > + DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN), > > + DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN), > > + DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN), > > + DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN), > > Please sort PLLn by index. Oops. I'll fix the order. > > + > > + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), > > + DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1), > > + DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1), > > + DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1), > > + DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1), > > + DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1), > > + DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), > > + DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL5_DIV2, 2, 1), > > This relies on the default setting of the SD-IF0 Clock Frequency > Control Register 1 (SD0CKCR1)? You're correct. So, we should not use DEF_FIXED for SDSRC... > > + DEF_RATE(".oco", CLK_OCO, 32768), > > + > > + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5), > > + DEF_BASE(".rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), > > + DEF_BASE("rpcd2", R8A779F0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC), > > + > > + /* Core Clock Outputs */ > > + DEF_FIXED("s0d2", R8A779F0_CLK_S0D2, CLK_S0, 2, 1), > > + DEF_FIXED("s0d3", R8A779F0_CLK_S0D3, CLK_S0, 3, 1), > > + DEF_FIXED("s0d4", R8A779F0_CLK_S0D4, CLK_S0, 4, 1), > > + DEF_FIXED("cl16m", R8A779F0_CLK_CL16M, CLK_S0, 48, 1), > > + DEF_FIXED("s0d2_mm", R8A779F0_CLK_S0D2_MM, CLK_S0, 2, 1), > > + DEF_FIXED("s0d3_mm", R8A779F0_CLK_S0D3_MM, CLK_S0, 3, 1), > > + DEF_FIXED("s0d4_mm", R8A779F0_CLK_S0D4_MM, CLK_S0, 4, 1), > > + DEF_FIXED("cl16m_mm", R8A779F0_CLK_CL16M_MM, CLK_S0, 48, 1), > > + DEF_FIXED("s0d2_rt", R8A779F0_CLK_S0D2_RT, CLK_S0, 2, 1), > > + DEF_FIXED("s0d3_rt", R8A779F0_CLK_S0D3_RT, CLK_S0, 3, 1), > > + DEF_FIXED("s0d4_rt", R8A779F0_CLK_S0D4_RT, CLK_S0, 4, 1), > > + DEF_FIXED("s0d6_rt", R8A779F0_CLK_S0D6_RT, CLK_S0, 6, 1), > > + DEF_FIXED("cl16m_rt", R8A779F0_CLK_CL16M_RT, CLK_S0, 48, 1), > > + DEF_FIXED("s0d3_per", R8A779F0_CLK_S0D3_PER, CLK_S0, 3, 1), > > + DEF_FIXED("s0d6_per", R8A779F0_CLK_S0D6_PER, CLK_S0, 6, 1), > > + DEF_FIXED("s0d12_per", R8A779F0_CLK_S0D12_PER, CLK_S0, 12, 1), > > + DEF_FIXED("s0d24_per", R8A779F0_CLK_S0D24_PER, CLK_S0, 24, 1), > > + DEF_FIXED("cl16m_per", R8A779F0_CLK_CL16M_PER, CLK_S0, 48, 1), > > + DEF_FIXED("s0d2_hsc", R8A779F0_CLK_S0D2_HSC, CLK_S0, 2, 1), > > + DEF_FIXED("s0d3_hsc", R8A779F0_CLK_S0D3_HSC, CLK_S0, 3, 1), > > + DEF_FIXED("s0d4_hsc", R8A779F0_CLK_S0D4_HSC, CLK_S0, 4, 1), > > + DEF_FIXED("s0d6_hsc", R8A779F0_CLK_S0D6_HSC, CLK_S0, 6, 1), > > + DEF_FIXED("s0d12_hsc", R8A779F0_CLK_S0D12_HSC, CLK_S0, 12, 1), > > + DEF_FIXED("cl16m_hsc", R8A779F0_CLK_CL16M_HSC, CLK_S0, 48, 1), > > + DEF_FIXED("s0d2_cc", R8A779F0_CLK_S0D2_CC, CLK_S0, 2, 1), > > + DEF_FIXED("rsw", R8A779F0_CLK_RSW2, CLK_PLL5, 2, 1), > > "rsw2"? Yes. I'll fix it. > > + DEF_FIXED("cbfusa", R8A779F0_CLK_CBFUSA, CLK_EXTAL, 2, 1), > > + DEF_FIXED("cpex", R8A779F0_CLK_CPEX, CLK_EXTAL, 2, 1), > > + > > + DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, CLK_SDSRC, 0x870), > > + DEF_DIV6P1("mso", R8A779F0_CLK_MSO, CLK_PLL5_DIV4, 0x087C), > > 0x87c Oops. I'll fix it. > > + > > + DEF_GEN4_OSC("osc", R8A779F0_CLK_OSC, CLK_EXTAL, 8), > > + DEF_GEN4_MDSEL("r", R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), > > +}; > > + > > +static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { > > + DEF_MOD("scif0", 702, R8A779F0_CLK_S0D12_PER), > > + DEF_MOD("scif1", 703, R8A779F0_CLK_S0D12_PER), > > + DEF_MOD("scif3", 704, R8A779F0_CLK_S0D12_PER), > > + DEF_MOD("scif4", 705, R8A779F0_CLK_S0D12_PER), > > +}; > > + > > +/* > > + * CPG Clock Data > > + */ > > +/* > > + * MD EXTAL PLL1 PLL2 PLL3 PLL5 PLL6 OSC > > + * 14 13 (MHz) > > + * ---------------------------------------------------------------- > > + * 0 0 16.66 / 1 x200 x150 x200 x200 x134 /15 > > EXTAL is 16 MHz? Oops. You're correct. I'll fix it. > > + * 0 1 20 / 1 x160 x120 x160 x160 x106 /19 > > + * 1 0 Prohibited setting > > + * 1 1 40 / 2 x160 x120 x160 x160 x106 /38 > > + */ > > +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ > > + (((md) & BIT(13)) >> 13)) > > + > > +static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = { > > + /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */ > > + { 1, 200, 1, 150, 1, 200, 1, 200, 1, 134, 1, 16, }, > > OSC prediv is 15? Thank you for the indicate. I'll fix it. > > + { 1, 160, 1, 120, 1, 160, 1, 160, 1, 106, 1, 19, }, > > + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, > > + { 2, 160, 1, 120, 1, 160, 1, 160, 1, 106, 1, 38, }, > > +}; > > > --- /dev/null > > +++ b/drivers/clk/renesas/rcar-gen4-cpg.c > > @@ -0,0 +1,141 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * R-Car Gen4 Clock Pulse Generator > > + * > > + * Copyright (C) 2021 Renesas Electronics Corp. > > + * > > + * Based on rcar-gen3-cpg.c > > + * > > + * Copyright (C) 2015-2018 Glider bvba > > + * Copyright (C) 2019 Renesas Electronics Corp. > > + */ > > + > > +#include <linux/bug.h> > > +#include <linux/bitfield.h> > > +#include <linux/clk.h> > > +#include <linux/clk-provider.h> > > +#include <linux/device.h> > > +#include <linux/err.h> > > +#include <linux/init.h> > > +#include <linux/io.h> > > +#include <linux/pm.h> > > +#include <linux/slab.h> > > +#include <linux/sys_soc.h> > > Several of these includes are not needed. I got it. I'll remove unnecessary header files. > > + > > +#include "renesas-cpg-mssr.h" > > +#include "rcar-gen4-cpg.h" > > +#include "rcar-cpg-lib.h" > > + > > +static const struct clk_div_table cpg_rpcsrc_div_table[] = { > > + { 2, 5 }, { 3, 6 }, { 0, 0 }, > > The datasheet says { 0, 4 } and { 1, 6} are also supported, > just like on R-Car V3U. I got it. > > +}; > > > +struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev, > > + const struct cpg_core_clk *core, const struct cpg_mssr_info *info, > > + struct clk **clks, void __iomem *base, > > + struct raw_notifier_head *notifiers) > > +{ > > + const struct clk *parent; > > + unsigned int mult = 1; > > + unsigned int div = 1; > > + > > + parent = clks[core->parent & 0xffff]; /* some types use high bits */ > > + if (IS_ERR(parent)) > > + return ERR_CAST(parent); > > + > > + switch (core->type) { > > + case CLK_TYPE_GEN4_MAIN: > > + div = cpg_pll_config->extal_div; > > + break; > > + > > + case CLK_TYPE_GEN4_PLL1: > > + mult = cpg_pll_config->pll1_mult; > > + div = cpg_pll_config->pll1_div; > > + break; > > + > > + case CLK_TYPE_GEN4_PLL2: > > + mult = cpg_pll_config->pll2_mult; > > + div = cpg_pll_config->pll2_div; > > + break; > > + > > + case CLK_TYPE_GEN4_PLL3: > > + mult = cpg_pll_config->pll3_mult; > > + div = cpg_pll_config->pll3_div; > > + break; > > + > > + case CLK_TYPE_GEN4_PLL5: > > + mult = cpg_pll_config->pll5_mult; > > + div = cpg_pll_config->pll5_div; > > + break; > > + > > + case CLK_TYPE_GEN4_PLL6: > > + mult = cpg_pll_config->pll6_mult; > > + div = cpg_pll_config->pll6_div; > > + break; > > The Z clock handling for R-Car S4-8 seems to be the same as for R-Car > V3U, so you can move that here, too. > > That leaves us with the different PLLn handling: > 1. I think you can just move the PLL2X_3C clock type for R-Car > V3U here, too. It's only 4 lines of code. Then rcar-gen4-cpg.c > can be shared by R-Car V3U and R-Car S4-8. I got it. I'll modify it. > 2. Future full PLLn handling for R-Car S4-8 (using the PLLnCR1 > registers) will need switching from CLK_TYPE_GEN4_PLLn to a > new clock type anyway. I got it. > > + case CLK_TYPE_GEN4_SD: > > + return cpg_sd_clk_register(core->name, base, core->offset, > > + __clk_get_name(parent), notifiers, > > + 0); > > This should be changed to: > > return cpg_sd_clk_register(core->name, base + core->offset, > __clk_get_name(parent)); > > due to the recent changes in renesas-clk to handle the SDH clock. Thank you for the comment. I'll rebase it on the recent renesas-clk. > > + > > + default: > > + return ERR_PTR(-EINVAL); > > + } > > + > > + return clk_register_fixed_factor(NULL, core->name, > > + __clk_get_name(parent), 0, mult, div); > > +} > > > --- /dev/null > > +++ b/drivers/clk/renesas/rcar-gen4-cpg.h > > @@ -0,0 +1,76 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * R-Car Gen4 Clock Pulse Generator > > + * > > + * Copyright (C) 2021 Renesas Electronics Corp. > > + * > > + */ > > + > > +#ifndef __CLK_RENESAS_RCAR_GEN4_CPG_H__ > > +#define __CLK_RENESAS_RCAR_GEN4_CPG_H__ > > + > > +enum rcar_gen4_clk_types { > > + CLK_TYPE_GEN4_MAIN = CLK_TYPE_CUSTOM, > > + CLK_TYPE_GEN4_PLL1, > > + CLK_TYPE_GEN4_PLL2, > > + CLK_TYPE_GEN4_PLL3, > > + CLK_TYPE_GEN4_PLL5, > > + CLK_TYPE_GEN4_PLL6, > > + CLK_TYPE_GEN4_SD, > > + CLK_TYPE_GEN4_R, > > So far unused. I'll remove CLK_TYPE_GEN4_R. > > + CLK_TYPE_GEN4_MDSEL, /* Select parent/divider using mode pin */ > > + CLK_TYPE_GEN4_Z, > > + CLK_TYPE_GEN4_ZG, > > Both unused. I'll remove CLK_TYPE_GEN4_Z[G]. > > + CLK_TYPE_GEN4_OSC, /* OSC EXTAL predivider and fixed divider */ > > + CLK_TYPE_GEN4_RPCSRC, > > + CLK_TYPE_GEN4_RPC, > > + CLK_TYPE_GEN4_RPCD2, > > + > > + /* SoC specific definitions start here */ > > + CLK_TYPE_GEN4_SOC_BASE, > > +}; > > + > > +#define DEF_GEN4_SD(_name, _id, _parent, _offset) \ > > + DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset) > > + > > +#define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ > > + DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL, \ > > + (_parent0) << 16 | (_parent1), \ > > + .div = (_div0) << 16 | (_div1), .offset = _md) > > + > > +#define DEF_GEN4_PE(_name, _id, _parent_clean, _div_clean, _parent_sscg, \ > > + _div_sscg) \ > > + DEF_GEN4_MDSEL(_name, _id, 12, _parent_clean, _div_clean, \ > > + _parent_sscg, _div_sscg) > > R-Car S4 does not have a PE clock, so please drop this. I got it. Best regards, Yoshihiro Shimoda ^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 12/16] clk: renesas: cpg-mssr: Add support for R-Car S4-8 2021-11-29 8:35 ` Yoshihiro Shimoda @ 2021-11-29 8:47 ` Geert Uytterhoeven 0 siblings, 0 replies; 47+ messages in thread From: Geert Uytterhoeven @ 2021-11-29 8:47 UTC (permalink / raw) To: Yoshihiro Shimoda Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS Hi Shimoda-san, On Mon, Nov 29, 2021 at 9:36 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > > From: Geert Uytterhoeven, Sent: Wednesday, November 24, 2021 10:48 PM > > On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda > > <yoshihiro.shimoda.uh@renesas.com> wrote: > > > Initial support for R-Car S4-8 (r8a779f0), including core, module > > > clocks, resets, and register access, because register specification > > > differs from R-Car Gen2/3. The register layout of V3U is a similar > > > with R-Car S4-8 so that renames CLK_REG_LAYOUT_RCAR_V3U as > > > CLK_REG_LAYOUT_RCAR_GEN4. However, PLL names differ between V3U > > > and S4-8. > > > > > > Inspired by patches in the BSP by LUU HOAI. > > > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > > > + > > > + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), > > > + DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1), > > > + DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1), > > > + DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1), > > > + DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1), > > > + DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1), > > > + DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), > > > + DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL5_DIV2, 2, 1), > > > > This relies on the default setting of the SD-IF0 Clock Frequency > > Control Register 1 (SD0CKCR1)? > > You're correct. So, we should not use DEF_FIXED for SDSRC... You can use DEF_FIXED in the initial version, and add proper SD0CKCR1 support later. This is similar to the handling of the various PLLs: currently they're treated as fixed ratio clocks, later they can become programmable by adding support for the PLLnCR1 registers. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH 13/16] tty: serial: sh-sci: Add support for R-Car Gen4 2021-11-16 7:41 [PATCH 00/16] treewide: Initial support for R-Car S4-8 Yoshihiro Shimoda ` (11 preceding siblings ...) 2021-11-16 7:41 ` [PATCH 12/16] clk: renesas: cpg-mssr: " Yoshihiro Shimoda @ 2021-11-16 7:41 ` Yoshihiro Shimoda 2021-11-18 19:11 ` Geert Uytterhoeven 2021-11-16 7:41 ` [PATCH 14/16] arm64: dts: renesas: Add Renesas R8A779F0 SoC support Yoshihiro Shimoda ` (2 subsequent siblings) 15 siblings, 1 reply; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-11-16 7:41 UTC (permalink / raw) To: geert+renesas, magnus.damm, robh+dt, gregkh, jirislaby Cc: linux-renesas-soc, devicetree, linux-serial, Yoshihiro Shimoda Add serial support for R-Car Gen4 SoC. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- drivers/tty/serial/sh-sci.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 89ee43061d3a..55f5b96663b9 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -3180,6 +3180,9 @@ static const struct of_device_id of_sci_match[] = { }, { .compatible = "renesas,rcar-gen3-scif", .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), + }, { + .compatible = "renesas,rcar-gen4-scif", + .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), }, /* Generic types */ { -- 2.25.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH 13/16] tty: serial: sh-sci: Add support for R-Car Gen4 2021-11-16 7:41 ` [PATCH 13/16] tty: serial: sh-sci: Add support for R-Car Gen4 Yoshihiro Shimoda @ 2021-11-18 19:11 ` Geert Uytterhoeven 0 siblings, 0 replies; 47+ messages in thread From: Geert Uytterhoeven @ 2021-11-18 19:11 UTC (permalink / raw) To: Yoshihiro Shimoda Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > Add serial support for R-Car Gen4 SoC. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH 14/16] arm64: dts: renesas: Add Renesas R8A779F0 SoC support 2021-11-16 7:41 [PATCH 00/16] treewide: Initial support for R-Car S4-8 Yoshihiro Shimoda ` (12 preceding siblings ...) 2021-11-16 7:41 ` [PATCH 13/16] tty: serial: sh-sci: Add support for R-Car Gen4 Yoshihiro Shimoda @ 2021-11-16 7:41 ` Yoshihiro Shimoda 2021-11-24 14:02 ` Geert Uytterhoeven 2021-11-16 7:41 ` [PATCH 15/16] arm64: dts: renesas: Add Renesas Spider boards support Yoshihiro Shimoda 2021-11-16 7:41 ` [PATCH 16/16] arm64: defconfig: Enable R-Car S4-8 Yoshihiro Shimoda 15 siblings, 1 reply; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-11-16 7:41 UTC (permalink / raw) To: geert+renesas, magnus.damm, robh+dt, gregkh, jirislaby Cc: linux-renesas-soc, devicetree, linux-serial, Yoshihiro Shimoda Add initial support for the Renesas R8A779F0 (R-Car S4-8) support. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 121 ++++++++++++++++++++++ 1 file changed, 121 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779f0.dtsi diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi new file mode 100644 index 000000000000..eda597766eaf --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* + * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include <dt-bindings/clock/r8a779f0-cpg-mssr.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/r8a779f0-sysc.h> + +/ { + compatible = "renesas,r8a779f0"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a55_0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + pmu_a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a779f0-cpg-mssr"; + reg = <0 0xe6150000 0 0x4000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a779f0-rst"; + reg = <0 0xe6160000 0 0x4000>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a779f0-sysc"; + reg = <0 0xe6180000 0 0x4000>; + #power-domain-cells = <1>; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a779f0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 704>, + <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + }; + + gic: interrupt-controller@f1000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1000000 0 0x20000>, + <0x0 0xf1060000 0 0x110000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; -- 2.25.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH 14/16] arm64: dts: renesas: Add Renesas R8A779F0 SoC support 2021-11-16 7:41 ` [PATCH 14/16] arm64: dts: renesas: Add Renesas R8A779F0 SoC support Yoshihiro Shimoda @ 2021-11-24 14:02 ` Geert Uytterhoeven 0 siblings, 0 replies; 47+ messages in thread From: Geert Uytterhoeven @ 2021-11-24 14:02 UTC (permalink / raw) To: Yoshihiro Shimoda Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > Add initial support for the Renesas R8A779F0 (R-Car S4-8) support. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH 15/16] arm64: dts: renesas: Add Renesas Spider boards support 2021-11-16 7:41 [PATCH 00/16] treewide: Initial support for R-Car S4-8 Yoshihiro Shimoda ` (13 preceding siblings ...) 2021-11-16 7:41 ` [PATCH 14/16] arm64: dts: renesas: Add Renesas R8A779F0 SoC support Yoshihiro Shimoda @ 2021-11-16 7:41 ` Yoshihiro Shimoda 2021-11-24 14:06 ` Geert Uytterhoeven 2021-11-16 7:41 ` [PATCH 16/16] arm64: defconfig: Enable R-Car S4-8 Yoshihiro Shimoda 15 siblings, 1 reply; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-11-16 7:41 UTC (permalink / raw) To: geert+renesas, magnus.damm, robh+dt, gregkh, jirislaby Cc: linux-renesas-soc, devicetree, linux-serial, Yoshihiro Shimoda, Takehito Nakamura Initial support for the Renesas Spider CPU and BreakOut boards support. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Takehito Nakamura <takehito.nakamura.nx@renesas.com> --- arch/arm64/boot/dts/renesas/Makefile | 2 ++ .../boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 36 +++++++++++++++++++ .../boot/dts/renesas/r8a779f0-spider.dts | 22 ++++++++++++ 3 files changed, 60 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r8a779f0-spider.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index d1c5c21d8d14..5bc8065a7864 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -63,6 +63,8 @@ dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb +dtb-$(CONFIG_ARCH_R8A779F0) += r8a779f0-spider.dtb + dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb.dtb dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb-kf.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi new file mode 100644 index 000000000000..156586532c84 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* + * Device Tree Source for the Spider CPU board + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include "r8a779f0.dtsi" + +/ { + model = "Renesas Spider CPU board"; + compatible = "renesas,spider-cpu", "renesas,r8a779f0"; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@480000000 { + device_type = "memory"; + reg = <0x4 0x80000000 0x0 0x80000000>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&scif3 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts new file mode 100644 index 000000000000..f286254b41d8 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* + * Device Tree Source for the Spider CPU and BreakOut boards + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a779f0-spider-cpu.dtsi" + +/ { + model = "Renesas Spider CPU and Breakout boards based on r8a779f0"; + compatible = "renesas,spider-breakout", "renesas,spider-cpu", "renesas,r8a779f0"; + + aliases { + serial0 = &scif3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; -- 2.25.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH 15/16] arm64: dts: renesas: Add Renesas Spider boards support 2021-11-16 7:41 ` [PATCH 15/16] arm64: dts: renesas: Add Renesas Spider boards support Yoshihiro Shimoda @ 2021-11-24 14:06 ` Geert Uytterhoeven 2021-12-08 9:21 ` Geert Uytterhoeven 0 siblings, 1 reply; 47+ messages in thread From: Geert Uytterhoeven @ 2021-11-24 14:06 UTC (permalink / raw) To: Yoshihiro Shimoda Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS, Takehito Nakamura On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > Initial support for the Renesas Spider CPU and BreakOut boards > support. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > Tested-by: Takehito Nakamura <takehito.nakamura.nx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> (assuming memory size, extal clock frequency, and serial console port are correct) Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 15/16] arm64: dts: renesas: Add Renesas Spider boards support 2021-11-24 14:06 ` Geert Uytterhoeven @ 2021-12-08 9:21 ` Geert Uytterhoeven 2021-12-08 9:36 ` Yoshihiro Shimoda 0 siblings, 1 reply; 47+ messages in thread From: Geert Uytterhoeven @ 2021-12-08 9:21 UTC (permalink / raw) To: Yoshihiro Shimoda Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS, Takehito Nakamura Hi Shimoda-san, On Wed, Nov 24, 2021 at 3:06 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda > <yoshihiro.shimoda.uh@renesas.com> wrote: > > Initial support for the Renesas Spider CPU and BreakOut boards > > support. > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > > Tested-by: Takehito Nakamura <takehito.nakamura.nx@renesas.com> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > (assuming memory size, extal clock frequency, and serial console port > are correct) (with the schematics) So the console is actually SCIF3 pinmuxed to the HSCIF0 pins on the Debug Serial USB connector on the CPU board? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 47+ messages in thread
* RE: [PATCH 15/16] arm64: dts: renesas: Add Renesas Spider boards support 2021-12-08 9:21 ` Geert Uytterhoeven @ 2021-12-08 9:36 ` Yoshihiro Shimoda 0 siblings, 0 replies; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-12-08 9:36 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS, Takehito Nakamura Hi Geert-san, > From: Geert Uytterhoeven, Sent: Wednesday, December 8, 2021 6:21 PM > > Hi Shimoda-san, > > On Wed, Nov 24, 2021 at 3:06 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda > > <yoshihiro.shimoda.uh@renesas.com> wrote: > > > Initial support for the Renesas Spider CPU and BreakOut boards > > > support. > > > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > > > Tested-by: Takehito Nakamura <takehito.nakamura.nx@renesas.com> > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > (assuming memory size, extal clock frequency, and serial console port > > are correct) > > (with the schematics) > So the console is actually SCIF3 pinmuxed to the HSCIF0 pins on the > Debug Serial USB connector on the CPU board? Yes, the console is SCIF3. Best regards, Yoshihiro Shimoda ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH 16/16] arm64: defconfig: Enable R-Car S4-8 2021-11-16 7:41 [PATCH 00/16] treewide: Initial support for R-Car S4-8 Yoshihiro Shimoda ` (14 preceding siblings ...) 2021-11-16 7:41 ` [PATCH 15/16] arm64: dts: renesas: Add Renesas Spider boards support Yoshihiro Shimoda @ 2021-11-16 7:41 ` Yoshihiro Shimoda 2021-11-24 14:03 ` Geert Uytterhoeven 15 siblings, 1 reply; 47+ messages in thread From: Yoshihiro Shimoda @ 2021-11-16 7:41 UTC (permalink / raw) To: geert+renesas, magnus.damm, robh+dt, gregkh, jirislaby Cc: linux-renesas-soc, devicetree, linux-serial, Yoshihiro Shimoda Enable the Renesas R-Car S4-8 (R8A779F0) SoC in the ARM64 defconfig. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index f2e2b9bdd702..04db99bfbf9d 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1069,6 +1069,7 @@ CONFIG_ARCH_R8A77980=y CONFIG_ARCH_R8A77990=y CONFIG_ARCH_R8A77995=y CONFIG_ARCH_R8A779A0=y +CONFIG_ARCH_R8A779F0=y CONFIG_ARCH_R9A07G044=y CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_ARCH_TEGRA_132_SOC=y -- 2.25.1 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH 16/16] arm64: defconfig: Enable R-Car S4-8 2021-11-16 7:41 ` [PATCH 16/16] arm64: defconfig: Enable R-Car S4-8 Yoshihiro Shimoda @ 2021-11-24 14:03 ` Geert Uytterhoeven 0 siblings, 0 replies; 47+ messages in thread From: Geert Uytterhoeven @ 2021-11-24 14:03 UTC (permalink / raw) To: Yoshihiro Shimoda Cc: Magnus Damm, Rob Herring, Greg KH, Jiri Slaby, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list:SERIAL DRIVERS On Tue, Nov 16, 2021 at 8:43 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > Enable the Renesas R-Car S4-8 (R8A779F0) SoC in the ARM64 defconfig. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 47+ messages in thread
end of thread, other threads:[~2021-12-08 9:36 UTC | newest] Thread overview: 47+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-11-16 7:41 [PATCH 00/16] treewide: Initial support for R-Car S4-8 Yoshihiro Shimoda 2021-11-16 7:41 ` [PATCH 01/16] dt-bindings: arm: renesas: Document R-Car S4-8 SoC DT bindings Yoshihiro Shimoda 2021-11-18 17:50 ` Geert Uytterhoeven 2021-11-16 7:41 ` [PATCH 02/16] dt-bindings: arm: renesas: Document Renesas Spider boards Yoshihiro Shimoda 2021-11-16 14:02 ` Rob Herring 2021-11-18 17:53 ` Geert Uytterhoeven 2021-11-19 2:14 ` Yoshihiro Shimoda 2021-11-16 7:41 ` [PATCH 03/16] dt-bindings: reset: renesas,rst: Document r8a779f0 reset module Yoshihiro Shimoda 2021-11-18 18:19 ` Geert Uytterhoeven 2021-11-16 7:41 ` [PATCH 04/16] dt-bindings: power: renesas,rcar-sysc: Document r8a779f0 SYSC bindings Yoshihiro Shimoda 2021-11-18 18:38 ` Geert Uytterhoeven 2021-11-16 7:41 ` [PATCH 05/16] dt-bindings: power: Add r8a779f0 SYSC power domain definitions Yoshihiro Shimoda 2021-11-18 18:42 ` Geert Uytterhoeven 2021-11-19 2:16 ` Yoshihiro Shimoda 2021-11-16 7:41 ` [PATCH 06/16] dt-bindings: clock: renesas,cpg-mssr: Document r8a779f0 Yoshihiro Shimoda 2021-11-18 18:43 ` Geert Uytterhoeven 2021-11-16 7:41 ` [PATCH 07/16] dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions Yoshihiro Shimoda 2021-11-18 18:53 ` Geert Uytterhoeven 2021-11-19 2:21 ` Yoshihiro Shimoda 2021-11-16 7:41 ` [PATCH 08/16] dt-bindings: serial: renesas,scif: Document r8a779f0 bindings Yoshihiro Shimoda 2021-11-18 18:56 ` Geert Uytterhoeven 2021-11-19 2:24 ` Yoshihiro Shimoda 2021-11-16 7:41 ` [PATCH 09/16] soc: renesas: Identify R-Car S4-8 Yoshihiro Shimoda 2021-11-18 19:03 ` Geert Uytterhoeven 2021-11-19 2:27 ` Yoshihiro Shimoda 2021-11-18 19:04 ` Geert Uytterhoeven 2021-11-19 2:32 ` Yoshihiro Shimoda 2021-11-16 7:41 ` [PATCH 10/16] soc: renesas: r8a779f0-sysc: Add r8a779f0 support Yoshihiro Shimoda 2021-11-23 16:18 ` Geert Uytterhoeven 2021-11-24 6:49 ` Yoshihiro Shimoda 2021-11-16 7:41 ` [PATCH 11/16] soc: renesas: rcar-rst: Add support for R-Car S4-8 Yoshihiro Shimoda 2021-11-18 19:10 ` Geert Uytterhoeven 2021-11-19 2:35 ` Yoshihiro Shimoda 2021-11-16 7:41 ` [PATCH 12/16] clk: renesas: cpg-mssr: " Yoshihiro Shimoda 2021-11-24 13:48 ` Geert Uytterhoeven 2021-11-29 8:35 ` Yoshihiro Shimoda 2021-11-29 8:47 ` Geert Uytterhoeven 2021-11-16 7:41 ` [PATCH 13/16] tty: serial: sh-sci: Add support for R-Car Gen4 Yoshihiro Shimoda 2021-11-18 19:11 ` Geert Uytterhoeven 2021-11-16 7:41 ` [PATCH 14/16] arm64: dts: renesas: Add Renesas R8A779F0 SoC support Yoshihiro Shimoda 2021-11-24 14:02 ` Geert Uytterhoeven 2021-11-16 7:41 ` [PATCH 15/16] arm64: dts: renesas: Add Renesas Spider boards support Yoshihiro Shimoda 2021-11-24 14:06 ` Geert Uytterhoeven 2021-12-08 9:21 ` Geert Uytterhoeven 2021-12-08 9:36 ` Yoshihiro Shimoda 2021-11-16 7:41 ` [PATCH 16/16] arm64: defconfig: Enable R-Car S4-8 Yoshihiro Shimoda 2021-11-24 14:03 ` Geert Uytterhoeven
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