* [PATCH 0/2] Add RZ/G2L Sound support @ 2021-08-14 13:55 Biju Das 2021-08-14 13:55 ` [PATCH 1/2] arm64: dts: renesas: r9a07g044: Add external audio clock nodes Biju Das 2021-08-14 13:55 ` [PATCH 2/2] arm64: dts: renesas: r9a07g044: Add SSI support Biju Das 0 siblings, 2 replies; 5+ messages in thread From: Biju Das @ 2021-08-14 13:55 UTC (permalink / raw) To: Rob Herring Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc, devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad This patch series aims to add RZ/G2L sound support by adding SSIF and audio clock nodes to SoC dtsi. Currently SSI interrupt support is added in SoC dtsi, later will add DMA support, once DMA patches accepted in mainline. This patches are tested(audio playback/record) with renesas-devel and is based upon[1] & [2] [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20210812151808.7916-3-biju.das.jz@bp.renesas.com/ [2] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20210812151808.7916-4-biju.das.jz@bp.renesas.com/ Biju Das (2): arm64: dts: renesas: r9a07g044: Add external audio clock nodes arm64: dts: renesas: r9a07g044: Add SSI support arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 94 ++++++++++++++++++++++ 1 file changed, 94 insertions(+) -- 2.17.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] arm64: dts: renesas: r9a07g044: Add external audio clock nodes 2021-08-14 13:55 [PATCH 0/2] Add RZ/G2L Sound support Biju Das @ 2021-08-14 13:55 ` Biju Das 2021-09-06 12:44 ` Geert Uytterhoeven 2021-08-14 13:55 ` [PATCH 2/2] arm64: dts: renesas: r9a07g044: Add SSI support Biju Das 1 sibling, 1 reply; 5+ messages in thread From: Biju Das @ 2021-08-14 13:55 UTC (permalink / raw) To: Rob Herring Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc, devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad Add external audio clocks nodes to RZ/G2L (a.k.a R9A07G044) SoC DTSI. The external audio clocks are configured as 0 Hz fixed frequency clocks by default. Boards that provide audio clocks should override them. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 2f313c2a81c7..6bbf1fae8ca5 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -13,6 +13,20 @@ #address-cells = <2>; #size-cells = <2>; + audio_clk1: audio_clk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by boards that provide it */ + clock-frequency = <0>; + }; + + audio_clk2: audio_clk2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by boards that provide it */ + clock-frequency = <0>; + }; + /* External CAN clock - to be overridden by boards that provide it */ can_clk: can { compatible = "fixed-clock"; -- 2.17.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] arm64: dts: renesas: r9a07g044: Add external audio clock nodes 2021-08-14 13:55 ` [PATCH 1/2] arm64: dts: renesas: r9a07g044: Add external audio clock nodes Biju Das @ 2021-09-06 12:44 ` Geert Uytterhoeven 0 siblings, 0 replies; 5+ messages in thread From: Geert Uytterhoeven @ 2021-09-06 12:44 UTC (permalink / raw) To: Biju Das Cc: Rob Herring, Magnus Damm, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Chris Paterson, Biju Das, Prabhakar Mahadev Lad On Sat, Aug 14, 2021 at 3:55 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > Add external audio clocks nodes to RZ/G2L (a.k.a R9A07G044) SoC DTSI. > > The external audio clocks are configured as 0 Hz fixed frequency clocks by > default. Boards that provide audio clocks should override them. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v5.16. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/2] arm64: dts: renesas: r9a07g044: Add SSI support 2021-08-14 13:55 [PATCH 0/2] Add RZ/G2L Sound support Biju Das 2021-08-14 13:55 ` [PATCH 1/2] arm64: dts: renesas: r9a07g044: Add external audio clock nodes Biju Das @ 2021-08-14 13:55 ` Biju Das 2021-09-06 12:44 ` Geert Uytterhoeven 1 sibling, 1 reply; 5+ messages in thread From: Biju Das @ 2021-08-14 13:55 UTC (permalink / raw) To: Rob Herring Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc, devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad Add SSI{0,1,2,3} nodes to RZ/G2L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 80 ++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 6bbf1fae8ca5..c8b517d235e3 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -92,6 +92,86 @@ #size-cells = <2>; ranges; + ssi0: ssi@10049c00 { + compatible = "renesas,r9a07g044-ssi", + "renesas,rz-ssi"; + reg = <0 0x10049c00 0 0x400>; + interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>, + <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>, + <&audio_clk1>, + <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G044_SSI0_RST_M2_REG>; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi1: ssi@1004a000 { + compatible = "renesas,r9a07g044-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a000 0 0x400>; + interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>, + <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>, + <&audio_clk1>, + <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G044_SSI1_RST_M2_REG>; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi2: ssi@1004a400 { + compatible = "renesas,r9a07g044-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a400 0 0x400>; + interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>, + <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>, + <&audio_clk1>, + <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G044_SSI2_RST_M2_REG>; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi3: ssi@1004a800 { + compatible = "renesas,r9a07g044-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a800 0 0x400>; + interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>, + <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>, + <&audio_clk1>, + <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G044_SSI3_RST_M2_REG>; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + scif0: serial@1004b800 { compatible = "renesas,scif-r9a07g044"; reg = <0 0x1004b800 0 0x400>; -- 2.17.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] arm64: dts: renesas: r9a07g044: Add SSI support 2021-08-14 13:55 ` [PATCH 2/2] arm64: dts: renesas: r9a07g044: Add SSI support Biju Das @ 2021-09-06 12:44 ` Geert Uytterhoeven 0 siblings, 0 replies; 5+ messages in thread From: Geert Uytterhoeven @ 2021-09-06 12:44 UTC (permalink / raw) To: Biju Das Cc: Rob Herring, Magnus Damm, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Chris Paterson, Biju Das, Prabhakar Mahadev Lad On Sat, Aug 14, 2021 at 3:55 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > Add SSI{0,1,2,3} nodes to RZ/G2L SoC DTSI. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v5.16. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-09-06 12:45 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-08-14 13:55 [PATCH 0/2] Add RZ/G2L Sound support Biju Das 2021-08-14 13:55 ` [PATCH 1/2] arm64: dts: renesas: r9a07g044: Add external audio clock nodes Biju Das 2021-09-06 12:44 ` Geert Uytterhoeven 2021-08-14 13:55 ` [PATCH 2/2] arm64: dts: renesas: r9a07g044: Add SSI support Biju Das 2021-09-06 12:44 ` Geert Uytterhoeven
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