* [PATCH 0/5] Add RZ/G2M SYSC/RST/Clock support
@ 2018-07-30 7:48 Biju Das
2018-07-30 7:48 ` [PATCH 1/5] dt-bindings: power: Add r8a774a1 SYSC power domain definitions Biju Das
` (4 more replies)
0 siblings, 5 replies; 15+ messages in thread
From: Biju Das @ 2018-07-30 7:48 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Biju Das, Simon Horman, Magnus Damm, linux-renesas-soc,
devicetree, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
This patch series aims to add SYSC/RST/Clock support for
for RZ/G2M SoC. RZ/G2M SoC is similar to R-Car Gen3 M3-W SoC.
Biju Das (5):
dt-bindings: power: Add r8a774a1 SYSC power domain definitions
soc: renesas: rcar-sysc: Add r8a774a1 support
soc: renesas: rcar-rst: Add support for RZ/G2M
clk: renesas: Add r8a774a1 CPG Core Clock Definitions
clk: renesas: cpg-mssr: Add r8a774a1 support
.../devicetree/bindings/clock/renesas,cpg-mssr.txt | 9 +-
.../bindings/power/renesas,rcar-sysc.txt | 1 +
.../devicetree/bindings/reset/renesas,rst.txt | 1 +
drivers/clk/renesas/Kconfig | 5 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r8a774a1-cpg-mssr.c | 322 +++++++++++++++++++++
drivers/clk/renesas/renesas-cpg-mssr.c | 6 +
drivers/clk/renesas/renesas-cpg-mssr.h | 1 +
drivers/soc/renesas/Kconfig | 11 +-
drivers/soc/renesas/Makefile | 1 +
drivers/soc/renesas/r8a774a1-sysc.c | 45 +++
drivers/soc/renesas/rcar-rst.c | 4 +-
drivers/soc/renesas/rcar-sysc.c | 3 +
drivers/soc/renesas/rcar-sysc.h | 1 +
include/dt-bindings/clock/r8a774a1-cpg-mssr.h | 59 ++++
include/dt-bindings/power/r8a774a1-sysc.h | 31 ++
16 files changed, 493 insertions(+), 8 deletions(-)
create mode 100644 drivers/clk/renesas/r8a774a1-cpg-mssr.c
create mode 100644 drivers/soc/renesas/r8a774a1-sysc.c
create mode 100644 include/dt-bindings/clock/r8a774a1-cpg-mssr.h
create mode 100644 include/dt-bindings/power/r8a774a1-sysc.h
--
2.7.4
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 1/5] dt-bindings: power: Add r8a774a1 SYSC power domain definitions 2018-07-30 7:48 [PATCH 0/5] Add RZ/G2M SYSC/RST/Clock support Biju Das @ 2018-07-30 7:48 ` Biju Das 2018-08-01 8:01 ` Geert Uytterhoeven 2018-07-30 7:48 ` [PATCH 2/5] soc: renesas: rcar-sysc: Add r8a774a1 support Biju Das ` (3 subsequent siblings) 4 siblings, 1 reply; 15+ messages in thread From: Biju Das @ 2018-07-30 7:48 UTC (permalink / raw) To: Rob Herring, Mark Rutland Cc: Biju Das, devicetree, Simon Horman, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro, linux-renesas-soc This patch adds power domain indices for RZ/G2M. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Chris Paterson <chris.paterson2@renesas.com> --- include/dt-bindings/power/r8a774a1-sysc.h | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 include/dt-bindings/power/r8a774a1-sysc.h diff --git a/include/dt-bindings/power/r8a774a1-sysc.h b/include/dt-bindings/power/r8a774a1-sysc.h new file mode 100644 index 0000000..580f431 --- /dev/null +++ b/include/dt-bindings/power/r8a774a1-sysc.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A774A1_PD_CA57_CPU0 0 +#define R8A774A1_PD_CA57_CPU1 1 +#define R8A774A1_PD_CA53_CPU0 5 +#define R8A774A1_PD_CA53_CPU1 6 +#define R8A774A1_PD_CA53_CPU2 7 +#define R8A774A1_PD_CA53_CPU3 8 +#define R8A774A1_PD_CA57_SCU 12 +#define R8A774A1_PD_A3VC 14 +#define R8A774A1_PD_3DG_A 17 +#define R8A774A1_PD_3DG_B 18 +#define R8A774A1_PD_CA53_SCU 21 +#define R8A774A1_PD_A2VC0 25 +#define R8A774A1_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A774A1_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ */ -- 2.7.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 1/5] dt-bindings: power: Add r8a774a1 SYSC power domain definitions 2018-07-30 7:48 ` [PATCH 1/5] dt-bindings: power: Add r8a774a1 SYSC power domain definitions Biju Das @ 2018-08-01 8:01 ` Geert Uytterhoeven 0 siblings, 0 replies; 15+ messages in thread From: Geert Uytterhoeven @ 2018-08-01 8:01 UTC (permalink / raw) To: Biju Das Cc: Rob Herring, Mark Rutland, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Simon Horman, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro, Linux-Renesas On Mon, Jul 30, 2018 at 9:54 AM Biju Das <biju.das@bp.renesas.com> wrote: > This patch adds power domain indices for RZ/G2M. > > Signed-off-by: Biju Das <biju.das@bp.renesas.com> > Reviewed-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/5] soc: renesas: rcar-sysc: Add r8a774a1 support 2018-07-30 7:48 [PATCH 0/5] Add RZ/G2M SYSC/RST/Clock support Biju Das 2018-07-30 7:48 ` [PATCH 1/5] dt-bindings: power: Add r8a774a1 SYSC power domain definitions Biju Das @ 2018-07-30 7:48 ` Biju Das 2018-08-01 8:05 ` Geert Uytterhoeven 2018-07-30 7:48 ` [PATCH 3/5] soc: renesas: rcar-rst: Add support for RZ/G2M Biju Das ` (2 subsequent siblings) 4 siblings, 1 reply; 15+ messages in thread From: Biju Das @ 2018-07-30 7:48 UTC (permalink / raw) To: Rob Herring, Mark Rutland Cc: Biju Das, Simon Horman, Magnus Damm, Geert Uytterhoeven, Vladimir Barinov, Sergei Shtylyov, Takeshi Kihara, Jacopo Mondi, devicetree, linux-renesas-soc, Chris Paterson, Fabrizio Castro Add support for RZ/G2M (R8A774A1) SoC power areas to the R-Car SYSC driver. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Chris Paterson <chris.paterson2@renesas.com> --- .../bindings/power/renesas,rcar-sysc.txt | 1 + drivers/soc/renesas/Kconfig | 5 +++ drivers/soc/renesas/Makefile | 1 + drivers/soc/renesas/r8a774a1-sysc.c | 45 ++++++++++++++++++++++ drivers/soc/renesas/rcar-sysc.c | 3 ++ drivers/soc/renesas/rcar-sysc.h | 1 + 6 files changed, 56 insertions(+) create mode 100644 drivers/soc/renesas/r8a774a1-sysc.c diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt index 180ae65..4e3ec6a 100644 --- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt +++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt @@ -10,6 +10,7 @@ Required properties: - "renesas,r8a7743-sysc" (RZ/G1M) - "renesas,r8a7745-sysc" (RZ/G1E) - "renesas,r8a77470-sysc" (RZ/G1C) + - "renesas,r8a774a1-sysc" (RZ/G2M) - "renesas,r8a7779-sysc" (R-Car H1) - "renesas,r8a7790-sysc" (R-Car H2) - "renesas,r8a7791-sysc" (R-Car M2-W) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 1d824cb..d769330 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -9,6 +9,7 @@ config SOC_RENESAS select SYSC_R8A7743 if ARCH_R8A7743 select SYSC_R8A7745 if ARCH_R8A7745 select SYSC_R8A77470 if ARCH_R8A77470 + select SYSC_R8A774A1 if ARCH_R8A774A1 select SYSC_R8A7779 if ARCH_R8A7779 select SYSC_R8A7790 if ARCH_R8A7790 select SYSC_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793 @@ -37,6 +38,10 @@ config SYSC_R8A77470 bool "RZ/G1C System Controller support" if COMPILE_TEST select SYSC_RCAR +config SYSC_R8A774A1 + bool "RZ/G2M System Controller support" if COMPILE_TEST + select SYSC_RCAR + config SYSC_R8A7779 bool "R-Car H1 System Controller support" if COMPILE_TEST select SYSC_RCAR diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index c37b080..6adb9d6 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_SOC_RENESAS) += renesas-soc.o obj-$(CONFIG_SYSC_R8A7743) += r8a7743-sysc.o obj-$(CONFIG_SYSC_R8A7745) += r8a7745-sysc.o obj-$(CONFIG_SYSC_R8A77470) += r8a77470-sysc.o +obj-$(CONFIG_SYSC_R8A774A1) += r8a774a1-sysc.o obj-$(CONFIG_SYSC_R8A7779) += r8a7779-sysc.o obj-$(CONFIG_SYSC_R8A7790) += r8a7790-sysc.o obj-$(CONFIG_SYSC_R8A7791) += r8a7791-sysc.o diff --git a/drivers/soc/renesas/r8a774a1-sysc.c b/drivers/soc/renesas/r8a774a1-sysc.c new file mode 100644 index 0000000..9db51ff --- /dev/null +++ b/drivers/soc/renesas/r8a774a1-sysc.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/G2M System Controller + * Copyright (C) 2018 Renesas Electronics Corp. + * + * Based on Renesas R-Car M3-W System Controller + * Copyright (C) 2016 Glider bvba + */ + +#include <linux/bug.h> +#include <linux/kernel.h> + +#include <dt-bindings/power/r8a774a1-sysc.h> + +#include "rcar-sysc.h" + +static const struct rcar_sysc_area r8a774a1_areas[] __initconst = { + { "always-on", 0, 0, R8A774A1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, + { "ca57-scu", 0x1c0, 0, R8A774A1_PD_CA57_SCU, R8A774A1_PD_ALWAYS_ON, + PD_SCU }, + { "ca57-cpu0", 0x80, 0, R8A774A1_PD_CA57_CPU0, R8A774A1_PD_CA57_SCU, + PD_CPU_NOCR }, + { "ca57-cpu1", 0x80, 1, R8A774A1_PD_CA57_CPU1, R8A774A1_PD_CA57_SCU, + PD_CPU_NOCR }, + { "ca53-scu", 0x140, 0, R8A774A1_PD_CA53_SCU, R8A774A1_PD_ALWAYS_ON, + PD_SCU }, + { "ca53-cpu0", 0x200, 0, R8A774A1_PD_CA53_CPU0, R8A774A1_PD_CA53_SCU, + PD_CPU_NOCR }, + { "ca53-cpu1", 0x200, 1, R8A774A1_PD_CA53_CPU1, R8A774A1_PD_CA53_SCU, + PD_CPU_NOCR }, + { "ca53-cpu2", 0x200, 2, R8A774A1_PD_CA53_CPU2, R8A774A1_PD_CA53_SCU, + PD_CPU_NOCR }, + { "ca53-cpu3", 0x200, 3, R8A774A1_PD_CA53_CPU3, R8A774A1_PD_CA53_SCU, + PD_CPU_NOCR }, + { "a3vc", 0x380, 0, R8A774A1_PD_A3VC, R8A774A1_PD_ALWAYS_ON }, + { "a2vc0", 0x3c0, 0, R8A774A1_PD_A2VC0, R8A774A1_PD_A3VC }, + { "a2vc1", 0x3c0, 1, R8A774A1_PD_A2VC1, R8A774A1_PD_A3VC }, + { "3dg-a", 0x100, 0, R8A774A1_PD_3DG_A, R8A774A1_PD_ALWAYS_ON }, + { "3dg-b", 0x100, 1, R8A774A1_PD_3DG_B, R8A774A1_PD_3DG_A }, +}; + +const struct rcar_sysc_info r8a774a1_sysc_info __initconst = { + .areas = r8a774a1_areas, + .num_areas = ARRAY_SIZE(r8a774a1_areas), +}; diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c index 029188e..fe32f7a 100644 --- a/drivers/soc/renesas/rcar-sysc.c +++ b/drivers/soc/renesas/rcar-sysc.c @@ -275,6 +275,9 @@ static const struct of_device_id rcar_sysc_matches[] __initconst = { #ifdef CONFIG_SYSC_R8A77470 { .compatible = "renesas,r8a77470-sysc", .data = &r8a77470_sysc_info }, #endif +#ifdef CONFIG_SYSC_R8A774A1 + { .compatible = "renesas,r8a774a1-sysc", .data = &r8a774a1_sysc_info }, +#endif #ifdef CONFIG_SYSC_R8A7779 { .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info }, #endif diff --git a/drivers/soc/renesas/rcar-sysc.h b/drivers/soc/renesas/rcar-sysc.h index a22e7cf..33defe6 100644 --- a/drivers/soc/renesas/rcar-sysc.h +++ b/drivers/soc/renesas/rcar-sysc.h @@ -52,6 +52,7 @@ struct rcar_sysc_info { extern const struct rcar_sysc_info r8a7743_sysc_info; extern const struct rcar_sysc_info r8a7745_sysc_info; extern const struct rcar_sysc_info r8a77470_sysc_info; +extern const struct rcar_sysc_info r8a774a1_sysc_info; extern const struct rcar_sysc_info r8a7779_sysc_info; extern const struct rcar_sysc_info r8a7790_sysc_info; extern const struct rcar_sysc_info r8a7791_sysc_info; -- 2.7.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 2/5] soc: renesas: rcar-sysc: Add r8a774a1 support 2018-07-30 7:48 ` [PATCH 2/5] soc: renesas: rcar-sysc: Add r8a774a1 support Biju Das @ 2018-08-01 8:05 ` Geert Uytterhoeven 0 siblings, 0 replies; 15+ messages in thread From: Geert Uytterhoeven @ 2018-08-01 8:05 UTC (permalink / raw) To: Biju Das Cc: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm, Geert Uytterhoeven, Vladimir Barinov, Sergei Shtylyov, Takeshi Kihara, Jacopo Mondi, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux-Renesas, Chris Paterson, Fabrizio Castro On Mon, Jul 30, 2018 at 9:54 AM Biju Das <biju.das@bp.renesas.com> wrote: > Add support for RZ/G2M (R8A774A1) SoC power areas to the R-Car SYSC > driver. > > Signed-off-by: Biju Das <biju.das@bp.renesas.com> > Reviewed-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 3/5] soc: renesas: rcar-rst: Add support for RZ/G2M 2018-07-30 7:48 [PATCH 0/5] Add RZ/G2M SYSC/RST/Clock support Biju Das 2018-07-30 7:48 ` [PATCH 1/5] dt-bindings: power: Add r8a774a1 SYSC power domain definitions Biju Das 2018-07-30 7:48 ` [PATCH 2/5] soc: renesas: rcar-sysc: Add r8a774a1 support Biju Das @ 2018-07-30 7:48 ` Biju Das 2018-08-01 8:46 ` Geert Uytterhoeven 2018-07-30 7:48 ` [PATCH 4/5] clk: renesas: Add r8a774a1 CPG Core Clock Definitions Biju Das 2018-07-30 7:48 ` [PATCH 5/5] clk: renesas: cpg-mssr: Add r8a774a1 support Biju Das 4 siblings, 1 reply; 15+ messages in thread From: Biju Das @ 2018-07-30 7:48 UTC (permalink / raw) To: Philipp Zabel, Rob Herring, Mark Rutland Cc: Biju Das, Simon Horman, Magnus Damm, devicetree, linux-renesas-soc, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Chris Paterson <chris.paterson2@renesas.com> --- Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 + drivers/soc/renesas/Kconfig | 6 +++--- drivers/soc/renesas/rcar-rst.c | 4 +++- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt index 67e83b0..e4fe0ab 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rst.txt +++ b/Documentation/devicetree/bindings/reset/renesas,rst.txt @@ -18,6 +18,7 @@ Required properties: - "renesas,r8a7743-rst" (RZ/G1M) - "renesas,r8a7745-rst" (RZ/G1E) - "renesas,r8a77470-rst" (RZ/G1C) + - "renesas,r8a774a1-rst" (RZ/G2M) - "renesas,r8a7778-reset-wdt" (R-Car M1A) - "renesas,r8a7779-reset-wdt" (R-Car H1) - "renesas,r8a7790-rst" (R-Car H2) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index d769330..00d4c9d 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -3,9 +3,9 @@ config SOC_RENESAS default y if ARCH_RENESAS select SOC_BUS select RST_RCAR if ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2 || \ - ARCH_R8A7795 || ARCH_R8A7796 || ARCH_R8A77965 || \ - ARCH_R8A77970 || ARCH_R8A77980 || ARCH_R8A77990 || \ - ARCH_R8A77995 + ARCH_R8A774A1 || ARCH_R8A7795 || ARCH_R8A7796 || \ + ARCH_R8A77965 || ARCH_R8A77970 || ARCH_R8A77980 || \ + ARCH_R8A77990 || ARCH_R8A77995 select SYSC_R8A7743 if ARCH_R8A7743 select SYSC_R8A7745 if ARCH_R8A7745 select SYSC_R8A77470 if ARCH_R8A77470 diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c index d9c1034..a447873 100644 --- a/drivers/soc/renesas/rcar-rst.c +++ b/drivers/soc/renesas/rcar-rst.c @@ -41,10 +41,12 @@ static const struct rst_config rcar_rst_gen3 __initconst = { }; static const struct of_device_id rcar_rst_matches[] __initconst = { - /* RZ/G is handled like R-Car Gen2 */ + /* RZ/G1 is handled like R-Car Gen2 */ { .compatible = "renesas,r8a7743-rst", .data = &rcar_rst_gen2 }, { .compatible = "renesas,r8a7745-rst", .data = &rcar_rst_gen2 }, { .compatible = "renesas,r8a77470-rst", .data = &rcar_rst_gen2 }, + /* RZ/G2 is handled like R-Car Gen3 */ + { .compatible = "renesas,r8a774a1-rst", .data = &rcar_rst_gen3 }, /* R-Car Gen1 */ { .compatible = "renesas,r8a7778-reset-wdt", .data = &rcar_rst_gen1 }, { .compatible = "renesas,r8a7779-reset-wdt", .data = &rcar_rst_gen1 }, -- 2.7.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 3/5] soc: renesas: rcar-rst: Add support for RZ/G2M 2018-07-30 7:48 ` [PATCH 3/5] soc: renesas: rcar-rst: Add support for RZ/G2M Biju Das @ 2018-08-01 8:46 ` Geert Uytterhoeven 0 siblings, 0 replies; 15+ messages in thread From: Geert Uytterhoeven @ 2018-08-01 8:46 UTC (permalink / raw) To: Biju Das Cc: Philipp Zabel, Rob Herring, Mark Rutland, Simon Horman, Magnus Damm, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux-Renesas, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro On Mon, Jul 30, 2018 at 9:54 AM Biju Das <biju.das@bp.renesas.com> wrote: > Signed-off-by: Biju Das <biju.das@bp.renesas.com> > Reviewed-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 4/5] clk: renesas: Add r8a774a1 CPG Core Clock Definitions 2018-07-30 7:48 [PATCH 0/5] Add RZ/G2M SYSC/RST/Clock support Biju Das ` (2 preceding siblings ...) 2018-07-30 7:48 ` [PATCH 3/5] soc: renesas: rcar-rst: Add support for RZ/G2M Biju Das @ 2018-07-30 7:48 ` Biju Das 2018-08-01 8:46 ` Geert Uytterhoeven 2018-07-30 7:48 ` [PATCH 5/5] clk: renesas: cpg-mssr: Add r8a774a1 support Biju Das 4 siblings, 1 reply; 15+ messages in thread From: Biju Das @ 2018-07-30 7:48 UTC (permalink / raw) To: Rob Herring, Mark Rutland Cc: Biju Das, devicetree, Simon Horman, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro, linux-renesas-soc Add all RZ/G2M Clock Pulse Generator Core Clock Outputs, as listed in Table 8.2b ("List of Clocks [RZ/G2M]") of the RZ/G2M Hardware User's Manual. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> --- include/dt-bindings/clock/r8a774a1-cpg-mssr.h | 59 +++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 include/dt-bindings/clock/r8a774a1-cpg-mssr.h diff --git a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h new file mode 100644 index 0000000..144c341 --- /dev/null +++ b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a774a1 CPG Core Clocks */ +#define R8A774A1_CLK_Z 0 +#define R8A774A1_CLK_Z2 1 +#define R8A774A1_CLK_ZG 2 +#define R8A774A1_CLK_ZTR 3 +#define R8A774A1_CLK_ZTRD2 4 +#define R8A774A1_CLK_ZT 5 +#define R8A774A1_CLK_ZX 6 +#define R8A774A1_CLK_S0D1 7 +#define R8A774A1_CLK_S0D2 8 +#define R8A774A1_CLK_S0D3 9 +#define R8A774A1_CLK_S0D4 10 +#define R8A774A1_CLK_S0D6 11 +#define R8A774A1_CLK_S0D8 12 +#define R8A774A1_CLK_S0D12 13 +#define R8A774A1_CLK_S1D2 14 +#define R8A774A1_CLK_S1D4 15 +#define R8A774A1_CLK_S2D1 16 +#define R8A774A1_CLK_S2D2 17 +#define R8A774A1_CLK_S2D4 18 +#define R8A774A1_CLK_S3D1 19 +#define R8A774A1_CLK_S3D2 20 +#define R8A774A1_CLK_S3D4 21 +#define R8A774A1_CLK_LB 22 +#define R8A774A1_CLK_CL 23 +#define R8A774A1_CLK_ZB3 24 +#define R8A774A1_CLK_ZB3D2 25 +#define R8A774A1_CLK_ZB3D4 26 +#define R8A774A1_CLK_CR 27 +#define R8A774A1_CLK_CRD2 28 +#define R8A774A1_CLK_SD0H 29 +#define R8A774A1_CLK_SD0 30 +#define R8A774A1_CLK_SD1H 31 +#define R8A774A1_CLK_SD1 32 +#define R8A774A1_CLK_SD2H 33 +#define R8A774A1_CLK_SD2 34 +#define R8A774A1_CLK_SD3H 35 +#define R8A774A1_CLK_SD3 36 +#define R8A774A1_CLK_RPC 37 +#define R8A774A1_CLK_RPCD2 38 +#define R8A774A1_CLK_MSO 39 +#define R8A774A1_CLK_HDMI 40 +#define R8A774A1_CLK_CSI0 41 +#define R8A774A1_CLK_CP 42 +#define R8A774A1_CLK_POST2 43 +#define R8A774A1_CLK_CPEX 44 +#define R8A774A1_CLK_R 45 +#define R8A774A1_CLK_OSC 46 + +#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */ -- 2.7.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 4/5] clk: renesas: Add r8a774a1 CPG Core Clock Definitions 2018-07-30 7:48 ` [PATCH 4/5] clk: renesas: Add r8a774a1 CPG Core Clock Definitions Biju Das @ 2018-08-01 8:46 ` Geert Uytterhoeven 2018-08-01 9:33 ` Biju Das 0 siblings, 1 reply; 15+ messages in thread From: Geert Uytterhoeven @ 2018-08-01 8:46 UTC (permalink / raw) To: Biju Das Cc: Rob Herring, Mark Rutland, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Simon Horman, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro, Linux-Renesas Hi Biju, On Mon, Jul 30, 2018 at 9:54 AM Biju Das <biju.das@bp.renesas.com> wrote: > Add all RZ/G2M Clock Pulse Generator Core Clock Outputs, as listed in > Table 8.2b ("List of Clocks [RZ/G2M]") of the RZ/G2M Hardware User's > Manual. > > Signed-off-by: Biju Das <biju.das@bp.renesas.com> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Thanks for your patch! > --- /dev/null > +++ b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h > @@ -0,0 +1,59 @@ > +/* SPDX-License-Identifier: GPL-2.0 > + * > + * Copyright (C) 2018 Renesas Electronics Corp. > + */ > +#ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ > +#define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ > + > +#include <dt-bindings/clock/renesas-cpg-mssr.h> > + > +/* r8a774a1 CPG Core Clocks */ > +#define R8A774A1_CLK_Z 0 > +#define R8A774A1_CLK_Z2 1 > +#define R8A774A1_CLK_ZG 2 > +#define R8A774A1_CLK_ZTR 3 > +#define R8A774A1_CLK_ZTRD2 4 > +#define R8A774A1_CLK_ZT 5 > +#define R8A774A1_CLK_ZX 6 > +#define R8A774A1_CLK_S0D1 7 > +#define R8A774A1_CLK_S0D2 8 > +#define R8A774A1_CLK_S0D3 9 > +#define R8A774A1_CLK_S0D4 10 > +#define R8A774A1_CLK_S0D6 11 > +#define R8A774A1_CLK_S0D8 12 > +#define R8A774A1_CLK_S0D12 13 > +#define R8A774A1_CLK_S1D2 14 > +#define R8A774A1_CLK_S1D4 15 > +#define R8A774A1_CLK_S2D1 16 > +#define R8A774A1_CLK_S2D2 17 > +#define R8A774A1_CLK_S2D4 18 > +#define R8A774A1_CLK_S3D1 19 > +#define R8A774A1_CLK_S3D2 20 > +#define R8A774A1_CLK_S3D4 21 > +#define R8A774A1_CLK_LB 22 > +#define R8A774A1_CLK_CL 23 > +#define R8A774A1_CLK_ZB3 24 > +#define R8A774A1_CLK_ZB3D2 25 > +#define R8A774A1_CLK_ZB3D4 26 > +#define R8A774A1_CLK_CR 27 > +#define R8A774A1_CLK_CRD2 28 > +#define R8A774A1_CLK_SD0H 29 > +#define R8A774A1_CLK_SD0 30 > +#define R8A774A1_CLK_SD1H 31 > +#define R8A774A1_CLK_SD1 32 > +#define R8A774A1_CLK_SD2H 33 > +#define R8A774A1_CLK_SD2 34 > +#define R8A774A1_CLK_SD3H 35 > +#define R8A774A1_CLK_SD3 36 > +#define R8A774A1_CLK_RPC 37 > +#define R8A774A1_CLK_RPCD2 38 > +#define R8A774A1_CLK_MSO 39 > +#define R8A774A1_CLK_HDMI 40 > +#define R8A774A1_CLK_CSI0 41 > +#define R8A774A1_CLK_CP 42 > +#define R8A774A1_CLK_POST2 43 POST2 is an internal clock, which doesn't need to be referred to from DT. So please drop it from the bindings. > +#define R8A774A1_CLK_CPEX 44 > +#define R8A774A1_CLK_R 45 > +#define R8A774A1_CLK_OSC 46 With the above fixed: Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH 4/5] clk: renesas: Add r8a774a1 CPG Core Clock Definitions 2018-08-01 8:46 ` Geert Uytterhoeven @ 2018-08-01 9:33 ` Biju Das 0 siblings, 0 replies; 15+ messages in thread From: Biju Das @ 2018-08-01 9:33 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Rob Herring, Mark Rutland, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Simon Horman, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro, Linux-Renesas Hi Geert, Thanks for the feedback. > Subject: Re: [PATCH 4/5] clk: renesas: Add r8a774a1 CPG Core Clock > Definitions > > Hi Biju, > > On Mon, Jul 30, 2018 at 9:54 AM Biju Das <biju.das@bp.renesas.com> wrote: > > Add all RZ/G2M Clock Pulse Generator Core Clock Outputs, as listed in > > Table 8.2b ("List of Clocks [RZ/G2M]") of the RZ/G2M Hardware User's > > Manual. > > > > Signed-off-by: Biju Das <biju.das@bp.renesas.com> > > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > > Thanks for your patch! > > > --- /dev/null > > +++ b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h > > @@ -0,0 +1,59 @@ > > +/* SPDX-License-Identifier: GPL-2.0 > > + * > > + * Copyright (C) 2018 Renesas Electronics Corp. > > + */ > > +#ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ > > +#define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ > > + > > +#include <dt-bindings/clock/renesas-cpg-mssr.h> > > + > > +/* r8a774a1 CPG Core Clocks */ > > +#define R8A774A1_CLK_Z 0 > > +#define R8A774A1_CLK_Z2 1 > > +#define R8A774A1_CLK_ZG 2 > > +#define R8A774A1_CLK_ZTR 3 > > +#define R8A774A1_CLK_ZTRD2 4 > > +#define R8A774A1_CLK_ZT 5 > > +#define R8A774A1_CLK_ZX 6 > > +#define R8A774A1_CLK_S0D1 7 > > +#define R8A774A1_CLK_S0D2 8 > > +#define R8A774A1_CLK_S0D3 9 > > +#define R8A774A1_CLK_S0D4 10 > > +#define R8A774A1_CLK_S0D6 11 > > +#define R8A774A1_CLK_S0D8 12 > > +#define R8A774A1_CLK_S0D12 13 > > +#define R8A774A1_CLK_S1D2 14 > > +#define R8A774A1_CLK_S1D4 15 > > +#define R8A774A1_CLK_S2D1 16 > > +#define R8A774A1_CLK_S2D2 17 > > +#define R8A774A1_CLK_S2D4 18 > > +#define R8A774A1_CLK_S3D1 19 > > +#define R8A774A1_CLK_S3D2 20 > > +#define R8A774A1_CLK_S3D4 21 > > +#define R8A774A1_CLK_LB 22 > > +#define R8A774A1_CLK_CL 23 > > +#define R8A774A1_CLK_ZB3 24 > > +#define R8A774A1_CLK_ZB3D2 25 > > +#define R8A774A1_CLK_ZB3D4 26 > > +#define R8A774A1_CLK_CR 27 > > +#define R8A774A1_CLK_CRD2 28 > > +#define R8A774A1_CLK_SD0H 29 > > +#define R8A774A1_CLK_SD0 30 > > +#define R8A774A1_CLK_SD1H 31 > > +#define R8A774A1_CLK_SD1 32 > > +#define R8A774A1_CLK_SD2H 33 > > +#define R8A774A1_CLK_SD2 34 > > +#define R8A774A1_CLK_SD3H 35 > > +#define R8A774A1_CLK_SD3 36 > > +#define R8A774A1_CLK_RPC 37 > > +#define R8A774A1_CLK_RPCD2 38 > > +#define R8A774A1_CLK_MSO 39 > > +#define R8A774A1_CLK_HDMI 40 > > +#define R8A774A1_CLK_CSI0 41 > > +#define R8A774A1_CLK_CP 42 > > +#define R8A774A1_CLK_POST2 43 > > POST2 is an internal clock, which doesn't need to be referred to from DT. > So please drop it from the bindings. Will send V2 with the above fix. > > +#define R8A774A1_CLK_CPEX 44 > > +#define R8A774A1_CLK_R 45 > > +#define R8A774A1_CLK_OSC 46 > > With the above fixed: > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Regards, Biju Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709. ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 5/5] clk: renesas: cpg-mssr: Add r8a774a1 support 2018-07-30 7:48 [PATCH 0/5] Add RZ/G2M SYSC/RST/Clock support Biju Das ` (3 preceding siblings ...) 2018-07-30 7:48 ` [PATCH 4/5] clk: renesas: Add r8a774a1 CPG Core Clock Definitions Biju Das @ 2018-07-30 7:48 ` Biju Das 2018-08-01 9:26 ` Geert Uytterhoeven 4 siblings, 1 reply; 15+ messages in thread From: Biju Das @ 2018-07-30 7:48 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland Cc: Biju Das, Geert Uytterhoeven, linux-clk, devicetree, linux-renesas-soc, Simon Horman, Chris Paterson, Fabrizio Castro Add RZ/G2M (R8A774A1) Clock Pulse Generator / Module Standby and Software Reset support. Based on the Table 8.2b of "RZ/G Series, 2nd Generation User's Manual: Hardware ((Rev. 0.61, June 12, 2018)". Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> --- .../devicetree/bindings/clock/renesas,cpg-mssr.txt | 9 +- drivers/clk/renesas/Kconfig | 5 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r8a774a1-cpg-mssr.c | 322 +++++++++++++++++++++ drivers/clk/renesas/renesas-cpg-mssr.c | 6 + drivers/clk/renesas/renesas-cpg-mssr.h | 1 + 6 files changed, 340 insertions(+), 4 deletions(-) create mode 100644 drivers/clk/renesas/r8a774a1-cpg-mssr.c diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt index db542ab..42d0f83 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt @@ -16,6 +16,7 @@ Required Properties: - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M) - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E) - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C) + - "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M) - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2) - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W) - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H) @@ -35,10 +36,10 @@ Required Properties: - clocks: References to external parent clocks, one entry for each entry in clock-names - clock-names: List of external parent clock names. Valid names are: - - "extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7792, - r8a7793, r8a7794, r8a7795, r8a7796, r8a77965, r8a77970, - r8a77980, r8a77990, r8a77995) - - "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980) + - "extal" (r8a7743, r8a7745, r8a77470, r8a774a1, r8a7790, r8a7791, + r8a7792, r8a7793, r8a7794, r8a7795, r8a7796, r8a77965, + r8a77970, r8a77980, r8a77990, r8a77995) + - "extalr" (r8a774a1, r8a7795, r8a7796, r8a77965, r8a77970, r8a77980) - "usb_extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793, r8a7794) diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index f9ba71311..fd36f18 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -8,6 +8,7 @@ config CLK_RENESAS select CLK_R8A7743 if ARCH_R8A7743 select CLK_R8A7745 if ARCH_R8A7745 select CLK_R8A77470 if ARCH_R8A77470 + select CLK_R8A774A1 if ARCH_R8A774A1 select CLK_R8A7778 if ARCH_R8A7778 select CLK_R8A7779 if ARCH_R8A7779 select CLK_R8A7790 if ARCH_R8A7790 @@ -66,6 +67,10 @@ config CLK_R8A77470 bool "RZ/G1C clock support" if COMPILE_TEST select CLK_RCAR_GEN2_CPG +config CLK_R8A774A1 + bool "RZ/G2M clock support" if COMPILE_TEST + select CLK_RCAR_GEN3_CPG + config CLK_R8A7778 bool "R-Car M1A clock support" if COMPILE_TEST select CLK_RENESAS_CPG_MSTP diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index fe5bac9..0eb56bc 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o +obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o obj-$(CONFIG_CLK_R8A7778) += clk-r8a7778.o obj-$(CONFIG_CLK_R8A7779) += clk-r8a7779.o obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c new file mode 100644 index 0000000..0993513 --- /dev/null +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c @@ -0,0 +1,322 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * r8a774a1 Clock Pulse Generator / Module Standby and Software Reset + * + * Copyright (C) 2018 Renesas Electronics Corp. + * + * Based on r8a7796-cpg-mssr.c + * + * Copyright (C) 2016 Glider bvba + */ + +#include <linux/device.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/soc/renesas/rcar-rst.h> + +#include <dt-bindings/clock/r8a774a1-cpg-mssr.h> + +#include "renesas-cpg-mssr.h" +#include "rcar-gen3-cpg.h" + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R8A774A1_CLK_OSC, + + /* External Input Clocks */ + CLK_EXTAL, + CLK_EXTALR, + + /* Internal Core Clocks */ + CLK_MAIN, + CLK_PLL0, + CLK_PLL1, + CLK_PLL2, + CLK_PLL3, + CLK_PLL4, + CLK_PLL1_DIV2, + CLK_PLL1_DIV4, + CLK_S0, + CLK_S1, + CLK_S2, + CLK_S3, + CLK_SDSRC, + CLK_RINT, + + /* Module Clocks */ + MOD_CLK_BASE +}; + +static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + DEF_INPUT("extalr", CLK_EXTALR), + + /* Internal Core Clocks */ + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), + DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), + DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), + DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), + DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN), + + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), + DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), + DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), + DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), + DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), + + /* Core Clock Outputs */ + DEF_BASE("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), + DEF_BASE("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2), + DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), + DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), + DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1), + DEF_FIXED("zx", R8A774A1_CLK_ZX, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED("s0d1", R8A774A1_CLK_S0D1, CLK_S0, 1, 1), + DEF_FIXED("s0d2", R8A774A1_CLK_S0D2, CLK_S0, 2, 1), + DEF_FIXED("s0d3", R8A774A1_CLK_S0D3, CLK_S0, 3, 1), + DEF_FIXED("s0d4", R8A774A1_CLK_S0D4, CLK_S0, 4, 1), + DEF_FIXED("s0d6", R8A774A1_CLK_S0D6, CLK_S0, 6, 1), + DEF_FIXED("s0d8", R8A774A1_CLK_S0D8, CLK_S0, 8, 1), + DEF_FIXED("s0d12", R8A774A1_CLK_S0D12, CLK_S0, 12, 1), + DEF_FIXED("s1d2", R8A774A1_CLK_S1D2, CLK_S1, 2, 1), + DEF_FIXED("s1d4", R8A774A1_CLK_S1D4, CLK_S1, 4, 1), + DEF_FIXED("s2d1", R8A774A1_CLK_S2D1, CLK_S2, 1, 1), + DEF_FIXED("s2d2", R8A774A1_CLK_S2D2, CLK_S2, 2, 1), + DEF_FIXED("s2d4", R8A774A1_CLK_S2D4, CLK_S2, 4, 1), + DEF_FIXED("s3d1", R8A774A1_CLK_S3D1, CLK_S3, 1, 1), + DEF_FIXED("s3d2", R8A774A1_CLK_S3D2, CLK_S3, 2, 1), + DEF_FIXED("s3d4", R8A774A1_CLK_S3D4, CLK_S3, 4, 1), + + DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, CLK_SDSRC, 0x074), + DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, CLK_SDSRC, 0x078), + DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, CLK_SDSRC, 0x268), + DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, CLK_SDSRC, 0x26c), + + DEF_FIXED("cl", R8A774A1_CLK_CL, CLK_PLL1_DIV2, 48, 1), + DEF_FIXED("cp", R8A774A1_CLK_CP, CLK_EXTAL, 2, 1), + + DEF_DIV6P1("csi0", R8A774A1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), + DEF_DIV6P1("mso", R8A774A1_CLK_MSO, CLK_PLL1_DIV4, 0x014), + DEF_DIV6P1("hdmi", R8A774A1_CLK_HDMI, CLK_PLL1_DIV4, 0x250), + + DEF_DIV6_RO("osc", R8A774A1_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), + DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), + + DEF_BASE("r", R8A774A1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), +}; + +static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = { + DEF_MOD("fdp1-0", 119, R8A774A1_CLK_S0D1), + DEF_MOD("scif5", 202, R8A774A1_CLK_S3D4), + DEF_MOD("scif4", 203, R8A774A1_CLK_S3D4), + DEF_MOD("scif3", 204, R8A774A1_CLK_S3D4), + DEF_MOD("scif1", 206, R8A774A1_CLK_S3D4), + DEF_MOD("scif0", 207, R8A774A1_CLK_S3D4), + DEF_MOD("msiof3", 208, R8A774A1_CLK_MSO), + DEF_MOD("msiof2", 209, R8A774A1_CLK_MSO), + DEF_MOD("msiof1", 210, R8A774A1_CLK_MSO), + DEF_MOD("msiof0", 211, R8A774A1_CLK_MSO), + DEF_MOD("sys-dmac2", 217, R8A774A1_CLK_S0D3), + DEF_MOD("sys-dmac1", 218, R8A774A1_CLK_S0D3), + DEF_MOD("sys-dmac0", 219, R8A774A1_CLK_S0D3), + DEF_MOD("cmt3", 300, R8A774A1_CLK_R), + DEF_MOD("cmt2", 301, R8A774A1_CLK_R), + DEF_MOD("cmt1", 302, R8A774A1_CLK_R), + DEF_MOD("cmt0", 303, R8A774A1_CLK_R), + DEF_MOD("scif2", 310, R8A774A1_CLK_S3D4), + DEF_MOD("sdif3", 311, R8A774A1_CLK_SD3), + DEF_MOD("sdif2", 312, R8A774A1_CLK_SD2), + DEF_MOD("sdif1", 313, R8A774A1_CLK_SD1), + DEF_MOD("sdif0", 314, R8A774A1_CLK_SD0), + DEF_MOD("pcie1", 318, R8A774A1_CLK_S3D1), + DEF_MOD("pcie0", 319, R8A774A1_CLK_S3D1), + DEF_MOD("usb3-if0", 328, R8A774A1_CLK_S3D1), + DEF_MOD("usb-dmac0", 330, R8A774A1_CLK_S3D1), + DEF_MOD("usb-dmac1", 331, R8A774A1_CLK_S3D1), + DEF_MOD("rwdt", 402, R8A774A1_CLK_R), + DEF_MOD("intc-ex", 407, R8A774A1_CLK_CP), + DEF_MOD("intc-ap", 408, R8A774A1_CLK_S0D3), + DEF_MOD("audmac1", 501, R8A774A1_CLK_S0D3), + DEF_MOD("audmac0", 502, R8A774A1_CLK_S0D3), + DEF_MOD("hscif4", 516, R8A774A1_CLK_S3D1), + DEF_MOD("hscif3", 517, R8A774A1_CLK_S3D1), + DEF_MOD("hscif2", 518, R8A774A1_CLK_S3D1), + DEF_MOD("hscif1", 519, R8A774A1_CLK_S3D1), + DEF_MOD("hscif0", 520, R8A774A1_CLK_S3D1), + DEF_MOD("thermal", 522, R8A774A1_CLK_CP), + DEF_MOD("pwm", 523, R8A774A1_CLK_S0D12), + DEF_MOD("fcpvd2", 601, R8A774A1_CLK_S0D2), + DEF_MOD("fcpvd1", 602, R8A774A1_CLK_S0D2), + DEF_MOD("fcpvd0", 603, R8A774A1_CLK_S0D2), + DEF_MOD("fcpvb0", 607, R8A774A1_CLK_S0D1), + DEF_MOD("fcpvi0", 611, R8A774A1_CLK_S0D1), + DEF_MOD("fcpf0", 615, R8A774A1_CLK_S0D1), + DEF_MOD("fcpci0", 617, R8A774A1_CLK_S0D2), + DEF_MOD("fcpcs", 619, R8A774A1_CLK_S0D2), + DEF_MOD("vspd2", 621, R8A774A1_CLK_S0D2), + DEF_MOD("vspd1", 622, R8A774A1_CLK_S0D2), + DEF_MOD("vspd0", 623, R8A774A1_CLK_S0D2), + DEF_MOD("vspb", 626, R8A774A1_CLK_S0D1), + DEF_MOD("vspi0", 631, R8A774A1_CLK_S0D1), + DEF_MOD("ehci1", 702, R8A774A1_CLK_S3D4), + DEF_MOD("ehci0", 703, R8A774A1_CLK_S3D4), + DEF_MOD("hsusb", 704, R8A774A1_CLK_S3D4), + DEF_MOD("csi20", 714, R8A774A1_CLK_CSI0), + DEF_MOD("csi40", 716, R8A774A1_CLK_CSI0), + DEF_MOD("du2", 722, R8A774A1_CLK_S2D1), + DEF_MOD("du1", 723, R8A774A1_CLK_S2D1), + DEF_MOD("du0", 724, R8A774A1_CLK_S2D1), + DEF_MOD("lvds", 727, R8A774A1_CLK_S2D1), + DEF_MOD("hdmi0", 729, R8A774A1_CLK_HDMI), + DEF_MOD("vin7", 804, R8A774A1_CLK_S0D2), + DEF_MOD("vin6", 805, R8A774A1_CLK_S0D2), + DEF_MOD("vin5", 806, R8A774A1_CLK_S0D2), + DEF_MOD("vin4", 807, R8A774A1_CLK_S0D2), + DEF_MOD("vin3", 808, R8A774A1_CLK_S0D2), + DEF_MOD("vin2", 809, R8A774A1_CLK_S0D2), + DEF_MOD("vin1", 810, R8A774A1_CLK_S0D2), + DEF_MOD("vin0", 811, R8A774A1_CLK_S0D2), + DEF_MOD("etheravb", 812, R8A774A1_CLK_S0D6), + DEF_MOD("gpio7", 905, R8A774A1_CLK_S3D4), + DEF_MOD("gpio6", 906, R8A774A1_CLK_S3D4), + DEF_MOD("gpio5", 907, R8A774A1_CLK_S3D4), + DEF_MOD("gpio4", 908, R8A774A1_CLK_S3D4), + DEF_MOD("gpio3", 909, R8A774A1_CLK_S3D4), + DEF_MOD("gpio2", 910, R8A774A1_CLK_S3D4), + DEF_MOD("gpio1", 911, R8A774A1_CLK_S3D4), + DEF_MOD("gpio0", 912, R8A774A1_CLK_S3D4), + DEF_MOD("can-if1", 915, R8A774A1_CLK_S3D4), + DEF_MOD("can-if0", 916, R8A774A1_CLK_S3D4), + DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6), + DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6), + DEF_MOD("i2c-dvfs", 926, R8A774A1_CLK_CP), + DEF_MOD("i2c4", 927, R8A774A1_CLK_S0D6), + DEF_MOD("i2c3", 928, R8A774A1_CLK_S0D6), + DEF_MOD("i2c2", 929, R8A774A1_CLK_S3D2), + DEF_MOD("i2c1", 930, R8A774A1_CLK_S3D2), + DEF_MOD("i2c0", 931, R8A774A1_CLK_S3D2), + DEF_MOD("ssi-all", 1005, R8A774A1_CLK_S3D4), + DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), + DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), + DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), + DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), + DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), + DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), + DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), + DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), + DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), + DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), + DEF_MOD("scu-all", 1017, R8A774A1_CLK_S3D4), + DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), + DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), + DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), + DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), + DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), + DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), + DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), + DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), + DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), + DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), + DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), + DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), + DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), + DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), +}; + +static const unsigned int r8a774a1_crit_mod_clks[] __initconst = { + MOD_CLK_ID(408), /* INTC-AP (GIC) */ +}; + +/* + * CPG Clock Data + */ + +/* + * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 + * 14 13 19 17 (MHz) + *------------------------------------------------------------------- + * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 + * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 + * 0 0 1 0 Prohibited setting + * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 + * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 + * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 + * 0 1 1 0 Prohibited setting + * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 + * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 + * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 + * 1 0 1 0 Prohibited setting + * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 + * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 + * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 + * 1 1 1 0 Prohibited setting + * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 + */ +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ + (((md) & BIT(13)) >> 11) | \ + (((md) & BIT(19)) >> 18) | \ + (((md) & BIT(17)) >> 17)) + +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { + /* EXTAL div PLL1 mult/div PLL3 mult/div */ + { 1, 192, 1, 192, 1, }, + { 1, 192, 1, 128, 1, }, + { 0, /* Prohibited setting */ }, + { 1, 192, 1, 192, 1, }, + { 1, 160, 1, 160, 1, }, + { 1, 160, 1, 106, 1, }, + { 0, /* Prohibited setting */ }, + { 1, 160, 1, 160, 1, }, + { 1, 128, 1, 128, 1, }, + { 1, 128, 1, 84, 1, }, + { 0, /* Prohibited setting */ }, + { 1, 128, 1, 128, 1, }, + { 2, 192, 1, 192, 1, }, + { 2, 192, 1, 128, 1, }, + { 0, /* Prohibited setting */ }, + { 2, 192, 1, 192, 1, }, +}; + +static int __init r8a774a1_cpg_mssr_init(struct device *dev) +{ + const struct rcar_gen3_cpg_pll_config *cpg_pll_config; + u32 cpg_mode; + int error; + + error = rcar_rst_read_mode_pins(&cpg_mode); + if (error) + return error; + + cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; + if (!cpg_pll_config->extal_div) { + dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); + return -EINVAL; + } + + return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); +} + +const struct cpg_mssr_info r8a774a1_cpg_mssr_info __initconst = { + /* Core Clocks */ + .core_clks = r8a774a1_core_clks, + .num_core_clks = ARRAY_SIZE(r8a774a1_core_clks), + .last_dt_core_clk = LAST_DT_CORE_CLK, + .num_total_core_clks = MOD_CLK_BASE, + + /* Module Clocks */ + .mod_clks = r8a774a1_mod_clks, + .num_mod_clks = ARRAY_SIZE(r8a774a1_mod_clks), + .num_hw_mod_clks = 12 * 32, + + /* Critical Module Clocks */ + .crit_mod_clks = r8a774a1_crit_mod_clks, + .num_crit_mod_clks = ARRAY_SIZE(r8a774a1_crit_mod_clks), + + /* Callbacks */ + .init = r8a774a1_cpg_mssr_init, + .cpg_clk_register = rcar_gen3_cpg_clk_register, +}; diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index f4b013e..0e4938a 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -659,6 +659,12 @@ static const struct of_device_id cpg_mssr_match[] = { .data = &r8a77470_cpg_mssr_info, }, #endif +#ifdef CONFIG_CLK_R8A774A1 + { + .compatible = "renesas,r8a774a1-cpg-mssr", + .data = &r8a774a1_cpg_mssr_info, + }, +#endif #ifdef CONFIG_CLK_R8A7790 { .compatible = "renesas,r8a7790-cpg-mssr", diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index 642f720..14e5a19 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -134,6 +134,7 @@ struct cpg_mssr_info { extern const struct cpg_mssr_info r8a7743_cpg_mssr_info; extern const struct cpg_mssr_info r8a7745_cpg_mssr_info; extern const struct cpg_mssr_info r8a77470_cpg_mssr_info; +extern const struct cpg_mssr_info r8a774a1_cpg_mssr_info; extern const struct cpg_mssr_info r8a7790_cpg_mssr_info; extern const struct cpg_mssr_info r8a7791_cpg_mssr_info; extern const struct cpg_mssr_info r8a7792_cpg_mssr_info; -- 2.7.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 5/5] clk: renesas: cpg-mssr: Add r8a774a1 support 2018-07-30 7:48 ` [PATCH 5/5] clk: renesas: cpg-mssr: Add r8a774a1 support Biju Das @ 2018-08-01 9:26 ` Geert Uytterhoeven 2018-08-01 9:31 ` Biju Das 0 siblings, 1 reply; 15+ messages in thread From: Geert Uytterhoeven @ 2018-08-01 9:26 UTC (permalink / raw) To: Biju Das Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland, Geert Uytterhoeven, linux-clk, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux-Renesas, Simon Horman, Chris Paterson, Fabrizio Castro Hi Biju, On Mon, Jul 30, 2018 at 9:54 AM Biju Das <biju.das@bp.renesas.com> wrote: > Add RZ/G2M (R8A774A1) Clock Pulse Generator / Module Standby and Software > Reset support. > > Based on the Table 8.2b of "RZ/G Series, 2nd Generation User's Manual: > Hardware ((Rev. 0.61, June 12, 2018)". > > Signed-off-by: Biju Das <biju.das@bp.renesas.com> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Thanks for your patch! > --- /dev/null > +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c > +static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { > + DEF_DIV6_RO("osc", R8A774A1_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), > + DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), RZ/G2M does not have the CPG_RCKCR register. The internal R CLK is an internal clock, hence please name it ".r". Please have a look at "clk: renesas: rcar-gen3: OSC and RCLK improvements" (https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=2063) > +/* > + * CPG Clock Data > + */ > + > +/* > + * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 > + * 14 13 19 17 (MHz) > + *------------------------------------------------------------------- > + * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 > + * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 > + * 0 0 1 0 Prohibited setting > + * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 > + * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 > + * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 > + * 0 1 1 0 Prohibited setting > + * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 > + * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 > + * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 > + * 1 0 1 0 Prohibited setting > + * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 > + * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 > + * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 > + * 1 1 1 0 Prohibited setting > + * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 > + */ > +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ > + (((md) & BIT(13)) >> 11) | \ > + (((md) & BIT(19)) >> 18) | \ > + (((md) & BIT(17)) >> 17)) > + > +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { > + /* EXTAL div PLL1 mult/div PLL3 mult/div */ > + { 1, 192, 1, 192, 1, }, > + { 1, 192, 1, 128, 1, }, > + { 0, /* Prohibited setting */ }, > + { 1, 192, 1, 192, 1, }, > + { 1, 160, 1, 160, 1, }, > + { 1, 160, 1, 106, 1, }, > + { 0, /* Prohibited setting */ }, > + { 1, 160, 1, 160, 1, }, > + { 1, 128, 1, 128, 1, }, > + { 1, 128, 1, 84, 1, }, > + { 0, /* Prohibited setting */ }, > + { 1, 128, 1, 128, 1, }, > + { 2, 192, 1, 192, 1, }, > + { 2, 192, 1, 128, 1, }, > + { 0, /* Prohibited setting */ }, > + { 2, 192, 1, 192, 1, }, > +}; Please add the new OSC predividers. You're gonna need them for the corrected OSC clock. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH 5/5] clk: renesas: cpg-mssr: Add r8a774a1 support 2018-08-01 9:26 ` Geert Uytterhoeven 2018-08-01 9:31 ` Biju Das @ 2018-08-01 9:31 ` Biju Das 0 siblings, 0 replies; 15+ messages in thread From: Biju Das @ 2018-08-01 9:31 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland, Geert Uytterhoeven, linux-clk, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS <devicetree@vger.kernel.org>, Linux-Renesas, Simon Horman, Chris Paterson, Fabrizio Castro Hi Geert, Thanks for the feedback. > Subject: Re: [PATCH 5/5] clk: renesas: cpg-mssr: Add r8a774a1 support > > Hi Biju, > > On Mon, Jul 30, 2018 at 9:54 AM Biju Das <biju.das@bp.renesas.com> wrote: > > Add RZ/G2M (R8A774A1) Clock Pulse Generator / Module Standby and > > Software Reset support. > > > > Based on the Table 8.2b of "RZ/G Series, 2nd Generation User's Manual: > > Hardware ((Rev. 0.61, June 12, 2018)". > > > > Signed-off-by: Biju Das <biju.das@bp.renesas.com> > > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > > Thanks for your patch! > > > --- /dev/null > > +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c > > > +static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { > > > + DEF_DIV6_RO("osc", R8A774A1_CLK_OSC, CLK_EXTAL, > CPG_RCKCR, 8), > > + DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), > > RZ/G2M does not have the CPG_RCKCR register. > The internal R CLK is an internal clock, hence please name it ".r". > > Please have a look at "clk: renesas: rcar-gen3: OSC and RCLK improvements" > (https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=2063) Will send V2 incorporating this changes. > > +/* > > + * CPG Clock Data > > + */ > > + > > +/* > > + * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 > > + * 14 13 19 17 (MHz) > > + *------------------------------------------------------------------- > > + * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 > > + * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 > > + * 0 0 1 0 Prohibited setting > > + * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 > > + * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 > > + * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 > > + * 0 1 1 0 Prohibited setting > > + * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 > > + * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 > > + * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 > > + * 1 0 1 0 Prohibited setting > > + * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 > > + * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 > > + * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 > > + * 1 1 1 0 Prohibited setting > > + * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 > > + */ > > +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ > > + (((md) & BIT(13)) >> 11) | \ > > + (((md) & BIT(19)) >> 18) | \ > > + (((md) & BIT(17)) >> 17)) > > + > > +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] > __initconst = { > > + /* EXTAL div PLL1 mult/div PLL3 mult/div */ > > + { 1, 192, 1, 192, 1, }, > > + { 1, 192, 1, 128, 1, }, > > + { 0, /* Prohibited setting */ }, > > + { 1, 192, 1, 192, 1, }, > > + { 1, 160, 1, 160, 1, }, > > + { 1, 160, 1, 106, 1, }, > > + { 0, /* Prohibited setting */ }, > > + { 1, 160, 1, 160, 1, }, > > + { 1, 128, 1, 128, 1, }, > > + { 1, 128, 1, 84, 1, }, > > + { 0, /* Prohibited setting */ }, > > + { 1, 128, 1, 128, 1, }, > > + { 2, 192, 1, 192, 1, }, > > + { 2, 192, 1, 128, 1, }, > > + { 0, /* Prohibited setting */ }, > > + { 2, 192, 1, 192, 1, }, > > +}; > > Please add the new OSC predividers. You're gonna need them for the > corrected OSC clock. Will send V2 incorporating this changes. Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709. ^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH 5/5] clk: renesas: cpg-mssr: Add r8a774a1 support @ 2018-08-01 9:31 ` Biju Das 0 siblings, 0 replies; 15+ messages in thread From: Biju Das @ 2018-08-01 9:31 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland, Geert Uytterhoeven, linux-clk, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux-Renesas, Simon Horman, Chris Paterson, Fabrizio Castro SGkgR2VlcnQsDQoNClRoYW5rcyBmb3IgdGhlIGZlZWRiYWNrLg0KDQo+IFN1YmplY3Q6IFJlOiBb UEFUQ0ggNS81XSBjbGs6IHJlbmVzYXM6IGNwZy1tc3NyOiBBZGQgcjhhNzc0YTEgc3VwcG9ydA0K Pg0KPiBIaSBCaWp1LA0KPg0KPiBPbiBNb24sIEp1bCAzMCwgMjAxOCBhdCA5OjU0IEFNIEJpanUg RGFzIDxiaWp1LmRhc0BicC5yZW5lc2FzLmNvbT4gd3JvdGU6DQo+ID4gQWRkIFJaL0cyTSAoUjhB Nzc0QTEpIENsb2NrIFB1bHNlIEdlbmVyYXRvciAvIE1vZHVsZSBTdGFuZGJ5IGFuZA0KPiA+IFNv ZnR3YXJlIFJlc2V0IHN1cHBvcnQuDQo+ID4NCj4gPiBCYXNlZCBvbiB0aGUgVGFibGUgOC4yYiBv ZiAiUlovRyBTZXJpZXMsIDJuZCBHZW5lcmF0aW9uIFVzZXIncyBNYW51YWw6DQo+ID4gSGFyZHdh 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* RE: [PATCH 5/5] clk: renesas: cpg-mssr: Add r8a774a1 support @ 2018-08-01 9:31 ` Biju Das 0 siblings, 0 replies; 15+ messages in thread From: Biju Das @ 2018-08-01 9:31 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland, Geert Uytterhoeven, linux-clk, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux-Renesas, Simon Horman, Chris Paterson, Fabrizio Castro Hi Geert, Thanks for the feedback. > Subject: Re: [PATCH 5/5] clk: renesas: cpg-mssr: Add r8a774a1 support > > Hi Biju, > > On Mon, Jul 30, 2018 at 9:54 AM Biju Das <biju.das@bp.renesas.com> wrote: > > Add RZ/G2M (R8A774A1) Clock Pulse Generator / Module Standby and > > Software Reset support. > > > > Based on the Table 8.2b of "RZ/G Series, 2nd Generation User's Manual: > > Hardware ((Rev. 0.61, June 12, 2018)". > > > > Signed-off-by: Biju Das <biju.das@bp.renesas.com> > > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > > Thanks for your patch! > > > --- /dev/null > > +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c > > > +static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { > > > + DEF_DIV6_RO("osc", R8A774A1_CLK_OSC, CLK_EXTAL, > CPG_RCKCR, 8), > > + DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), > > RZ/G2M does not have the CPG_RCKCR register. > The internal R CLK is an internal clock, hence please name it ".r". > > Please have a look at "clk: renesas: rcar-gen3: OSC and RCLK improvements" > (https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=2063) Will send V2 incorporating this changes. > > +/* > > + * CPG Clock Data > > + */ > > + > > +/* > > + * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 > > + * 14 13 19 17 (MHz) > > + *------------------------------------------------------------------- > > + * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 > > + * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 > > + * 0 0 1 0 Prohibited setting > > + * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 > > + * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 > > + * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 > > + * 0 1 1 0 Prohibited setting > > + * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 > > + * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 > > + * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 > > + * 1 0 1 0 Prohibited setting > > + * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 > > + * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 > > + * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 > > + * 1 1 1 0 Prohibited setting > > + * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 > > + */ > > +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ > > + (((md) & BIT(13)) >> 11) | \ > > + (((md) & BIT(19)) >> 18) | \ > > + (((md) & BIT(17)) >> 17)) > > + > > +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] > __initconst = { > > + /* EXTAL div PLL1 mult/div PLL3 mult/div */ > > + { 1, 192, 1, 192, 1, }, > > + { 1, 192, 1, 128, 1, }, > > + { 0, /* Prohibited setting */ }, > > + { 1, 192, 1, 192, 1, }, > > + { 1, 160, 1, 160, 1, }, > > + { 1, 160, 1, 106, 1, }, > > + { 0, /* Prohibited setting */ }, > > + { 1, 160, 1, 160, 1, }, > > + { 1, 128, 1, 128, 1, }, > > + { 1, 128, 1, 84, 1, }, > > + { 0, /* Prohibited setting */ }, > > + { 1, 128, 1, 128, 1, }, > > + { 2, 192, 1, 192, 1, }, > > + { 2, 192, 1, 128, 1, }, > > + { 0, /* Prohibited setting */ }, > > + { 2, 192, 1, 192, 1, }, > > +}; > > Please add the new OSC predividers. You're gonna need them for the > corrected OSC clock. Will send V2 incorporating this changes. Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709. ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2018-08-01 11:16 UTC | newest] Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-07-30 7:48 [PATCH 0/5] Add RZ/G2M SYSC/RST/Clock support Biju Das 2018-07-30 7:48 ` [PATCH 1/5] dt-bindings: power: Add r8a774a1 SYSC power domain definitions Biju Das 2018-08-01 8:01 ` Geert Uytterhoeven 2018-07-30 7:48 ` [PATCH 2/5] soc: renesas: rcar-sysc: Add r8a774a1 support Biju Das 2018-08-01 8:05 ` Geert Uytterhoeven 2018-07-30 7:48 ` [PATCH 3/5] soc: renesas: rcar-rst: Add support for RZ/G2M Biju Das 2018-08-01 8:46 ` Geert Uytterhoeven 2018-07-30 7:48 ` [PATCH 4/5] clk: renesas: Add r8a774a1 CPG Core Clock Definitions Biju Das 2018-08-01 8:46 ` Geert Uytterhoeven 2018-08-01 9:33 ` Biju Das 2018-07-30 7:48 ` [PATCH 5/5] clk: renesas: cpg-mssr: Add r8a774a1 support Biju Das 2018-08-01 9:26 ` Geert Uytterhoeven 2018-08-01 9:31 ` Biju Das 2018-08-01 9:31 ` Biju Das 2018-08-01 9:31 ` Biju Das
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