[PATCH 0/4] Enable RZ/G2LC OSTM, QSPI0, RSPI and Voltage regulator for GPU

[PATCH 0/4] Enable RZ/G2LC OSTM, QSPI0, RSPI and Voltage regulator for GPU

[Biju Das]

This patch enables OSTM, QSPI0, RSPI and Voltage regulator for GPU
on RZ/G2LC SMARC EVK.

This patch depend upon [1]
[1] https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=620047

Biju Das (4):
  arm64: dts: renesas: rzg2lc-smarc-som: Enable serial NOR flash
  arm64: dts: renesas: rzg2lc-smarc-som: Enable OSTM
  arm64: dts: renesas: rzg2lc-smarc-som: Add vdd core regulator
  arm64: dts: renesas: rzg2lc-smarc: Enable RSPI1 on carrier board

 .../boot/dts/renesas/r9a07g044c2-smarc.dts    |  6 --
 .../dts/renesas/rzg2lc-smarc-pinfunction.dtsi |  7 +++
 .../boot/dts/renesas/rzg2lc-smarc-som.dtsi    | 61 +++++++++++++++++++
 arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi |  8 +++
 4 files changed, 76 insertions(+), 6 deletions(-)

-- 
2.17.1

[PATCH 1/4] arm64: dts: renesas: rzg2lc-smarc-som: Enable serial NOR flash

[Biju Das]

Enable mt25qu512a flash connected to QSPI0.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../boot/dts/renesas/rzg2lc-smarc-som.dtsi    | 40 +++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
index 88a7938017aa..80c9a1146cb7 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
@@ -110,6 +110,18 @@
 		line-name = "gpio_sd0_pwr_en";
 	};
 
+	qspi0_pins: qspi0 {
+		qspi0-data {
+			pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
+			power-source = <1800>;
+		};
+
+		qspi0-ctrl {
+			pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
+			power-source = <1800>;
+		};
+	};
+
 	/*
 	 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
 	 * The below switch logic can be used to select the device between
@@ -175,6 +187,34 @@
 	};
 };
 
+&sbc {
+	pinctrl-0 = <&qspi0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	flash@0 {
+		compatible = "micron,mt25qu512a", "jedec,spi-nor";
+		reg = <0>;
+		m25p,fast-read;
+		spi-max-frequency = <50000000>;
+		spi-rx-bus-width = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			boot@0 {
+				reg = <0x00000000 0x2000000>;
+				read-only;
+			};
+			user@2000000 {
+				reg = <0x2000000 0x2000000>;
+			};
+		};
+	};
+};
+
 #if (!SW_SD0_DEV_SEL)
 &sdhi0 {
 	pinctrl-0 = <&sdhi0_pins>;
-- 
2.17.1

[PATCH 2/4] arm64: dts: renesas: rzg2lc-smarc-som: Enable OSTM

[Biju Das]

Enable OSTM{1, 2} interfaces on RZ/G2LC SMARC EVK.
OSTM0 is reserved for TF-A.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
index 80c9a1146cb7..05b117ac414c 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
@@ -84,6 +84,14 @@
 	clock-frequency = <24000000>;
 };
 
+&ostm1 {
+	status = "okay";
+};
+
+&ostm2 {
+	status = "okay";
+};
+
 &pinctrl {
 	eth0_pins: eth0 {
 		pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
-- 
2.17.1

[PATCH 3/4] arm64: dts: renesas: rzg2lc-smarc-som: Add vdd core regulator

[Biju Das]

Add vdd core regulator (1.1 V) for GPU.

This patch add regulator support for GPU.

The H/W manual mentions nothing about a GPU regulator. So using vdd
core regulator for GPU.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
index 05b117ac414c..959a0ad1d367 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
@@ -41,6 +41,15 @@
 		regulator-always-on;
 	};
 
+	reg_1p1v: regulator-vdd-core {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.1V";
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
 	vccq_sdhi0: regulator-vccq-sdhi0 {
 		compatible = "regulator-gpio";
 
@@ -84,6 +93,10 @@
 	clock-frequency = <24000000>;
 };
 
+&gpu {
+	mali-supply = <&reg_1p1v>;
+};
+
 &ostm1 {
 	status = "okay";
 };
-- 
2.17.1

[PATCH 4/4] arm64: dts: renesas: rzg2lc-smarc: Enable RSPI1 on carrier board

[Biju Das]

RSPI1 (SPI1) interface is available on PMOD0 connector (J1) on the
carrier board.  This patch adds pinmux and spi1 nodes to the carrier
board dtsi file and drops deleting pinctl* properties from DTS file.

RSPI1 interface is tested by setting the macro SW_RSPI_CAN to 0.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts         | 6 ------
 arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 7 +++++++
 arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi             | 8 ++++++++
 3 files changed, 15 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
index 74a2f2bade10..fc34058002e2 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
@@ -13,9 +13,3 @@
 	model = "Renesas SMARC EVK based on r9a07g044c2";
 	compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044";
 };
-
-&spi1 {
-	/delete-property/ pinctrl-0;
-	/delete-property/ pinctrl-names;
-	status = "disabled";
-};
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
index d275a55333e3..a78a8def363e 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
@@ -106,6 +106,13 @@
 		input-enable;
 	};
 
+	spi1_pins: spi1 {
+		pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
+			 <RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
+			 <RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
+			 <RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
+	};
+
 	ssi0_pins: ssi0 {
 		pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
 			 <RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
index f73b4acb8f9e..292513635baf 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
@@ -74,6 +74,14 @@
 	};
 };
 
+#if (!SW_RSPI_CAN)
+&spi1 {
+	pinctrl-0 = <&spi1_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+#endif
+
 /*
  * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
  * SW1 should be at position 2->3 so that SER0_CTS# line is activated
-- 
2.17.1

Re: [PATCH 1/4] arm64: dts: renesas: rzg2lc-smarc-som: Enable serial NOR flash

[Geert Uytterhoeven]

On Mon, Mar 7, 2022 at 8:24 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Enable mt25qu512a flash connected to QSPI0.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.19.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/4] arm64: dts: renesas: rzg2lc-smarc-som: Enable OSTM

[Geert Uytterhoeven]

On Mon, Mar 7, 2022 at 8:24 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Enable OSTM{1, 2} interfaces on RZ/G2LC SMARC EVK.
> OSTM0 is reserved for TF-A.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.19.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/4] arm64: dts: renesas: rzg2lc-smarc-som: Add vdd core regulator

[Geert Uytterhoeven]

On Mon, Mar 7, 2022 at 8:24 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add vdd core regulator (1.1 V) for GPU.
>
> This patch add regulator support for GPU.
>
> The H/W manual mentions nothing about a GPU regulator. So using vdd
> core regulator for GPU.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.19.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 4/4] arm64: dts: renesas: rzg2lc-smarc: Enable RSPI1 on carrier board

[Geert Uytterhoeven]

Hi Biju,

On Mon, Mar 7, 2022 at 8:24 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> RSPI1 (SPI1) interface is available on PMOD0 connector (J1) on the
> carrier board.  This patch adds pinmux and spi1 nodes to the carrier
> board dtsi file and drops deleting pinctl* properties from DTS file.
>
> RSPI1 interface is tested by setting the macro SW_RSPI_CAN to 0.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
> +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
> @@ -13,9 +13,3 @@
>         model = "Renesas SMARC EVK based on r9a07g044c2";
>         compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044";
>  };
> -
> -&spi1 {
> -       /delete-property/ pinctrl-0;
> -       /delete-property/ pinctrl-names;
> -       status = "disabled";
> -};

The common properties in rz-smarc-common.dtsi are indeed no
longer removed...

> --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
> @@ -74,6 +74,14 @@
>         };
>  };
>
> +#if (!SW_RSPI_CAN)
> +&spi1 {

Spi1 should be inserted after scif1 below.

> +       pinctrl-0 = <&spi1_pins>;
> +       pinctrl-names = "default";
> +       status = "okay";
> +};
> +#endif

... so regardless of the value of SW_RSPI_CAN, spi1 will be enabled?

I think you want to protect the disable block in r9a07g044c2-smarc.dts
by #if SW_RSPI_CAN/#endif instead?

  + #if SW_RSPI_CAN
    &spi1 {
           /delete-property/ pinctrl-0;
           /delete-property/ pinctrl-names;
           status = "disabled";
    };
  + #endif

> +
>  /*
>   * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
>   * SW1 should be at position 2->3 so that SER0_CTS# line is activated

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 4/4] arm64: dts: renesas: rzg2lc-smarc: Enable RSPI1 on carrier board

[Biju Das]

Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH 4/4] arm64: dts: renesas: rzg2lc-smarc: Enable RSPI1
> on carrier board
> 
> Hi Biju,
> 
> On Mon, Mar 7, 2022 at 8:24 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > RSPI1 (SPI1) interface is available on PMOD0 connector (J1) on the
> > carrier board.  This patch adds pinmux and spi1 nodes to the carrier
> > board dtsi file and drops deleting pinctl* properties from DTS file.
> >
> > RSPI1 interface is tested by setting the macro SW_RSPI_CAN to 0.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Thanks for your patch!
> 
> > --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
> > @@ -13,9 +13,3 @@
> >         model = "Renesas SMARC EVK based on r9a07g044c2";
> >         compatible = "renesas,smarc-evk", "renesas,r9a07g044c2",
> > "renesas,r9a07g044";  };
> > -
> > -&spi1 {
> > -       /delete-property/ pinctrl-0;
> > -       /delete-property/ pinctrl-names;
> > -       status = "disabled";
> > -};
> 
> The common properties in rz-smarc-common.dtsi are indeed no longer
> removed...
> 
> > --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
> > @@ -74,6 +74,14 @@
> >         };
> >  };
> >
> > +#if (!SW_RSPI_CAN)
> > +&spi1 {
> 
> Spi1 should be inserted after scif1 below.

Agreed.

> 
> > +       pinctrl-0 = <&spi1_pins>;
> > +       pinctrl-names = "default";
> > +       status = "okay";
> > +};
> > +#endif
> 
> ... so regardless of the value of SW_RSPI_CAN, spi1 will be enabled?
> 
> I think you want to protect the disable block in r9a07g044c2-smarc.dts by

OK, will fix this in next version.


Cheers,
Biju

> #if SW_RSPI_CAN/#endif instead?
> 
>   + #if SW_RSPI_CAN
>     &spi1 {
>            /delete-property/ pinctrl-0;
>            /delete-property/ pinctrl-names;
>            status = "disabled";
>     };
>   + #endif
> 
> > +
> >  /*
> >   * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
> >   * SW1 should be at position 2->3 so that SER0_CTS# line is activated
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
>                                 -- Linus Torvalds