[PATCH 0/5] clk: renesas: r-car gen2: Fix LB clock divider

[PATCH 0/5] clk: renesas: r-car gen2: Fix LB clock divider

[Geert Uytterhoeven]

	Hi all,

The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
the LB clock divider depends on the value of the MD18 pin.

However, on most RZ/G1 and R-Car Gen2 SoCs, the LB clock divider is
fixed to 24.  Hence this series corrects the LB clock on affected SoCs
by modelling it as a fixed factor clock instead.

This doesn't have much impact, as no kernel code relies on the rate of
the LB clock.

To be queued in clk-renesas-for-v4.18.

Geert Uytterhoeven (5):
  clk: renesas: r8a7743: Fix LB clock divider
  clk: renesas: r8a7745: Fix LB clock divider
  clk: renesas: r8a7791/r8a7793: Fix LB clock divider
  clk: renesas: r8a7792: Fix LB clock divider
  clk: renesas: r8a7794: Fix LB clock divider

 drivers/clk/renesas/r8a7743-cpg-mssr.c | 2 +-
 drivers/clk/renesas/r8a7745-cpg-mssr.c | 2 +-
 drivers/clk/renesas/r8a7791-cpg-mssr.c | 2 +-
 drivers/clk/renesas/r8a7792-cpg-mssr.c | 2 +-
 drivers/clk/renesas/r8a7794-cpg-mssr.c | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

-- 
2.7.4

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH 1/5] clk: renesas: r8a7743: Fix LB clock divider

[Geert Uytterhoeven]

The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
the LB clock divider depends on the value of the MD18 pin.

On RZ/G1M, the LB clock divider is fixed to 24.  Hence model the clock
as a fixed factor clock instead.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/clk/renesas/r8a7743-cpg-mssr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r8a7743-cpg-mssr.c b/drivers/clk/renesas/r8a7743-cpg-mssr.c
index d3c8b1e2969fd305..011c170ec3f95d65 100644
--- a/drivers/clk/renesas/r8a7743-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7743-cpg-mssr.c
@@ -52,7 +52,6 @@ static const struct cpg_core_clk r8a7743_core_clks[] __initconst = {
 
 	/* Core Clock Outputs */
 	DEF_BASE("z",    R8A7743_CLK_Z,    CLK_TYPE_GEN2_Z,	CLK_PLL0),
-	DEF_BASE("lb",   R8A7743_CLK_LB,   CLK_TYPE_GEN2_LB,	CLK_PLL1),
 	DEF_BASE("sdh",  R8A7743_CLK_SDH,  CLK_TYPE_GEN2_SDH,	CLK_PLL1),
 	DEF_BASE("sd0",  R8A7743_CLK_SD0,  CLK_TYPE_GEN2_SD0,	CLK_PLL1),
 	DEF_BASE("qspi", R8A7743_CLK_QSPI, CLK_TYPE_GEN2_QSPI,	CLK_PLL1_DIV2),
@@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7743_core_clks[] __initconst = {
 	DEF_FIXED("zs",    R8A7743_CLK_ZS,	CLK_PLL1,	    6, 1),
 	DEF_FIXED("hp",    R8A7743_CLK_HP,	CLK_PLL1,	   12, 1),
 	DEF_FIXED("b",     R8A7743_CLK_B,	CLK_PLL1,	   12, 1),
+	DEF_FIXED("lb",    R8A7743_CLK_LB,	CLK_PLL1,	   24, 1),
 	DEF_FIXED("p",     R8A7743_CLK_P,	CLK_PLL1,	   24, 1),
 	DEF_FIXED("cl",    R8A7743_CLK_CL,	CLK_PLL1,	   48, 1),
 	DEF_FIXED("m2",    R8A7743_CLK_M2,	CLK_PLL1,	    8, 1),
-- 
2.7.4

[PATCH 2/5] clk: renesas: r8a7745: Fix LB clock divider

[Geert Uytterhoeven]

The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
the LB clock divider depends on the value of the MD18 pin.

On RZ/G1E, the LB clock divider is fixed to 24.  Hence model the clock
as a fixed factor clock instead.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/clk/renesas/r8a7745-cpg-mssr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c b/drivers/clk/renesas/r8a7745-cpg-mssr.c
index 87f5a3619e4f9d60..4b0a9243b7481176 100644
--- a/drivers/clk/renesas/r8a7745-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c
@@ -51,7 +51,6 @@ static const struct cpg_core_clk r8a7745_core_clks[] __initconst = {
 	DEF_FIXED(".pll1_div2",	CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
 
 	/* Core Clock Outputs */
-	DEF_BASE("lb",   R8A7745_CLK_LB,   CLK_TYPE_GEN2_LB,	CLK_PLL1),
 	DEF_BASE("sdh",  R8A7745_CLK_SDH,  CLK_TYPE_GEN2_SDH,	CLK_PLL1),
 	DEF_BASE("sd0",  R8A7745_CLK_SD0,  CLK_TYPE_GEN2_SD0,	CLK_PLL1),
 	DEF_BASE("qspi", R8A7745_CLK_QSPI, CLK_TYPE_GEN2_QSPI,	CLK_PLL1_DIV2),
@@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7745_core_clks[] __initconst = {
 	DEF_FIXED("zs",    R8A7745_CLK_ZS,	CLK_PLL1,	    6, 1),
 	DEF_FIXED("hp",    R8A7745_CLK_HP,	CLK_PLL1,	   12, 1),
 	DEF_FIXED("b",     R8A7745_CLK_B,	CLK_PLL1,	   12, 1),
+	DEF_FIXED("lb",    R8A7745_CLK_LB,	CLK_PLL1,	   24, 1),
 	DEF_FIXED("p",     R8A7745_CLK_P,	CLK_PLL1,	   24, 1),
 	DEF_FIXED("cl",    R8A7745_CLK_CL,	CLK_PLL1,	   48, 1),
 	DEF_FIXED("cp",    R8A7745_CLK_CP,	CLK_PLL1,	   48, 1),
-- 
2.7.4

[PATCH 3/5] clk: renesas: r8a7791/r8a7793: Fix LB clock divider

[Geert Uytterhoeven]

The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
the LB clock divider depends on the value of the MD18 pin.

On R-Car M2-W and M2-N, the LB clock divider is fixed to 24.  Hence
model the clock as a fixed factor clock instead.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/clk/renesas/r8a7791-cpg-mssr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c b/drivers/clk/renesas/r8a7791-cpg-mssr.c
index 820b220b09cc6bdb..1b91f03b75980766 100644
--- a/drivers/clk/renesas/r8a7791-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c
@@ -57,7 +57,6 @@ static struct cpg_core_clk r8a7791_core_clks[] __initdata = {
 
 	/* Core Clock Outputs */
 	DEF_BASE("z",    R8A7791_CLK_Z,    CLK_TYPE_GEN2_Z,    CLK_PLL0),
-	DEF_BASE("lb",   R8A7791_CLK_LB,   CLK_TYPE_GEN2_LB,   CLK_PLL1),
 	DEF_BASE("adsp", R8A7791_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
 	DEF_BASE("sdh",  R8A7791_CLK_SDH,  CLK_TYPE_GEN2_SDH,  CLK_PLL1),
 	DEF_BASE("sd0",  R8A7791_CLK_SD0,  CLK_TYPE_GEN2_SD0,  CLK_PLL1),
@@ -70,6 +69,7 @@ static struct cpg_core_clk r8a7791_core_clks[] __initdata = {
 	DEF_FIXED("hp",     R8A7791_CLK_HP,    CLK_PLL1,         12, 1),
 	DEF_FIXED("i",      R8A7791_CLK_I,     CLK_PLL1,          2, 1),
 	DEF_FIXED("b",      R8A7791_CLK_B,     CLK_PLL1,         12, 1),
+	DEF_FIXED("lb",     R8A7791_CLK_LB,    CLK_PLL1,         24, 1),
 	DEF_FIXED("p",      R8A7791_CLK_P,     CLK_PLL1,         24, 1),
 	DEF_FIXED("cl",     R8A7791_CLK_CL,    CLK_PLL1,         48, 1),
 	DEF_FIXED("m2",     R8A7791_CLK_M2,    CLK_PLL1,          8, 1),
-- 
2.7.4

[PATCH 4/5] clk: renesas: r8a7792: Fix LB clock divider

[Geert Uytterhoeven]

The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
the LB clock divider depends on the value of the MD18 pin.

On R-Car V2H, the LB clock divider is fixed to 24.  Hence model the
clock as a fixed factor clock instead.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/clk/renesas/r8a7792-cpg-mssr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c
index 609a540804965c40..8b66e6f4b4584de1 100644
--- a/drivers/clk/renesas/r8a7792-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c
@@ -53,7 +53,6 @@ static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
 	DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
 
 	/* Core Clock Outputs */
-	DEF_BASE("lb",   R8A7792_CLK_LB,   CLK_TYPE_GEN2_LB,   CLK_PLL1),
 	DEF_BASE("qspi", R8A7792_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
 
 	DEF_FIXED("z",      R8A7792_CLK_Z,     CLK_PLL0,          1, 1),
@@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
 	DEF_FIXED("hp",     R8A7792_CLK_HP,    CLK_PLL1,         12, 1),
 	DEF_FIXED("i",      R8A7792_CLK_I,     CLK_PLL1,          3, 1),
 	DEF_FIXED("b",      R8A7792_CLK_B,     CLK_PLL1,         12, 1),
+	DEF_FIXED("lb",     R8A7792_CLK_B,     CLK_PLL1,         24, 1),
 	DEF_FIXED("p",      R8A7792_CLK_P,     CLK_PLL1,         24, 1),
 	DEF_FIXED("cl",     R8A7792_CLK_CL,    CLK_PLL1,         48, 1),
 	DEF_FIXED("m2",     R8A7792_CLK_M2,    CLK_PLL1,          8, 1),
-- 
2.7.4

[PATCH 5/5] clk: renesas: r8a7794: Fix LB clock divider

[Geert Uytterhoeven]

The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
the LB clock divider depends on the value of the MD18 pin.

On R-Car E2, the LB clock divider is fixed to 24.  Hence model the clock
as a fixed factor clock instead.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/clk/renesas/r8a7794-cpg-mssr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c b/drivers/clk/renesas/r8a7794-cpg-mssr.c
index 2a40bbeaeeafc2a4..3ce74f063fa86b19 100644
--- a/drivers/clk/renesas/r8a7794-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c
@@ -55,7 +55,6 @@ static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
 	DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
 
 	/* Core Clock Outputs */
-	DEF_BASE("lb",   R8A7794_CLK_LB,   CLK_TYPE_GEN2_LB,   CLK_PLL1),
 	DEF_BASE("adsp", R8A7794_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
 	DEF_BASE("sdh",  R8A7794_CLK_SDH,  CLK_TYPE_GEN2_SDH,  CLK_PLL1),
 	DEF_BASE("sd0",  R8A7794_CLK_SD0,  CLK_TYPE_GEN2_SD0,  CLK_PLL1),
@@ -69,6 +68,7 @@ static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
 	DEF_FIXED("hp",     R8A7794_CLK_HP,    CLK_PLL1,         12, 1),
 	DEF_FIXED("i",      R8A7794_CLK_I,     CLK_PLL1,          2, 1),
 	DEF_FIXED("b",      R8A7794_CLK_B,     CLK_PLL1,         12, 1),
+	DEF_FIXED("lb",     R8A7794_CLK_B,     CLK_PLL1,         24, 1),
 	DEF_FIXED("p",      R8A7794_CLK_P,     CLK_PLL1,         24, 1),
 	DEF_FIXED("cl",     R8A7794_CLK_CL,    CLK_PLL1,         48, 1),
 	DEF_FIXED("cp",     R8A7794_CLK_CP,    CLK_PLL1,         48, 1),
-- 
2.7.4

Re: [PATCH 0/5] clk: renesas: r-car gen2: Fix LB clock divider

[Simon Horman]

On Thu, Mar 29, 2018 at 07:33:05PM +0200, Geert Uytterhoeven wrote:
> 	Hi all,
> 
> The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
> the LB clock divider depends on the value of the MD18 pin.
> 
> However, on most RZ/G1 and R-Car Gen2 SoCs, the LB clock divider is
> fixed to 24.  Hence this series corrects the LB clock on affected SoCs
> by modelling it as a fixed factor clock instead.
> 
> This doesn't have much impact, as no kernel code relies on the rate of
> the LB clock.
> 
> To be queued in clk-renesas-for-v4.18.

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

RE: [PATCH 1/5] clk: renesas: r8a7743: Fix LB clock divider

[Fabrizio Castro]

> Subject: [PATCH 1/5] clk: renesas: r8a7743: Fix LB clock divider
>
> The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
> the LB clock divider depends on the value of the MD18 pin.
>
> On RZ/G1M, the LB clock divider is fixed to 24.  Hence model the clock
> as a fixed factor clock instead.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

> ---
>  drivers/clk/renesas/r8a7743-cpg-mssr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/renesas/r8a7743-cpg-mssr.c b/drivers/clk/renesas/r8a7743-cpg-mssr.c
> index d3c8b1e2969fd305..011c170ec3f95d65 100644
> --- a/drivers/clk/renesas/r8a7743-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7743-cpg-mssr.c
> @@ -52,7 +52,6 @@ static const struct cpg_core_clk r8a7743_core_clks[] __initconst = {
>
>  /* Core Clock Outputs */
>  DEF_BASE("z",    R8A7743_CLK_Z,    CLK_TYPE_GEN2_Z,CLK_PLL0),
> -DEF_BASE("lb",   R8A7743_CLK_LB,   CLK_TYPE_GEN2_LB,CLK_PLL1),
>  DEF_BASE("sdh",  R8A7743_CLK_SDH,  CLK_TYPE_GEN2_SDH,CLK_PLL1),
>  DEF_BASE("sd0",  R8A7743_CLK_SD0,  CLK_TYPE_GEN2_SD0,CLK_PLL1),
>  DEF_BASE("qspi", R8A7743_CLK_QSPI, CLK_TYPE_GEN2_QSPI,CLK_PLL1_DIV2),
> @@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7743_core_clks[] __initconst = {
>  DEF_FIXED("zs",    R8A7743_CLK_ZS,CLK_PLL1,    6, 1),
>  DEF_FIXED("hp",    R8A7743_CLK_HP,CLK_PLL1,   12, 1),
>  DEF_FIXED("b",     R8A7743_CLK_B,CLK_PLL1,   12, 1),
> +DEF_FIXED("lb",    R8A7743_CLK_LB,CLK_PLL1,   24, 1),
>  DEF_FIXED("p",     R8A7743_CLK_P,CLK_PLL1,   24, 1),
>  DEF_FIXED("cl",    R8A7743_CLK_CL,CLK_PLL1,   48, 1),
>  DEF_FIXED("m2",    R8A7743_CLK_M2,CLK_PLL1,    8, 1),
> --
> 2.7.4




Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

RE: [PATCH 1/5] clk: renesas: r8a7743: Fix LB clock divider

[Fabrizio Castro]

> Subject: [PATCH 1/5] clk: renesas: r8a7743: Fix LB clock divider
>
> The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
> the LB clock divider depends on the value of the MD18 pin.
>
> On RZ/G1M, the LB clock divider is fixed to 24.  Hence model the clock
> as a fixed factor clock instead.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

> ---
>  drivers/clk/renesas/r8a7743-cpg-mssr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/renesas/r8a7743-cpg-mssr.c b/drivers/clk/renesas=
/r8a7743-cpg-mssr.c
> index d3c8b1e2969fd305..011c170ec3f95d65 100644
> --- a/drivers/clk/renesas/r8a7743-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7743-cpg-mssr.c
> @@ -52,7 +52,6 @@ static const struct cpg_core_clk r8a7743_core_clks[] __=
initconst =3D {
>
>  /* Core Clock Outputs */
>  DEF_BASE("z",    R8A7743_CLK_Z,    CLK_TYPE_GEN2_Z,CLK_PLL0),
> -DEF_BASE("lb",   R8A7743_CLK_LB,   CLK_TYPE_GEN2_LB,CLK_PLL1),
>  DEF_BASE("sdh",  R8A7743_CLK_SDH,  CLK_TYPE_GEN2_SDH,CLK_PLL1),
>  DEF_BASE("sd0",  R8A7743_CLK_SD0,  CLK_TYPE_GEN2_SD0,CLK_PLL1),
>  DEF_BASE("qspi", R8A7743_CLK_QSPI, CLK_TYPE_GEN2_QSPI,CLK_PLL1_DIV2),
> @@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7743_core_clks[] __=
initconst =3D {
>  DEF_FIXED("zs",    R8A7743_CLK_ZS,CLK_PLL1,    6, 1),
>  DEF_FIXED("hp",    R8A7743_CLK_HP,CLK_PLL1,   12, 1),
>  DEF_FIXED("b",     R8A7743_CLK_B,CLK_PLL1,   12, 1),
> +DEF_FIXED("lb",    R8A7743_CLK_LB,CLK_PLL1,   24, 1),
>  DEF_FIXED("p",     R8A7743_CLK_P,CLK_PLL1,   24, 1),
>  DEF_FIXED("cl",    R8A7743_CLK_CL,CLK_PLL1,   48, 1),
>  DEF_FIXED("m2",    R8A7743_CLK_M2,CLK_PLL1,    8, 1),
> --
> 2.7.4




Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, B=
uckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered=
 No. 04586709.

RE: [PATCH 2/5] clk: renesas: r8a7745: Fix LB clock divider

[Fabrizio Castro]

> Subject: [PATCH 2/5] clk: renesas: r8a7745: Fix LB clock divider
>
> The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
> the LB clock divider depends on the value of the MD18 pin.
>
> On RZ/G1E, the LB clock divider is fixed to 24.  Hence model the clock
> as a fixed factor clock instead.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

> ---
>  drivers/clk/renesas/r8a7745-cpg-mssr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c b/drivers/clk/renesas/r8a7745-cpg-mssr.c
> index 87f5a3619e4f9d60..4b0a9243b7481176 100644
> --- a/drivers/clk/renesas/r8a7745-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c
> @@ -51,7 +51,6 @@ static const struct cpg_core_clk r8a7745_core_clks[] __initconst = {
>  DEF_FIXED(".pll1_div2",CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
>
>  /* Core Clock Outputs */
> -DEF_BASE("lb",   R8A7745_CLK_LB,   CLK_TYPE_GEN2_LB,CLK_PLL1),
>  DEF_BASE("sdh",  R8A7745_CLK_SDH,  CLK_TYPE_GEN2_SDH,CLK_PLL1),
>  DEF_BASE("sd0",  R8A7745_CLK_SD0,  CLK_TYPE_GEN2_SD0,CLK_PLL1),
>  DEF_BASE("qspi", R8A7745_CLK_QSPI, CLK_TYPE_GEN2_QSPI,CLK_PLL1_DIV2),
> @@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7745_core_clks[] __initconst = {
>  DEF_FIXED("zs",    R8A7745_CLK_ZS,CLK_PLL1,    6, 1),
>  DEF_FIXED("hp",    R8A7745_CLK_HP,CLK_PLL1,   12, 1),
>  DEF_FIXED("b",     R8A7745_CLK_B,CLK_PLL1,   12, 1),
> +DEF_FIXED("lb",    R8A7745_CLK_LB,CLK_PLL1,   24, 1),
>  DEF_FIXED("p",     R8A7745_CLK_P,CLK_PLL1,   24, 1),
>  DEF_FIXED("cl",    R8A7745_CLK_CL,CLK_PLL1,   48, 1),
>  DEF_FIXED("cp",    R8A7745_CLK_CP,CLK_PLL1,   48, 1),
> --
> 2.7.4




Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

RE: [PATCH 2/5] clk: renesas: r8a7745: Fix LB clock divider

[Fabrizio Castro]

> Subject: [PATCH 2/5] clk: renesas: r8a7745: Fix LB clock divider
>
> The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
> the LB clock divider depends on the value of the MD18 pin.
>
> On RZ/G1E, the LB clock divider is fixed to 24.  Hence model the clock
> as a fixed factor clock instead.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

> ---
>  drivers/clk/renesas/r8a7745-cpg-mssr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c b/drivers/clk/renesas=
/r8a7745-cpg-mssr.c
> index 87f5a3619e4f9d60..4b0a9243b7481176 100644
> --- a/drivers/clk/renesas/r8a7745-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c
> @@ -51,7 +51,6 @@ static const struct cpg_core_clk r8a7745_core_clks[] __=
initconst =3D {
>  DEF_FIXED(".pll1_div2",CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
>
>  /* Core Clock Outputs */
> -DEF_BASE("lb",   R8A7745_CLK_LB,   CLK_TYPE_GEN2_LB,CLK_PLL1),
>  DEF_BASE("sdh",  R8A7745_CLK_SDH,  CLK_TYPE_GEN2_SDH,CLK_PLL1),
>  DEF_BASE("sd0",  R8A7745_CLK_SD0,  CLK_TYPE_GEN2_SD0,CLK_PLL1),
>  DEF_BASE("qspi", R8A7745_CLK_QSPI, CLK_TYPE_GEN2_QSPI,CLK_PLL1_DIV2),
> @@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7745_core_clks[] __=
initconst =3D {
>  DEF_FIXED("zs",    R8A7745_CLK_ZS,CLK_PLL1,    6, 1),
>  DEF_FIXED("hp",    R8A7745_CLK_HP,CLK_PLL1,   12, 1),
>  DEF_FIXED("b",     R8A7745_CLK_B,CLK_PLL1,   12, 1),
> +DEF_FIXED("lb",    R8A7745_CLK_LB,CLK_PLL1,   24, 1),
>  DEF_FIXED("p",     R8A7745_CLK_P,CLK_PLL1,   24, 1),
>  DEF_FIXED("cl",    R8A7745_CLK_CL,CLK_PLL1,   48, 1),
>  DEF_FIXED("cp",    R8A7745_CLK_CP,CLK_PLL1,   48, 1),
> --
> 2.7.4




Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, B=
uckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered=
 No. 04586709.

RE: [PATCH 4/5] clk: renesas: r8a7792: Fix LB clock divider

[Fabrizio Castro]

Hello Geert

> Subject: [PATCH 4/5] clk: renesas: r8a7792: Fix LB clock divider
>
> The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
> the LB clock divider depends on the value of the MD18 pin.
>
> On R-Car V2H, the LB clock divider is fixed to 24.  Hence model the
> clock as a fixed factor clock instead.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  drivers/clk/renesas/r8a7792-cpg-mssr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c
> index 609a540804965c40..8b66e6f4b4584de1 100644
> --- a/drivers/clk/renesas/r8a7792-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c
> @@ -53,7 +53,6 @@ static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
>  DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
>
>  /* Core Clock Outputs */
> -DEF_BASE("lb",   R8A7792_CLK_LB,   CLK_TYPE_GEN2_LB,   CLK_PLL1),
>  DEF_BASE("qspi", R8A7792_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
>
>  DEF_FIXED("z",      R8A7792_CLK_Z,     CLK_PLL0,          1, 1),
> @@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
>  DEF_FIXED("hp",     R8A7792_CLK_HP,    CLK_PLL1,         12, 1),
>  DEF_FIXED("i",      R8A7792_CLK_I,     CLK_PLL1,          3, 1),
>  DEF_FIXED("b",      R8A7792_CLK_B,     CLK_PLL1,         12, 1),
> +DEF_FIXED("lb",     R8A7792_CLK_B,     CLK_PLL1,         24, 1),

s/ R8A7792_CLK_B/ R8A7792_CLK_LB/

With that fixed:
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

>  DEF_FIXED("p",      R8A7792_CLK_P,     CLK_PLL1,         24, 1),
>  DEF_FIXED("cl",     R8A7792_CLK_CL,    CLK_PLL1,         48, 1),
>  DEF_FIXED("m2",     R8A7792_CLK_M2,    CLK_PLL1,          8, 1),
> --
> 2.7.4




Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

RE: [PATCH 4/5] clk: renesas: r8a7792: Fix LB clock divider

[Fabrizio Castro]

Hello Geert

> Subject: [PATCH 4/5] clk: renesas: r8a7792: Fix LB clock divider
>
> The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
> the LB clock divider depends on the value of the MD18 pin.
>
> On R-Car V2H, the LB clock divider is fixed to 24.  Hence model the
> clock as a fixed factor clock instead.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  drivers/clk/renesas/r8a7792-cpg-mssr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas=
/r8a7792-cpg-mssr.c
> index 609a540804965c40..8b66e6f4b4584de1 100644
> --- a/drivers/clk/renesas/r8a7792-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c
> @@ -53,7 +53,6 @@ static const struct cpg_core_clk r8a7792_core_clks[] __=
initconst =3D {
>  DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
>
>  /* Core Clock Outputs */
> -DEF_BASE("lb",   R8A7792_CLK_LB,   CLK_TYPE_GEN2_LB,   CLK_PLL1),
>  DEF_BASE("qspi", R8A7792_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
>
>  DEF_FIXED("z",      R8A7792_CLK_Z,     CLK_PLL0,          1, 1),
> @@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7792_core_clks[] __=
initconst =3D {
>  DEF_FIXED("hp",     R8A7792_CLK_HP,    CLK_PLL1,         12, 1),
>  DEF_FIXED("i",      R8A7792_CLK_I,     CLK_PLL1,          3, 1),
>  DEF_FIXED("b",      R8A7792_CLK_B,     CLK_PLL1,         12, 1),
> +DEF_FIXED("lb",     R8A7792_CLK_B,     CLK_PLL1,         24, 1),

s/ R8A7792_CLK_B/ R8A7792_CLK_LB/

With that fixed:
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

>  DEF_FIXED("p",      R8A7792_CLK_P,     CLK_PLL1,         24, 1),
>  DEF_FIXED("cl",     R8A7792_CLK_CL,    CLK_PLL1,         48, 1),
>  DEF_FIXED("m2",     R8A7792_CLK_M2,    CLK_PLL1,          8, 1),
> --
> 2.7.4




Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, B=
uckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered=
 No. 04586709.

RE: [PATCH 3/5] clk: renesas: r8a7791/r8a7793: Fix LB clock divider

[Fabrizio Castro]

> Subject: [PATCH 3/5] clk: renesas: r8a7791/r8a7793: Fix LB clock divider
>
> The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
> the LB clock divider depends on the value of the MD18 pin.
>
> On R-Car M2-W and M2-N, the LB clock divider is fixed to 24.  Hence
> model the clock as a fixed factor clock instead.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

> ---
>  drivers/clk/renesas/r8a7791-cpg-mssr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c b/drivers/clk/renesas/r8a7791-cpg-mssr.c
> index 820b220b09cc6bdb..1b91f03b75980766 100644
> --- a/drivers/clk/renesas/r8a7791-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c
> @@ -57,7 +57,6 @@ static struct cpg_core_clk r8a7791_core_clks[] __initdata = {
>
>  /* Core Clock Outputs */
>  DEF_BASE("z",    R8A7791_CLK_Z,    CLK_TYPE_GEN2_Z,    CLK_PLL0),
> -DEF_BASE("lb",   R8A7791_CLK_LB,   CLK_TYPE_GEN2_LB,   CLK_PLL1),
>  DEF_BASE("adsp", R8A7791_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
>  DEF_BASE("sdh",  R8A7791_CLK_SDH,  CLK_TYPE_GEN2_SDH,  CLK_PLL1),
>  DEF_BASE("sd0",  R8A7791_CLK_SD0,  CLK_TYPE_GEN2_SD0,  CLK_PLL1),
> @@ -70,6 +69,7 @@ static struct cpg_core_clk r8a7791_core_clks[] __initdata = {
>  DEF_FIXED("hp",     R8A7791_CLK_HP,    CLK_PLL1,         12, 1),
>  DEF_FIXED("i",      R8A7791_CLK_I,     CLK_PLL1,          2, 1),
>  DEF_FIXED("b",      R8A7791_CLK_B,     CLK_PLL1,         12, 1),
> +DEF_FIXED("lb",     R8A7791_CLK_LB,    CLK_PLL1,         24, 1),
>  DEF_FIXED("p",      R8A7791_CLK_P,     CLK_PLL1,         24, 1),
>  DEF_FIXED("cl",     R8A7791_CLK_CL,    CLK_PLL1,         48, 1),
>  DEF_FIXED("m2",     R8A7791_CLK_M2,    CLK_PLL1,          8, 1),
> --
> 2.7.4




Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

RE: [PATCH 3/5] clk: renesas: r8a7791/r8a7793: Fix LB clock divider

[Fabrizio Castro]

> Subject: [PATCH 3/5] clk: renesas: r8a7791/r8a7793: Fix LB clock divider
>
> The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
> the LB clock divider depends on the value of the MD18 pin.
>
> On R-Car M2-W and M2-N, the LB clock divider is fixed to 24.  Hence
> model the clock as a fixed factor clock instead.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

> ---
>  drivers/clk/renesas/r8a7791-cpg-mssr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c b/drivers/clk/renesas=
/r8a7791-cpg-mssr.c
> index 820b220b09cc6bdb..1b91f03b75980766 100644
> --- a/drivers/clk/renesas/r8a7791-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c
> @@ -57,7 +57,6 @@ static struct cpg_core_clk r8a7791_core_clks[] __initda=
ta =3D {
>
>  /* Core Clock Outputs */
>  DEF_BASE("z",    R8A7791_CLK_Z,    CLK_TYPE_GEN2_Z,    CLK_PLL0),
> -DEF_BASE("lb",   R8A7791_CLK_LB,   CLK_TYPE_GEN2_LB,   CLK_PLL1),
>  DEF_BASE("adsp", R8A7791_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
>  DEF_BASE("sdh",  R8A7791_CLK_SDH,  CLK_TYPE_GEN2_SDH,  CLK_PLL1),
>  DEF_BASE("sd0",  R8A7791_CLK_SD0,  CLK_TYPE_GEN2_SD0,  CLK_PLL1),
> @@ -70,6 +69,7 @@ static struct cpg_core_clk r8a7791_core_clks[] __initda=
ta =3D {
>  DEF_FIXED("hp",     R8A7791_CLK_HP,    CLK_PLL1,         12, 1),
>  DEF_FIXED("i",      R8A7791_CLK_I,     CLK_PLL1,          2, 1),
>  DEF_FIXED("b",      R8A7791_CLK_B,     CLK_PLL1,         12, 1),
> +DEF_FIXED("lb",     R8A7791_CLK_LB,    CLK_PLL1,         24, 1),
>  DEF_FIXED("p",      R8A7791_CLK_P,     CLK_PLL1,         24, 1),
>  DEF_FIXED("cl",     R8A7791_CLK_CL,    CLK_PLL1,         48, 1),
>  DEF_FIXED("m2",     R8A7791_CLK_M2,    CLK_PLL1,          8, 1),
> --
> 2.7.4




Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, B=
uckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered=
 No. 04586709.

RE: [PATCH 5/5] clk: renesas: r8a7794: Fix LB clock divider

[Fabrizio Castro]

Hello Geert,

> Subject: [PATCH 5/5] clk: renesas: r8a7794: Fix LB clock divider
>
> The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
> the LB clock divider depends on the value of the MD18 pin.
>
> On R-Car E2, the LB clock divider is fixed to 24.  Hence model the clock
> as a fixed factor clock instead.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  drivers/clk/renesas/r8a7794-cpg-mssr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c b/drivers/clk/renesas/r8a7794-cpg-mssr.c
> index 2a40bbeaeeafc2a4..3ce74f063fa86b19 100644
> --- a/drivers/clk/renesas/r8a7794-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c
> @@ -55,7 +55,6 @@ static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
>  DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
>
>  /* Core Clock Outputs */
> -DEF_BASE("lb",   R8A7794_CLK_LB,   CLK_TYPE_GEN2_LB,   CLK_PLL1),
>  DEF_BASE("adsp", R8A7794_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
>  DEF_BASE("sdh",  R8A7794_CLK_SDH,  CLK_TYPE_GEN2_SDH,  CLK_PLL1),
>  DEF_BASE("sd0",  R8A7794_CLK_SD0,  CLK_TYPE_GEN2_SD0,  CLK_PLL1),
> @@ -69,6 +68,7 @@ static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
>  DEF_FIXED("hp",     R8A7794_CLK_HP,    CLK_PLL1,         12, 1),
>  DEF_FIXED("i",      R8A7794_CLK_I,     CLK_PLL1,          2, 1),
>  DEF_FIXED("b",      R8A7794_CLK_B,     CLK_PLL1,         12, 1),
> +DEF_FIXED("lb",     R8A7794_CLK_B,     CLK_PLL1,         24, 1),

s/R8A7794_CLK_B/R8A7794_CLK_LB/

With that fixed:
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

>  DEF_FIXED("p",      R8A7794_CLK_P,     CLK_PLL1,         24, 1),
>  DEF_FIXED("cl",     R8A7794_CLK_CL,    CLK_PLL1,         48, 1),
>  DEF_FIXED("cp",     R8A7794_CLK_CP,    CLK_PLL1,         48, 1),
> --
> 2.7.4




Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

RE: [PATCH 5/5] clk: renesas: r8a7794: Fix LB clock divider

[Fabrizio Castro]

Hello Geert,

> Subject: [PATCH 5/5] clk: renesas: r8a7794: Fix LB clock divider
>
> The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
> the LB clock divider depends on the value of the MD18 pin.
>
> On R-Car E2, the LB clock divider is fixed to 24.  Hence model the clock
> as a fixed factor clock instead.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  drivers/clk/renesas/r8a7794-cpg-mssr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c b/drivers/clk/renesas=
/r8a7794-cpg-mssr.c
> index 2a40bbeaeeafc2a4..3ce74f063fa86b19 100644
> --- a/drivers/clk/renesas/r8a7794-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c
> @@ -55,7 +55,6 @@ static const struct cpg_core_clk r8a7794_core_clks[] __=
initconst =3D {
>  DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
>
>  /* Core Clock Outputs */
> -DEF_BASE("lb",   R8A7794_CLK_LB,   CLK_TYPE_GEN2_LB,   CLK_PLL1),
>  DEF_BASE("adsp", R8A7794_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
>  DEF_BASE("sdh",  R8A7794_CLK_SDH,  CLK_TYPE_GEN2_SDH,  CLK_PLL1),
>  DEF_BASE("sd0",  R8A7794_CLK_SD0,  CLK_TYPE_GEN2_SD0,  CLK_PLL1),
> @@ -69,6 +68,7 @@ static const struct cpg_core_clk r8a7794_core_clks[] __=
initconst =3D {
>  DEF_FIXED("hp",     R8A7794_CLK_HP,    CLK_PLL1,         12, 1),
>  DEF_FIXED("i",      R8A7794_CLK_I,     CLK_PLL1,          2, 1),
>  DEF_FIXED("b",      R8A7794_CLK_B,     CLK_PLL1,         12, 1),
> +DEF_FIXED("lb",     R8A7794_CLK_B,     CLK_PLL1,         24, 1),

s/R8A7794_CLK_B/R8A7794_CLK_LB/

With that fixed:
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

>  DEF_FIXED("p",      R8A7794_CLK_P,     CLK_PLL1,         24, 1),
>  DEF_FIXED("cl",     R8A7794_CLK_CL,    CLK_PLL1,         48, 1),
>  DEF_FIXED("cp",     R8A7794_CLK_CP,    CLK_PLL1,         48, 1),
> --
> 2.7.4




Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, B=
uckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered=
 No. 04586709.

Re: [PATCH 4/5] clk: renesas: r8a7792: Fix LB clock divider

[Geert Uytterhoeven]

Hi Fabrizio,

On Tue, Apr 3, 2018 at 12:17 PM, Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
>> Subject: [PATCH 4/5] clk: renesas: r8a7792: Fix LB clock divider
>>
>> The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
>> the LB clock divider depends on the value of the MD18 pin.
>>
>> On R-Car V2H, the LB clock divider is fixed to 24.  Hence model the
>> clock as a fixed factor clock instead.
>>
>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>> ---
>>  drivers/clk/renesas/r8a7792-cpg-mssr.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c
>> index 609a540804965c40..8b66e6f4b4584de1 100644
>> --- a/drivers/clk/renesas/r8a7792-cpg-mssr.c
>> +++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c
>> @@ -53,7 +53,6 @@ static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
>>  DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
>>
>>  /* Core Clock Outputs */
>> -DEF_BASE("lb",   R8A7792_CLK_LB,   CLK_TYPE_GEN2_LB,   CLK_PLL1),
>>  DEF_BASE("qspi", R8A7792_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
>>
>>  DEF_FIXED("z",      R8A7792_CLK_Z,     CLK_PLL0,          1, 1),
>> @@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
>>  DEF_FIXED("hp",     R8A7792_CLK_HP,    CLK_PLL1,         12, 1),
>>  DEF_FIXED("i",      R8A7792_CLK_I,     CLK_PLL1,          3, 1),
>>  DEF_FIXED("b",      R8A7792_CLK_B,     CLK_PLL1,         12, 1),
>> +DEF_FIXED("lb",     R8A7792_CLK_B,     CLK_PLL1,         24, 1),
>
> s/ R8A7792_CLK_B/ R8A7792_CLK_LB/
>
> With that fixed:
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Thanks, nice catch. Fixing up (also for r8a7794).

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds