* [PATCH v3 0/7] Add Renesas RZ/G2UL Type-1 {SoC,SMARC EVK} support
@ 2022-03-15 14:26 Biju Das
2022-03-15 14:26 ` [PATCH v3 1/7] dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoC Biju Das
` (5 more replies)
0 siblings, 6 replies; 22+ messages in thread
From: Biju Das @ 2022-03-15 14:26 UTC (permalink / raw)
To: Rob Herring, Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Hi All,
RZ/G2UL Family SoC consists of Type-1 and Type-2 SoC's.
Both these SoC's has single Core 1.0GHz CA-55 with similar
peripheral IP's to that of RZ/G2LC and RZ/G2L.
The difference between Type1 and Type2 SoC's are as follows
Function Type1 Type2
SCIF 5ch {0,1,2,3,4} 4ch {0,1,2,3}
Ethernet 2ch {0,1} 1ch {0}
SSI 4ch {0,1,2,3} 3ch {0,1,2}
ADC 2ch {0,1} N/A
DU 1ch Parallel I/F N/A
RZ/G2UL Type-2 is pin compatible with RZ/G2LC, so the number of channels
for each IP matches with RZ/G2LC.
The table below shows the functional differences between RZ/G2LC and
RZ/G2UL Type-2.
Function RZ/G2LC RZ/G2UL Type-2
Cortex-A55 Dual 1.2GHz Single 1.0GHz
DU 1ch MIPI-DSI N/A
GPT 6ch {0,3,4,5,6,7} N/A
Mali-31 1ch N/A
This patch series aims to add support for Renesas RZ/G2UL Type-1 SoC and
basic support for Renesas RZ/G2UL SMARC EVK (based on R9A07G043U11)
- memory
- External input clock
- SCIF
- GbEthernet
It shares the same carrier board with RZ/G2L, but the pin mapping is
different. Place holders are added in device nodes to avoid compilation
errors for the devices which have not been enabled yet on RZ/G2UL SoC.
Also disable the device nodes which is not tested and delete the
corresponding pinctrl definitions.
Test logs:-
/ # for i in machine family soc_id revision; do echo -n "$i: "; cat /sys/devices/soc0/$i;done
machine: Renesas SMARC EVK based on r9a07g043u11
family: RZ/G2UL
soc_id: r9a07g043
revision: 0
/ # cat /proc/cpuinfo
processor : 0
BogoMIPS : 48.00
Features : fp asimd evtstrm crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x2
CPU part : 0xd05
CPU revision : 0
/ # cat /proc/interrupts
CPU0
11: 1439 GICv3 27 Level arch_timer
13: 0 GICv3 412 Level 1004b800.serial:rx err
14: 15 GICv3 414 Level 1004b800.serial:rx full
15: 351 GICv3 415 Level 1004b800.serial:tx empty
16: 0 GICv3 413 Level 1004b800.serial:break
17: 5 GICv3 416 Level 1004b800.serial:rx ready
18: 0 GICv3 173 Edge error
19: 0 GICv3 157 Edge 11820000.dma-controller:0
20: 0 GICv3 158 Edge 11820000.dma-controller:1
21: 0 GICv3 159 Edge 11820000.dma-controller:2
22: 0 GICv3 160 Edge 11820000.dma-controller:3
23: 0 GICv3 161 Edge 11820000.dma-controller:4
24: 0 GICv3 162 Edge 11820000.dma-controller:5
25: 0 GICv3 163 Edge 11820000.dma-controller:6
26: 0 GICv3 164 Edge 11820000.dma-controller:7
27: 0 GICv3 165 Edge 11820000.dma-controller:8
28: 0 GICv3 166 Edge 11820000.dma-controller:9
29: 0 GICv3 167 Edge 11820000.dma-controller:10
30: 0 GICv3 168 Edge 11820000.dma-controller:11
31: 0 GICv3 169 Edge 11820000.dma-controller:12
32: 0 GICv3 170 Edge 11820000.dma-controller:13
33: 0 GICv3 171 Edge 11820000.dma-controller:14
34: 0 GICv3 172 Edge 11820000.dma-controller:15
IPI0: 0 Rescheduling interrupts
IPI1: 0 Function call interrupts
IPI2: 0 CPU stop interrupts
IPI3: 0 CPU stop (for crash dump) interrupts
IPI4: 0 Timer broadcast interrupts
IPI5: 1 IRQ work interrupts
IPI6: 0 CPU wake-up interrupts
Err: 0
/ # cat /proc/meminfo
MemTotal: 868744 kB
MemFree: 820840 kB
MemAvailable: 797676 kB
Buffers: 0 kB
Cached: 3948 kB
SwapCached: 0 kB
Active: 4 kB
Inactive: 72 kB
Active(anon): 4 kB
Inactive(anon): 72 kB
Active(file): 0 kB
Inactive(file): 0 kB
Unevictable: 3948 kB
Mlocked: 0 kB
SwapTotal: 0 kB
SwapFree: 0 kB
Dirty: 0 kB
Writeback: 0 kB
AnonPages: 112 kB
Mapped: 1300 kB
Shmem: 0 kB
KReclaimable: 21256 kB
Slab: 30352 kB
SReclaimable: 21256 kB
SUnreclaim: 9096 kB
KernelStack: 908 kB
PageTables: 64 kB
NFS_Unstable: 0 kB
Bounce: 0 kB
WritebackTmp: 0 kB
CommitLimit: 434372 kB
Committed_AS: 592 kB
VmallocTotal: 133143592960 kB
VmallocUsed: 1188 kB
VmallocChunk: 0 kB
Percpu: 120 kB
AnonHugePages: 0 kB
ShmemHugePages: 0 kB
ShmemPmdMapped: 0 kB
FileHugePages: 0 kB
FilePmdMapped: 0 kB
CmaTotal: 131072 kB
CmaFree: 130688 kB
HugePages_Total: 0
HugePages_Free: 0
HugePages_Rsvd: 0
HugePages_Surp: 0
Hugepagesize: 2048 kB
Hugetlb: 0 kB
/ # mount -t debugfs none /sys/kernel/debug/
/ # cat /sys/kernel/debug/clk/clk_summary
enable prepare protect duty hardware
clock count count count rate accuracy phase cycle enable
-------------------------------------------------------------------------------------------------------
audio_mclock 0 0 0 11289600 0 0 50000 Y
extal 2 2 0 24000000 0 0 50000 Y
.pll6 0 0 0 500000000 0 0 50000 Y
.pll5 0 0 0 3000000000 0 0 50000 Y
.pll3 1 1 0 1600000000 0 0 50000 Y
.pll3_div2 1 1 0 800000000 0 0 50000 Y
.pll3_div2_4 1 1 0 200000000 0 0 50000 Y
P1 4 4 0 200000000 0 0 50000 Y
dmac_aclk 2 2 0 200000000 0 0 50000 Y
ia55_clk 1 1 0 200000000 0 0 50000 Y
gic 1 1 0 200000000 0 0 50000 Y
P1_DIV2 1 1 0 100000000 0 0 50000 Y
dmac_pclk 1 1 0 100000000 0 0 50000 Y
.pll3_div2_4_2 0 0 0 100000000 0 0 50000 Y
P2 0 0 0 100000000 0 0 50000 Y
ia55_pclk 0 0 0 100000000 0 0 50000 N
.pll2 1 1 0 1600000000 0 0 50000 Y
.pll2_div2 1 1 0 800000000 0 0 50000 Y
.pll2_div2_8 1 1 0 100000000 0 0 50000 Y
P0 1 1 0 100000000 0 0 50000 Y
sci1 0 0 0 100000000 0 0 50000 N
sci0 0 0 0 100000000 0 0 50000 N
scif4 0 0 0 100000000 0 0 50000 N
scif3 0 0 0 100000000 0 0 50000 N
scif2 0 0 0 100000000 0 0 50000 N
scif1 0 0 0 100000000 0 0 50000 N
scif0 2 2 0 100000000 0 0 50000 Y
.pll1 0 0 0 1000000000 0 0 50000 Y
I 0 0 0 1000000000 0 0 50000 Y
.osc_div1000 0 0 0 24000 0 0 50000 Y
.osc 0 0 0 24000000 0 0 50000 Y
can 0 0 0 0 0 0 50000 Y
audio_clk2 0 0 0 12288000 0 0 50000 Y
audio_clk1 0 0 0 11289600 0 0 50000 Y
/ #
v2->v3:
* Changed the compatible from r9a07g043u-sysc->r9a07g043-sysc
* Changed the compatible from r9a07g043u-cpg->r9a07g043-cpg
* Retained Rb tag from Rob as it is trivial change.
* Changed the config from ARCH_R9A07G043U->ARCH_R9A07G043
* renamed the file r9a07g043u-cpg.h->r9a07g043-cpg.h
* Prepared Common Module Clock/Reset indices for RZ/G2UL and RZ/Five
* Prepared RZ/G2UL specific Module Clock/Reset indices.
*
Biju Das (7):
dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoC
soc: renesas: Identify RZ/G2UL SoC
dt-bindings: clock: Add R9A07G043 CPG Clock and Reset Definitions
dt-bindings: clock: renesas: Document RZ/G2UL SoC
clk: renesas: Add support for RZ/G2UL SoC
arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC
arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC
EVK
.../bindings/clock/renesas,rzg2l-cpg.yaml | 7 +-
.../bindings/power/renesas,rzg2l-sysc.yaml | 9 +-
arch/arm64/boot/dts/renesas/Makefile | 2 +
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 413 ++++++++++++++++++
.../boot/dts/renesas/r9a07g043u11-smarc.dts | 111 +++++
.../boot/dts/renesas/rzg2ul-smarc-som.dtsi | 25 ++
drivers/clk/renesas/Kconfig | 7 +-
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r9a07g043-cpg.c | 157 +++++++
drivers/clk/renesas/rzg2l-cpg.c | 6 +
drivers/clk/renesas/rzg2l-cpg.h | 1 +
drivers/soc/renesas/Kconfig | 6 +
drivers/soc/renesas/renesas-soc.c | 13 +
include/dt-bindings/clock/r9a07g043-cpg.h | 190 ++++++++
14 files changed, 940 insertions(+), 8 deletions(-)
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
create mode 100644 arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
create mode 100644 drivers/clk/renesas/r9a07g043-cpg.c
create mode 100644 include/dt-bindings/clock/r9a07g043-cpg.h
--
2.17.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 1/7] dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoC
2022-03-15 14:26 [PATCH v3 0/7] Add Renesas RZ/G2UL Type-1 {SoC,SMARC EVK} support Biju Das
@ 2022-03-15 14:26 ` Biju Das
2022-03-30 13:09 ` Geert Uytterhoeven
2022-03-15 14:26 ` [PATCH v3 2/7] soc: renesas: Identify " Biju Das
` (4 subsequent siblings)
5 siblings, 1 reply; 22+ messages in thread
From: Biju Das @ 2022-03-15 14:26 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Geert Uytterhoeven, Lad Prabhakar, devicetree,
Chris Paterson, Biju Das, linux-renesas-soc
Add DT binding documentation for SYSC controller found on RZ/G2UL SoC's.
SYSC controller found on the RZ/G2UL SoC is almost identical to one found
on the RZ/G2L SoC's only difference being that the RZ/G2UL has only CA55
core0 reset vector address configuration register.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
v2->v3:
* Changed the compatible from r9a07g043u-sysc->r9a07g043-sysc
* Retained Rb tag from Rob as it is trivial change.
V1->V2:
* No change
---
.../devicetree/bindings/power/renesas,rzg2l-sysc.yaml | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
index bb433e75a0ee..9ccc23ae7054 100644
--- a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
+++ b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
@@ -10,8 +10,8 @@ maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
description:
- The RZ/{G2L,V2L} System Controller (SYSC) performs system control of the LSI
- and supports following functions,
+ The RZ/{G2L,V2L}-alike System Controller (SYSC) performs system control of
+ the LSI and supports following functions,
- External terminal state capture function
- 34-bit address space access function
- Low power consumption control
@@ -20,8 +20,9 @@ description:
properties:
compatible:
enum:
- - renesas,r9a07g044-sysc # RZ/G2{L,LC}
- - renesas,r9a07g054-sysc # RZ/V2L
+ - renesas,r9a07g043-sysc # RZ/G2UL
+ - renesas,r9a07g044-sysc # RZ/G2{L,LC}
+ - renesas,r9a07g054-sysc # RZ/V2L
reg:
maxItems: 1
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3 2/7] soc: renesas: Identify RZ/G2UL SoC
2022-03-15 14:26 [PATCH v3 0/7] Add Renesas RZ/G2UL Type-1 {SoC,SMARC EVK} support Biju Das
2022-03-15 14:26 ` [PATCH v3 1/7] dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoC Biju Das
@ 2022-03-15 14:26 ` Biju Das
2022-03-30 13:17 ` Geert Uytterhoeven
2022-03-15 14:26 ` [PATCH v3 3/7] dt-bindings: clock: Add R9A07G043 CPG Clock and Reset Definitions Biju Das
` (3 subsequent siblings)
5 siblings, 1 reply; 22+ messages in thread
From: Biju Das @ 2022-03-15 14:26 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Biju Das, Magnus Damm, linux-renesas-soc, Chris Paterson,
Biju Das, Prabhakar Mahadev Lad
Add support for identifying the RZ/G2UL SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2->v3:
* Changed compatible from r9a07g043u11->r9a07g043.
* Changed the config from ARCH_R9A07G043U->ARCH_R9A07G043
* Changed sysc compatible from r9a07g043u-sysc->r9a07g043-sysc
v1->v2:
* Change compatible from r9a07g043u->r9a07g043u11.
---
drivers/soc/renesas/Kconfig | 6 ++++++
drivers/soc/renesas/renesas-soc.c | 13 +++++++++++++
2 files changed, 19 insertions(+)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index fdc99a05a7e0..63477f05fbaf 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -296,6 +296,12 @@ config ARCH_R8A774B1
help
This enables support for the Renesas RZ/G2N SoC.
+config ARCH_R9A07G043
+ bool "ARM64 Platform support for RZ/G2UL"
+ select ARCH_RZG2L
+ help
+ This enables support for the Renesas RZ/G2UL SoC variants.
+
config ARCH_R9A07G044
bool "ARM64 Platform support for RZ/G2L"
select ARCH_RZG2L
diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index 92c7b42250ee..30192a099d38 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -64,6 +64,10 @@ static const struct renesas_family fam_rzg2l __initconst __maybe_unused = {
.name = "RZ/G2L",
};
+static const struct renesas_family fam_rzg2ul __initconst __maybe_unused = {
+ .name = "RZ/G2UL",
+};
+
static const struct renesas_family fam_rzv2l __initconst __maybe_unused = {
.name = "RZ/V2L",
};
@@ -148,6 +152,11 @@ static const struct renesas_soc soc_rz_g2l __initconst __maybe_unused = {
.id = 0x841c447,
};
+static const struct renesas_soc soc_rz_g2ul __initconst __maybe_unused = {
+ .family = &fam_rzg2ul,
+ .id = 0x8450447,
+};
+
static const struct renesas_soc soc_rz_v2l __initconst __maybe_unused = {
.family = &fam_rzv2l,
.id = 0x8447447,
@@ -340,6 +349,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
#ifdef CONFIG_ARCH_R8A779F0
{ .compatible = "renesas,r8a779f0", .data = &soc_rcar_s4 },
#endif
+#if defined(CONFIG_ARCH_R9A07G043)
+ { .compatible = "renesas,r9a07g043", .data = &soc_rz_g2ul },
+#endif
#if defined(CONFIG_ARCH_R9A07G044)
{ .compatible = "renesas,r9a07g044", .data = &soc_rz_g2l },
#endif
@@ -378,6 +390,7 @@ static const struct renesas_id id_prr __initconst = {
static const struct of_device_id renesas_ids[] __initconst = {
{ .compatible = "renesas,bsid", .data = &id_bsid },
+ { .compatible = "renesas,r9a07g043-sysc", .data = &id_rzg2l },
{ .compatible = "renesas,r9a07g044-sysc", .data = &id_rzg2l },
{ .compatible = "renesas,r9a07g054-sysc", .data = &id_rzg2l },
{ .compatible = "renesas,prr", .data = &id_prr },
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3 3/7] dt-bindings: clock: Add R9A07G043 CPG Clock and Reset Definitions
2022-03-15 14:26 [PATCH v3 0/7] Add Renesas RZ/G2UL Type-1 {SoC,SMARC EVK} support Biju Das
2022-03-15 14:26 ` [PATCH v3 1/7] dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoC Biju Das
2022-03-15 14:26 ` [PATCH v3 2/7] soc: renesas: Identify " Biju Das
@ 2022-03-15 14:26 ` Biju Das
2022-03-23 18:41 ` Rob Herring
2022-03-30 19:27 ` Geert Uytterhoeven
2022-03-15 14:26 ` [PATCH v3 5/7] clk: renesas: Add support for RZ/G2UL SoC Biju Das
` (2 subsequent siblings)
5 siblings, 2 replies; 22+ messages in thread
From: Biju Das @ 2022-03-15 14:26 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, devicetree, Geert Uytterhoeven, Chris Paterson,
Biju Das, Prabhakar Mahadev Lad, linux-renesas-soc
Define RZ/G2UL (R9A07G043U) Clock Pulse Generator Core Clock and module
clock outputs, as listed in Table 7.1.4.2 ("Clock List r0.51") and also
add Reset definitions referring to registers CPG_RST_* in Section 7.2.3
("Register configuration") of the RZ/G2UL Hardware User's Manual (Rev.
0.51, Nov. 2021).
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2->v3:
* Removed leading u/U from r9a07g043
* renamed the file r9a07g043u-cpg.h->r9a07g043-cpg.h
* Prepared Common Module Clock/Reset indices for RZ/G2UL and RZ/Five
* Prepared RZ/G2UL specific Module Clock/Reset indices.
v1->v2:
* No change
---
include/dt-bindings/clock/r9a07g043-cpg.h | 190 ++++++++++++++++++++++
1 file changed, 190 insertions(+)
create mode 100644 include/dt-bindings/clock/r9a07g043-cpg.h
diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-bindings/clock/r9a07g043-cpg.h
new file mode 100644
index 000000000000..a3429ad15aad
--- /dev/null
+++ b/include/dt-bindings/clock/r9a07g043-cpg.h
@@ -0,0 +1,190 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__
+#define __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R9A07G043 CPG Core Clocks */
+#define R9A07G043_CLK_I 0
+#define R9A07G043_CLK_I2 1
+#define R9A07G043_CLK_S0 2
+#define R9A07G043_CLK_SPI0 3
+#define R9A07G043_CLK_SPI1 4
+#define R9A07G043_CLK_SD0 5
+#define R9A07G043_CLK_SD1 6
+#define R9A07G043_CLK_M0 7
+#define R9A07G043_CLK_M2 8
+#define R9A07G043_CLK_M3 9
+#define R9A07G043_CLK_HP 10
+#define R9A07G043_CLK_TSU 11
+#define R9A07G043_CLK_ZT 12
+#define R9A07G043_CLK_P0 13
+#define R9A07G043_CLK_P1 14
+#define R9A07G043_CLK_P2 15
+#define R9A07G043_CLK_AT 16
+#define R9A07G043_OSCCLK 17
+#define R9A07G043_CLK_P0_DIV2 18
+
+/* R9A07G043 Common Module Clocks */
+#define R9A07G043_IA55_CLK 0
+#define R9A07G043_IA55_PCLK 1
+#define R9A07G043_DMAC_ACLK 2
+#define R9A07G043_DMAC_PCLK 3
+#define R9A07G043_OSTM0_PCLK 4
+#define R9A07G043_OSTM1_PCLK 5
+#define R9A07G043_OSTM2_PCLK 6
+#define R9A07G043_MTU_X_MCK_MTU3 7
+#define R9A07G043_POE3_CLKM_POE 8
+#define R9A07G043_WDT0_PCLK 9
+#define R9A07G043_WDT0_CLK 10
+#define R9A07G043_SPI_CLK2 11
+#define R9A07G043_SPI_CLK 12
+#define R9A07G043_SDHI0_IMCLK 13
+#define R9A07G043_SDHI0_IMCLK2 14
+#define R9A07G043_SDHI0_CLK_HS 15
+#define R9A07G043_SDHI0_ACLK 16
+#define R9A07G043_SDHI1_IMCLK 17
+#define R9A07G043_SDHI1_IMCLK2 18
+#define R9A07G043_SDHI1_CLK_HS 19
+#define R9A07G043_SDHI1_ACLK 20
+#define R9A07G043_SSI0_PCLK2 21
+#define R9A07G043_SSI0_PCLK_SFR 22
+#define R9A07G043_SSI1_PCLK2 23
+#define R9A07G043_SSI1_PCLK_SFR 24
+#define R9A07G043_SSI2_PCLK2 25
+#define R9A07G043_SSI2_PCLK_SFR 26
+#define R9A07G043_SSI3_PCLK2 27
+#define R9A07G043_SSI3_PCLK_SFR 28
+#define R9A07G043_SRC_CLKP 29
+#define R9A07G043_USB_U2H0_HCLK 30
+#define R9A07G043_USB_U2H1_HCLK 31
+#define R9A07G043_USB_U2P_EXR_CPUCLK 32
+#define R9A07G043_USB_PCLK 33
+#define R9A07G043_ETH0_CLK_AXI 34
+#define R9A07G043_ETH0_CLK_CHI 35
+#define R9A07G043_ETH1_CLK_AXI 36
+#define R9A07G043_ETH1_CLK_CHI 37
+#define R9A07G043_I2C0_PCLK 38
+#define R9A07G043_I2C1_PCLK 39
+#define R9A07G043_I2C2_PCLK 40
+#define R9A07G043_I2C3_PCLK 41
+#define R9A07G043_SCIF0_CLK_PCK 42
+#define R9A07G043_SCIF1_CLK_PCK 43
+#define R9A07G043_SCIF2_CLK_PCK 44
+#define R9A07G043_SCIF3_CLK_PCK 45
+#define R9A07G043_SCIF4_CLK_PCK 46
+#define R9A07G043_SCI0_CLKP 47
+#define R9A07G043_SCI1_CLKP 48
+#define R9A07G043_IRDA_CLKP 49
+#define R9A07G043_RSPI0_CLKB 50
+#define R9A07G043_RSPI1_CLKB 51
+#define R9A07G043_RSPI2_CLKB 52
+#define R9A07G043_CANFD_PCLK 53
+#define R9A07G043_GPIO_HCLK 54
+#define R9A07G043_ADC_ADCLK 55
+#define R9A07G043_ADC_PCLK 56
+#define R9A07G043_TSU_PCLK 57
+#define R9A07G043_LAST_COMMON_CLK (R9A07G043_TSU_PCLK)
+
+/* RZ/G2UL Specific */
+#define R9A07G043_CA55_SCLK (R9A07G043_LAST_COMMON_CLK + 1)
+#define R9A07G043_CA55_PCLK (R9A07G043_LAST_COMMON_CLK + 2)
+#define R9A07G043_CA55_ATCLK (R9A07G043_LAST_COMMON_CLK + 3)
+#define R9A07G043_CA55_GICCLK (R9A07G043_LAST_COMMON_CLK + 4)
+#define R9A07G043_CA55_PERICLK (R9A07G043_LAST_COMMON_CLK + 5)
+#define R9A07G043_CA55_ACLK (R9A07G043_LAST_COMMON_CLK + 6)
+#define R9A07G043_CA55_TSCLK (R9A07G043_LAST_COMMON_CLK + 7)
+#define R9A07G043_GIC600_GICCLK (R9A07G043_LAST_COMMON_CLK + 8)
+#define R9A07G043_MHU_PCLK (R9A07G043_LAST_COMMON_CLK + 9)
+#define R9A07G043_SYC_CNT_CLK (R9A07G043_LAST_COMMON_CLK + 10)
+#define R9A07G043_WDT2_PCLK (R9A07G043_LAST_COMMON_CLK + 11)
+#define R9A07G043_WDT2_CLK (R9A07G043_LAST_COMMON_CLK + 12)
+#define R9A07G043_ISU_ACLK (R9A07G043_LAST_COMMON_CLK + 13)
+#define R9A07G043_ISU_PCLK (R9A07G043_LAST_COMMON_CLK + 14)
+#define R9A07G043_CRU_SYSCLK (R9A07G043_LAST_COMMON_CLK + 15)
+#define R9A07G043_CRU_VCLK (R9A07G043_LAST_COMMON_CLK + 16)
+#define R9A07G043_CRU_PCLK (R9A07G043_LAST_COMMON_CLK + 17)
+#define R9A07G043_CRU_ACLK (R9A07G043_LAST_COMMON_CLK + 18)
+#define R9A07G043_LCDC_CLK_A (R9A07G043_LAST_COMMON_CLK + 19)
+#define R9A07G043_LCDC_CLK_P (R9A07G043_LAST_COMMON_CLK + 20)
+#define R9A07G043_LCDC_CLK_D (R9A07G043_LAST_COMMON_CLK + 21)
+
+/* R9A07G043 Common Resets */
+#define R9A07G043_IA55_RESETN 0
+#define R9A07G043_DMAC_ARESETN 1
+#define R9A07G043_DMAC_RST_ASYNC 2
+#define R9A07G043_OSTM0_PRESETZ 3
+#define R9A07G043_OSTM1_PRESETZ 4
+#define R9A07G043_OSTM2_PRESETZ 5
+#define R9A07G043_MTU_X_PRESET_MTU3 6
+#define R9A07G043_POE3_RST_M_REG 7
+#define R9A07G043_WDT0_PRESETN 8
+#define R9A07G043_SPI_RST 9
+#define R9A07G043_SDHI0_IXRST 10
+#define R9A07G043_SDHI1_IXRST 11
+#define R9A07G043_SRC_RST 12
+#define R9A07G043_USB_U2H0_HRESETN 13
+#define R9A07G043_USB_U2H1_HRESETN 14
+#define R9A07G043_USB_U2P_EXL_SYSRST 15
+#define R9A07G043_USB_PRESETN 16
+#define R9A07G043_I2C0_MRST 17
+#define R9A07G043_I2C1_MRST 18
+#define R9A07G043_I2C2_MRST 19
+#define R9A07G043_I2C3_MRST 20
+#define R9A07G043_SCI0_RST 21
+#define R9A07G043_SCI1_RST 22
+#define R9A07G043_IRDA_RST 23
+#define R9A07G043_RSPI0_RST 24
+#define R9A07G043_RSPI1_RST 25
+#define R9A07G043_RSPI2_RST 26
+#define R9A07G043_CANFD_RSTP_N 27
+#define R9A07G043_CANFD_RSTC_N 28
+#define R9A07G043_GPIO_RSTN 29
+#define R9A07G043_GPIO_PORT_RESETN 30
+#define R9A07G043_GPIO_SPARE_RESETN 31
+#define R9A07G043_TSU_PRESETN 32
+#define R9A07G043_SSI0_RST_M2_REG 33
+#define R9A07G043_SSI1_RST_M2_REG 34
+#define R9A07G043_SSI2_RST_M2_REG 35
+#define R9A07G043_SSI3_RST_M2_REG 36
+#define R9A07G043_ETH0_RST_HW_N 37
+#define R9A07G043_ETH1_RST_HW_N 38
+#define R9A07G043_SCIF0_RST_SYSTEM_N 39
+#define R9A07G043_SCIF1_RST_SYSTEM_N 40
+#define R9A07G043_SCIF2_RST_SYSTEM_N 41
+#define R9A07G043_SCIF3_RST_SYSTEM_N 42
+#define R9A07G043_SCIF4_RST_SYSTEM_N 43
+#define R9A07G043_ADC_PRESETN 44
+#define R9A07G043_ADC_ADRST_N 45
+#define R9A07G043_LAST_COMMON_RST (R9A07G043_ADC_ADRST_N)
+
+/* RZ/G2UL Specific */
+#define R9A07G043_CA55_RST_1_0 (R9A07G043_LAST_COMMON_RST + 1)
+#define R9A07G043_CA55_RST_1_1 (R9A07G043_LAST_COMMON_RST + 2)
+#define R9A07G043_CA55_RST_3_0 (R9A07G043_LAST_COMMON_RST + 3)
+#define R9A07G043_CA55_RST_3_1 (R9A07G043_LAST_COMMON_RST + 4)
+#define R9A07G043_CA55_RST_4 (R9A07G043_LAST_COMMON_RST + 5)
+#define R9A07G043_CA55_RST_5 (R9A07G043_LAST_COMMON_RST + 6)
+#define R9A07G043_CA55_RST_6 (R9A07G043_LAST_COMMON_RST + 7)
+#define R9A07G043_CA55_RST_7 (R9A07G043_LAST_COMMON_RST + 8)
+#define R9A07G043_CA55_RST_8 (R9A07G043_LAST_COMMON_RST + 9)
+#define R9A07G043_CA55_RST_9 (R9A07G043_LAST_COMMON_RST + 10)
+#define R9A07G043_CA55_RST_10 (R9A07G043_LAST_COMMON_RST + 11)
+#define R9A07G043_CA55_RST_11 (R9A07G043_LAST_COMMON_RST + 12)
+#define R9A07G043_CA55_RST_12 (R9A07G043_LAST_COMMON_RST + 13)
+#define R9A07G043_GIC600_GICRESET_N (R9A07G043_LAST_COMMON_RST + 14)
+#define R9A07G043_GIC600_DBG_GICRESET_N (R9A07G043_LAST_COMMON_RST + 15)
+#define R9A07G043_MHU_RESETN (R9A07G043_LAST_COMMON_RST + 16)
+#define R9A07G043_SYC_RESETN (R9A07G043_LAST_COMMON_RST + 17)
+#define R9A07G043_WDT2_PRESETN (R9A07G043_LAST_COMMON_RST + 18)
+#define R9A07G043_ISU_ARESETN (R9A07G043_LAST_COMMON_RST + 19)
+#define R9A07G043_ISU_PRESETN (R9A07G043_LAST_COMMON_RST + 20)
+#define R9A07G043_CRU_CMN_RSTB (R9A07G043_LAST_COMMON_RST + 21)
+#define R9A07G043_CRU_PRESETN (R9A07G043_LAST_COMMON_RST + 22)
+#define R9A07G043_CRU_ARESETN (R9A07G043_LAST_COMMON_RST + 23)
+#define R9A07G043_LCDC_RESET_N (R9A07G043_LAST_COMMON_RST + 24)
+
+#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3 5/7] clk: renesas: Add support for RZ/G2UL SoC
2022-03-15 14:26 [PATCH v3 0/7] Add Renesas RZ/G2UL Type-1 {SoC,SMARC EVK} support Biju Das
` (2 preceding siblings ...)
2022-03-15 14:26 ` [PATCH v3 3/7] dt-bindings: clock: Add R9A07G043 CPG Clock and Reset Definitions Biju Das
@ 2022-03-15 14:26 ` Biju Das
2022-03-31 9:56 ` Geert Uytterhoeven
2022-03-15 14:26 ` [PATCH v3 6/7] arm64: dts: renesas: Add initial DTSI " Biju Das
2022-03-15 14:26 ` [PATCH v3 7/7] arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC EVK Biju Das
5 siblings, 1 reply; 22+ messages in thread
From: Biju Das @ 2022-03-15 14:26 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
The clock structure for RZ/G2UL is almost identical to RZ/G2L SoC with
fewer IP blocks. The IP blocks such as WDT1, GPT, H264, GPU and POEG are
not present on RZ/G2UL.
This patch adds minimal clock and reset entries required to boot the
system on Renesas RZ/G2UL SMARC EVK and binds it with the RZ/G2L CPG core
driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2->v3:
* Replaced R9A07G043U->R9A07G043 and r9a07g043u->r9a07g043
v1->v2:
* No change
---
drivers/clk/renesas/Kconfig | 7 +-
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r9a07g043-cpg.c | 157 ++++++++++++++++++++++++++++
drivers/clk/renesas/rzg2l-cpg.c | 6 ++
drivers/clk/renesas/rzg2l-cpg.h | 1 +
5 files changed, 171 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/renesas/r9a07g043-cpg.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index c281f3af5716..a95ed8f310da 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -33,6 +33,7 @@ config CLK_RENESAS
select CLK_R8A779A0 if ARCH_R8A779A0
select CLK_R8A779F0 if ARCH_R8A779F0
select CLK_R9A06G032 if ARCH_R9A06G032
+ select CLK_R9A07G043 if ARCH_R9A07G043
select CLK_R9A07G044 if ARCH_R9A07G044
select CLK_R9A07G054 if ARCH_R9A07G054
select CLK_SH73A0 if ARCH_SH73A0
@@ -160,6 +161,10 @@ config CLK_R8A779F0
config CLK_R9A06G032
bool "RZ/N1D clock support" if COMPILE_TEST
+config CLK_R9A07G043
+ bool "RZ/G2UL clock support" if COMPILE_TEST
+ select CLK_RZG2L
+
config CLK_R9A07G044
bool "RZ/G2L clock support" if COMPILE_TEST
select CLK_RZG2L
@@ -200,7 +205,7 @@ config CLK_RCAR_USB2_CLOCK_SEL
This is a driver for R-Car USB2 clock selector
config CLK_RZG2L
- bool "Renesas RZ/{G2L,V2L} family clock support" if COMPILE_TEST
+ bool "Renesas RZ/{G2L,G2UL,V2L} family clock support" if COMPILE_TEST
select RESET_CONTROLLER
# Generic
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index d5e571699a30..ca3a9bbcf27a 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
+obj-$(CONFIG_CLK_R9A07G043) += r9a07g043-cpg.o
obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
new file mode 100644
index 000000000000..ac8e3f182a66
--- /dev/null
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/G2UL CPG driver
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include <dt-bindings/clock/r9a07g043-cpg.h>
+
+#include "rzg2l-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R9A07G043_CLK_P0_DIV2,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+
+ /* Internal Core Clocks */
+ CLK_OSC_DIV1000,
+ CLK_PLL1,
+ CLK_PLL2,
+ CLK_PLL2_DIV2,
+ CLK_PLL2_DIV2_8,
+ CLK_PLL3,
+ CLK_PLL3_DIV2,
+ CLK_PLL3_DIV2_4,
+ CLK_PLL3_DIV2_4_2,
+ CLK_PLL5,
+ CLK_PLL6,
+ CLK_P1_DIV2,
+
+ /* Module Clocks */
+ MOD_CLK_BASE,
+};
+
+/* Divider tables */
+static const struct clk_div_table dtable_1_8[] = {
+ {0, 1},
+ {1, 2},
+ {2, 4},
+ {3, 8},
+ {0, 0},
+};
+
+static const struct clk_div_table dtable_1_32[] = {
+ {0, 1},
+ {1, 2},
+ {2, 4},
+ {3, 8},
+ {4, 32},
+ {0, 0},
+};
+
+static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+
+ /* Internal Core Clocks */
+ DEF_FIXED(".osc", R9A07G043_OSCCLK, CLK_EXTAL, 1, 1),
+ DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
+ DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
+ DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
+ DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
+ DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),
+ DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
+ DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
+ DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
+ DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
+ DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
+ DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
+
+ /* Core output clk */
+ DEF_DIV("I", R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
+ CLK_DIVIDER_HIWORD_MASK),
+ DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A,
+ dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+ DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4,
+ DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+ DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2),
+ DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2,
+ DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+};
+
+static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
+ DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1,
+ 0x514, 0),
+ DEF_MOD("ia55_pclk", R9A07G043_IA55_PCLK, R9A07G043_CLK_P2,
+ 0x518, 0),
+ DEF_MOD("ia55_clk", R9A07G043_IA55_CLK, R9A07G043_CLK_P1,
+ 0x518, 1),
+ DEF_MOD("dmac_aclk", R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1,
+ 0x52c, 0),
+ DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2,
+ 0x52c, 1),
+ DEF_MOD("scif0", R9A07G043_SCIF0_CLK_PCK, R9A07G043_CLK_P0,
+ 0x584, 0),
+ DEF_MOD("scif1", R9A07G043_SCIF1_CLK_PCK, R9A07G043_CLK_P0,
+ 0x584, 1),
+ DEF_MOD("scif2", R9A07G043_SCIF2_CLK_PCK, R9A07G043_CLK_P0,
+ 0x584, 2),
+ DEF_MOD("scif3", R9A07G043_SCIF3_CLK_PCK, R9A07G043_CLK_P0,
+ 0x584, 3),
+ DEF_MOD("scif4", R9A07G043_SCIF4_CLK_PCK, R9A07G043_CLK_P0,
+ 0x584, 4),
+ DEF_MOD("sci0", R9A07G043_SCI0_CLKP, R9A07G043_CLK_P0,
+ 0x588, 0),
+ DEF_MOD("sci1", R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0,
+ 0x588, 1),
+};
+
+static struct rzg2l_reset r9a07g043_resets[] = {
+ DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0),
+ DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1),
+ DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0),
+ DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0),
+ DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1),
+ DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0),
+ DEF_RST(R9A07G043_SCIF1_RST_SYSTEM_N, 0x884, 1),
+ DEF_RST(R9A07G043_SCIF2_RST_SYSTEM_N, 0x884, 2),
+ DEF_RST(R9A07G043_SCIF3_RST_SYSTEM_N, 0x884, 3),
+ DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4),
+ DEF_RST(R9A07G043_SCI0_RST, 0x888, 0),
+ DEF_RST(R9A07G043_SCI1_RST, 0x888, 1),
+};
+
+static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
+ MOD_CLK_BASE + R9A07G043_GIC600_GICCLK,
+ MOD_CLK_BASE + R9A07G043_IA55_CLK,
+ MOD_CLK_BASE + R9A07G043_DMAC_ACLK,
+};
+
+const struct rzg2l_cpg_info r9a07g043_cpg_info = {
+ /* Core Clocks */
+ .core_clks = r9a07g043_core_clks,
+ .num_core_clks = ARRAY_SIZE(r9a07g043_core_clks),
+ .last_dt_core_clk = LAST_DT_CORE_CLK,
+ .num_total_core_clks = MOD_CLK_BASE,
+
+ /* Critical Module Clocks */
+ .crit_mod_clks = r9a07g043_crit_mod_clks,
+ .num_crit_mod_clks = ARRAY_SIZE(r9a07g043_crit_mod_clks),
+
+ /* Module Clocks */
+ .mod_clks = r9a07g043_mod_clks,
+ .num_mod_clks = ARRAY_SIZE(r9a07g043_mod_clks),
+ .num_hw_mod_clks = R9A07G043_LCDC_CLK_D + 1,
+
+ /* Resets */
+ .resets = r9a07g043_resets,
+ .num_resets = R9A07G043_LCDC_RESET_N + 1, /* Last reset ID + 1 */
+};
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 486d0656c58a..8c0a6252c984 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -947,6 +947,12 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
}
static const struct of_device_id rzg2l_cpg_match[] = {
+#ifdef CONFIG_CLK_R9A07G043
+ {
+ .compatible = "renesas,r9a07g043-cpg",
+ .data = &r9a07g043_cpg_info,
+ },
+#endif
#ifdef CONFIG_CLK_R9A07G044
{
.compatible = "renesas,r9a07g044-cpg",
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index ce657beaf160..92c88f42ca7f 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -202,6 +202,7 @@ struct rzg2l_cpg_info {
unsigned int num_crit_mod_clks;
};
+extern const struct rzg2l_cpg_info r9a07g043_cpg_info;
extern const struct rzg2l_cpg_info r9a07g044_cpg_info;
extern const struct rzg2l_cpg_info r9a07g054_cpg_info;
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3 6/7] arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC
2022-03-15 14:26 [PATCH v3 0/7] Add Renesas RZ/G2UL Type-1 {SoC,SMARC EVK} support Biju Das
` (3 preceding siblings ...)
2022-03-15 14:26 ` [PATCH v3 5/7] clk: renesas: Add support for RZ/G2UL SoC Biju Das
@ 2022-03-15 14:26 ` Biju Das
2022-03-31 9:59 ` Geert Uytterhoeven
2022-03-15 14:26 ` [PATCH v3 7/7] arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC EVK Biju Das
5 siblings, 1 reply; 22+ messages in thread
From: Biju Das @ 2022-03-15 14:26 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add initial DTSI for RZ/G2UL SoC.
Both RZ/G2L and RZ/G2UL uses the same SMARC EVK. Therefore they share
the common dtsi (rz-smarc.dtsi) file. Place holders are added in
device nodes to avoid compilation errors for the devices which have
not been enabled yet on RZ/G2UL SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2->v3:
* Replaced clocks from R9A07G043U->R9A07G043
* Replaced compatible from r9a07g043u->r9a07g043
v1->v2:
* Changed soc compatible from r9a07g043u->r9a07g043.
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 413 +++++++++++++++++++++
1 file changed, 413 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043.dtsi
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
new file mode 100644
index 000000000000..ad898cab64a6
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -0,0 +1,413 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2UL SoC
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r9a07g043-cpg.h>
+
+/ {
+ compatible = "renesas,r9a07g043";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ audio_clk1: audio_clk1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by boards that provide it */
+ clock-frequency = <0>;
+ };
+
+ audio_clk2: audio_clk2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by boards that provide it */
+ clock-frequency = <0>;
+ };
+
+ /* External CAN clock - to be overridden by boards that provide it */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a55";
+ reg = <0>;
+ device_type = "cpu";
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
+ };
+
+ L3_CA55: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-size = <0x40000>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ssi0: ssi@10049c00 {
+ reg = <0 0x10049c00 0 0x400>;
+ #sound-dai-cells = <0>;
+ /* place holder */
+ };
+
+ spi1: spi@1004b000 {
+ reg = <0 0x1004b000 0 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* place holder */
+ };
+
+ scif0: serial@1004b800 {
+ compatible = "renesas,scif-r9a07g043",
+ "renesas,scif-r9a07g044";
+ reg = <0 0x1004b800 0 0x400>;
+ interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif1: serial@1004bc00 {
+ compatible = "renesas,scif-r9a07g043",
+ "renesas,scif-r9a07g044";
+ reg = <0 0x1004bc00 0 0x400>;
+ interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif2: serial@1004c000 {
+ compatible = "renesas,scif-r9a07g043",
+ "renesas,scif-r9a07g044";
+ reg = <0 0x1004c000 0 0x400>;
+ interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif3: serial@1004c400 {
+ compatible = "renesas,scif-r9a07g043",
+ "renesas,scif-r9a07g044";
+ reg = <0 0x1004c400 0 0x400>;
+ interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif4: serial@1004c800 {
+ compatible = "renesas,scif-r9a07g043",
+ "renesas,scif-r9a07g044";
+ reg = <0 0x1004c800 0 0x400>;
+ interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ sci0: serial@1004d000 {
+ compatible = "renesas,r9a07g043-sci", "renesas,sci";
+ reg = <0 0x1004d000 0 0x400>;
+ interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_SCI0_RST>;
+ status = "disabled";
+ };
+
+ sci1: serial@1004d400 {
+ compatible = "renesas,r9a07g043-sci", "renesas,sci";
+ reg = <0 0x1004d400 0 0x400>;
+ interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_SCI1_RST>;
+ status = "disabled";
+ };
+
+ canfd: can@10050000 {
+ reg = <0 0x10050000 0 0x8000>;
+ /* place holder */
+ };
+
+ i2c0: i2c@10058000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x10058000 0 0x400>;
+ /* place holder */
+ };
+
+ i2c1: i2c@10058400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x10058400 0 0x400>;
+ /* place holder */
+ };
+
+ i2c3: i2c@10058c00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x10058c00 0 0x400>;
+ /* place holder */
+ };
+
+ adc: adc@10059000 {
+ reg = <0 0x10059000 0 0x400>;
+ /* place holder */
+ };
+
+ sbc: spi@10060000 {
+ reg = <0 0x10060000 0 0x10000>,
+ <0 0x20000000 0 0x10000000>,
+ <0 0x10070000 0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* place holder */
+ };
+
+ cpg: clock-controller@11010000 {
+ compatible = "renesas,r9a07g043-cpg";
+ reg = <0 0x11010000 0 0x10000>;
+ clocks = <&extal_clk>;
+ clock-names = "extal";
+ #clock-cells = <2>;
+ #reset-cells = <1>;
+ #power-domain-cells = <0>;
+ };
+
+ sysc: system-controller@11020000 {
+ compatible = "renesas,r9a07g043-sysc";
+ reg = <0 0x11020000 0 0x10000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "lpm_int", "ca55stbydone_int",
+ "cm33stbyr_int", "ca55_deny";
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl@11030000 {
+ reg = <0 0x11030000 0 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* place holder */
+ };
+
+ dmac: dma-controller@11820000 {
+ compatible = "renesas,r9a07g043-dmac",
+ "renesas,rz-dmac";
+ reg = <0 0x11820000 0 0x10000>,
+ <0 0x11830000 0 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>,
+ <&cpg CPG_MOD R9A07G043_DMAC_PCLK>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_DMAC_ARESETN>,
+ <&cpg R9A07G043_DMAC_RST_ASYNC>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
+ gic: interrupt-controller@11900000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0x11900000 0 0x40000>,
+ <0x0 0x11940000 0 0x60000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ sdhi0: mmc@11c00000 {
+ reg = <0x0 0x11c00000 0 0x10000>;
+ /* place holder */
+ };
+
+ sdhi1: mmc@11c10000 {
+ reg = <0x0 0x11c10000 0 0x10000>;
+ /* place holder */
+ };
+
+ phyrst: usbphy-ctrl@11c40000 {
+ reg = <0 0x11c40000 0 0x10000>;
+ /* place holder */
+ };
+
+ ohci0: usb@11c50000 {
+ reg = <0 0x11c50000 0 0x100>;
+ /* place holder */
+ };
+
+ ohci1: usb@11c70000 {
+ reg = <0 0x11c70000 0 0x100>;
+ /* place holder */
+ };
+
+ ehci0: usb@11c50100 {
+ reg = <0 0x11c50100 0 0x100>;
+ /* place holder */
+ };
+
+ ehci1: usb@11c70100 {
+ reg = <0 0x11c70100 0 0x100>;
+ /* place holder */
+ };
+
+ usb2_phy0: usb-phy@11c50200 {
+ reg = <0 0x11c50200 0 0x700>;
+ /* place holder */
+ };
+
+ usb2_phy1: usb-phy@11c70200 {
+ reg = <0 0x11c70200 0 0x700>;
+ /* place holder */
+ };
+
+ hsusb: usb@11c60000 {
+ reg = <0 0x11c60000 0 0x10000>;
+ /* place holder */
+ };
+
+ wdt0: watchdog@12800800 {
+ reg = <0 0x12800800 0 0x400>;
+ /* place holder */
+ };
+
+ wdt2: watchdog@12800400 {
+ reg = <0 0x12800400 0 0x400>;
+ /* place holder */
+ };
+
+ ostm0: timer@12801000 {
+ reg = <0x0 0x12801000 0x0 0x400>;
+ /* place holder */
+ };
+
+ ostm1: timer@12801400 {
+ reg = <0x0 0x12801400 0x0 0x400>;
+ /* place holder */
+ };
+
+ ostm2: timer@12801800 {
+ reg = <0x0 0x12801800 0x0 0x400>;
+ /* place holder */
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3 7/7] arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC EVK
2022-03-15 14:26 [PATCH v3 0/7] Add Renesas RZ/G2UL Type-1 {SoC,SMARC EVK} support Biju Das
` (4 preceding siblings ...)
2022-03-15 14:26 ` [PATCH v3 6/7] arm64: dts: renesas: Add initial DTSI " Biju Das
@ 2022-03-15 14:26 ` Biju Das
2022-03-31 10:08 ` Geert Uytterhoeven
2022-03-31 14:26 ` Geert Uytterhoeven
5 siblings, 2 replies; 22+ messages in thread
From: Biju Das @ 2022-03-15 14:26 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add basic support for RZ/G2UL SMARC EVK (based on R9A07G043U11):
- memory
- External input clock
- CPG
- DMA
- SCIF
It shares the same carrier board with RZ/G2L, but the pin mapping is
different. Disable the device nodes which are not tested and delete the
corresponding pinctrl definitions.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2->v3:
* Replaced CONFIG_ARCH_R9A07G043U->CONFIG_ARCH_R9A07G043
* Renamed SoC file r9a07g043u.dtsi->r9a07g043.dtsi
v1->v2:
* Changed soc compatible from r9a07g043u->r9a07g043.
---
arch/arm64/boot/dts/renesas/Makefile | 2 +
.../boot/dts/renesas/r9a07g043u11-smarc.dts | 111 ++++++++++++++++++
.../boot/dts/renesas/rzg2ul-smarc-som.dtsi | 25 ++++
3 files changed, 138 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
create mode 100644 arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index d000f6b131dc..fa9811251fd7 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -75,6 +75,8 @@ dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb
+dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc.dtb
+
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
new file mode 100644
index 000000000000..aaa29f83e84c
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2UL Type-1 SMARC EVK board
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g043.dtsi"
+#include "rzg2ul-smarc-som.dtsi"
+#include "rz-smarc-common.dtsi"
+
+/ {
+ model = "Renesas SMARC EVK based on r9a07g043u11";
+ compatible = "renesas,smarc-evk", "renesas,r9a07g043u11", "renesas,r9a07g043";
+};
+
+&canfd {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&ehci0 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&ehci1 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&hsusb {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&i2c0 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&i2c1 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+
+ wm8978: codec@1a {
+ compatible = "wlf,wm8978";
+ #sound-dai-cells = <0>;
+ reg = <0x1a>;
+ };
+};
+
+&ohci0 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&ohci1 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&phyrst {
+ status = "disabled";
+};
+
+&scif0 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+};
+
+&sdhi1 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-1;
+ /delete-property/ pinctrl-names;
+ /delete-property/ vmmc-supply;
+ status = "disabled";
+};
+
+&spi1 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&ssi0 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&usb2_phy0 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&usb2_phy1 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
new file mode 100644
index 000000000000..3bbb8fcd604c
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2UL SMARC SOM common parts
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/ {
+ chosen {
+ bootargs = "ignore_loglevel";
+ };
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x38000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <24000000>;
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v3 3/7] dt-bindings: clock: Add R9A07G043 CPG Clock and Reset Definitions
2022-03-15 14:26 ` [PATCH v3 3/7] dt-bindings: clock: Add R9A07G043 CPG Clock and Reset Definitions Biju Das
@ 2022-03-23 18:41 ` Rob Herring
2022-03-30 19:27 ` Geert Uytterhoeven
1 sibling, 0 replies; 22+ messages in thread
From: Rob Herring @ 2022-03-23 18:41 UTC (permalink / raw)
To: Biju Das
Cc: Biju Das, Geert Uytterhoeven, Rob Herring, Prabhakar Mahadev Lad,
devicetree, Chris Paterson, linux-renesas-soc
On Tue, 15 Mar 2022 14:26:40 +0000, Biju Das wrote:
> Define RZ/G2UL (R9A07G043U) Clock Pulse Generator Core Clock and module
> clock outputs, as listed in Table 7.1.4.2 ("Clock List r0.51") and also
> add Reset definitions referring to registers CPG_RST_* in Section 7.2.3
> ("Register configuration") of the RZ/G2UL Hardware User's Manual (Rev.
> 0.51, Nov. 2021).
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3:
> * Removed leading u/U from r9a07g043
> * renamed the file r9a07g043u-cpg.h->r9a07g043-cpg.h
> * Prepared Common Module Clock/Reset indices for RZ/G2UL and RZ/Five
> * Prepared RZ/G2UL specific Module Clock/Reset indices.
> v1->v2:
> * No change
> ---
> include/dt-bindings/clock/r9a07g043-cpg.h | 190 ++++++++++++++++++++++
> 1 file changed, 190 insertions(+)
> create mode 100644 include/dt-bindings/clock/r9a07g043-cpg.h
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 1/7] dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoC
2022-03-15 14:26 ` [PATCH v3 1/7] dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoC Biju Das
@ 2022-03-30 13:09 ` Geert Uytterhoeven
2022-03-30 13:45 ` Biju Das
0 siblings, 1 reply; 22+ messages in thread
From: Geert Uytterhoeven @ 2022-03-30 13:09 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Geert Uytterhoeven, Lad Prabhakar,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Linux-Renesas
Hi Biju,
On Tue, Mar 15, 2022 at 3:26 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add DT binding documentation for SYSC controller found on RZ/G2UL SoC's.
> SYSC controller found on the RZ/G2UL SoC is almost identical to one found
> on the RZ/G2L SoC's only difference being that the RZ/G2UL has only CA55
> core0 reset vector address configuration register.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
> v2->v3:
> * Changed the compatible from r9a07g043u-sysc->r9a07g043-sysc
> * Retained Rb tag from Rob as it is trivial change.
Thanks for the update!
> --- a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
> +++ b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
> @@ -20,8 +20,9 @@ description:
> properties:
> compatible:
> enum:
> - - renesas,r9a07g044-sysc # RZ/G2{L,LC}
> - - renesas,r9a07g054-sysc # RZ/V2L
> + - renesas,r9a07g043-sysc # RZ/G2UL
> + - renesas,r9a07g044-sysc # RZ/G2{L,LC}
> + - renesas,r9a07g054-sysc # RZ/V2L
No need to add one more space before the #.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.19, with the above fixed.
No need to resend.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 2/7] soc: renesas: Identify RZ/G2UL SoC
2022-03-15 14:26 ` [PATCH v3 2/7] soc: renesas: Identify " Biju Das
@ 2022-03-30 13:17 ` Geert Uytterhoeven
0 siblings, 0 replies; 22+ messages in thread
From: Geert Uytterhoeven @ 2022-03-30 13:17 UTC (permalink / raw)
To: Biju Das
Cc: Magnus Damm, Linux-Renesas, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
On Tue, Mar 15, 2022 at 3:26 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add support for identifying the RZ/G2UL SoC.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3:
> * Changed compatible from r9a07g043u11->r9a07g043.
> * Changed the config from ARCH_R9A07G043U->ARCH_R9A07G043
> * Changed sysc compatible from r9a07g043u-sysc->r9a07g043-sysc
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.19.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH v3 1/7] dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoC
2022-03-30 13:09 ` Geert Uytterhoeven
@ 2022-03-30 13:45 ` Biju Das
0 siblings, 0 replies; 22+ messages in thread
From: Biju Das @ 2022-03-30 13:45 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Rob Herring, Geert Uytterhoeven, Prabhakar Mahadev Lad,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Linux-Renesas
Hi Geert,
> Subject: Re: [PATCH v3 1/7] dt-bindings: power: renesas,rzg2l-sysc:
> Document RZ/G2UL SoC
>
> Hi Biju,
>
> On Tue, Mar 15, 2022 at 3:26 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > Add DT binding documentation for SYSC controller found on RZ/G2UL SoC's.
> > SYSC controller found on the RZ/G2UL SoC is almost identical to one
> > found on the RZ/G2L SoC's only difference being that the RZ/G2UL has
> > only CA55
> > core0 reset vector address configuration register.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > ---
> > v2->v3:
> > * Changed the compatible from r9a07g043u-sysc->r9a07g043-sysc
> > * Retained Rb tag from Rob as it is trivial change.
>
> Thanks for the update!
>
> > --- a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
> > +++ b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
>
> > @@ -20,8 +20,9 @@ description:
> > properties:
> > compatible:
> > enum:
> > - - renesas,r9a07g044-sysc # RZ/G2{L,LC}
> > - - renesas,r9a07g054-sysc # RZ/V2L
> > + - renesas,r9a07g043-sysc # RZ/G2UL
> > + - renesas,r9a07g044-sysc # RZ/G2{L,LC}
> > + - renesas,r9a07g054-sysc # RZ/V2L
>
> No need to add one more space before the #.
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue
> in renesas-devel for v5.19, with the above fixed.
> No need to resend.
Thank you
Biju
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 3/7] dt-bindings: clock: Add R9A07G043 CPG Clock and Reset Definitions
2022-03-15 14:26 ` [PATCH v3 3/7] dt-bindings: clock: Add R9A07G043 CPG Clock and Reset Definitions Biju Das
2022-03-23 18:41 ` Rob Herring
@ 2022-03-30 19:27 ` Geert Uytterhoeven
2022-03-30 19:45 ` Geert Uytterhoeven
2022-03-31 7:38 ` Biju Das
1 sibling, 2 replies; 22+ messages in thread
From: Geert Uytterhoeven @ 2022-03-30 19:27 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad, Linux-Renesas
Hi Biju,
On Tue, Mar 15, 2022 at 3:26 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Define RZ/G2UL (R9A07G043U) Clock Pulse Generator Core Clock and module
> clock outputs, as listed in Table 7.1.4.2 ("Clock List r0.51") and also
> add Reset definitions referring to registers CPG_RST_* in Section 7.2.3
> ("Register configuration") of the RZ/G2UL Hardware User's Manual (Rev.
> 0.51, Nov. 2021).
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3:
> * Removed leading u/U from r9a07g043
> * renamed the file r9a07g043u-cpg.h->r9a07g043-cpg.h
> * Prepared Common Module Clock/Reset indices for RZ/G2UL and RZ/Five
> * Prepared RZ/G2UL specific Module Clock/Reset indices.
Thanks for the update!
> --- /dev/null
> +++ b/include/dt-bindings/clock/r9a07g043-cpg.h
> @@ -0,0 +1,190 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +#ifndef __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__
> +#define __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* R9A07G043 CPG Core Clocks */
> +#define R9A07G043_CLK_I 0
> +#define R9A07G043_CLK_I2 1
> +#define R9A07G043_CLK_S0 2
> +#define R9A07G043_CLK_SPI0 3
> +#define R9A07G043_CLK_SPI1 4
> +#define R9A07G043_CLK_SD0 5
> +#define R9A07G043_CLK_SD1 6
> +#define R9A07G043_CLK_M0 7
> +#define R9A07G043_CLK_M2 8
> +#define R9A07G043_CLK_M3 9
> +#define R9A07G043_CLK_HP 10
> +#define R9A07G043_CLK_TSU 11
> +#define R9A07G043_CLK_ZT 12
> +#define R9A07G043_CLK_P0 13
> +#define R9A07G043_CLK_P1 14
> +#define R9A07G043_CLK_P2 15
> +#define R9A07G043_CLK_AT 16
> +#define R9A07G043_OSCCLK 17
> +#define R9A07G043_CLK_P0_DIV2 18
> +
> +/* R9A07G043 Common Module Clocks */
> +#define R9A07G043_IA55_CLK 0
> +#define R9A07G043_IA55_PCLK 1
I think IA55 does not exist on RZ/Five?
> +#define R9A07G043_DMAC_ACLK 2
> +#define R9A07G043_DMAC_PCLK 3
> +#define R9A07G043_OSTM0_PCLK 4
> +#define R9A07G043_OSTM1_PCLK 5
> +#define R9A07G043_OSTM2_PCLK 6
> +#define R9A07G043_MTU_X_MCK_MTU3 7
> +#define R9A07G043_POE3_CLKM_POE 8
> +#define R9A07G043_WDT0_PCLK 9
> +#define R9A07G043_WDT0_CLK 10
> +#define R9A07G043_SPI_CLK2 11
> +#define R9A07G043_SPI_CLK 12
> +#define R9A07G043_SDHI0_IMCLK 13
> +#define R9A07G043_SDHI0_IMCLK2 14
> +#define R9A07G043_SDHI0_CLK_HS 15
> +#define R9A07G043_SDHI0_ACLK 16
> +#define R9A07G043_SDHI1_IMCLK 17
> +#define R9A07G043_SDHI1_IMCLK2 18
> +#define R9A07G043_SDHI1_CLK_HS 19
> +#define R9A07G043_SDHI1_ACLK 20
> +#define R9A07G043_SSI0_PCLK2 21
> +#define R9A07G043_SSI0_PCLK_SFR 22
> +#define R9A07G043_SSI1_PCLK2 23
> +#define R9A07G043_SSI1_PCLK_SFR 24
> +#define R9A07G043_SSI2_PCLK2 25
> +#define R9A07G043_SSI2_PCLK_SFR 26
> +#define R9A07G043_SSI3_PCLK2 27
> +#define R9A07G043_SSI3_PCLK_SFR 28
> +#define R9A07G043_SRC_CLKP 29
> +#define R9A07G043_USB_U2H0_HCLK 30
> +#define R9A07G043_USB_U2H1_HCLK 31
> +#define R9A07G043_USB_U2P_EXR_CPUCLK 32
> +#define R9A07G043_USB_PCLK 33
> +#define R9A07G043_ETH0_CLK_AXI 34
> +#define R9A07G043_ETH0_CLK_CHI 35
> +#define R9A07G043_ETH1_CLK_AXI 36
> +#define R9A07G043_ETH1_CLK_CHI 37
> +#define R9A07G043_I2C0_PCLK 38
> +#define R9A07G043_I2C1_PCLK 39
> +#define R9A07G043_I2C2_PCLK 40
> +#define R9A07G043_I2C3_PCLK 41
> +#define R9A07G043_SCIF0_CLK_PCK 42
> +#define R9A07G043_SCIF1_CLK_PCK 43
> +#define R9A07G043_SCIF2_CLK_PCK 44
> +#define R9A07G043_SCIF3_CLK_PCK 45
> +#define R9A07G043_SCIF4_CLK_PCK 46
> +#define R9A07G043_SCI0_CLKP 47
> +#define R9A07G043_SCI1_CLKP 48
> +#define R9A07G043_IRDA_CLKP 49
> +#define R9A07G043_RSPI0_CLKB 50
> +#define R9A07G043_RSPI1_CLKB 51
> +#define R9A07G043_RSPI2_CLKB 52
> +#define R9A07G043_CANFD_PCLK 53
> +#define R9A07G043_GPIO_HCLK 54
> +#define R9A07G043_ADC_ADCLK 55
> +#define R9A07G043_ADC_PCLK 56
> +#define R9A07G043_TSU_PCLK 57
> +#define R9A07G043_LAST_COMMON_CLK (R9A07G043_TSU_PCLK)
Does R9A07G043_LAST_COMMON_CLK need to be part of the bindings?
Do you actually have a use case for this definition, besides the use
below? If not, I would get rid of the definition, and just hardcode
the numeric values below.
Perhaps you planned to start enumerating RZ/Five-specific clocks from
R9A07G043_LAST_COMMON_CLK + 1, too? I don't think that's a good idea,
as it would complicate validation of indices in the driver.
> +
> +/* RZ/G2UL Specific */
> +#define R9A07G043_CA55_SCLK (R9A07G043_LAST_COMMON_CLK + 1)
> +#define R9A07G043_CA55_PCLK (R9A07G043_LAST_COMMON_CLK + 2)
> +#define R9A07G043_CA55_ATCLK (R9A07G043_LAST_COMMON_CLK + 3)
> +#define R9A07G043_CA55_GICCLK (R9A07G043_LAST_COMMON_CLK + 4)
> +#define R9A07G043_CA55_PERICLK (R9A07G043_LAST_COMMON_CLK + 5)
> +#define R9A07G043_CA55_ACLK (R9A07G043_LAST_COMMON_CLK + 6)
> +#define R9A07G043_CA55_TSCLK (R9A07G043_LAST_COMMON_CLK + 7)
> +#define R9A07G043_GIC600_GICCLK (R9A07G043_LAST_COMMON_CLK + 8)
> +#define R9A07G043_MHU_PCLK (R9A07G043_LAST_COMMON_CLK + 9)
> +#define R9A07G043_SYC_CNT_CLK (R9A07G043_LAST_COMMON_CLK + 10)
I think SYC_CNT does exist on RZ/Five?
So I'm not 100% convinced it's a good idea to split the definitions in
common, RZ/G2UL-specific, and RZ/Five-specific definitions like this.
If we make a mistake, the end result won't look pretty.
And we can't do compile-time validation that way anyway.
So I'm in favor of listing all clocks (in the same order as on RZ/G2L),
and adding a comment if a clock is RZ/G2UL-only.
> +#define R9A07G043_WDT2_PCLK (R9A07G043_LAST_COMMON_CLK + 11)
> +#define R9A07G043_WDT2_CLK (R9A07G043_LAST_COMMON_CLK + 12)
> +#define R9A07G043_ISU_ACLK (R9A07G043_LAST_COMMON_CLK + 13)
> +#define R9A07G043_ISU_PCLK (R9A07G043_LAST_COMMON_CLK + 14)
> +#define R9A07G043_CRU_SYSCLK (R9A07G043_LAST_COMMON_CLK + 15)
> +#define R9A07G043_CRU_VCLK (R9A07G043_LAST_COMMON_CLK + 16)
> +#define R9A07G043_CRU_PCLK (R9A07G043_LAST_COMMON_CLK + 17)
> +#define R9A07G043_CRU_ACLK (R9A07G043_LAST_COMMON_CLK + 18)
> +#define R9A07G043_LCDC_CLK_A (R9A07G043_LAST_COMMON_CLK + 19)
> +#define R9A07G043_LCDC_CLK_P (R9A07G043_LAST_COMMON_CLK + 20)
> +#define R9A07G043_LCDC_CLK_D (R9A07G043_LAST_COMMON_CLK + 21)
> +
> +/* R9A07G043 Common Resets */
> +#define R9A07G043_IA55_RESETN 0
All my comments above apply to resets, too.
> +#define R9A07G043_DMAC_ARESETN 1
> +#define R9A07G043_DMAC_RST_ASYNC 2
> +#define R9A07G043_OSTM0_PRESETZ 3
> +#define R9A07G043_OSTM1_PRESETZ 4
> +#define R9A07G043_OSTM2_PRESETZ 5
> +#define R9A07G043_MTU_X_PRESET_MTU3 6
> +#define R9A07G043_POE3_RST_M_REG 7
> +#define R9A07G043_WDT0_PRESETN 8
> +#define R9A07G043_SPI_RST 9
> +#define R9A07G043_SDHI0_IXRST 10
> +#define R9A07G043_SDHI1_IXRST 11
Move SSI resets here? (see below)
> +#define R9A07G043_SRC_RST 12
> +#define R9A07G043_USB_U2H0_HRESETN 13
> +#define R9A07G043_USB_U2H1_HRESETN 14
> +#define R9A07G043_USB_U2P_EXL_SYSRST 15
> +#define R9A07G043_USB_PRESETN 16
Move ETH resets here? (see below)
> +#define R9A07G043_I2C0_MRST 17
> +#define R9A07G043_I2C1_MRST 18
> +#define R9A07G043_I2C2_MRST 19
> +#define R9A07G043_I2C3_MRST 20
Move SCIF resets here? (see below)
> +#define R9A07G043_SCI0_RST 21
> +#define R9A07G043_SCI1_RST 22
> +#define R9A07G043_IRDA_RST 23
> +#define R9A07G043_RSPI0_RST 24
> +#define R9A07G043_RSPI1_RST 25
> +#define R9A07G043_RSPI2_RST 26
> +#define R9A07G043_CANFD_RSTP_N 27
> +#define R9A07G043_CANFD_RSTC_N 28
> +#define R9A07G043_GPIO_RSTN 29
> +#define R9A07G043_GPIO_PORT_RESETN 30
> +#define R9A07G043_GPIO_SPARE_RESETN 31
> +#define R9A07G043_TSU_PRESETN 32
> +#define R9A07G043_SSI0_RST_M2_REG 33
> +#define R9A07G043_SSI1_RST_M2_REG 34
> +#define R9A07G043_SSI2_RST_M2_REG 35
> +#define R9A07G043_SSI3_RST_M2_REG 36
> +#define R9A07G043_ETH0_RST_HW_N 37
> +#define R9A07G043_ETH1_RST_HW_N 38
> +#define R9A07G043_SCIF0_RST_SYSTEM_N 39
> +#define R9A07G043_SCIF1_RST_SYSTEM_N 40
> +#define R9A07G043_SCIF2_RST_SYSTEM_N 41
> +#define R9A07G043_SCIF3_RST_SYSTEM_N 42
> +#define R9A07G043_SCIF4_RST_SYSTEM_N 43
Is there any specific reason the SSI, ETH, and SCIF resets are
ordered differently than the corresponding clocks, and than the
resets on RZ/G2L?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 3/7] dt-bindings: clock: Add R9A07G043 CPG Clock and Reset Definitions
2022-03-30 19:27 ` Geert Uytterhoeven
@ 2022-03-30 19:45 ` Geert Uytterhoeven
2022-04-01 15:12 ` Biju Das
2022-03-31 7:38 ` Biju Das
1 sibling, 1 reply; 22+ messages in thread
From: Geert Uytterhoeven @ 2022-03-30 19:45 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad, Linux-Renesas
On Wed, Mar 30, 2022 at 9:27 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Tue, Mar 15, 2022 at 3:26 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > Define RZ/G2UL (R9A07G043U) Clock Pulse Generator Core Clock and module
> > clock outputs, as listed in Table 7.1.4.2 ("Clock List r0.51") and also
> > add Reset definitions referring to registers CPG_RST_* in Section 7.2.3
> > ("Register configuration") of the RZ/G2UL Hardware User's Manual (Rev.
> > 0.51, Nov. 2021).
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v2->v3:
> > * Removed leading u/U from r9a07g043
> > * renamed the file r9a07g043u-cpg.h->r9a07g043-cpg.h
> > * Prepared Common Module Clock/Reset indices for RZ/G2UL and RZ/Five
> > * Prepared RZ/G2UL specific Module Clock/Reset indices.
>
> Thanks for the update!
>
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/r9a07g043-cpg.h
> > +/* R9A07G043 Common Module Clocks */
> > +#define R9A07G043_IA55_CLK 0
> > +#define R9A07G043_IA55_PCLK 1
>
> I think IA55 does not exist on RZ/Five?
Looks like I was wrong, and it does exist.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH v3 3/7] dt-bindings: clock: Add R9A07G043 CPG Clock and Reset Definitions
2022-03-30 19:27 ` Geert Uytterhoeven
2022-03-30 19:45 ` Geert Uytterhoeven
@ 2022-03-31 7:38 ` Biju Das
2022-03-31 7:46 ` Biju Das
1 sibling, 1 reply; 22+ messages in thread
From: Biju Das @ 2022-03-31 7:38 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad, Linux-Renesas
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH v3 3/7] dt-bindings: clock: Add R9A07G043 CPG Clock
> and Reset Definitions
>
> Hi Biju,
>
> On Tue, Mar 15, 2022 at 3:26 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > Define RZ/G2UL (R9A07G043U) Clock Pulse Generator Core Clock and
> > module clock outputs, as listed in Table 7.1.4.2 ("Clock List r0.51")
> > and also add Reset definitions referring to registers CPG_RST_* in
> > Section 7.2.3 ("Register configuration") of the RZ/G2UL Hardware User's
> Manual (Rev.
> > 0.51, Nov. 2021).
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v2->v3:
> > * Removed leading u/U from r9a07g043
> > * renamed the file r9a07g043u-cpg.h->r9a07g043-cpg.h
> > * Prepared Common Module Clock/Reset indices for RZ/G2UL and RZ/Five
> > * Prepared RZ/G2UL specific Module Clock/Reset indices.
>
> Thanks for the update!
>
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/r9a07g043-cpg.h
> > @@ -0,0 +1,190 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > + *
> > + * Copyright (C) 2022 Renesas Electronics Corp.
> > + */
> > +#ifndef __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__
> > +#define __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__
> > +
> > +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> > +
> > +/* R9A07G043 CPG Core Clocks */
> > +#define R9A07G043_CLK_I 0
> > +#define R9A07G043_CLK_I2 1
> > +#define R9A07G043_CLK_S0 2
> > +#define R9A07G043_CLK_SPI0 3
> > +#define R9A07G043_CLK_SPI1 4
> > +#define R9A07G043_CLK_SD0 5
> > +#define R9A07G043_CLK_SD1 6
> > +#define R9A07G043_CLK_M0 7
> > +#define R9A07G043_CLK_M2 8
> > +#define R9A07G043_CLK_M3 9
> > +#define R9A07G043_CLK_HP 10
> > +#define R9A07G043_CLK_TSU 11
> > +#define R9A07G043_CLK_ZT 12
> > +#define R9A07G043_CLK_P0 13
> > +#define R9A07G043_CLK_P1 14
> > +#define R9A07G043_CLK_P2 15
> > +#define R9A07G043_CLK_AT 16
> > +#define R9A07G043_OSCCLK 17
> > +#define R9A07G043_CLK_P0_DIV2 18
> > +
> > +/* R9A07G043 Common Module Clocks */
> > +#define R9A07G043_IA55_CLK 0
> > +#define R9A07G043_IA55_PCLK 1
>
> I think IA55 does not exist on RZ/Five?
>
> > +#define R9A07G043_DMAC_ACLK 2
> > +#define R9A07G043_DMAC_PCLK 3
> > +#define R9A07G043_OSTM0_PCLK 4
> > +#define R9A07G043_OSTM1_PCLK 5
> > +#define R9A07G043_OSTM2_PCLK 6
> > +#define R9A07G043_MTU_X_MCK_MTU3 7
> > +#define R9A07G043_POE3_CLKM_POE 8
> > +#define R9A07G043_WDT0_PCLK 9
> > +#define R9A07G043_WDT0_CLK 10
> > +#define R9A07G043_SPI_CLK2 11
> > +#define R9A07G043_SPI_CLK 12
> > +#define R9A07G043_SDHI0_IMCLK 13
> > +#define R9A07G043_SDHI0_IMCLK2 14
> > +#define R9A07G043_SDHI0_CLK_HS 15
> > +#define R9A07G043_SDHI0_ACLK 16
> > +#define R9A07G043_SDHI1_IMCLK 17
> > +#define R9A07G043_SDHI1_IMCLK2 18
> > +#define R9A07G043_SDHI1_CLK_HS 19
> > +#define R9A07G043_SDHI1_ACLK 20
> > +#define R9A07G043_SSI0_PCLK2 21
> > +#define R9A07G043_SSI0_PCLK_SFR 22
> > +#define R9A07G043_SSI1_PCLK2 23
> > +#define R9A07G043_SSI1_PCLK_SFR 24
> > +#define R9A07G043_SSI2_PCLK2 25
> > +#define R9A07G043_SSI2_PCLK_SFR 26
> > +#define R9A07G043_SSI3_PCLK2 27
> > +#define R9A07G043_SSI3_PCLK_SFR 28
> > +#define R9A07G043_SRC_CLKP 29
> > +#define R9A07G043_USB_U2H0_HCLK 30
> > +#define R9A07G043_USB_U2H1_HCLK 31
> > +#define R9A07G043_USB_U2P_EXR_CPUCLK 32
> > +#define R9A07G043_USB_PCLK 33
> > +#define R9A07G043_ETH0_CLK_AXI 34
> > +#define R9A07G043_ETH0_CLK_CHI 35
> > +#define R9A07G043_ETH1_CLK_AXI 36
> > +#define R9A07G043_ETH1_CLK_CHI 37
> > +#define R9A07G043_I2C0_PCLK 38
> > +#define R9A07G043_I2C1_PCLK 39
> > +#define R9A07G043_I2C2_PCLK 40
> > +#define R9A07G043_I2C3_PCLK 41
> > +#define R9A07G043_SCIF0_CLK_PCK 42
> > +#define R9A07G043_SCIF1_CLK_PCK 43
> > +#define R9A07G043_SCIF2_CLK_PCK 44
> > +#define R9A07G043_SCIF3_CLK_PCK 45
> > +#define R9A07G043_SCIF4_CLK_PCK 46
> > +#define R9A07G043_SCI0_CLKP 47
> > +#define R9A07G043_SCI1_CLKP 48
> > +#define R9A07G043_IRDA_CLKP 49
> > +#define R9A07G043_RSPI0_CLKB 50
> > +#define R9A07G043_RSPI1_CLKB 51
> > +#define R9A07G043_RSPI2_CLKB 52
> > +#define R9A07G043_CANFD_PCLK 53
> > +#define R9A07G043_GPIO_HCLK 54
> > +#define R9A07G043_ADC_ADCLK 55
> > +#define R9A07G043_ADC_PCLK 56
> > +#define R9A07G043_TSU_PCLK 57
> > +#define R9A07G043_LAST_COMMON_CLK (R9A07G043_TSU_PCLK)
>
> Does R9A07G043_LAST_COMMON_CLK need to be part of the bindings?
I thought we can reuse same header file for both RZ/Five and RZ/G2UL.
The same can be achieved as per your suggestion below.
> Do you actually have a use case for this definition, besides the use
> below? If not, I would get rid of the definition, and just hardcode the
> numeric values below.
>
> Perhaps you planned to start enumerating RZ/Five-specific clocks from
> R9A07G043_LAST_COMMON_CLK + 1, too? I don't think that's a good idea, as
> it would complicate validation of indices in the driver.
OK, Agreed.
>
> > +
> > +/* RZ/G2UL Specific */
> > +#define R9A07G043_CA55_SCLK (R9A07G043_LAST_COMMON_CLK + 1)
> > +#define R9A07G043_CA55_PCLK (R9A07G043_LAST_COMMON_CLK + 2)
> > +#define R9A07G043_CA55_ATCLK (R9A07G043_LAST_COMMON_CLK + 3)
> > +#define R9A07G043_CA55_GICCLK (R9A07G043_LAST_COMMON_CLK + 4)
> > +#define R9A07G043_CA55_PERICLK (R9A07G043_LAST_COMMON_CLK + 5)
> > +#define R9A07G043_CA55_ACLK (R9A07G043_LAST_COMMON_CLK + 6)
> > +#define R9A07G043_CA55_TSCLK (R9A07G043_LAST_COMMON_CLK + 7)
> > +#define R9A07G043_GIC600_GICCLK
> (R9A07G043_LAST_COMMON_CLK + 8)
> > +#define R9A07G043_MHU_PCLK (R9A07G043_LAST_COMMON_CLK + 9)
> > +#define R9A07G043_SYC_CNT_CLK (R9A07G043_LAST_COMMON_CLK + 10)
>
> I think SYC_CNT does exist on RZ/Five?
Basically SYC (System Counter) for RZ/G2UL
and MT (Machine Timer) for RZ/Five. See page 26 of RZ/Five HW manual
>
> So I'm not 100% convinced it's a good idea to split the definitions in
> common, RZ/G2UL-specific, and RZ/Five-specific definitions like this.
> If we make a mistake, the end result won't look pretty.
> And we can't do compile-time validation that way anyway.
>
> So I'm in favor of listing all clocks (in the same order as on RZ/G2L),
> and adding a comment if a clock is RZ/G2UL-only.
OK. Will do.
>
> > +#define R9A07G043_WDT2_PCLK (R9A07G043_LAST_COMMON_CLK + 11)
> > +#define R9A07G043_WDT2_CLK (R9A07G043_LAST_COMMON_CLK + 12)
> > +#define R9A07G043_ISU_ACLK (R9A07G043_LAST_COMMON_CLK + 13)
> > +#define R9A07G043_ISU_PCLK (R9A07G043_LAST_COMMON_CLK + 14)
> > +#define R9A07G043_CRU_SYSCLK (R9A07G043_LAST_COMMON_CLK + 15)
> > +#define R9A07G043_CRU_VCLK (R9A07G043_LAST_COMMON_CLK + 16)
> > +#define R9A07G043_CRU_PCLK (R9A07G043_LAST_COMMON_CLK + 17)
> > +#define R9A07G043_CRU_ACLK (R9A07G043_LAST_COMMON_CLK + 18)
> > +#define R9A07G043_LCDC_CLK_A (R9A07G043_LAST_COMMON_CLK + 19)
> > +#define R9A07G043_LCDC_CLK_P (R9A07G043_LAST_COMMON_CLK + 20)
> > +#define R9A07G043_LCDC_CLK_D (R9A07G043_LAST_COMMON_CLK + 21)
> > +
> > +/* R9A07G043 Common Resets */
> > +#define R9A07G043_IA55_RESETN 0
>
> All my comments above apply to resets, too.
OK.
>
> > +#define R9A07G043_DMAC_ARESETN 1
> > +#define R9A07G043_DMAC_RST_ASYNC 2
> > +#define R9A07G043_OSTM0_PRESETZ 3
> > +#define R9A07G043_OSTM1_PRESETZ 4
> > +#define R9A07G043_OSTM2_PRESETZ 5
> > +#define R9A07G043_MTU_X_PRESET_MTU3 6
> > +#define R9A07G043_POE3_RST_M_REG 7
> > +#define R9A07G043_WDT0_PRESETN 8
> > +#define R9A07G043_SPI_RST 9
> > +#define R9A07G043_SDHI0_IXRST 10
> > +#define R9A07G043_SDHI1_IXRST 11
>
> Move SSI resets here? (see below)
>
> > +#define R9A07G043_SRC_RST 12
> > +#define R9A07G043_USB_U2H0_HRESETN 13
> > +#define R9A07G043_USB_U2H1_HRESETN 14
> > +#define R9A07G043_USB_U2P_EXL_SYSRST 15
> > +#define R9A07G043_USB_PRESETN 16
>
> Move ETH resets here? (see below)
>
> > +#define R9A07G043_I2C0_MRST 17
> > +#define R9A07G043_I2C1_MRST 18
> > +#define R9A07G043_I2C2_MRST 19
> > +#define R9A07G043_I2C3_MRST 20
>
> Move SCIF resets here? (see below)
>
> > +#define R9A07G043_SCI0_RST 21
> > +#define R9A07G043_SCI1_RST 22
> > +#define R9A07G043_IRDA_RST 23
> > +#define R9A07G043_RSPI0_RST 24
> > +#define R9A07G043_RSPI1_RST 25
> > +#define R9A07G043_RSPI2_RST 26
> > +#define R9A07G043_CANFD_RSTP_N 27
> > +#define R9A07G043_CANFD_RSTC_N 28
> > +#define R9A07G043_GPIO_RSTN 29
> > +#define R9A07G043_GPIO_PORT_RESETN 30
> > +#define R9A07G043_GPIO_SPARE_RESETN 31
> > +#define R9A07G043_TSU_PRESETN 32
> > +#define R9A07G043_SSI0_RST_M2_REG 33
> > +#define R9A07G043_SSI1_RST_M2_REG 34
> > +#define R9A07G043_SSI2_RST_M2_REG 35
> > +#define R9A07G043_SSI3_RST_M2_REG 36
> > +#define R9A07G043_ETH0_RST_HW_N 37
> > +#define R9A07G043_ETH1_RST_HW_N 38
> > +#define R9A07G043_SCIF0_RST_SYSTEM_N 39
> > +#define R9A07G043_SCIF1_RST_SYSTEM_N 40
> > +#define R9A07G043_SCIF2_RST_SYSTEM_N 41
> > +#define R9A07G043_SCIF3_RST_SYSTEM_N 42
> > +#define R9A07G043_SCIF4_RST_SYSTEM_N 43
>
> Is there any specific reason the SSI, ETH, and SCIF resets are ordered
> differently than the corresponding clocks, and than the resets on RZ/G2L?
I thought of taking care type-1 and Type-2 RZ/G2UL SoC's as Type-2 has fewer
Clocks than Type-1. At the moment we are upstreaming only type-1.
OK, Will do Same ordering as RZ/G2L.
Cheers,
Biju
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH v3 3/7] dt-bindings: clock: Add R9A07G043 CPG Clock and Reset Definitions
2022-03-31 7:38 ` Biju Das
@ 2022-03-31 7:46 ` Biju Das
0 siblings, 0 replies; 22+ messages in thread
From: Biju Das @ 2022-03-31 7:46 UTC (permalink / raw)
To: Biju Das, Geert Uytterhoeven
Cc: Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad, Linux-Renesas
> Subject: RE: [PATCH v3 3/7] dt-bindings: clock: Add R9A07G043 CPG Clock
> and Reset Definitions
>
> Hi Geert,
>
> Thanks for the feedback.
>
> > Subject: Re: [PATCH v3 3/7] dt-bindings: clock: Add R9A07G043 CPG
> > Clock and Reset Definitions
> >
> > Hi Biju,
> >
> > On Tue, Mar 15, 2022 at 3:26 PM Biju Das <biju.das.jz@bp.renesas.com>
> > wrote:
> > > Define RZ/G2UL (R9A07G043U) Clock Pulse Generator Core Clock and
> > > module clock outputs, as listed in Table 7.1.4.2 ("Clock List
> > > r0.51") and also add Reset definitions referring to registers
> > > CPG_RST_* in Section 7.2.3 ("Register configuration") of the RZ/G2UL
> > > Hardware User's
> > Manual (Rev.
> > > 0.51, Nov. 2021).
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > v2->v3:
> > > * Removed leading u/U from r9a07g043
> > > * renamed the file r9a07g043u-cpg.h->r9a07g043-cpg.h
> > > * Prepared Common Module Clock/Reset indices for RZ/G2UL and
> > > RZ/Five
> > > * Prepared RZ/G2UL specific Module Clock/Reset indices.
> >
> > Thanks for the update!
> >
> > > --- /dev/null
> > > +++ b/include/dt-bindings/clock/r9a07g043-cpg.h
> > > @@ -0,0 +1,190 @@
> > > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > + *
> > > + * Copyright (C) 2022 Renesas Electronics Corp.
> > > + */
> > > +#ifndef __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__
> > > +#define __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__
> > > +
> > > +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> > > +
> > > +/* R9A07G043 CPG Core Clocks */
> > > +#define R9A07G043_CLK_I 0
> > > +#define R9A07G043_CLK_I2 1
> > > +#define R9A07G043_CLK_S0 2
> > > +#define R9A07G043_CLK_SPI0 3
> > > +#define R9A07G043_CLK_SPI1 4
> > > +#define R9A07G043_CLK_SD0 5
> > > +#define R9A07G043_CLK_SD1 6
> > > +#define R9A07G043_CLK_M0 7
> > > +#define R9A07G043_CLK_M2 8
> > > +#define R9A07G043_CLK_M3 9
> > > +#define R9A07G043_CLK_HP 10
> > > +#define R9A07G043_CLK_TSU 11
> > > +#define R9A07G043_CLK_ZT 12
> > > +#define R9A07G043_CLK_P0 13
> > > +#define R9A07G043_CLK_P1 14
> > > +#define R9A07G043_CLK_P2 15
> > > +#define R9A07G043_CLK_AT 16
> > > +#define R9A07G043_OSCCLK 17
> > > +#define R9A07G043_CLK_P0_DIV2 18
> > > +
> > > +/* R9A07G043 Common Module Clocks */
> > > +#define R9A07G043_IA55_CLK 0
> > > +#define R9A07G043_IA55_PCLK 1
> >
> > I think IA55 does not exist on RZ/Five?
> >
> > > +#define R9A07G043_DMAC_ACLK 2
> > > +#define R9A07G043_DMAC_PCLK 3
> > > +#define R9A07G043_OSTM0_PCLK 4
> > > +#define R9A07G043_OSTM1_PCLK 5
> > > +#define R9A07G043_OSTM2_PCLK 6
> > > +#define R9A07G043_MTU_X_MCK_MTU3 7
> > > +#define R9A07G043_POE3_CLKM_POE 8
> > > +#define R9A07G043_WDT0_PCLK 9
> > > +#define R9A07G043_WDT0_CLK 10
> > > +#define R9A07G043_SPI_CLK2 11
> > > +#define R9A07G043_SPI_CLK 12
> > > +#define R9A07G043_SDHI0_IMCLK 13
> > > +#define R9A07G043_SDHI0_IMCLK2 14
> > > +#define R9A07G043_SDHI0_CLK_HS 15
> > > +#define R9A07G043_SDHI0_ACLK 16
> > > +#define R9A07G043_SDHI1_IMCLK 17
> > > +#define R9A07G043_SDHI1_IMCLK2 18
> > > +#define R9A07G043_SDHI1_CLK_HS 19
> > > +#define R9A07G043_SDHI1_ACLK 20
> > > +#define R9A07G043_SSI0_PCLK2 21
> > > +#define R9A07G043_SSI0_PCLK_SFR 22
> > > +#define R9A07G043_SSI1_PCLK2 23
> > > +#define R9A07G043_SSI1_PCLK_SFR 24
> > > +#define R9A07G043_SSI2_PCLK2 25
> > > +#define R9A07G043_SSI2_PCLK_SFR 26
> > > +#define R9A07G043_SSI3_PCLK2 27
> > > +#define R9A07G043_SSI3_PCLK_SFR 28
> > > +#define R9A07G043_SRC_CLKP 29
> > > +#define R9A07G043_USB_U2H0_HCLK 30
> > > +#define R9A07G043_USB_U2H1_HCLK 31
> > > +#define R9A07G043_USB_U2P_EXR_CPUCLK 32
> > > +#define R9A07G043_USB_PCLK 33
> > > +#define R9A07G043_ETH0_CLK_AXI 34
> > > +#define R9A07G043_ETH0_CLK_CHI 35
> > > +#define R9A07G043_ETH1_CLK_AXI 36
> > > +#define R9A07G043_ETH1_CLK_CHI 37
> > > +#define R9A07G043_I2C0_PCLK 38
> > > +#define R9A07G043_I2C1_PCLK 39
> > > +#define R9A07G043_I2C2_PCLK 40
> > > +#define R9A07G043_I2C3_PCLK 41
> > > +#define R9A07G043_SCIF0_CLK_PCK 42
> > > +#define R9A07G043_SCIF1_CLK_PCK 43
> > > +#define R9A07G043_SCIF2_CLK_PCK 44
> > > +#define R9A07G043_SCIF3_CLK_PCK 45
> > > +#define R9A07G043_SCIF4_CLK_PCK 46
> > > +#define R9A07G043_SCI0_CLKP 47
> > > +#define R9A07G043_SCI1_CLKP 48
> > > +#define R9A07G043_IRDA_CLKP 49
> > > +#define R9A07G043_RSPI0_CLKB 50
> > > +#define R9A07G043_RSPI1_CLKB 51
> > > +#define R9A07G043_RSPI2_CLKB 52
> > > +#define R9A07G043_CANFD_PCLK 53
> > > +#define R9A07G043_GPIO_HCLK 54
> > > +#define R9A07G043_ADC_ADCLK 55
> > > +#define R9A07G043_ADC_PCLK 56
> > > +#define R9A07G043_TSU_PCLK 57
> > > +#define R9A07G043_LAST_COMMON_CLK (R9A07G043_TSU_PCLK)
> >
> > Does R9A07G043_LAST_COMMON_CLK need to be part of the bindings?
>
> I thought we can reuse same header file for both RZ/Five and RZ/G2UL.
> The same can be achieved as per your suggestion below.
>
> > Do you actually have a use case for this definition, besides the use
> > below? If not, I would get rid of the definition, and just hardcode
> > the numeric values below.
> >
> > Perhaps you planned to start enumerating RZ/Five-specific clocks from
> > R9A07G043_LAST_COMMON_CLK + 1, too? I don't think that's a good idea,
> > as it would complicate validation of indices in the driver.
>
> OK, Agreed.
>
> >
> > > +
> > > +/* RZ/G2UL Specific */
> > > +#define R9A07G043_CA55_SCLK (R9A07G043_LAST_COMMON_CLK +
> 1)
> > > +#define R9A07G043_CA55_PCLK (R9A07G043_LAST_COMMON_CLK +
> 2)
> > > +#define R9A07G043_CA55_ATCLK (R9A07G043_LAST_COMMON_CLK +
> 3)
> > > +#define R9A07G043_CA55_GICCLK (R9A07G043_LAST_COMMON_CLK +
> 4)
> > > +#define R9A07G043_CA55_PERICLK (R9A07G043_LAST_COMMON_CLK +
> 5)
> > > +#define R9A07G043_CA55_ACLK (R9A07G043_LAST_COMMON_CLK +
> 6)
> > > +#define R9A07G043_CA55_TSCLK (R9A07G043_LAST_COMMON_CLK +
> 7)
> > > +#define R9A07G043_GIC600_GICCLK
> > (R9A07G043_LAST_COMMON_CLK + 8)
> > > +#define R9A07G043_MHU_PCLK (R9A07G043_LAST_COMMON_CLK +
> 9)
> > > +#define R9A07G043_SYC_CNT_CLK (R9A07G043_LAST_COMMON_CLK +
> 10)
> >
> > I think SYC_CNT does exist on RZ/Five?
>
> Basically SYC (System Counter) for RZ/G2UL and MT (Machine Timer) for
> RZ/Five. See page 26 of RZ/Five HW manual
Since RZ/Five Clock list Document mention it as SYC_CNT, I guess we can
use SYS_CNT for RZ/Five. Any way I will check this with HW team.
Regards,
Biju
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 5/7] clk: renesas: Add support for RZ/G2UL SoC
2022-03-15 14:26 ` [PATCH v3 5/7] clk: renesas: Add support for RZ/G2UL SoC Biju Das
@ 2022-03-31 9:56 ` Geert Uytterhoeven
2022-03-31 16:43 ` Biju Das
0 siblings, 1 reply; 22+ messages in thread
From: Geert Uytterhoeven @ 2022-03-31 9:56 UTC (permalink / raw)
To: Biju Das
Cc: Michael Turquette, Stephen Boyd, Geert Uytterhoeven,
Linux-Renesas, linux-clk, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
Hi Biju,
On Tue, Mar 15, 2022 at 3:27 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> The clock structure for RZ/G2UL is almost identical to RZ/G2L SoC with
> fewer IP blocks. The IP blocks such as WDT1, GPT, H264, GPU and POEG are
> not present on RZ/G2UL.
>
> This patch adds minimal clock and reset entries required to boot the
> system on Renesas RZ/G2UL SMARC EVK and binds it with the RZ/G2L CPG core
> driver.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3:
> * Replaced R9A07G043U->R9A07G043 and r9a07g043u->r9a07g043
Thanks for the update!
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> --- /dev/null
> +++ b/drivers/clk/renesas/r9a07g043-cpg.c
> +const struct rzg2l_cpg_info r9a07g043_cpg_info = {
> + /* Core Clocks */
> + .core_clks = r9a07g043_core_clks,
> + .num_core_clks = ARRAY_SIZE(r9a07g043_core_clks),
> + .last_dt_core_clk = LAST_DT_CORE_CLK,
> + .num_total_core_clks = MOD_CLK_BASE,
> +
> + /* Critical Module Clocks */
> + .crit_mod_clks = r9a07g043_crit_mod_clks,
> + .num_crit_mod_clks = ARRAY_SIZE(r9a07g043_crit_mod_clks),
This may need an update if you change the Clock and Reset Definitions.
> +
> + /* Module Clocks */
> + .mod_clks = r9a07g043_mod_clks,
> + .num_mod_clks = ARRAY_SIZE(r9a07g043_mod_clks),
> + .num_hw_mod_clks = R9A07G043_LCDC_CLK_D + 1,
> +
> + /* Resets */
> + .resets = r9a07g043_resets,
> + .num_resets = R9A07G043_LCDC_RESET_N + 1, /* Last reset ID + 1 */
Likewise.
> +};
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 6/7] arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC
2022-03-15 14:26 ` [PATCH v3 6/7] arm64: dts: renesas: Add initial DTSI " Biju Das
@ 2022-03-31 9:59 ` Geert Uytterhoeven
0 siblings, 0 replies; 22+ messages in thread
From: Geert Uytterhoeven @ 2022-03-31 9:59 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Magnus Damm, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
On Tue, Mar 15, 2022 at 3:27 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add initial DTSI for RZ/G2UL SoC.
>
> Both RZ/G2L and RZ/G2UL uses the same SMARC EVK. Therefore they share
> the common dtsi (rz-smarc.dtsi) file. Place holders are added in
> device nodes to avoid compilation errors for the devices which have
> not been enabled yet on RZ/G2UL SoC.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3:
> * Replaced clocks from R9A07G043U->R9A07G043
> * Replaced compatible from r9a07g043u->r9a07g043
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 7/7] arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC EVK
2022-03-15 14:26 ` [PATCH v3 7/7] arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC EVK Biju Das
@ 2022-03-31 10:08 ` Geert Uytterhoeven
2022-03-31 14:26 ` Geert Uytterhoeven
1 sibling, 0 replies; 22+ messages in thread
From: Geert Uytterhoeven @ 2022-03-31 10:08 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Magnus Damm, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
On Tue, Mar 15, 2022 at 3:27 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add basic support for RZ/G2UL SMARC EVK (based on R9A07G043U11):
> - memory
> - External input clock
> - CPG
> - DMA
> - SCIF
>
> It shares the same carrier board with RZ/G2L, but the pin mapping is
> different. Disable the device nodes which are not tested and delete the
> corresponding pinctrl definitions.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3:
> * Replaced CONFIG_ARCH_R9A07G043U->CONFIG_ARCH_R9A07G043
> * Renamed SoC file r9a07g043u.dtsi->r9a07g043.dtsi
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 7/7] arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC EVK
2022-03-15 14:26 ` [PATCH v3 7/7] arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC EVK Biju Das
2022-03-31 10:08 ` Geert Uytterhoeven
@ 2022-03-31 14:26 ` Geert Uytterhoeven
2022-03-31 14:33 ` Biju Das
1 sibling, 1 reply; 22+ messages in thread
From: Geert Uytterhoeven @ 2022-03-31 14:26 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Geert Uytterhoeven, Magnus Damm, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Hi Biju,
On Tue, Mar 15, 2022 at 3:27 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add basic support for RZ/G2UL SMARC EVK (based on R9A07G043U11):
> - memory
> - External input clock
> - CPG
> - DMA
> - SCIF
>
> It shares the same carrier board with RZ/G2L, but the pin mapping is
> different. Disable the device nodes which are not tested and delete the
> corresponding pinctrl definitions.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
> @@ -0,0 +1,111 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/G2UL Type-1 SMARC EVK board
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +/dts-v1/;
> +#include "r9a07g043.dtsi"
> +#include "rzg2ul-smarc-som.dtsi"
> +#include "rz-smarc-common.dtsi"
> +
> +/ {
> + model = "Renesas SMARC EVK based on r9a07g043u11";
> + compatible = "renesas,smarc-evk", "renesas,r9a07g043u11", "renesas,r9a07g043";
Can you please send a patch to add this combination to
Documentation/devicetree/bindings/arm/renesas.yaml?
Thanks!
> +};
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH v3 7/7] arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC EVK
2022-03-31 14:26 ` Geert Uytterhoeven
@ 2022-03-31 14:33 ` Biju Das
0 siblings, 0 replies; 22+ messages in thread
From: Biju Das @ 2022-03-31 14:33 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Rob Herring, Geert Uytterhoeven, Magnus Damm, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH v3 7/7] arm64: dts: renesas: Add initial device tree
> for RZ/G2UL Type-1 SMARC EVK
>
> Hi Biju,
>
> On Tue, Mar 15, 2022 at 3:27 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > Add basic support for RZ/G2UL SMARC EVK (based on R9A07G043U11):
> > - memory
> > - External input clock
> > - CPG
> > - DMA
> > - SCIF
> >
> > It shares the same carrier board with RZ/G2L, but the pin mapping is
> > different. Disable the device nodes which are not tested and delete
> > the corresponding pinctrl definitions.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
> > @@ -0,0 +1,111 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the RZ/G2UL Type-1 SMARC EVK board
> > + *
> > + * Copyright (C) 2022 Renesas Electronics Corp.
> > + */
> > +
> > +/dts-v1/;
> > +#include "r9a07g043.dtsi"
> > +#include "rzg2ul-smarc-som.dtsi"
> > +#include "rz-smarc-common.dtsi"
> > +
> > +/ {
> > + model = "Renesas SMARC EVK based on r9a07g043u11";
> > + compatible = "renesas,smarc-evk", "renesas,r9a07g043u11",
> > +"renesas,r9a07g043";
>
> Can you please send a patch to add this combination to
> Documentation/devicetree/bindings/arm/renesas.yaml?
OK, Will do.
Cheers,
Biju
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH v3 5/7] clk: renesas: Add support for RZ/G2UL SoC
2022-03-31 9:56 ` Geert Uytterhoeven
@ 2022-03-31 16:43 ` Biju Das
0 siblings, 0 replies; 22+ messages in thread
From: Biju Das @ 2022-03-31 16:43 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Geert Uytterhoeven,
Linux-Renesas, linux-clk, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH v3 5/7] clk: renesas: Add support for RZ/G2UL SoC
>
> Hi Biju,
>
> On Tue, Mar 15, 2022 at 3:27 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > The clock structure for RZ/G2UL is almost identical to RZ/G2L SoC with
> > fewer IP blocks. The IP blocks such as WDT1, GPT, H264, GPU and POEG
> > are not present on RZ/G2UL.
> >
> > This patch adds minimal clock and reset entries required to boot the
> > system on Renesas RZ/G2UL SMARC EVK and binds it with the RZ/G2L CPG
> > core driver.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v2->v3:
> > * Replaced R9A07G043U->R9A07G043 and r9a07g043u->r9a07g043
>
> Thanks for the update!
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> > --- /dev/null
> > +++ b/drivers/clk/renesas/r9a07g043-cpg.c
>
> > +const struct rzg2l_cpg_info r9a07g043_cpg_info = {
> > + /* Core Clocks */
> > + .core_clks = r9a07g043_core_clks,
> > + .num_core_clks = ARRAY_SIZE(r9a07g043_core_clks),
> > + .last_dt_core_clk = LAST_DT_CORE_CLK,
> > + .num_total_core_clks = MOD_CLK_BASE,
> > +
> > + /* Critical Module Clocks */
> > + .crit_mod_clks = r9a07g043_crit_mod_clks,
> > + .num_crit_mod_clks = ARRAY_SIZE(r9a07g043_crit_mod_clks),
>
> This may need an update if you change the Clock and Reset Definitions.
OK. Will update
Cheers,
Biju
>
> > +
> > + /* Module Clocks */
> > + .mod_clks = r9a07g043_mod_clks,
> > + .num_mod_clks = ARRAY_SIZE(r9a07g043_mod_clks),
> > + .num_hw_mod_clks = R9A07G043_LCDC_CLK_D + 1,
> > +
> > + /* Resets */
> > + .resets = r9a07g043_resets,
> > + .num_resets = R9A07G043_LCDC_RESET_N + 1, /* Last reset ID + 1
> > + */
>
> Likewise.
>
> > +};
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH v3 3/7] dt-bindings: clock: Add R9A07G043 CPG Clock and Reset Definitions
2022-03-30 19:45 ` Geert Uytterhoeven
@ 2022-04-01 15:12 ` Biju Das
0 siblings, 0 replies; 22+ messages in thread
From: Biju Das @ 2022-04-01 15:12 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad, Linux-Renesas
Hi Geert,
> Subject: Re: [PATCH v3 3/7] dt-bindings: clock: Add R9A07G043 CPG Clock
> and Reset Definitions
>
> On Wed, Mar 30, 2022 at 9:27 PM Geert Uytterhoeven <geert@linux-m68k.org>
> wrote:
> > On Tue, Mar 15, 2022 at 3:26 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > > Define RZ/G2UL (R9A07G043U) Clock Pulse Generator Core Clock and
> > > module clock outputs, as listed in Table 7.1.4.2 ("Clock List
> > > r0.51") and also add Reset definitions referring to registers
> > > CPG_RST_* in Section 7.2.3 ("Register configuration") of the RZ/G2UL
> Hardware User's Manual (Rev.
> > > 0.51, Nov. 2021).
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > v2->v3:
> > > * Removed leading u/U from r9a07g043
> > > * renamed the file r9a07g043u-cpg.h->r9a07g043-cpg.h
> > > * Prepared Common Module Clock/Reset indices for RZ/G2UL and
> > > RZ/Five
> > > * Prepared RZ/G2UL specific Module Clock/Reset indices.
> >
> > Thanks for the update!
> >
> > > --- /dev/null
> > > +++ b/include/dt-bindings/clock/r9a07g043-cpg.h
>
> > > +/* R9A07G043 Common Module Clocks */
> > > +#define R9A07G043_IA55_CLK 0
> > > +#define R9A07G043_IA55_PCLK 1
> >
> > I think IA55 does not exist on RZ/Five?
>
> Looks like I was wrong, and it does exist.
Indeed you are correct. As per latest RZ/Five Hw manual,
the IP is called as IAX45.
Regards,
Biju
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2022-04-01 15:54 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-15 14:26 [PATCH v3 0/7] Add Renesas RZ/G2UL Type-1 {SoC,SMARC EVK} support Biju Das
2022-03-15 14:26 ` [PATCH v3 1/7] dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoC Biju Das
2022-03-30 13:09 ` Geert Uytterhoeven
2022-03-30 13:45 ` Biju Das
2022-03-15 14:26 ` [PATCH v3 2/7] soc: renesas: Identify " Biju Das
2022-03-30 13:17 ` Geert Uytterhoeven
2022-03-15 14:26 ` [PATCH v3 3/7] dt-bindings: clock: Add R9A07G043 CPG Clock and Reset Definitions Biju Das
2022-03-23 18:41 ` Rob Herring
2022-03-30 19:27 ` Geert Uytterhoeven
2022-03-30 19:45 ` Geert Uytterhoeven
2022-04-01 15:12 ` Biju Das
2022-03-31 7:38 ` Biju Das
2022-03-31 7:46 ` Biju Das
2022-03-15 14:26 ` [PATCH v3 5/7] clk: renesas: Add support for RZ/G2UL SoC Biju Das
2022-03-31 9:56 ` Geert Uytterhoeven
2022-03-31 16:43 ` Biju Das
2022-03-15 14:26 ` [PATCH v3 6/7] arm64: dts: renesas: Add initial DTSI " Biju Das
2022-03-31 9:59 ` Geert Uytterhoeven
2022-03-15 14:26 ` [PATCH v3 7/7] arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC EVK Biju Das
2022-03-31 10:08 ` Geert Uytterhoeven
2022-03-31 14:26 ` Geert Uytterhoeven
2022-03-31 14:33 ` Biju Das
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