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* [PATCH v5 0/3] arm64: dts: renesas: r8a779f0: Add/Enable Ethernet Switch and SERDES nodes
@ 2022-11-10 13:16 Yoshihiro Shimoda
  2022-11-10 13:16 ` [PATCH v5 1/3] arm64: dts: renesas: r8a779f0: Add " Yoshihiro Shimoda
                   ` (3 more replies)
  0 siblings, 4 replies; 10+ messages in thread
From: Yoshihiro Shimoda @ 2022-11-10 13:16 UTC (permalink / raw)
  To: geert+renesas, magnus.damm; +Cc: linux-renesas-soc, Yoshihiro Shimoda

Add/enable Ethernet Switch and SERDES for R-Car S4-8 (r8a779f0).

Notes that we need to modify Marvell 10G PHY driver for Spider board. I have
local patches to use the Marvell 10G driver on the Spider board. But, it needs
to update for upstraming.

JFYI, if we don't modify the Marvell 10G PHY driver, the ethernet device cannot
work correctly with the following error messages:

[    2.137800] phy phy-e6444000.phy.0: phy init failed --> -110
[    2.148809] renesas_eth_sw: probe of e6880000.ethernet failed with error -110

Changes from v4:
https://lore.kernel.org/all/20221019083538.933127-1-yoshihiro.shimoda.uh@renesas.com/
 - Rebased on renesas-devel-2022-11-08-v6.1-rc4.
 - Fix node name of eth_serdes.
 - Modify defconfig for using NFS root on the Spider board.

Changes from v3:
 https://lore.kernel.org/all/20220922051706.3442382-1-yoshihiro.shimoda.uh@renesas.com/
 - Rebased on next-20221017.
 - Update some propeties which are related to the latest dt-bindings doc.

Yoshihiro Shimoda (3):
  arm64: dts: renesas: r8a779f0: Add Ethernet Switch and SERDES nodes
  arm64: dts: renesas: r8a779f0: spider: Enable Ethernet Switch and
    SERDES
  arm64: configs: Enable Renesas R-Car S4-8 Spider Ethernet devices

 .../dts/renesas/r8a779f0-spider-ethernet.dtsi |  77 +++++++++++++
 arch/arm64/boot/dts/renesas/r8a779f0.dtsi     | 109 ++++++++++++++++++
 arch/arm64/configs/defconfig                  |   4 +-
 3 files changed, 189 insertions(+), 1 deletion(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH v5 1/3] arm64: dts: renesas: r8a779f0: Add Ethernet Switch and SERDES nodes
  2022-11-10 13:16 [PATCH v5 0/3] arm64: dts: renesas: r8a779f0: Add/Enable Ethernet Switch and SERDES nodes Yoshihiro Shimoda
@ 2022-11-10 13:16 ` Yoshihiro Shimoda
  2022-11-14 15:54   ` Geert Uytterhoeven
  2022-11-10 13:16 ` [PATCH v5 2/3] arm64: dts: renesas: r8a779f0: spider: Enable Ethernet Switch and SERDES Yoshihiro Shimoda
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 10+ messages in thread
From: Yoshihiro Shimoda @ 2022-11-10 13:16 UTC (permalink / raw)
  To: geert+renesas, magnus.damm; +Cc: linux-renesas-soc, Yoshihiro Shimoda

Add Ethernet Switch and SERDES nodes into R-Car S4-8 (r8a779f0).

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 109 ++++++++++++++++++++++
 1 file changed, 109 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
index 4092c0016035..d21345974c9f 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
@@ -469,6 +469,16 @@ tmu4: timer@ffc00000 {
 			status = "disabled";
 		};
 
+		eth_serdes: phy@e6444000 {
+			compatible = "renesas,r8a779f0-ether-serdes";
+			reg = <0 0xe6444000 0 0x2800>;
+			clocks = <&cpg CPG_MOD 1506>;
+			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+			resets = <&cpg 1506>;
+			#phy-cells = <1>;
+			status = "disabled";
+		};
+
 		i2c0: i2c@e6500000 {
 			compatible = "renesas,i2c-r8a779f0",
 				     "renesas,rcar-gen4-i2c";
@@ -651,6 +661,105 @@ ufs: ufs@e6860000 {
 			status = "disabled";
 		};
 
+		rswitch: ethernet@e6880000 {
+			compatible = "renesas,r8a779f0-ether-switch";
+			reg = <0 0xe6880000 0 0x20000>, <0 0xe68c0000 0 0x20000>;
+			reg-names = "base", "secure_base";
+			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "mfwd_error", "race_error",
+					  "coma_error", "gwca0_error",
+					  "gwca1_error", "etha0_error",
+					  "etha1_error", "etha2_error",
+					  "gptp0_status", "gptp1_status",
+					  "mfwd_status", "race_status",
+					  "coma_status", "gwca0_status",
+					  "gwca1_status", "etha0_status",
+					  "etha1_status", "etha2_status",
+					  "rmac0_status", "rmac1_status",
+					  "rmac2_status",
+					  "gwca0_rxtx0", "gwca0_rxtx1",
+					  "gwca0_rxtx2", "gwca0_rxtx3",
+					  "gwca0_rxtx4", "gwca0_rxtx5",
+					  "gwca0_rxtx6", "gwca0_rxtx7",
+					  "gwca1_rxtx0", "gwca1_rxtx1",
+					  "gwca1_rxtx2", "gwca1_rxtx3",
+					  "gwca1_rxtx4", "gwca1_rxtx5",
+					  "gwca1_rxtx6", "gwca1_rxtx7",
+					  "gwca0_rxts0", "gwca0_rxts1",
+					  "gwca1_rxts0", "gwca1_rxts1",
+					  "rmac0_mdio", "rmac1_mdio",
+					  "rmac2_mdio",
+					  "rmac0_phy", "rmac1_phy",
+					  "rmac2_phy";
+			clocks = <&cpg CPG_MOD 1505>;
+			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+			resets = <&cpg 1505>;
+			status = "disabled";
+
+			ethernet-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				port@0 {
+					reg = <0>;
+					phys = <&eth_serdes 0>;
+				};
+				port@1 {
+					reg = <1>;
+					phys = <&eth_serdes 1>;
+				};
+				port@2 {
+					reg = <2>;
+					phys = <&eth_serdes 2>;
+				};
+			};
+		};
+
 		scif0: serial@e6e60000 {
 			compatible = "renesas,scif-r8a779f0",
 				     "renesas,rcar-gen4-scif", "renesas,scif";
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 10+ messages in thread

* [PATCH v5 2/3] arm64: dts: renesas: r8a779f0: spider: Enable Ethernet Switch and SERDES
  2022-11-10 13:16 [PATCH v5 0/3] arm64: dts: renesas: r8a779f0: Add/Enable Ethernet Switch and SERDES nodes Yoshihiro Shimoda
  2022-11-10 13:16 ` [PATCH v5 1/3] arm64: dts: renesas: r8a779f0: Add " Yoshihiro Shimoda
@ 2022-11-10 13:16 ` Yoshihiro Shimoda
  2022-11-14 15:57   ` Geert Uytterhoeven
  2022-11-10 13:16 ` [PATCH v5 3/3] arm64: configs: Enable Renesas R-Car S4-8 Spider Ethernet devices Yoshihiro Shimoda
  2022-11-10 14:33 ` [PATCH v5 0/3] arm64: dts: renesas: r8a779f0: Add/Enable Ethernet Switch and SERDES nodes Geert Uytterhoeven
  3 siblings, 1 reply; 10+ messages in thread
From: Yoshihiro Shimoda @ 2022-11-10 13:16 UTC (permalink / raw)
  To: geert+renesas, magnus.damm; +Cc: linux-renesas-soc, Yoshihiro Shimoda

Enable Ethernet Switch and SERDES for R-Car S4-8 (r8a779f0).

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 .../dts/renesas/r8a779f0-spider-ethernet.dtsi | 77 +++++++++++++++++++
 1 file changed, 77 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi
index 15e8d1ebf575..5642d69f76ca 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi
@@ -5,6 +5,10 @@
  * Copyright (C) 2021 Renesas Electronics Corp.
  */
 
+&eth_serdes {
+	status = "okay";
+};
+
 &i2c4 {
 	eeprom@52 {
 		compatible = "rohm,br24g01", "atmel,24c01";
@@ -13,3 +17,76 @@ eeprom@52 {
 		pagesize = <8>;
 	};
 };
+
+&pfc {
+	tsn0_pins: tsn0 {
+		groups = "tsn0_mdio_b", "tsn0_link_b";
+		function = "tsn0";
+		power-source = <1800>;
+	};
+
+	tsn1_pins: tsn1 {
+		groups = "tsn1_mdio_b", "tsn1_link_b";
+		function = "tsn1";
+		power-source = <1800>;
+	};
+
+	tsn2_pins: tsn2 {
+		groups = "tsn2_mdio_b", "tsn2_link_b";
+		function = "tsn2";
+		power-source = <1800>;
+	};
+};
+
+&rswitch {
+	pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>, <&tsn2_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	ethernet-ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			phy-handle = <&u101>;
+			phy-mode = "sgmii";
+			phys = <&eth_serdes 0>;
+			mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				u101: ethernet-phy@1 {
+					reg = <1>;
+					compatible = "ethernet-phy-ieee802.3-c45";
+				};
+			};
+		};
+		port@1 {
+			reg = <1>;
+			phy-handle = <&u201>;
+			phy-mode = "sgmii";
+			phys = <&eth_serdes 1>;
+			mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				u201: ethernet-phy@2 {
+					reg = <2>;
+					compatible = "ethernet-phy-ieee802.3-c45";
+				};
+			};
+		};
+		port@2 {
+			reg = <2>;
+			phy-handle = <&u301>;
+			phy-mode = "sgmii";
+			phys = <&eth_serdes 2>;
+			mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				u301: ethernet-phy@3 {
+					reg = <3>;
+					compatible = "ethernet-phy-ieee802.3-c45";
+				};
+			};
+		};
+	};
+};
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 10+ messages in thread

* [PATCH v5 3/3] arm64: configs: Enable Renesas R-Car S4-8 Spider Ethernet devices
  2022-11-10 13:16 [PATCH v5 0/3] arm64: dts: renesas: r8a779f0: Add/Enable Ethernet Switch and SERDES nodes Yoshihiro Shimoda
  2022-11-10 13:16 ` [PATCH v5 1/3] arm64: dts: renesas: r8a779f0: Add " Yoshihiro Shimoda
  2022-11-10 13:16 ` [PATCH v5 2/3] arm64: dts: renesas: r8a779f0: spider: Enable Ethernet Switch and SERDES Yoshihiro Shimoda
@ 2022-11-10 13:16 ` Yoshihiro Shimoda
  2022-11-14 15:57   ` Geert Uytterhoeven
  2022-11-10 14:33 ` [PATCH v5 0/3] arm64: dts: renesas: r8a779f0: Add/Enable Ethernet Switch and SERDES nodes Geert Uytterhoeven
  3 siblings, 1 reply; 10+ messages in thread
From: Yoshihiro Shimoda @ 2022-11-10 13:16 UTC (permalink / raw)
  To: geert+renesas, magnus.damm; +Cc: linux-renesas-soc, Yoshihiro Shimoda

Enable Renesas "Ethernet Switch", Ethernet SERDES and Marvell 10G PHY
drivers to be used by NFS root on the Renesas Spider board.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 arch/arm64/configs/defconfig | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 0b6af3348e79..311e0b134b27 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -357,6 +357,7 @@ CONFIG_RMNET=m
 CONFIG_R8169=m
 CONFIG_SH_ETH=y
 CONFIG_RAVB=y
+CONFIG_RENESAS_ETHER_SWITCH=y
 CONFIG_SMC91X=y
 CONFIG_SMSC911X=y
 CONFIG_SNI_AVE=y
@@ -369,7 +370,7 @@ CONFIG_MESON_GXL_PHY=m
 CONFIG_AQUANTIA_PHY=y
 CONFIG_BCM54140_PHY=m
 CONFIG_MARVELL_PHY=m
-CONFIG_MARVELL_10G_PHY=m
+CONFIG_MARVELL_10G_PHY=y
 CONFIG_MICREL_PHY=y
 CONFIG_MICROSEMI_PHY=y
 CONFIG_AT803X_PHY=y
@@ -1239,6 +1240,7 @@ CONFIG_PHY_QCOM_USB_HS=m
 CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=m
 CONFIG_PHY_QCOM_USB_HS_28NM=m
 CONFIG_PHY_QCOM_USB_SS=m
+CONFIG_PHY_R8A779F0_ETHERNET_SERDES=y
 CONFIG_PHY_RCAR_GEN3_PCIE=y
 CONFIG_PHY_RCAR_GEN3_USB2=y
 CONFIG_PHY_RCAR_GEN3_USB3=m
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 10+ messages in thread

* Re: [PATCH v5 0/3] arm64: dts: renesas: r8a779f0: Add/Enable Ethernet Switch and SERDES nodes
  2022-11-10 13:16 [PATCH v5 0/3] arm64: dts: renesas: r8a779f0: Add/Enable Ethernet Switch and SERDES nodes Yoshihiro Shimoda
                   ` (2 preceding siblings ...)
  2022-11-10 13:16 ` [PATCH v5 3/3] arm64: configs: Enable Renesas R-Car S4-8 Spider Ethernet devices Yoshihiro Shimoda
@ 2022-11-10 14:33 ` Geert Uytterhoeven
  3 siblings, 0 replies; 10+ messages in thread
From: Geert Uytterhoeven @ 2022-11-10 14:33 UTC (permalink / raw)
  To: Yoshihiro Shimoda; +Cc: magnus.damm, linux-renesas-soc

Hi Shimoda-san,

On Thu, Nov 10, 2022 at 2:16 PM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Add/enable Ethernet Switch and SERDES for R-Car S4-8 (r8a779f0).

Thanks for the update!

> Notes that we need to modify Marvell 10G PHY driver for Spider board. I have
> local patches to use the Marvell 10G driver on the Spider board. But, it needs
> to update for upstraming.
>
> JFYI, if we don't modify the Marvell 10G PHY driver, the ethernet device cannot
> work correctly with the following error messages:
>
> [    2.137800] phy phy-e6444000.phy.0: phy init failed --> -110
> [    2.148809] renesas_eth_sw: probe of e6880000.ethernet failed with error -110

Yes, I had noticed that failure ;-)

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH v5 1/3] arm64: dts: renesas: r8a779f0: Add Ethernet Switch and SERDES nodes
  2022-11-10 13:16 ` [PATCH v5 1/3] arm64: dts: renesas: r8a779f0: Add " Yoshihiro Shimoda
@ 2022-11-14 15:54   ` Geert Uytterhoeven
  2022-11-15  1:38     ` Yoshihiro Shimoda
  0 siblings, 1 reply; 10+ messages in thread
From: Geert Uytterhoeven @ 2022-11-14 15:54 UTC (permalink / raw)
  To: Yoshihiro Shimoda; +Cc: magnus.damm, linux-renesas-soc

Hi Shimoda-san,

On Thu, Nov 10, 2022 at 2:16 PM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Add Ethernet Switch and SERDES nodes into R-Car S4-8 (r8a779f0).
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Thanks for your patch!

LGTM, but...

> --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi

> @@ -651,6 +661,105 @@ ufs: ufs@e6860000 {
>                         status = "disabled";
>                 };
>
> +               rswitch: ethernet@e6880000 {
> +                       compatible = "renesas,r8a779f0-ether-switch";
> +                       reg = <0 0xe6880000 0 0x20000>, <0 0xe68c0000 0 0x20000>;
> +                       reg-names = "base", "secure_base";
> +                       interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "mfwd_error", "race_error",
> +                                         "coma_error", "gwca0_error",
> +                                         "gwca1_error", "etha0_error",
> +                                         "etha1_error", "etha2_error",
> +                                         "gptp0_status", "gptp1_status",
> +                                         "mfwd_status", "race_status",
> +                                         "coma_status", "gwca0_status",
> +                                         "gwca1_status", "etha0_status",
> +                                         "etha1_status", "etha2_status",
> +                                         "rmac0_status", "rmac1_status",
> +                                         "rmac2_status",
> +                                         "gwca0_rxtx0", "gwca0_rxtx1",
> +                                         "gwca0_rxtx2", "gwca0_rxtx3",
> +                                         "gwca0_rxtx4", "gwca0_rxtx5",
> +                                         "gwca0_rxtx6", "gwca0_rxtx7",
> +                                         "gwca1_rxtx0", "gwca1_rxtx1",
> +                                         "gwca1_rxtx2", "gwca1_rxtx3",
> +                                         "gwca1_rxtx4", "gwca1_rxtx5",
> +                                         "gwca1_rxtx6", "gwca1_rxtx7",
> +                                         "gwca0_rxts0", "gwca0_rxts1",
> +                                         "gwca1_rxts0", "gwca1_rxts1",
> +                                         "rmac0_mdio", "rmac1_mdio",
> +                                         "rmac2_mdio",
> +                                         "rmac0_phy", "rmac1_phy",
> +                                         "rmac2_phy";
> +                       clocks = <&cpg CPG_MOD 1505>;
> +                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
> +                       resets = <&cpg 1505>;
> +                       status = "disabled";
> +
> +                       ethernet-ports {
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;

... please insert a blank line between properties and subnodes.

> +                               port@0 {
> +                                       reg = <0>;
> +                                       phys = <&eth_serdes 0>;
> +                               };
> +                               port@1 {
> +                                       reg = <1>;
> +                                       phys = <&eth_serdes 1>;
> +                               };
> +                               port@2 {
> +                                       reg = <2>;
> +                                       phys = <&eth_serdes 2>;
> +                               };
> +                       };
> +               };
> +
>                 scif0: serial@e6e60000 {
>                         compatible = "renesas,scif-r8a779f0",
>                                      "renesas,rcar-gen4-scif", "renesas,scif";

With the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH v5 2/3] arm64: dts: renesas: r8a779f0: spider: Enable Ethernet Switch and SERDES
  2022-11-10 13:16 ` [PATCH v5 2/3] arm64: dts: renesas: r8a779f0: spider: Enable Ethernet Switch and SERDES Yoshihiro Shimoda
@ 2022-11-14 15:57   ` Geert Uytterhoeven
  2022-11-15  1:41     ` Yoshihiro Shimoda
  0 siblings, 1 reply; 10+ messages in thread
From: Geert Uytterhoeven @ 2022-11-14 15:57 UTC (permalink / raw)
  To: Yoshihiro Shimoda; +Cc: magnus.damm, linux-renesas-soc

Hi Shimoda-san,

On Thu, Nov 10, 2022 at 2:16 PM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Enable Ethernet Switch and SERDES for R-Car S4-8 (r8a779f0).
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi
> @@ -13,3 +17,76 @@ eeprom@52 {
>                 pagesize = <8>;
>         };
>  };
> +
> +&pfc {
> +       tsn0_pins: tsn0 {
> +               groups = "tsn0_mdio_b", "tsn0_link_b";
> +               function = "tsn0";
> +               power-source = <1800>;
> +       };
> +
> +       tsn1_pins: tsn1 {
> +               groups = "tsn1_mdio_b", "tsn1_link_b";
> +               function = "tsn1";
> +               power-source = <1800>;
> +       };
> +
> +       tsn2_pins: tsn2 {
> +               groups = "tsn2_mdio_b", "tsn2_link_b";
> +               function = "tsn2";
> +               power-source = <1800>;
> +       };
> +};
> +
> +&rswitch {
> +       pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>, <&tsn2_pins>;
> +       pinctrl-names = "default";
> +       status = "okay";
> +
> +       ethernet-ports {
> +               #address-cells = <1>;
> +               #size-cells = <0>;

Please insert a blank line between properties and subnodes (everywhere).

> +               port@0 {
> +                       reg = <0>;
> +                       phy-handle = <&u101>;
> +                       phy-mode = "sgmii";
> +                       phys = <&eth_serdes 0>;
> +                       mdio {
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               u101: ethernet-phy@1 {
> +                                       reg = <1>;
> +                                       compatible = "ethernet-phy-ieee802.3-c45";

Missing PHY interrupt:

    interrupt-parent = <&gpio3>;
    interrupts = <10 IRQ_TYPE_LEVEL_LOW>;

> +                               };
> +                       };
> +               };
> +               port@1 {
> +                       reg = <1>;
> +                       phy-handle = <&u201>;
> +                       phy-mode = "sgmii";
> +                       phys = <&eth_serdes 1>;
> +                       mdio {
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               u201: ethernet-phy@2 {
> +                                       reg = <2>;
> +                                       compatible = "ethernet-phy-ieee802.3-c45";

    interrupt-parent = <&gpio3>;
    interrupts = <11 IRQ_TYPE_LEVEL_LOW>;

> +                               };
> +                       };
> +               };
> +               port@2 {
> +                       reg = <2>;
> +                       phy-handle = <&u301>;
> +                       phy-mode = "sgmii";
> +                       phys = <&eth_serdes 2>;
> +                       mdio {
> +                               #address-cells = <1>;
> +                               #size-cells = <0>;
> +                               u301: ethernet-phy@3 {
> +                                       reg = <3>;
> +                                       compatible = "ethernet-phy-ieee802.3-c45";

    interrupt-parent = <&gpio3>;
    interrupts = <9 IRQ_TYPE_LEVEL_LOW>;

> +                               };
> +                       };
> +               };
> +       };
> +};

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH v5 3/3] arm64: configs: Enable Renesas R-Car S4-8 Spider Ethernet devices
  2022-11-10 13:16 ` [PATCH v5 3/3] arm64: configs: Enable Renesas R-Car S4-8 Spider Ethernet devices Yoshihiro Shimoda
@ 2022-11-14 15:57   ` Geert Uytterhoeven
  0 siblings, 0 replies; 10+ messages in thread
From: Geert Uytterhoeven @ 2022-11-14 15:57 UTC (permalink / raw)
  To: Yoshihiro Shimoda; +Cc: magnus.damm, linux-renesas-soc

On Thu, Nov 10, 2022 at 2:16 PM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Enable Renesas "Ethernet Switch", Ethernet SERDES and Marvell 10G PHY
> drivers to be used by NFS root on the Renesas Spider board.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 10+ messages in thread

* RE: [PATCH v5 1/3] arm64: dts: renesas: r8a779f0: Add Ethernet Switch and SERDES nodes
  2022-11-14 15:54   ` Geert Uytterhoeven
@ 2022-11-15  1:38     ` Yoshihiro Shimoda
  0 siblings, 0 replies; 10+ messages in thread
From: Yoshihiro Shimoda @ 2022-11-15  1:38 UTC (permalink / raw)
  To: Geert Uytterhoeven; +Cc: magnus.damm, linux-renesas-soc

Hi Geert-san,

> From: Geert Uytterhoeven, Sent: Tuesday, November 15, 2022 12:55 AM
> 
> Hi Shimoda-san,
> 
> On Thu, Nov 10, 2022 at 2:16 PM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > Add Ethernet Switch and SERDES nodes into R-Car S4-8 (r8a779f0).
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> 
> Thanks for your patch!
> 
> LGTM, but...
> 
> > --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
> 
> > @@ -651,6 +661,105 @@ ufs: ufs@e6860000 {
> >                         status = "disabled";
> >                 };
> >
> > +               rswitch: ethernet@e6880000 {
> > +                       compatible = "renesas,r8a779f0-ether-switch";
> > +                       reg = <0 0xe6880000 0 0x20000>, <0 0xe68c0000 0 0x20000>;
> > +                       reg-names = "base", "secure_base";
> > +                       interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
> > +                       interrupt-names = "mfwd_error", "race_error",
> > +                                         "coma_error", "gwca0_error",
> > +                                         "gwca1_error", "etha0_error",
> > +                                         "etha1_error", "etha2_error",
> > +                                         "gptp0_status", "gptp1_status",
> > +                                         "mfwd_status", "race_status",
> > +                                         "coma_status", "gwca0_status",
> > +                                         "gwca1_status", "etha0_status",
> > +                                         "etha1_status", "etha2_status",
> > +                                         "rmac0_status", "rmac1_status",
> > +                                         "rmac2_status",
> > +                                         "gwca0_rxtx0", "gwca0_rxtx1",
> > +                                         "gwca0_rxtx2", "gwca0_rxtx3",
> > +                                         "gwca0_rxtx4", "gwca0_rxtx5",
> > +                                         "gwca0_rxtx6", "gwca0_rxtx7",
> > +                                         "gwca1_rxtx0", "gwca1_rxtx1",
> > +                                         "gwca1_rxtx2", "gwca1_rxtx3",
> > +                                         "gwca1_rxtx4", "gwca1_rxtx5",
> > +                                         "gwca1_rxtx6", "gwca1_rxtx7",
> > +                                         "gwca0_rxts0", "gwca0_rxts1",
> > +                                         "gwca1_rxts0", "gwca1_rxts1",
> > +                                         "rmac0_mdio", "rmac1_mdio",
> > +                                         "rmac2_mdio",
> > +                                         "rmac0_phy", "rmac1_phy",
> > +                                         "rmac2_phy";
> > +                       clocks = <&cpg CPG_MOD 1505>;
> > +                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
> > +                       resets = <&cpg 1505>;
> > +                       status = "disabled";
> > +
> > +                       ethernet-ports {
> > +                               #address-cells = <1>;
> > +                               #size-cells = <0>;
> 
> ... please insert a blank line between properties and subnodes.

Thank you for your review! I got it. I'll fix it.

> > +                               port@0 {
> > +                                       reg = <0>;
> > +                                       phys = <&eth_serdes 0>;
> > +                               };
> > +                               port@1 {
> > +                                       reg = <1>;
> > +                                       phys = <&eth_serdes 1>;
> > +                               };
> > +                               port@2 {
> > +                                       reg = <2>;
> > +                                       phys = <&eth_serdes 2>;
> > +                               };
> > +                       };
> > +               };
> > +
> >                 scif0: serial@e6e60000 {
> >                         compatible = "renesas,scif-r8a779f0",
> >                                      "renesas,rcar-gen4-scif", "renesas,scif";
> 
> With the above fixed:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Thanks!

Best regards,
Yoshihiro Shimoda

> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

^ permalink raw reply	[flat|nested] 10+ messages in thread

* RE: [PATCH v5 2/3] arm64: dts: renesas: r8a779f0: spider: Enable Ethernet Switch and SERDES
  2022-11-14 15:57   ` Geert Uytterhoeven
@ 2022-11-15  1:41     ` Yoshihiro Shimoda
  0 siblings, 0 replies; 10+ messages in thread
From: Yoshihiro Shimoda @ 2022-11-15  1:41 UTC (permalink / raw)
  To: Geert Uytterhoeven; +Cc: magnus.damm, linux-renesas-soc

Hi Geert-san,

> From: Geert Uytterhoeven, Sent: Tuesday, November 15, 2022 12:57 AM
> 
> Hi Shimoda-san,
> 
> On Thu, Nov 10, 2022 at 2:16 PM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > Enable Ethernet Switch and SERDES for R-Car S4-8 (r8a779f0).
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> 
> Thanks for your patch!
> 
> > --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi
> > @@ -13,3 +17,76 @@ eeprom@52 {
> >                 pagesize = <8>;
> >         };
> >  };
> > +
> > +&pfc {
> > +       tsn0_pins: tsn0 {
> > +               groups = "tsn0_mdio_b", "tsn0_link_b";
> > +               function = "tsn0";
> > +               power-source = <1800>;
> > +       };
> > +
> > +       tsn1_pins: tsn1 {
> > +               groups = "tsn1_mdio_b", "tsn1_link_b";
> > +               function = "tsn1";
> > +               power-source = <1800>;
> > +       };
> > +
> > +       tsn2_pins: tsn2 {
> > +               groups = "tsn2_mdio_b", "tsn2_link_b";
> > +               function = "tsn2";
> > +               power-source = <1800>;
> > +       };
> > +};
> > +
> > +&rswitch {
> > +       pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>, <&tsn2_pins>;
> > +       pinctrl-names = "default";
> > +       status = "okay";
> > +
> > +       ethernet-ports {
> > +               #address-cells = <1>;
> > +               #size-cells = <0>;
> 
> Please insert a blank line between properties and subnodes (everywhere).

I understood it. I'll fix this patch.

> > +               port@0 {
> > +                       reg = <0>;
> > +                       phy-handle = <&u101>;
> > +                       phy-mode = "sgmii";
> > +                       phys = <&eth_serdes 0>;
> > +                       mdio {
> > +                               #address-cells = <1>;
> > +                               #size-cells = <0>;
> > +                               u101: ethernet-phy@1 {
> > +                                       reg = <1>;
> > +                                       compatible = "ethernet-phy-ieee802.3-c45";
> 
> Missing PHY interrupt:
> 
>     interrupt-parent = <&gpio3>;
>     interrupts = <10 IRQ_TYPE_LEVEL_LOW>;

Oops. I'll add PHY interrupt properties.

> > +                               };
> > +                       };
> > +               };
> > +               port@1 {
> > +                       reg = <1>;
> > +                       phy-handle = <&u201>;
> > +                       phy-mode = "sgmii";
> > +                       phys = <&eth_serdes 1>;
> > +                       mdio {
> > +                               #address-cells = <1>;
> > +                               #size-cells = <0>;
> > +                               u201: ethernet-phy@2 {
> > +                                       reg = <2>;
> > +                                       compatible = "ethernet-phy-ieee802.3-c45";
> 
>     interrupt-parent = <&gpio3>;
>     interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
> 
> > +                               };
> > +                       };
> > +               };
> > +               port@2 {
> > +                       reg = <2>;
> > +                       phy-handle = <&u301>;
> > +                       phy-mode = "sgmii";
> > +                       phys = <&eth_serdes 2>;
> > +                       mdio {
> > +                               #address-cells = <1>;
> > +                               #size-cells = <0>;
> > +                               u301: ethernet-phy@3 {
> > +                                       reg = <3>;
> > +                                       compatible = "ethernet-phy-ieee802.3-c45";
> 
>     interrupt-parent = <&gpio3>;
>     interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
> 
> > +                               };
> > +                       };
> > +               };
> > +       };
> > +};
> 
> The rest LGTM.

Thanks!

Best regards,
Yoshihiro Shimoda

> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

^ permalink raw reply	[flat|nested] 10+ messages in thread

end of thread, other threads:[~2022-11-15  1:41 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-11-10 13:16 [PATCH v5 0/3] arm64: dts: renesas: r8a779f0: Add/Enable Ethernet Switch and SERDES nodes Yoshihiro Shimoda
2022-11-10 13:16 ` [PATCH v5 1/3] arm64: dts: renesas: r8a779f0: Add " Yoshihiro Shimoda
2022-11-14 15:54   ` Geert Uytterhoeven
2022-11-15  1:38     ` Yoshihiro Shimoda
2022-11-10 13:16 ` [PATCH v5 2/3] arm64: dts: renesas: r8a779f0: spider: Enable Ethernet Switch and SERDES Yoshihiro Shimoda
2022-11-14 15:57   ` Geert Uytterhoeven
2022-11-15  1:41     ` Yoshihiro Shimoda
2022-11-10 13:16 ` [PATCH v5 3/3] arm64: configs: Enable Renesas R-Car S4-8 Spider Ethernet devices Yoshihiro Shimoda
2022-11-14 15:57   ` Geert Uytterhoeven
2022-11-10 14:33 ` [PATCH v5 0/3] arm64: dts: renesas: r8a779f0: Add/Enable Ethernet Switch and SERDES nodes Geert Uytterhoeven

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