* [RFC PATCH v2 00/30] Device Tree support for SH7751 based board
@ 2023-09-13 9:23 Yoshinori Sato
2023-09-13 9:23 ` [RFC PATCH v2 01/30] arch/sh: head_32.S passing FDT address to initialize function Yoshinori Sato
` (29 more replies)
0 siblings, 30 replies; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
This is an updated version of something I wrote about 7 years ago.
Minimum support for R2D-plus and LANDISK.
I think R2D-1 will work if you add AX88796 to dts.
And board-specific functions and SCI's SPI functions are not supported.
v2 changes.
- Rebasing v6,6-rc1
- re-write irqchip driver.
- Add binding documents.
- Cleanup review comment.
Yoshinori Sato (30):
arch/sh: head_32.S passing FDT address to initialize function.
arch/sh: boards/Kconfig unified OF supported targets.
arch/sh: Disable SH specific drivers in OF enabled.
include: sh_intc.h Add stub function "intc_finalize".
arch/sh: setup.c update DeviceTree support.
drivers/pci: SH7751 PCI Host bridge header.
drivers/pci: SH7751 PCI Host bridge controller driver.
drivers/pci: Add SH7751 Host bridge controller
Documentation/devicetree: Add renesas,sh7751-pci binding document.
drivers/clk: SH7750 / SH7751 CPG Driver
drivers/clk: SuperH generai clock divider helper
drivers/clk: Add SH7750 CPG drivers entry.
Documentation/devicetree: Add renesas,sh7751-cpg binding document.
drivers/irqchip: Add SH7751 Internal INTC drivers.
Documentation/devicetree: Add renesas,sh7751-intc binding document.
drivers/irqchip: SH7751 IRL external encoder with enable gate.
Documentation/devicetree: Add renesas,sh7751-irl-ext binding document.
drivers/clocksource: sh_tmu clocks property support.
drivers/tty: sh-sci fix SH4 OF support.
drivers/mfd: sm501 add some properties.
Documentation/devicetree: sm501fb add properies.
arch/sh: Add dtbs target support.
arch/sh: Add SH7751 SoC Internal periphreal devicetree.
include/dt-bindings: Add SH7750 CPG header.
include/dt-bindings: Add sh_intc IRQ - EVT conversion helper
arch/sh: RTS7751R2D Plus DeviceTree.
arch/sh: LANDISK DeviceTree.
arch/sh: USL-5P DeviceTree.
arch/sh: RTS7751R2D Plus OF defconfig
arch/sh: LANDISK OF defconfig
.../bindings/clock/renesas,sh7750-cpg.yaml | 58 +++
.../devicetree/bindings/display/sm501fb.txt | 11 +
.../renesas,sh7751-intc.yaml | 45 +++
.../renesas,sh7751-irl-ext.yaml | 77 ++++
.../bindings/pci/renesas,sh7751-pci.yaml | 57 +++
arch/sh/Kconfig | 6 +-
arch/sh/boards/Kconfig | 26 +-
arch/sh/boards/of-generic.c | 23 +-
arch/sh/boot/compressed/head_32.S | 5 +-
arch/sh/boot/dts/Makefile | 5 +
arch/sh/boot/dts/include/dt-bindings | 1 +
arch/sh/boot/dts/landisk.dts | 103 ++++++
arch/sh/boot/dts/rts7751r2dplus.dts | 124 +++++++
arch/sh/boot/dts/sh7751.dtsi | 76 ++++
arch/sh/boot/dts/usl-5p.dts | 106 ++++++
arch/sh/configs/landisk-of_defconfig | 110 ++++++
arch/sh/configs/rts7751r2dplus-of_defconfig | 93 +++++
arch/sh/drivers/Makefile | 2 +
arch/sh/include/asm/io.h | 14 +-
arch/sh/include/asm/pci.h | 4 +
arch/sh/kernel/cpu/Makefile | 9 +-
arch/sh/kernel/cpu/sh4/Makefile | 2 +
arch/sh/kernel/setup.c | 34 +-
arch/sh/kernel/time.c | 7 +-
drivers/clk/renesas/Kconfig | 15 +-
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/clk-sh7750.c | 236 ++++++++++++
drivers/clk/renesas/clk-shdiv.c | 346 ++++++++++++++++++
drivers/clk/renesas/clk-shdiv.h | 18 +
drivers/clocksource/sh_tmu.c | 3 +
drivers/irqchip/Kconfig | 16 +
drivers/irqchip/Makefile | 3 +
drivers/irqchip/irq-renesas-sh7751.c | 232 ++++++++++++
drivers/irqchip/irq-renesas-sh7751irl.c | 183 +++++++++
drivers/mfd/sm501.c | 113 ++++++
drivers/pci/controller/Kconfig | 9 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pci-sh7751.c | 338 +++++++++++++++++
drivers/pci/controller/pci-sh7751.h | 270 ++++++++++++++
drivers/sh/Makefile | 2 +
drivers/tty/serial/sh-sci.c | 8 +-
include/dt-bindings/clock/sh7750.h | 13 +
.../interrupt-controller/sh_intc.h | 7 +
include/linux/sh_intc.h | 7 +-
44 files changed, 2772 insertions(+), 47 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
create mode 100644 Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml
create mode 120000 arch/sh/boot/dts/include/dt-bindings
create mode 100644 arch/sh/boot/dts/landisk.dts
create mode 100644 arch/sh/boot/dts/rts7751r2dplus.dts
create mode 100644 arch/sh/boot/dts/sh7751.dtsi
create mode 100644 arch/sh/boot/dts/usl-5p.dts
create mode 100644 arch/sh/configs/landisk-of_defconfig
create mode 100644 arch/sh/configs/rts7751r2dplus-of_defconfig
create mode 100644 drivers/clk/renesas/clk-sh7750.c
create mode 100644 drivers/clk/renesas/clk-shdiv.c
create mode 100644 drivers/clk/renesas/clk-shdiv.h
create mode 100644 drivers/irqchip/irq-renesas-sh7751.c
create mode 100644 drivers/irqchip/irq-renesas-sh7751irl.c
create mode 100644 drivers/pci/controller/pci-sh7751.c
create mode 100644 drivers/pci/controller/pci-sh7751.h
create mode 100644 include/dt-bindings/clock/sh7750.h
create mode 100644 include/dt-bindings/interrupt-controller/sh_intc.h
--
2.39.2
^ permalink raw reply [flat|nested] 83+ messages in thread
* [RFC PATCH v2 01/30] arch/sh: head_32.S passing FDT address to initialize function.
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-18 15:16 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 02/30] arch/sh: boards/Kconfig unified OF supported targets Yoshinori Sato
` (28 subsequent siblings)
29 siblings, 1 reply; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
R4 is caller saved in SH ABI.
Save it so it doesn't get corrupted until it's needed for initialization.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/boot/compressed/head_32.S | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/sh/boot/compressed/head_32.S b/arch/sh/boot/compressed/head_32.S
index 7bb168133dbb..c5227ef636c3 100644
--- a/arch/sh/boot/compressed/head_32.S
+++ b/arch/sh/boot/compressed/head_32.S
@@ -15,7 +15,8 @@ startup:
/* Load initial status register */
mov.l init_sr, r1
ldc r1, sr
-
+ /* Save FDT address */
+ mov r4, r13
/* Move myself to proper location if necessary */
mova 1f, r0
mov.l 1f, r2
@@ -84,7 +85,7 @@ l1:
/* Jump to the start of the decompressed kernel */
mov.l kernel_start_addr, r0
jmp @r0
- nop
+ mov r13,r4
.align 2
bss_start_addr:
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 02/30] arch/sh: boards/Kconfig unified OF supported targets.
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
2023-09-13 9:23 ` [RFC PATCH v2 01/30] arch/sh: head_32.S passing FDT address to initialize function Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-18 15:05 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 03/30] arch/sh: Disable SH specific drivers in OF enabled Yoshinori Sato
` (27 subsequent siblings)
29 siblings, 1 reply; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
Targets that support OF should be treated as one board.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/boards/Kconfig | 26 ++++++++++++++++----------
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig
index fafe15d3ba1d..523c8aac2650 100644
--- a/arch/sh/boards/Kconfig
+++ b/arch/sh/boards/Kconfig
@@ -19,16 +19,10 @@ config SH_DEVICE_TREE
select TIMER_OF
select COMMON_CLK
select GENERIC_CALIBRATE_DELAY
-
-config SH_JCORE_SOC
- bool "J-Core SoC"
- select SH_DEVICE_TREE
- select CLKSRC_JCORE_PIT
- select JCORE_AIC
- depends on CPU_J2
- help
- Select this option to include drivers core components of the
- J-Core SoC, including interrupt controllers and timers.
+ select GENERIC_IOMAP
+ select GENERIC_IRQ_CHIP
+ select SYS_SUPPORTS_PCI
+ select GENERIC_PCI_IOMAP if PCI
config SH_SOLUTION_ENGINE
bool "SolutionEngine"
@@ -300,6 +294,7 @@ config SH_LANDISK
bool "LANDISK"
depends on CPU_SUBTYPE_SH7751R
select HAVE_PCI
+ select SYS_SUPPORTS_PCI
help
I-O DATA DEVICE, INC. "LANDISK Series" support.
@@ -376,6 +371,17 @@ config SH_APSH4AD0A
help
Select AP-SH4AD-0A if configuring for an ALPHAPROJECT AP-SH4AD-0A.
+config SH_OF_BOARD
+ bool "General Open Firmware boards"
+ select SH_DEVICE_TREE
+ select CLKSRC_JCORE_PIT if CPU_J2
+ select JCORE_AIC if CPU_J2
+ select HAVE_PCI if CPU_SUBTYPE_SH7751R
+ help
+ This board means general OF supported targets.
+ Currentry supported.
+ J-Core, RTS7751R2DPlus and LANDISK.
+
source "arch/sh/boards/mach-r2d/Kconfig"
source "arch/sh/boards/mach-highlander/Kconfig"
source "arch/sh/boards/mach-sdk7780/Kconfig"
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 03/30] arch/sh: Disable SH specific drivers in OF enabled.
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
2023-09-13 9:23 ` [RFC PATCH v2 01/30] arch/sh: head_32.S passing FDT address to initialize function Yoshinori Sato
2023-09-13 9:23 ` [RFC PATCH v2 02/30] arch/sh: boards/Kconfig unified OF supported targets Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-18 15:14 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 04/30] include: sh_intc.h Add stub function "intc_finalize" Yoshinori Sato
` (26 subsequent siblings)
29 siblings, 1 reply; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
OF uses a common framework.
Avoid using clk, irq and PCI SH-specific drivers.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/Kconfig | 6 ++++--
arch/sh/boards/of-generic.c | 23 +++++++++--------------
arch/sh/drivers/Makefile | 2 ++
arch/sh/include/asm/io.h | 14 ++++++++++++--
arch/sh/include/asm/pci.h | 4 ++++
arch/sh/kernel/cpu/Makefile | 9 +++++++--
arch/sh/kernel/cpu/sh4/Makefile | 2 ++
arch/sh/kernel/time.c | 7 ++++++-
drivers/sh/Makefile | 2 ++
9 files changed, 48 insertions(+), 21 deletions(-)
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 33530b044953..451595ef6f4f 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -65,10 +65,10 @@ config SUPERH
select MODULES_USE_ELF_RELA
select NEED_SG_DMA_LENGTH
select NO_DMA if !MMU && !DMA_COHERENT
- select NO_GENERIC_PCI_IOPORT_MAP if PCI
+ select NO_GENERIC_PCI_IOPORT_MAP if !SH_DEVICE_TREE
select OLD_SIGACTION
select OLD_SIGSUSPEND
- select PCI_DOMAINS if PCI
+ select PCI_DOMAINS if PCI && !SH_DEVICE_TREE
select PERF_EVENTS
select PERF_USE_VMALLOC
select RTC_LIB
@@ -379,6 +379,7 @@ config CPU_SUBTYPE_SH7751
config CPU_SUBTYPE_SH7751R
bool "Support SH7751R processor"
select CPU_SH4
+ select PCI_SH7751 if SH_DEVICE_TREE
config CPU_SUBTYPE_SH7760
bool "Support SH7760 processor"
@@ -527,6 +528,7 @@ config SH_PCLK_FREQ
config SH_CLK_CPG
def_bool y
+ depends on !COMMON_CLK
config SH_CLK_CPG_LEGACY
depends on SH_CLK_CPG
diff --git a/arch/sh/boards/of-generic.c b/arch/sh/boards/of-generic.c
index f7f3e618e85b..51ad68c280bb 100644
--- a/arch/sh/boards/of-generic.c
+++ b/arch/sh/boards/of-generic.c
@@ -8,6 +8,7 @@
#include <linux/of.h>
#include <linux/of_clk.h>
#include <linux/of_fdt.h>
+#include <linux/of_platform.h>
#include <linux/clocksource.h>
#include <linux/irqchip.h>
#include <asm/machvec.h>
@@ -107,7 +108,7 @@ static int noopi(void)
return 0;
}
-static void __init sh_of_mem_reserve(void)
+static void __init sh_of_mem_init(void)
{
early_init_fdt_reserve_self();
early_init_fdt_scan_reserved_mem();
@@ -116,6 +117,8 @@ static void __init sh_of_mem_reserve(void)
static void __init sh_of_setup(char **cmdline_p)
{
struct device_node *root;
+ struct device_node *cpu;
+ int freq;
sh_mv.mv_name = "Unknown SH model";
root = of_find_node_by_path("/");
@@ -125,6 +128,9 @@ static void __init sh_of_setup(char **cmdline_p)
}
sh_of_smp_probe();
+ cpu = of_find_node_by_name(NULL, "cpu");
+ if (!of_property_read_u32(cpu, "clock-frequency", &freq))
+ preset_lpj = freq / 500;
}
static int sh_of_irq_demux(int irq)
@@ -140,25 +146,14 @@ static void __init sh_of_init_irq(void)
irqchip_init();
}
-static int __init sh_of_clk_init(void)
-{
-#ifdef CONFIG_COMMON_CLK
- /* Disabled pending move to COMMON_CLK framework. */
- pr_info("SH generic board support: scanning for clk providers\n");
- of_clk_init(NULL);
-#endif
- return 0;
-}
-
static struct sh_machine_vector __initmv sh_of_generic_mv = {
.mv_setup = sh_of_setup,
.mv_name = "devicetree", /* replaced by DT root's model */
.mv_irq_demux = sh_of_irq_demux,
.mv_init_irq = sh_of_init_irq,
- .mv_clk_init = sh_of_clk_init,
+ .mv_clk_init = noopi,
.mv_mode_pins = noopi,
- .mv_mem_init = noop,
- .mv_mem_reserve = sh_of_mem_reserve,
+ .mv_mem_init = sh_of_mem_init,
};
struct sh_clk_ops;
diff --git a/arch/sh/drivers/Makefile b/arch/sh/drivers/Makefile
index 56b0acace6e7..eacbcefb26b2 100644
--- a/arch/sh/drivers/Makefile
+++ b/arch/sh/drivers/Makefile
@@ -5,7 +5,9 @@
obj-y += dma/ platform_early.o
+ifndef CONFIG_SH_DEVICE_TREE
obj-$(CONFIG_PCI) += pci/
+endif
obj-$(CONFIG_SUPERHYWAY) += superhyway/
obj-$(CONFIG_PUSH_SWITCH) += push-switch.o
obj-$(CONFIG_HEARTBEAT) += heartbeat.o
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index f2f38e9d489a..3519eb6a9715 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -311,10 +311,20 @@ unsigned long long poke_real_address_q(unsigned long long addr,
#define xlate_dev_mem_ptr(p) __va(p)
#define unxlate_dev_mem_ptr(p, v) do { } while (0)
-#include <asm-generic/io.h>
-
#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
int valid_phys_addr_range(phys_addr_t addr, size_t size);
int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
+
+#ifdef __KERNEL__
+#define PCI_IOBASE 0xfe240000UL
+
+#define HAVE_ARCH_PIO_SIZE
+#define PIO_OFFSET PCI_IOBASE
+#define PIO_MASK 0x3ffffUL
+#define PIO_RESERVED 0x40000UL
+#endif /* __KERNEL__ */
+
+#include <asm-generic/io.h>
+
#endif /* __ASM_SH_IO_H */
diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h
index 54c30126ea17..92b3bd604319 100644
--- a/arch/sh/include/asm/pci.h
+++ b/arch/sh/include/asm/pci.h
@@ -2,6 +2,7 @@
#ifndef __ASM_SH_PCI_H
#define __ASM_SH_PCI_H
+#ifndef CONFIG_SH_DEVICE_TREE
/* Can be used to override the logic in pci_scan_bus for skipping
already-configured bus numbers - to be used for buggy BIOSes
or architectures with incomplete PCI setup by the loader */
@@ -88,4 +89,7 @@ static inline int pci_proc_domain(struct pci_bus *bus)
return hose->need_domain_info;
}
+#else /* CONFIG_SH_DEVICE_TREE */
+#include <asm-generic/pci.h>
+#endif
#endif /* __ASM_SH_PCI_H */
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index 46118236bf04..e00ebf134985 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -16,6 +16,11 @@ obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/
# Common interfaces.
obj-$(CONFIG_SH_ADC) += adc.o
+ifndef CONFIG_COMMON_CLK
+obj-y += clock.o
obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o
-
-obj-y += irq/ init.o clock.o fpu.o pfc.o proc.o
+endif
+ifndef CONFIG_GENERIC_IRQ_CHIP
+obj-y += irq/
+endif
+obj-y += init.o fpu.o pfc.o proc.o
diff --git a/arch/sh/kernel/cpu/sh4/Makefile b/arch/sh/kernel/cpu/sh4/Makefile
index 00c16331e07e..d8c3242c4a9f 100644
--- a/arch/sh/kernel/cpu/sh4/Makefile
+++ b/arch/sh/kernel/cpu/sh4/Makefile
@@ -15,6 +15,7 @@ perf-$(CONFIG_CPU_SUBTYPE_SH7750) := perf_event.o
perf-$(CONFIG_CPU_SUBTYPE_SH7750S) := perf_event.o
perf-$(CONFIG_CPU_SUBTYPE_SH7091) := perf_event.o
+ifndef CONFIG_SH_DEVICE_TREE
# CPU subtype setup
obj-$(CONFIG_CPU_SUBTYPE_SH7750) += setup-sh7750.o
obj-$(CONFIG_CPU_SUBTYPE_SH7750R) += setup-sh7750.o
@@ -32,6 +33,7 @@ endif
# Additional clocks by subtype
clock-$(CONFIG_CPU_SUBTYPE_SH4_202) += clock-sh4-202.o
+endif # CONFIG_SH_DEVICE_TREE
obj-y += $(clock-y)
obj-$(CONFIG_PERF_EVENTS) += $(perf-y)
diff --git a/arch/sh/kernel/time.c b/arch/sh/kernel/time.c
index 821a09cbd605..5911d7e8dfdb 100644
--- a/arch/sh/kernel/time.c
+++ b/arch/sh/kernel/time.c
@@ -19,6 +19,7 @@
#include <asm/clock.h>
#include <asm/rtc.h>
#include <asm/platform_early.h>
+#include <linux/of_clk.h>
static void __init sh_late_time_init(void)
{
@@ -39,7 +40,11 @@ void __init time_init(void)
{
timer_probe();
+#ifndef CONFIG_SH_DEVICE_TREE
clk_init();
-
+#else
+ pr_info("SH generic board support: scanning for clk providers\n");
+ of_clk_init(NULL);
+#endif
late_time_init = sh_late_time_init;
}
diff --git a/drivers/sh/Makefile b/drivers/sh/Makefile
index c53262835e85..9a3e126704aa 100644
--- a/drivers/sh/Makefile
+++ b/drivers/sh/Makefile
@@ -2,7 +2,9 @@
#
# Makefile for the SuperH specific drivers.
#
+ifneq ($(CONFIG_SH_DEVICE_TREE),y)
obj-$(CONFIG_SH_INTC) += intc/
+endif
ifneq ($(CONFIG_COMMON_CLK),y)
obj-$(CONFIG_HAVE_CLK) += clk/
endif
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 04/30] include: sh_intc.h Add stub function "intc_finalize".
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (2 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 03/30] arch/sh: Disable SH specific drivers in OF enabled Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-18 15:16 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 05/30] arch/sh: setup.c update DeviceTree support Yoshinori Sato
` (25 subsequent siblings)
29 siblings, 1 reply; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
This function not use in OF.
avoid unneeded call.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
include/linux/sh_intc.h | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/include/linux/sh_intc.h b/include/linux/sh_intc.h
index 27ae79191bdc..994b5b05a0d7 100644
--- a/include/linux/sh_intc.h
+++ b/include/linux/sh_intc.h
@@ -139,8 +139,13 @@ struct intc_desc symbol __initdata = { \
int register_intc_controller(struct intc_desc *desc);
int intc_set_priority(unsigned int irq, unsigned int prio);
int intc_irq_lookup(const char *chipname, intc_enum enum_id);
+#ifndef CONFIG_SH_DEVICE_TREE
void intc_finalize(void);
-
+#else
+static inline void intc_finalize(void)
+{
+}
+#endif
#ifdef CONFIG_INTC_USERIMASK
int register_intc_userimask(unsigned long addr);
#else
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 05/30] arch/sh: setup.c update DeviceTree support.
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (3 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 04/30] include: sh_intc.h Add stub function "intc_finalize" Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-13 9:23 ` [RFC PATCH v2 06/30] drivers/pci: SH7751 PCI Host bridge header Yoshinori Sato
` (24 subsequent siblings)
29 siblings, 0 replies; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
- Get CPU clock frequency for DeviceTree.
- Clean up fdt initialization.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/kernel/setup.c | 34 +++++++++++++++++++++++++---------
1 file changed, 25 insertions(+), 9 deletions(-)
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index b3da2757faaf..95628ecc41c8 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -31,6 +31,7 @@
#include <linux/memblock.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
+#include <linux/libfdt.h>
#include <linux/uaccess.h>
#include <uapi/linux/mount.h>
#include <asm/io.h>
@@ -79,7 +80,9 @@ extern int root_mountflags;
#define RAMDISK_PROMPT_FLAG 0x8000
#define RAMDISK_LOAD_FLAG 0x4000
+#if !defined(CONFIG_OF) || defined(USE_BUILTIN_DTB)
static char __initdata command_line[COMMAND_LINE_SIZE] = { 0, };
+#endif
static struct resource code_resource = {
.name = "Kernel code",
@@ -104,6 +107,8 @@ unsigned long memory_limit = 0;
static struct resource mem_resources[MAX_NUMNODES];
+static void *dt_virt;
+
int l1i_cache_shape, l1d_cache_shape, l2_cache_shape;
static int __init early_parse_mem(char *p)
@@ -180,7 +185,12 @@ void __init check_for_initrd(void)
#ifndef CONFIG_GENERIC_CALIBRATE_DELAY
void calibrate_delay(void)
{
+#ifndef CONFIG_OF
struct clk *clk = clk_get(NULL, "cpu_clk");
+#else
+ struct device_node *cpu = of_find_node_by_name(NULL, "cpu");
+ struct clk *clk = of_clk_get_by_name(cpu, NULL);
+#endif
if (IS_ERR(clk))
panic("Need a sane CPU clock definition!");
@@ -249,7 +259,6 @@ void __init __weak plat_early_device_setup(void)
void __ref sh_fdt_init(phys_addr_t dt_phys)
{
static int done = 0;
- void *dt_virt;
/* Avoid calling an __init function on secondary cpus. */
if (done) return;
@@ -274,8 +283,18 @@ void __ref sh_fdt_init(phys_addr_t dt_phys)
void __init setup_arch(char **cmdline_p)
{
+#ifdef CONFIG_OF
+#ifdef CONFIG_USE_BUILTIN_DTB
+ unflatten_and_copy_device_tree();
+#else
+ memblock_reserve(__pa(dt_virt), fdt_totalsize(dt_virt));
+ unflatten_device_tree();
+#endif
+#endif
enable_mmu();
+
+#ifndef CONFIG_OF
ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
printk(KERN_NOTICE "Boot params:\n"
@@ -313,10 +332,15 @@ void __init setup_arch(char **cmdline_p)
strlcat(command_line, CONFIG_CMDLINE, sizeof(command_line));
#endif
#endif
+#endif
+#if !defined(CONFIG_OF) || defined(USE_BUILTIN_DTB)
/* Save unparsed command line copy for /proc/cmdline */
memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
*cmdline_p = command_line;
+#else
+ *cmdline_p = boot_command_line;
+#endif
parse_early_param();
@@ -327,14 +351,6 @@ void __init setup_arch(char **cmdline_p)
/* Let earlyprintk output early console messages */
sh_early_platform_driver_probe("earlyprintk", 1, 1);
-#ifdef CONFIG_OF_EARLY_FLATTREE
-#ifdef CONFIG_USE_BUILTIN_DTB
- unflatten_and_copy_device_tree();
-#else
- unflatten_device_tree();
-#endif
-#endif
-
paging_init();
/* Perform the machine specific initialisation */
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 06/30] drivers/pci: SH7751 PCI Host bridge header.
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (4 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 05/30] arch/sh: setup.c update DeviceTree support Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-18 19:16 ` Bjorn Helgaas
2023-09-13 9:23 ` [RFC PATCH v2 07/30] drivers/pci: SH7751 PCI Host bridge controller driver Yoshinori Sato
` (23 subsequent siblings)
29 siblings, 1 reply; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, linux-pci, glaubitz
This file move from SH specific directory "arch/sh/drivers/pci/pci-sh7751.h"
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/pci/controller/pci-sh7751.h | 270 ++++++++++++++++++++++++++++
1 file changed, 270 insertions(+)
create mode 100644 drivers/pci/controller/pci-sh7751.h
diff --git a/drivers/pci/controller/pci-sh7751.h b/drivers/pci/controller/pci-sh7751.h
new file mode 100644
index 000000000000..9b7de8243e92
--- /dev/null
+++ b/drivers/pci/controller/pci-sh7751.h
@@ -0,0 +1,270 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Low-Level PCI Support for SH7751 targets
+ *
+ * Dustin McIntire (dustin@sensoria.com) (c) 2001
+ * Paul Mundt (lethal@linux-sh.org) (c) 2003
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License. See linux/COPYING for more information.
+ *
+ */
+
+#ifndef _PCI_SH7751_H_
+#define _PCI_SH7751_H_
+
+#define SH4_PCICR 0x100 /* PCI Control Register */
+ #define SH4_PCICR_PREFIX 0xA5000000 /* CR prefix for write */
+ #define SH4_PCICR_FTO 0x00000400 /* TRDY/IRDY Enable */
+ #define SH4_PCICR_TRSB 0x00000200 /* Target Read Single */
+ #define SH4_PCICR_BSWP 0x00000100 /* Target Byte Swap */
+ #define SH4_PCICR_PLUP 0x00000080 /* Enable PCI Pullup */
+ #define SH4_PCICR_ARBM 0x00000040 /* PCI Arbitration Mode */
+ #define SH4_PCICR_MD 0x00000030 /* MD9 and MD10 status */
+ #define SH4_PCICR_SERR 0x00000008 /* SERR output assert */
+ #define SH4_PCICR_INTA 0x00000004 /* INTA output assert */
+ #define SH4_PCICR_PRST 0x00000002 /* PCI Reset Assert */
+ #define SH4_PCICR_CFIN 0x00000001 /* Central Fun. Init Done */
+#define SH4_PCILSR0 0x104 /* PCI Local Space Register0 */
+#define SH4_PCILSR1 0x108 /* PCI Local Space Register1 */
+#define SH4_PCILAR0 0x10C /* PCI Local Addr Register1 */
+#define SH4_PCILAR1 0x110 /* PCI Local Addr Register1 */
+#define SH4_PCIINT 0x114 /* PCI Interrupt Register */
+ #define SH4_PCIINT_MLCK 0x00008000 /* Master Lock Error */
+ #define SH4_PCIINT_TABT 0x00004000 /* Target Abort Error */
+ #define SH4_PCIINT_TRET 0x00000200 /* Target Retry Error */
+ #define SH4_PCIINT_MFDE 0x00000100 /* Master Func. Disable Error */
+ #define SH4_PCIINT_PRTY 0x00000080 /* Address Parity Error */
+ #define SH4_PCIINT_SERR 0x00000040 /* SERR Detection Error */
+ #define SH4_PCIINT_TWDP 0x00000020 /* Tgt. Write Parity Error */
+ #define SH4_PCIINT_TRDP 0x00000010 /* Tgt. Read Parity Err Det. */
+ #define SH4_PCIINT_MTABT 0x00000008 /* Master-Tgt. Abort Error */
+ #define SH4_PCIINT_MMABT 0x00000004 /* Master-Master Abort Error */
+ #define SH4_PCIINT_MWPD 0x00000002 /* Master Write PERR Detect */
+ #define SH4_PCIINT_MRPD 0x00000001 /* Master Read PERR Detect */
+#define SH4_PCIINTM 0x118 /* PCI Interrupt Mask */
+ #define SH4_PCIINTM_TTADIM BIT(14) /* Target-target abort interrupt */
+ #define SH4_PCIINTM_TMTOIM BIT(9) /* Target retry timeout */
+ #define SH4_PCIINTM_MDEIM BIT(8) /* Master function disable error */
+ #define SH4_PCIINTM_APEDIM BIT(7) /* Address parity error detection */
+ #define SH4_PCIINTM_SDIM BIT(6) /* SERR detection */
+ #define SH4_PCIINTM_DPEITWM BIT(5) /* Data parity error for target write */
+ #define SH4_PCIINTM_PEDITRM BIT(4) /* PERR detection for target read */
+ #define SH4_PCIINTM_TADIMM BIT(3) /* Target abort for master */
+ #define SH4_PCIINTM_MADIMM BIT(2) /* Master abort for master */
+ #define SH4_PCIINTM_MWPDIM BIT(1) /* Master write data parity error */
+ #define SH4_PCIINTM_MRDPEIM BIT(0) /* Master read data parity error */
+#define SH4_PCIALR 0x11C /* Error Address Register */
+#define SH4_PCICLR 0x120 /* Error Command/Data */
+ #define SH4_PCICLR_MPIO 0x80000000
+ #define SH4_PCICLR_MDMA0 0x40000000 /* DMA0 Transfer Error */
+ #define SH4_PCICLR_MDMA1 0x20000000 /* DMA1 Transfer Error */
+ #define SH4_PCICLR_MDMA2 0x10000000 /* DMA2 Transfer Error */
+ #define SH4_PCICLR_MDMA3 0x08000000 /* DMA3 Transfer Error */
+ #define SH4_PCICLR_TGT 0x04000000 /* Target Transfer Error */
+ #define SH4_PCICLR_CMDL 0x0000000F /* PCI Command at Error */
+#define SH4_PCIAINT 0x130 /* Arbiter Interrupt Register */
+ #define SH4_PCIAINT_MBKN 0x00002000 /* Master Broken Interrupt */
+ #define SH4_PCIAINT_TBTO 0x00001000 /* Target Bus Time Out */
+ #define SH4_PCIAINT_MBTO 0x00000800 /* Master Bus Time Out */
+ #define SH4_PCIAINT_TABT 0x00000008 /* Target Abort */
+ #define SH4_PCIAINT_MABT 0x00000004 /* Master Abort */
+ #define SH4_PCIAINT_RDPE 0x00000002 /* Read Data Parity Error */
+ #define SH4_PCIAINT_WDPE 0x00000001 /* Write Data Parity Error */
+#define SH4_PCIAINTM 0x134 /* Arbiter Int. Mask Register */
+#define SH4_PCIBMLR 0x138 /* Error Bus Master Register */
+ #define SH4_PCIBMLR_REQ4 0x00000010 /* REQ4 bus master at error */
+ #define SH4_PCIBMLR_REQ3 0x00000008 /* REQ3 bus master at error */
+ #define SH4_PCIBMLR_REQ2 0x00000004 /* REQ2 bus master at error */
+ #define SH4_PCIBMLR_REQ1 0x00000002 /* REQ1 bus master at error */
+ #define SH4_PCIBMLR_REQ0 0x00000001 /* REQ0 bus master at error */
+#define SH4_PCIDMABT 0x140 /* DMA Transfer Arb. Register */
+ #define SH4_PCIDMABT_RRBN 0x00000001 /* DMA Arbitor Round-Robin */
+#define SH4_PCIDPA0 0x180 /* DMA0 Transfer Addr. */
+#define SH4_PCIDLA0 0x184 /* DMA0 Local Addr. */
+#define SH4_PCIDTC0 0x188 /* DMA0 Transfer Cnt. */
+#define SH4_PCIDCR0 0x18C /* DMA0 Control Register */
+ #define SH4_PCIDCR_ALGN 0x00000600 /* DMA Alignment Mode */
+ #define SH4_PCIDCR_MAST 0x00000100 /* DMA Termination Type */
+ #define SH4_PCIDCR_INTM 0x00000080 /* DMA Interrupt Done Mask*/
+ #define SH4_PCIDCR_INTS 0x00000040 /* DMA Interrupt Done Status */
+ #define SH4_PCIDCR_LHLD 0x00000020 /* Local Address Control */
+ #define SH4_PCIDCR_PHLD 0x00000010 /* PCI Address Control*/
+ #define SH4_PCIDCR_IOSEL 0x00000008 /* PCI Address Space Type */
+ #define SH4_PCIDCR_DIR 0x00000004 /* DMA Transfer Direction */
+ #define SH4_PCIDCR_STOP 0x00000002 /* Force DMA Stop */
+ #define SH4_PCIDCR_STRT 0x00000001 /* DMA Start */
+#define SH4_PCIDPA1 0x190 /* DMA1 Transfer Addr. */
+#define SH4_PCIDLA1 0x194 /* DMA1 Local Addr. */
+#define SH4_PCIDTC1 0x198 /* DMA1 Transfer Cnt. */
+#define SH4_PCIDCR1 0x19C /* DMA1 Control Register */
+#define SH4_PCIDPA2 0x1A0 /* DMA2 Transfer Addr. */
+#define SH4_PCIDLA2 0x1A4 /* DMA2 Local Addr. */
+#define SH4_PCIDTC2 0x1A8 /* DMA2 Transfer Cnt. */
+#define SH4_PCIDCR2 0x1AC /* DMA2 Control Register */
+#define SH4_PCIDPA3 0x1B0 /* DMA3 Transfer Addr. */
+#define SH4_PCIDLA3 0x1B4 /* DMA3 Local Addr. */
+#define SH4_PCIDTC3 0x1B8 /* DMA3 Transfer Cnt. */
+#define SH4_PCIDCR3 0x1BC /* DMA3 Control Register */
+#define SH4_PCIPAR 0x1C0 /* PIO Address Register */
+ #define SH4_PCIPAR_CFGEN 0x80000000 /* Configuration Enable */
+ #define SH4_PCIPAR_BUSNO 0x00FF0000 /* Config. Bus Number */
+ #define SH4_PCIPAR_DEVNO 0x0000FF00 /* Config. Device Number */
+ #define SH4_PCIPAR_REGAD 0x000000FC /* Register Address Number */
+#define SH4_PCIMBR 0x1C4 /* Memory Base Address */
+ #define SH4_PCIMBR_MASK 0xFF000000 /* Memory Space Mask */
+ #define SH4_PCIMBR_LOCK 0x00000001 /* Lock Memory Space */
+#define SH4_PCIIOBR 0x1C8 /* I/O Base Address Register */
+ #define SH4_PCIIOBR_MASK 0xFFFC0000 /* IO Space Mask */
+ #define SH4_PCIIOBR_LOCK 0x00000001 /* Lock IO Space */
+#define SH4_PCIPINT 0x1CC /* Power Mgmnt Int. Register */
+ #define SH4_PCIPINT_D3 0x00000002 /* D3 Pwr Mgmt. Interrupt */
+ #define SH4_PCIPINT_D0 0x00000001 /* D0 Pwr Mgmt. Interrupt */
+#define SH4_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */
+#define SH4_PCICLKR 0x1D4 /* Clock Ctrl. Register */
+ #define SH4_PCICLKR_PCSTP 0x00000002 /* PCI Clock Stop */
+ #define SH4_PCICLKR_BCSTP 0x00000001 /* BCLK Clock Stop */
+/* For definitions of BCR, MCR see ... */
+#define SH4_PCIBCR1 0x1E0 /* Memory BCR1 Register */
+ #define SH4_PCIMBR0 SH4_PCIBCR1
+#define SH4_PCIBCR2 0x1E4 /* Memory BCR2 Register */
+ #define SH4_PCIMBMR0 SH4_PCIBCR2
+#define SH4_PCIWCR1 0x1E8 /* Wait Control 1 Register */
+#define SH4_PCIWCR2 0x1EC /* Wait Control 2 Register */
+#define SH4_PCIWCR3 0x1F0 /* Wait Control 3 Register */
+ #define SH4_PCIMBR2 SH4_PCIWCR3
+#define SH4_PCIMCR 0x1F4 /* Memory Control Register */
+#define SH4_PCIBCR3 0x1f8 /* Memory BCR3 Register */
+#define SH4_PCIPCTR 0x200 /* Port Control Register */
+ #define SH4_PCIPCTR_P2EN 0x000400000 /* Port 2 Enable */
+ #define SH4_PCIPCTR_P1EN 0x000200000 /* Port 1 Enable */
+ #define SH4_PCIPCTR_P0EN 0x000100000 /* Port 0 Enable */
+ #define SH4_PCIPCTR_P2UP 0x000000020 /* Port2 Pull Up Enable */
+ #define SH4_PCIPCTR_P2IO 0x000000010 /* Port2 Output Enable */
+ #define SH4_PCIPCTR_P1UP 0x000000008 /* Port1 Pull Up Enable */
+ #define SH4_PCIPCTR_P1IO 0x000000004 /* Port1 Output Enable */
+ #define SH4_PCIPCTR_P0UP 0x000000002 /* Port0 Pull Up Enable */
+ #define SH4_PCIPCTR_P0IO 0x000000001 /* Port0 Output Enable */
+#define SH4_PCIPDTR 0x204 /* Port Data Register */
+ #define SH4_PCIPDTR_PB5 0x000000020 /* Port 5 Enable */
+ #define SH4_PCIPDTR_PB4 0x000000010 /* Port 4 Enable */
+ #define SH4_PCIPDTR_PB3 0x000000008 /* Port 3 Enable */
+ #define SH4_PCIPDTR_PB2 0x000000004 /* Port 2 Enable */
+ #define SH4_PCIPDTR_PB1 0x000000002 /* Port 1 Enable */
+ #define SH4_PCIPDTR_PB0 0x000000001 /* Port 0 Enable */
+#define SH4_PCIPDR 0x220 /* Port IO Data Register */
+
+/* Platform Specific Values */
+#define SH7751_VENDOR_ID 0x1054
+#define SH7751_DEVICE_ID 0x3505
+#define SH7751R_DEVICE_ID 0x350e
+
+/* SH7751 Specific Values */
+#define SH7751_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
+#define SH7751_PCI_CONFIG_SIZE 0x1000000 /* Config space size */
+#define SH7751_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
+#define SH7751_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
+#define SH7751_PCI_IO_BASE 0xFE240000 /* IO space base address */
+#define SH7751_PCI_IO_SIZE 0x40000 /* Size of IO window */
+
+#define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */
+
+#define SH7751_PCICONF0 0x0 /* PCI Config Reg 0 */
+ #define SH7751_PCICONF0_DEVID 0xFFFF0000 /* Device ID */
+ #define SH7751_PCICONF0_VNDID 0x0000FFFF /* Vendor ID */
+#define SH7751_PCICONF1 0x4 /* PCI Config Reg 1 */
+ #define SH7751_PCICONF1_DPE 0x80000000 /* Data Parity Error */
+ #define SH7751_PCICONF1_SSE 0x40000000 /* System Error Status */
+ #define SH7751_PCICONF1_RMA 0x20000000 /* Master Abort */
+ #define SH7751_PCICONF1_RTA 0x10000000 /* Target Abort Rx Status */
+ #define SH7751_PCICONF1_STA 0x08000000 /* Target Abort Exec Status */
+ #define SH7751_PCICONF1_DEV 0x06000000 /* Timing Status */
+ #define SH7751_PCICONF1_DPD 0x01000000 /* Data Parity Status */
+ #define SH7751_PCICONF1_FBBC 0x00800000 /* Back 2 Back Status */
+ #define SH7751_PCICONF1_UDF 0x00400000 /* User Defined Status */
+ #define SH7751_PCICONF1_66M 0x00200000 /* 66Mhz Operation Status */
+ #define SH7751_PCICONF1_PM 0x00100000 /* Power Management Status */
+ #define SH7751_PCICONF1_PBBE 0x00000200 /* Back 2 Back Control */
+ #define SH7751_PCICONF1_SER 0x00000100 /* SERR Output Control */
+ #define SH7751_PCICONF1_WCC 0x00000080 /* Wait Cycle Control */
+ #define SH7751_PCICONF1_PER 0x00000040 /* Parity Error Response */
+ #define SH7751_PCICONF1_VPS 0x00000020 /* VGA Pallet Snoop */
+ #define SH7751_PCICONF1_MWIE 0x00000010 /* Memory Write+Invalidate */
+ #define SH7751_PCICONF1_SPC 0x00000008 /* Special Cycle Control */
+ #define SH7751_PCICONF1_BUM 0x00000004 /* Bus Master Control */
+ #define SH7751_PCICONF1_MES 0x00000002 /* Memory Space Control */
+ #define SH7751_PCICONF1_IOS 0x00000001 /* I/O Space Control */
+#define SH7751_PCICONF2 0x8 /* PCI Config Reg 2 */
+ #define SH7751_PCICONF2_BCC 0xFF000000 /* Base Class Code */
+ #define SH7751_PCICONF2_SCC 0x00FF0000 /* Sub-Class Code */
+ #define SH7751_PCICONF2_RLPI 0x0000FF00 /* Programming Interface */
+ #define SH7751_PCICONF2_REV 0x000000FF /* Revision ID */
+#define SH7751_PCICONF3 0xC /* PCI Config Reg 3 */
+ #define SH7751_PCICONF3_BIST7 0x80000000 /* Bist Supported */
+ #define SH7751_PCICONF3_BIST6 0x40000000 /* Bist Executing */
+ #define SH7751_PCICONF3_BIST3_0 0x0F000000 /* Bist Passed */
+ #define SH7751_PCICONF3_HD7 0x00800000 /* Single Function device */
+ #define SH7751_PCICONF3_HD6_0 0x007F0000 /* Configuration Layout */
+ #define SH7751_PCICONF3_LAT 0x0000FF00 /* Latency Timer */
+ #define SH7751_PCICONF3_CLS 0x000000FF /* Cache Line Size */
+#define SH7751_PCICONF4 0x10 /* PCI Config Reg 4 */
+ #define SH7751_PCICONF4_BASE 0xFFFFFFFC /* I/O Space Base Addr */
+ #define SH7751_PCICONF4_ASI 0x00000001 /* Address Space Type */
+#define SH7751_PCICONF5 0x14 /* PCI Config Reg 5 */
+ #define SH7751_PCICONF5_BASE 0xFFFFFFF0 /* Mem Space Base Addr */
+ #define SH7751_PCICONF5_LAP 0x00000008 /* Prefetch Enabled */
+ #define SH7751_PCICONF5_LAT 0x00000006 /* Local Memory type */
+ #define SH7751_PCICONF5_ASI 0x00000001 /* Address Space Type */
+#define SH7751_PCICONF6 0x18 /* PCI Config Reg 6 */
+ #define SH7751_PCICONF6_BASE 0xFFFFFFF0 /* Mem Space Base Addr */
+ #define SH7751_PCICONF6_LAP 0x00000008 /* Prefetch Enabled */
+ #define SH7751_PCICONF6_LAT 0x00000006 /* Local Memory type */
+ #define SH7751_PCICONF6_ASI 0x00000001 /* Address Space Type */
+/* PCICONF7 - PCICONF10 are undefined */
+#define SH7751_PCICONF11 0x2C /* PCI Config Reg 11 */
+ #define SH7751_PCICONF11_SSID 0xFFFF0000 /* Subsystem ID */
+ #define SH7751_PCICONF11_SVID 0x0000FFFF /* Subsystem Vendor ID */
+/* PCICONF12 is undefined */
+#define SH7751_PCICONF13 0x34 /* PCI Config Reg 13 */
+ #define SH7751_PCICONF13_CPTR 0x000000FF /* PM function pointer */
+/* PCICONF14 is undefined */
+#define SH7751_PCICONF15 0x3C /* PCI Config Reg 15 */
+ #define SH7751_PCICONF15_IPIN 0x000000FF /* Interrupt Pin */
+#define SH7751_PCICONF16 0x40 /* PCI Config Reg 16 */
+ #define SH7751_PCICONF16_PMES 0xF8000000 /* PME Support */
+ #define SH7751_PCICONF16_D2S 0x04000000 /* D2 Support */
+ #define SH7751_PCICONF16_D1S 0x02000000 /* D1 Support */
+ #define SH7751_PCICONF16_DSI 0x00200000 /* Bit Device Init. */
+ #define SH7751_PCICONF16_PMCK 0x00080000 /* Clock for PME req. */
+ #define SH7751_PCICONF16_VER 0x00070000 /* PM Version */
+ #define SH7751_PCICONF16_NIP 0x0000FF00 /* Next Item Pointer */
+ #define SH7751_PCICONF16_CID 0x000000FF /* Capability Identifier */
+#define SH7751_PCICONF17 0x44 /* PCI Config Reg 17 */
+ #define SH7751_PCICONF17_DATA 0xFF000000 /* Data field for PM */
+ #define SH7751_PCICONF17_PMES 0x00800000 /* PME Status */
+ #define SH7751_PCICONF17_DSCL 0x00600000 /* Data Scaling Value */
+ #define SH7751_PCICONF17_DSEL 0x001E0000 /* Data Select */
+ #define SH7751_PCICONF17_PMEN 0x00010000 /* PME Enable */
+ #define SH7751_PCICONF17_PWST 0x00000003 /* Power State */
+/* SH7751 Internal PCI Registers */
+
+/* Memory Control Registers */
+#define SH7751_BCR1 0x0000 /* Memory BCR1 Register */
+#define SH7751_BCR2 0x0004 /* Memory BCR2 Register */
+#define SH7751_BCR3 0x0050 /* Memory BCR3 Register */
+#define SH7751_WCR1 0x0008 /* Wait Control 1 Register */
+#define SH7751_WCR2 0x000C /* Wait Control 2 Register */
+#define SH7751_WCR3 0x0010 /* Wait Control 3 Register */
+#define SH7751_MCR 0x0014 /* Memory Control Register */
+
+/* General Memory Config Addresses */
+#define SH7751_CS0_BASE_ADDR 0x0
+#define SH7751_MEM_REGION_SIZE 0x04000000
+#define SH7751_CS1_BASE_ADDR (SH7751_CS0_BASE_ADDR + SH7751_MEM_REGION_SIZE)
+#define SH7751_CS2_BASE_ADDR (SH7751_CS1_BASE_ADDR + SH7751_MEM_REGION_SIZE)
+#define SH7751_CS3_BASE_ADDR (SH7751_CS2_BASE_ADDR + SH7751_MEM_REGION_SIZE)
+#define SH7751_CS4_BASE_ADDR (SH7751_CS3_BASE_ADDR + SH7751_MEM_REGION_SIZE)
+#define SH7751_CS5_BASE_ADDR (SH7751_CS4_BASE_ADDR + SH7751_MEM_REGION_SIZE)
+#define SH7751_CS6_BASE_ADDR (SH7751_CS5_BASE_ADDR + SH7751_MEM_REGION_SIZE)
+
+#endif /* _PCI_SH7751_H_ */
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 07/30] drivers/pci: SH7751 PCI Host bridge controller driver.
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (5 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 06/30] drivers/pci: SH7751 PCI Host bridge header Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-18 15:32 ` Geert Uytterhoeven
2023-09-18 19:30 ` Bjorn Helgaas
2023-09-13 9:23 ` [RFC PATCH v2 08/30] drivers/pci: Add SH7751 Host bridge controller Yoshinori Sato
` (22 subsequent siblings)
29 siblings, 2 replies; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz, linux-pci
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/pci/controller/pci-sh7751.c | 338 ++++++++++++++++++++++++++++
1 file changed, 338 insertions(+)
create mode 100644 drivers/pci/controller/pci-sh7751.c
diff --git a/drivers/pci/controller/pci-sh7751.c b/drivers/pci/controller/pci-sh7751.c
new file mode 100644
index 000000000000..f6718c6b403b
--- /dev/null
+++ b/drivers/pci/controller/pci-sh7751.c
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SH7751 PCI driver
+ * Copyright (C) 2023 Yoshinori Sato
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/pci-ecam.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <asm-generic/pci.h>
+#include "pci-sh7751.h"
+
+#define pcic_writel(val, reg) __raw_writel(val, pci_reg_base + (reg))
+#define pcic_readl(reg) __raw_readl(pci_reg_base + (reg))
+
+DEFINE_RAW_SPINLOCK(pci_config_lock);
+
+/*
+ * PCIC fixups
+ */
+
+#define PCIMCR_MRSET 0x40000000
+#define PCIMCR_RFSH 0x00000004
+
+/* board depend PCI bus fixups */
+static void __init julian_fixup(void __iomem *pci_reg_base, void __iomem *bcr)
+{
+ unsigned long bcr1, mcr;
+
+ bcr1 = __raw_readl(bcr + SH7751_BCR1);
+ bcr1 |= 0x00080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
+ pcic_writel(bcr1, SH4_PCIBCR1);
+
+ mcr = __raw_readl(bcr + SH7751_MCR);
+ mcr &= (~PCIMCR_MRSET) & (~PCIMCR_RFSH);
+ pcic_writel(mcr, SH4_PCIMCR);
+
+ pcic_writel(0x0c000000, SH7751_PCICONF5);
+ pcic_writel(0xd0000000, SH7751_PCICONF6);
+ pcic_writel(0x0c000000, SH4_PCILAR0);
+ pcic_writel(0x00000000, SH4_PCILAR1);
+}
+
+static void __init r2d_fixup(void __iomem *pci_reg_base, void __iomem *bcr)
+{
+ unsigned long bcr1, mcr;
+
+ bcr1 = ioread32(bcr + SH7751_BCR1);
+ bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
+ pcic_writel(bcr1, SH4_PCIBCR1);
+
+ /* Enable all interrupts, so we known what to fix */
+ pcic_writel(0x0000c3ff, SH4_PCIINTM);
+ pcic_writel(0x0000380f, SH4_PCIAINTM);
+
+ pcic_writel(0xfb900047, SH7751_PCICONF1);
+ pcic_writel(0xab000001, SH7751_PCICONF4);
+
+ mcr = ioread32(bcr + SH7751_MCR);
+ mcr &= (~PCIMCR_MRSET) & (~PCIMCR_RFSH);
+ pcic_writel(mcr, SH4_PCIMCR);
+
+ pcic_writel(0x0c000000, SH7751_PCICONF5);
+ pcic_writel(0xd0000000, SH7751_PCICONF6);
+ pcic_writel(0x0c000000, SH4_PCILAR0);
+ pcic_writel(0x00000000, SH4_PCILAR1);
+}
+
+static const __initconst struct fixups {
+ char *compatible;
+ void (*fixup)(void __iomem *pci_reg_base, void __iomem *bcr);
+} fixup_list[] = {
+ {
+ .compatible = "iodata,julian-pci",
+ .fixup = julian_fixup,
+ },
+ {
+ .compatible = "renesas,r2d-pci",
+ .fixup = r2d_fixup,
+ },
+};
+
+static void pcic_fixups(struct device_node *np,
+ void __iomem *pcic, void __iomem *bcr)
+{
+ int i;
+ const struct fixups *f = fixup_list;
+
+ for (i = 0; i < ARRAY_SIZE(fixup_list); i++) {
+ if (of_device_is_compatible(np, f->compatible)) {
+ f->fixup(pcic, bcr);
+ break;
+ }
+ }
+}
+
+/*
+ * Direct access to PCI hardware...
+ */
+#define CONFIG_CMD(bus, devfn, where) \
+ (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
+
+/*
+ * Functions for accessing PCI configuration space with type 1 accesses
+ */
+static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val)
+{
+ struct pci_config_window *cfg = bus->sysdata;
+ void __iomem *pci_reg_base = (void __iomem *)cfg->res.start;
+ unsigned long flags;
+ u32 data;
+
+ /*
+ * PCIPDR may only be accessed as 32 bit words,
+ * so we must do byte alignment by hand
+ */
+ raw_spin_lock_irqsave(&pci_config_lock, flags);
+ pcic_writel(CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
+ data = pcic_readl(SH4_PCIPDR);
+ raw_spin_unlock_irqrestore(&pci_config_lock, flags);
+
+ switch (size) {
+ case 1:
+ *val = (data >> ((where & 3) << 3)) & 0xff;
+ break;
+ case 2:
+ *val = (data >> ((where & 2) << 3)) & 0xffff;
+ break;
+ case 4:
+ *val = data;
+ break;
+ default:
+ return PCIBIOS_FUNC_NOT_SUPPORTED;
+ }
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+/*
+ * Since SH4 only does 32bit access we'll have to do a read,
+ * mask,write operation.
+ * We'll allow an odd byte offset, though it should be illegal.
+ */
+static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 val)
+{
+ struct pci_config_window *cfg = bus->sysdata;
+ void __iomem *pci_reg_base = (void __iomem *)cfg->res.start;
+ unsigned long flags;
+ int shift;
+ u32 data;
+
+ raw_spin_lock_irqsave(&pci_config_lock, flags);
+ pcic_writel(CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
+ data = pcic_readl(SH4_PCIPDR);
+ raw_spin_unlock_irqrestore(&pci_config_lock, flags);
+
+ switch (size) {
+ case 1:
+ shift = (where & 3) << 3;
+ data &= ~(0xff << shift);
+ data |= ((val & 0xff) << shift);
+ break;
+ case 2:
+ shift = (where & 2) << 3;
+ data &= ~(0xffff << shift);
+ data |= ((val & 0xffff) << shift);
+ break;
+ case 4:
+ data = val;
+ break;
+ default:
+ return PCIBIOS_FUNC_NOT_SUPPORTED;
+ }
+
+ pcic_writel(data, SH4_PCIPDR);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int area_sdram_check(void __iomem *pci_reg_base,
+ void __iomem *bcr,
+ unsigned int area)
+{
+ unsigned long word;
+
+ word = __raw_readl(bcr + SH7751_BCR1);
+ /* check BCR for SDRAM in area */
+ if (((word >> area) & 1) == 0) {
+ pr_info("PCI: Area %d is not configured for SDRAM. BCR1=0x%lx\n",
+ area, word);
+ return 0;
+ }
+ pcic_writel(word, SH4_PCIBCR1);
+
+ word = __raw_readw(bcr + SH7751_BCR2);
+ /* check BCR2 for 32bit SDRAM interface*/
+ if (((word >> (area << 1)) & 0x3) != 0x3) {
+ pr_info("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%lx\n",
+ area, word);
+ return 0;
+ }
+ pcic_writel(word, SH4_PCIBCR2);
+
+ return 1;
+}
+
+static int sh7751_pci_probe(struct platform_device *pdev)
+{
+ struct resource *res, *wres;
+ u32 id;
+ u32 reg, word;
+ void __iomem *pci_reg_base;
+ void __iomem *bcr;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ pci_reg_base = (void __iomem *)res->start;
+ if (IS_ERR(pci_reg_base))
+ return PTR_ERR(pci_reg_base);
+
+ wres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (IS_ERR(wres))
+ return PTR_ERR(wres);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+ bcr = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(pci_reg_base))
+ return PTR_ERR(bcr);
+
+ /* check for SH7751/SH7751R hardware */
+ id = pcic_readl(SH7751_PCICONF0);
+ if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
+ id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
+ pr_warn("PCI: This is not an SH7751(R)\n");
+ return -ENODEV;
+ }
+ dev_info(&pdev->dev, "PCI core found at %p\n",
+ pci_reg_base);
+
+ /* Set the BCR's to enable PCI access */
+ reg = __raw_readl(bcr);
+ reg |= 0x80000;
+ __raw_writel(reg, bcr);
+
+ /* Turn the clocks back on (not done in reset)*/
+ pcic_writel(0, SH4_PCICLKR);
+ /* Clear Powerdown IRQ's (not done in reset) */
+ word = SH4_PCIPINT_D3 | SH4_PCIPINT_D0;
+ pcic_writel(word, SH4_PCIPINT);
+
+ /* set the command/status bits to:
+ * Wait Cycle Control + Parity Enable + Bus Master +
+ * Mem space enable
+ */
+ word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER |
+ SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES;
+ pcic_writel(word, SH7751_PCICONF1);
+
+ /* define this host as the host bridge */
+ word = PCI_BASE_CLASS_BRIDGE << 24;
+ pcic_writel(word, SH7751_PCICONF2);
+
+ /* Set IO and Mem windows to local address
+ * Make PCI and local address the same for easy 1 to 1 mapping
+ */
+ word = wres->end - wres->start - 1;
+ pcic_writel(word, SH4_PCILSR0);
+ /* Set the values on window 0 PCI config registers */
+ word = P2SEGADDR(wres->start);
+ pcic_writel(word, SH4_PCILAR0);
+ pcic_writel(word, SH7751_PCICONF5);
+
+ /* check BCR for SDRAM in specified area */
+ area_sdram_check(pci_reg_base, bcr, (wres->start >> 27) & 0x07);
+
+ /* configure the wait control registers */
+ word = __raw_readl(bcr + SH7751_WCR1);
+ pcic_writel(word, SH4_PCIWCR1);
+ word = __raw_readl(bcr + SH7751_WCR2);
+ pcic_writel(word, SH4_PCIWCR2);
+ word = __raw_readl(bcr + SH7751_WCR3);
+ pcic_writel(word, SH4_PCIWCR3);
+ word = __raw_readl(bcr + SH7751_MCR);
+ pcic_writel(word, SH4_PCIMCR);
+
+ pcic_fixups(pdev->dev.of_node, pci_reg_base, bcr);
+
+ /* SH7751 init done, set central function init complete */
+ /* use round robin mode to stop a device starving/overruning */
+ word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM;
+ pcic_writel(word, SH4_PCICR);
+
+ return pci_host_common_probe(pdev);
+}
+
+static void __iomem *sh4_pci_map_bus(struct pci_bus *bus,
+ unsigned int devfn, int where)
+{
+ struct pci_config_window *cfg = bus->sysdata;
+ void __iomem *pci_reg_base = (void __iomem *)cfg->res.start;
+
+ pcic_writel(CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
+ return pci_reg_base + SH4_PCIPDR;
+}
+
+static const struct pci_ecam_ops pci_sh7751_bus_ops = {
+ .pci_ops = {
+ .map_bus = sh4_pci_map_bus,
+ .read = sh4_pci_read,
+ .write = sh4_pci_write,
+ }
+};
+
+static const struct of_device_id sh7751_pci_of_match[] = {
+ { .compatible = "renesas,sh7751-pci",
+ .data = &pci_sh7751_bus_ops },
+
+ { },
+};
+MODULE_DEVICE_TABLE(of, sh7751_pci_of_match);
+
+static struct platform_driver sh7751_pci_driver = {
+ .driver = {
+ .name = "sh7751-pci",
+ .of_match_table = sh7751_pci_of_match,
+ },
+ .probe = sh7751_pci_probe,
+};
+module_platform_driver(sh7751_pci_driver);
+
+MODULE_DESCRIPTION("SH7751 PCI driver");
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 08/30] drivers/pci: Add SH7751 Host bridge controller
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (6 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 07/30] drivers/pci: SH7751 PCI Host bridge controller driver Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-18 15:34 ` Geert Uytterhoeven
` (2 more replies)
2023-09-13 9:23 ` [RFC PATCH v2 09/30] Documentation/devicetree: Add renesas,sh7751-pci binding document Yoshinori Sato
` (21 subsequent siblings)
29 siblings, 3 replies; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz, linux-pci
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/pci/controller/Kconfig | 9 +++++++++
drivers/pci/controller/Makefile | 1 +
2 files changed, 10 insertions(+)
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index c0c3f2824990..037ff44bd1e8 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -342,6 +342,15 @@ config PCIE_XILINX_CPM
Say 'Y' here if you want kernel support for the
Xilinx Versal CPM host bridge.
+config PCI_SH7751
+ bool "Renesas SH7751 PCI controller"
+ depends on OF
+ depends on CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R || COMPILE_TEST
+ select PCI_HOST_COMMON
+ help
+ Say 'Y' here if you want kernel to support the Renesas SH7751 PCI
+ Host Bridge driver.
+
source "drivers/pci/controller/cadence/Kconfig"
source "drivers/pci/controller/dwc/Kconfig"
source "drivers/pci/controller/mobiveil/Kconfig"
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index 37c8663de7fe..ce96cfe9f1f2 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o
obj-$(CONFIG_PCIE_APPLE) += pcie-apple.o
obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o
+obj-$(CONFIG_PCI_SH7751) += pci-sh7751.o
# pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
obj-y += dwc/
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 09/30] Documentation/devicetree: Add renesas,sh7751-pci binding document.
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (7 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 08/30] drivers/pci: Add SH7751 Host bridge controller Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-13 10:42 ` Krzysztof Kozlowski
2023-09-18 15:41 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 10/30] drivers/clk: SH7750 / SH7751 CPG Driver Yoshinori Sato
` (20 subsequent siblings)
29 siblings, 2 replies; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz, linux-pci
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
.../bindings/pci/renesas,sh7751-pci.yaml | 57 +++++++++++++++++++
1 file changed, 57 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml
diff --git a/Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml b/Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml
new file mode 100644
index 000000000000..17a24e24c393
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/renesas,sh7751-pci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7751 PCI Host controller
+
+maintainers:
+ - Yoshinori Sato <ysato@users.sourceforge.jp>
+
+properties:
+ compatible:
+ - items:
+ - enum:
+ - renesas,r2d-pci # Renesas RTS7751R2D board
+ - iodata,julian-pci # IO DATA DEVICE Julian board
+ - const: renesas,sh7751-pci
+
+ reg:
+ minItems: 3
+
+ interrupt-cells:
+ const: 1
+
+ address-cells:
+ const: 3
+
+ size-cells:
+ const: 2;
+
+ range:
+ description: |
+ The PCI bus memory area and I/O area.
+
+
+required:
+ - compatible
+ - reg
+ - interrupt-cells
+ - address-cells
+ - size-cells
+ - range
+
+examples:
+ - |
+ pci@fe200000 {
+ compatible = "renesas,sh7751-pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0 0xfd000000 0xfd000000 0 0x01000000>,
+ <0x01000000 0 0xfe240000 0xfe240000 0 0x00040000>;
+ reg = <0xfe200000 0x0400>,
+ <0x0c000000 0x04000000>,
+ <0xff800000 0x0030>;
+ #interrupt-cells = <1>;
+ };
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 10/30] drivers/clk: SH7750 / SH7751 CPG Driver
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (8 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 09/30] Documentation/devicetree: Add renesas,sh7751-pci binding document Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-13 10:43 ` Krzysztof Kozlowski
2023-09-18 16:05 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 11/30] drivers/clk: SuperH generai clock divider helper Yoshinori Sato
` (19 subsequent siblings)
29 siblings, 2 replies; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz, linux-clk
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/clk/renesas/clk-sh7750.c | 236 +++++++++++++++++++++++++++++++
1 file changed, 236 insertions(+)
create mode 100644 drivers/clk/renesas/clk-sh7750.c
diff --git a/drivers/clk/renesas/clk-sh7750.c b/drivers/clk/renesas/clk-sh7750.c
new file mode 100644
index 000000000000..51f1aecd23dc
--- /dev/null
+++ b/drivers/clk/renesas/clk-sh7750.c
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas SH7750/51 CPG driver
+ *
+ * Copyright 2023 Yoshinori Sato <ysato@users.sourceforge.jp>
+ */
+
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+#include "clk-shdiv.h"
+#include <dt-bindings/clock/sh7750.h>
+
+static DEFINE_SPINLOCK(clklock);
+
+/* PCLK divide rate selector */
+static const struct clk_div_table pdiv_table[] = {
+ { .val = 0, .div = 2, },
+ { .val = 1, .div = 3, },
+ { .val = 2, .div = 4, },
+ { .val = 3, .div = 6, },
+ { .val = 4, .div = 8, },
+ { }
+};
+
+/* ICLK and BCLK divide rate selector */
+static const struct clk_div_table div_table[] = {
+ { .val = 0, .div = 1, },
+ { .val = 1, .div = 2, },
+ { .val = 2, .div = 3, },
+ { .val = 3, .div = 4, },
+ { .val = 4, .div = 6, },
+ { .val = 5, .div = 8, },
+ { }
+};
+
+struct cpg_priv {
+ struct clk_hw hw;
+ void __iomem *frqcr;
+ void __iomem *wdt;
+ u32 mode;
+ bool have_div1;
+};
+
+#define to_priv(_hw) container_of(_hw, struct cpg_priv, hw)
+
+#define FRQCR_PLL1EN BIT(10)
+static const int pll1mult[] = { 12, 12, 6, 12, 6, 12, 1};
+
+static unsigned long pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct cpg_priv *cpg = to_priv(hw);
+ unsigned long rate = parent_rate;
+ uint16_t frqcr;
+
+ frqcr = ioread16(cpg->frqcr);
+ if (frqcr & FRQCR_PLL1EN) {
+ rate *= pll1mult[cpg->mode];
+ if (cpg->mode < 6 && cpg->have_div1)
+ rate /= 2;
+ }
+ return rate;
+}
+
+static void get_round_rate(struct cpg_priv *cpg,
+ unsigned long *out, bool *pllen,
+ unsigned long rate, unsigned long prate)
+{
+ long pllout, res;
+ bool pll;
+
+ if (cpg->mode < 6 && cpg->have_div1)
+ prate /= 2;
+
+ pllout = prate * pll1mult[cpg->mode];
+ if (abs(pllout - rate) > abs(prate - rate)) {
+ res = prate;
+ pll = false;
+ } else {
+ res = pllout;
+ pll = true;
+ }
+ if (out)
+ *out = res;
+ if (pllen)
+ *pllen = pll;
+}
+
+static int pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
+{
+ struct cpg_priv *cpg = to_priv(hw);
+
+ get_round_rate(cpg, &req->rate, NULL, req->rate, req->best_parent_rate);
+ return 0;
+}
+
+static int pll_set_rate(struct clk_hw *hw,
+ unsigned long rate, unsigned long prate)
+{
+ struct cpg_priv *cpg = to_priv(hw);
+ bool oldpll, newpll;
+ uint16_t frqcr;
+
+ frqcr = ioread16(cpg->frqcr);
+ get_round_rate(cpg, NULL, &newpll, rate, prate);
+ oldpll = frqcr & FRQCR_PLL1EN;
+ frqcr &= ~FRQCR_PLL1EN;
+
+ if (newpll) {
+ frqcr |= FRQCR_PLL1EN;
+ if (!oldpll) {
+ /* set PLL wakeup delay time */
+ iowrite16(0xa500, cpg->wdt + 4);
+ iowrite16(0xa507, cpg->wdt + 4);
+ iowrite16(0xa507, cpg->wdt + 4);
+ iowrite16(0x5a00, cpg->wdt);
+ }
+ }
+ iowrite16(frqcr, cpg->frqcr);
+
+ /* Test for new PLL state */
+ frqcr = ioread16(cpg->frqcr);
+ oldpll = frqcr & FRQCR_PLL1EN;
+ return !(oldpll == newpll);
+}
+
+static const struct clk_ops pll_ops = {
+ .recalc_rate = pll_recalc_rate,
+ .determine_rate = pll_determine_rate,
+ .set_rate = pll_set_rate,
+};
+
+#define PLLOUT "pllout"
+
+static int __init register_pll(struct device_node *node, struct cpg_priv *cpg)
+{
+ struct clk *clk;
+ const char *clk_name = node->name;
+ const char *parent_name;
+ struct clk_init_data init;
+
+ parent_name = of_clk_get_parent_name(node, 0);
+ init.name = PLLOUT;
+ init.ops = &pll_ops;
+ init.flags = 0;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+ cpg->hw.init = &init;
+
+ if (of_clk_hw_register(node, &cpg->hw) < 0) {
+ pr_err("%s: failed to register %s pll clock (%ld)\n",
+ __func__, clk_name, PTR_ERR(clk));
+ return 0;
+ }
+ of_clk_add_hw_provider(node, of_clk_hw_simple_get, &cpg->hw);
+
+ return 1;
+}
+
+static void __init register_div(struct device_node *node, struct cpg_priv *cpg)
+{
+ static const char * const divout[] = {
+ [SH7750_CPG_FCK] = "fck",
+ [SH7750_CPG_BCK] = "bck",
+ [SH7750_CPG_ICK] = "ick",
+ };
+ struct clk *clk;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(divout); i++) {
+ if (sh_div_clk_register(node, divout[i], PLLOUT,
+ cpg->frqcr, i * 3, 3,
+ (i == 0) ? pdiv_table : div_table,
+ &clklock) < 0)
+ pr_err("%s: failed to register %s div clock (%ld)\n",
+ __func__, divout[i], PTR_ERR(clk));
+ }
+}
+
+
+static void __init sh7750_cpg_setup(struct device_node *node)
+{
+ unsigned int num_parents;
+ struct cpg_priv *cpg;
+
+ num_parents = of_clk_get_parent_count(node);
+ if (num_parents < 1) {
+ pr_err("%s: no parent found", node->name);
+ return;
+ }
+
+ cpg = kzalloc(sizeof(struct cpg_priv), GFP_KERNEL);
+ if (!cpg) {
+ pr_err("%s: failed to alloc memory", node->name);
+ return;
+ }
+
+ of_property_read_u32_index(node, "renesas,mode", 0, &cpg->mode);
+ if (cpg->mode >= 7) {
+ pr_err("%s: Invalid clock mode setting (%u)\n",
+ node->name, cpg->mode);
+ goto cpg_free;
+ }
+ cpg->have_div1 = (of_device_is_compatible(node, "renesas,sh7750r-pll-clk") == 0);
+
+ cpg->frqcr = of_iomap(node, 0);
+ if (cpg->frqcr == NULL) {
+ pr_err("%s: failed to map divide register", node->name);
+ goto cpg_free;
+ }
+
+ cpg->wdt = of_iomap(node, 1);
+ if (cpg->wdt == NULL) {
+ pr_err("%s: failed to map watchdog register", node->name);
+ goto unmap_frqcr;
+ }
+
+ if (!register_pll(node, cpg))
+ goto unmap_wdt;
+
+ register_div(node, cpg);
+
+unmap_wdt:
+ iounmap(cpg->wdt);
+unmap_frqcr:
+ iounmap(cpg->frqcr);
+cpg_free:
+ kfree(cpg);
+}
+
+CLK_OF_DECLARE(sh7750_cpg, "renesas,sh7750-cpg",
+ sh7750_cpg_setup);
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 11/30] drivers/clk: SuperH generai clock divider helper
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (9 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 10/30] drivers/clk: SH7750 / SH7751 CPG Driver Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-18 18:59 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 12/30] drivers/clk: Add SH7750 CPG drivers entry Yoshinori Sato
` (18 subsequent siblings)
29 siblings, 1 reply; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz, linux-clk
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/clk/renesas/clk-shdiv.c | 346 ++++++++++++++++++++++++++++++++
drivers/clk/renesas/clk-shdiv.h | 18 ++
2 files changed, 364 insertions(+)
create mode 100644 drivers/clk/renesas/clk-shdiv.c
create mode 100644 drivers/clk/renesas/clk-shdiv.h
diff --git a/drivers/clk/renesas/clk-shdiv.c b/drivers/clk/renesas/clk-shdiv.c
new file mode 100644
index 000000000000..90055bc384c7
--- /dev/null
+++ b/drivers/clk/renesas/clk-shdiv.c
@@ -0,0 +1,346 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SuperH divider clock driver
+ */
+
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include "clk-shdiv.h"
+
+#define div_mask(width) ((1 << (width)) - 1)
+
+static unsigned int _get_table_maxdiv(const struct clk_div_table *table,
+ u8 width)
+{
+ unsigned int maxdiv = 0, mask = div_mask(width);
+ const struct clk_div_table *clkt;
+
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->div > maxdiv && clkt->val <= mask)
+ maxdiv = clkt->div;
+ return maxdiv;
+}
+
+static unsigned int _get_maxdiv(const struct clk_div_table *table, u8 width)
+{
+ if (table)
+ return _get_table_maxdiv(table, width);
+ return div_mask(width) + 1;
+}
+
+static unsigned int _get_table_div(const struct clk_div_table *table,
+ unsigned int val)
+{
+ const struct clk_div_table *clkt;
+
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->val == val)
+ return clkt->div;
+ return 0;
+}
+
+static unsigned int _get_div(const struct clk_div_table *table,
+ unsigned int val, u8 width)
+{
+ if (table)
+ return _get_table_div(table, val);
+ return val + 1;
+}
+
+static unsigned int _get_table_val(const struct clk_div_table *table,
+ unsigned int div)
+{
+ const struct clk_div_table *clkt;
+
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->div == div)
+ return clkt->val;
+ return 0;
+}
+
+static unsigned int _get_val(const struct clk_div_table *table,
+ unsigned int div, u8 width)
+{
+ if (table)
+ return _get_table_val(table, div);
+ return div - 1;
+}
+
+static unsigned long sh_divider_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate,
+ unsigned int val,
+ const struct clk_div_table *table)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned int div;
+
+ div = _get_div(table, val, divider->width);
+
+ return DIV_ROUND_UP_ULL((u64)parent_rate, div);
+}
+
+static unsigned long sh_clk_divider_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned int val;
+
+ val = __raw_readw(divider->reg) >> divider->shift;
+ val &= div_mask(divider->width);
+
+ return sh_divider_recalc_rate(hw, parent_rate, val, divider->table);
+}
+
+static bool _is_valid_table_div(const struct clk_div_table *table,
+ unsigned int div)
+{
+ const struct clk_div_table *clkt;
+
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->div == div)
+ return true;
+ return false;
+}
+
+static bool _is_valid_div(const struct clk_div_table *table, unsigned int div)
+{
+ if (table)
+ return _is_valid_table_div(table, div);
+ return true;
+}
+
+static int _round_up_table(const struct clk_div_table *table, int div)
+{
+ const struct clk_div_table *clkt;
+ int up = INT_MAX;
+
+ for (clkt = table; clkt->div; clkt++) {
+ if (clkt->div == div)
+ return clkt->div;
+ else if (clkt->div < div)
+ continue;
+
+ if ((clkt->div - div) < (up - div))
+ up = clkt->div;
+ }
+
+ return up;
+}
+
+static int _div_round_up(const struct clk_div_table *table,
+ unsigned long parent_rate, unsigned long rate)
+{
+ int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+
+ if (table)
+ div = _round_up_table(table, div);
+
+ return div;
+}
+
+static int _div_round(const struct clk_div_table *table,
+ unsigned long parent_rate, unsigned long rate)
+{
+ return _div_round_up(table, parent_rate, rate);
+}
+
+static bool _is_best_div(unsigned long rate, unsigned long now,
+ unsigned long best)
+{
+ return now <= rate && now > best;
+}
+
+static int _next_div(const struct clk_div_table *table, int div)
+{
+ div++;
+
+ if (table)
+ return _round_up_table(table, div);
+
+ return div;
+}
+
+static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
+ unsigned long *best_parent_rate,
+ const struct clk_div_table *table, u8 width)
+{
+ int i, bestdiv = 0;
+ unsigned long parent_rate, best = 0, now, maxdiv;
+ unsigned long parent_rate_saved = *best_parent_rate;
+
+ if (!rate)
+ rate = 1;
+
+ maxdiv = _get_maxdiv(table, width);
+
+ if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
+ parent_rate = *best_parent_rate;
+ bestdiv = _div_round(table, parent_rate, rate);
+ bestdiv = bestdiv == 0 ? 1 : bestdiv;
+ bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
+ return bestdiv;
+ }
+
+ /*
+ * The maximum divider we can use without overflowing
+ * unsigned long in rate * i below
+ */
+ maxdiv = min(ULONG_MAX / rate, maxdiv);
+
+ for (i = _next_div(table, 0); i <= maxdiv;
+ i = _next_div(table, i)) {
+ if (rate * i == parent_rate_saved) {
+ /*
+ * It's the most ideal case if the requested rate can be
+ * divided from parent clock without needing to change
+ * parent rate, so return the divider immediately.
+ */
+ *best_parent_rate = parent_rate_saved;
+ return i;
+ }
+ parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
+ rate * i);
+ now = DIV_ROUND_UP_ULL((u64)parent_rate, i);
+ if (_is_best_div(rate, now, best)) {
+ bestdiv = i;
+ best = now;
+ *best_parent_rate = parent_rate;
+ }
+ }
+
+ if (!bestdiv) {
+ bestdiv = _get_maxdiv(table, width);
+ *best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), 1);
+ }
+
+ return bestdiv;
+}
+
+static long sh_divider_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate, const struct clk_div_table *table,
+ u8 width)
+{
+ int div;
+
+ div = clk_divider_bestdiv(hw, rate, prate, table, width);
+
+ return DIV_ROUND_UP_ULL((u64)*prate, div);
+}
+
+static int sh_clk_divider_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ long rate, prate;
+
+ prate = req->best_parent_rate;
+ rate = sh_divider_round_rate(hw, req->rate, &prate, divider->table,
+ divider->width);
+ if (rate < 0)
+ return rate;
+ req->rate = rate;
+ req->best_parent_rate = prate;
+ return 0;
+}
+
+static int sh_divider_get_val(unsigned long rate, unsigned long parent_rate,
+ const struct clk_div_table *table, u8 width)
+{
+ unsigned int div, value;
+
+ div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+
+ if (!_is_valid_div(table, div))
+ return -EINVAL;
+
+ value = _get_val(table, div, width);
+
+ return min_t(unsigned int, value, div_mask(width));
+}
+
+static int sh_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned int value;
+ unsigned long flags = 0;
+ u16 val;
+
+ value = sh_divider_get_val(rate, parent_rate, divider->table,
+ divider->width);
+
+ if (divider->lock)
+ spin_lock_irqsave(divider->lock, flags);
+ else
+ __acquire(divider->lock);
+
+ val = __raw_readw(divider->reg);
+ val &= ~(div_mask(divider->width) << divider->shift);
+ val |= value << divider->shift;
+ __raw_writew(val, divider->reg);
+
+ if (divider->lock)
+ spin_unlock_irqrestore(divider->lock, flags);
+ else
+ __release(divider->lock);
+
+ return 0;
+}
+
+static const struct clk_ops sh_clk_divider_ops = {
+ .recalc_rate = sh_clk_divider_recalc_rate,
+ .determine_rate = sh_clk_divider_determine_rate,
+ .set_rate = sh_clk_divider_set_rate,
+};
+
+static int _register_divider(struct device_node *node, const char *name,
+ const char *parent_name,
+ void __iomem *reg, u8 shift, u8 width,
+ const struct clk_div_table *table,
+ spinlock_t *lock)
+{
+ struct clk_divider *div;
+ struct clk_init_data init;
+
+ /* allocate the divider */
+ div = kzalloc(sizeof(*div), GFP_KERNEL);
+ if (!div)
+ return -ENOMEM;
+
+ init.name = name;
+ init.ops = &sh_clk_divider_ops;
+ init.flags = 0;
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+
+ /* struct clk_divider assignments */
+ div->reg = reg;
+ div->shift = shift;
+ div->width = width;
+ div->lock = lock;
+ div->hw.init = &init;
+ div->table = table;
+
+ /* register the clock */
+ if (of_clk_hw_register(node, &div->hw) < 0)
+ kfree(div);
+ of_clk_add_hw_provider(node, of_clk_hw_simple_get, &div->hw);
+
+ return 0;
+}
+
+int sh_div_clk_register(struct device_node *node, const char *name,
+ const char *parent_name,
+ void __iomem *reg, u8 shift, u8 width,
+ const struct clk_div_table *table,
+ spinlock_t *lock)
+{
+ return _register_divider(node, name, parent_name, reg, shift,
+ width, table, lock);
+}
+EXPORT_SYMBOL_GPL(sh_div_clk_register);
diff --git a/drivers/clk/renesas/clk-shdiv.h b/drivers/clk/renesas/clk-shdiv.h
new file mode 100644
index 000000000000..fd49c06da9ff
--- /dev/null
+++ b/drivers/clk/renesas/clk-shdiv.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __CLK_SHDIV_H__
+#define __CLK_SHDIV_H__
+/*
+ * SuperH divider clock driver
+ */
+
+#include <linux/of.h>
+#include <linux/clk-provider.h>
+
+int sh_div_clk_register(struct device_node *node, const char *name,
+ const char *parent_name,
+ void __iomem *reg, u8 shift, u8 width,
+ const struct clk_div_table *table,
+ spinlock_t *lock);
+
+#endif
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 12/30] drivers/clk: Add SH7750 CPG drivers entry.
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (10 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 11/30] drivers/clk: SuperH generai clock divider helper Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-18 19:05 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 13/30] Documentation/devicetree: Add renesas,sh7751-cpg binding document Yoshinori Sato
` (17 subsequent siblings)
29 siblings, 1 reply; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz, linux-clk
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/clk/renesas/Kconfig | 15 ++++++++++++++-
drivers/clk/renesas/Makefile | 1 +
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 37632a0659d8..c4e2f7d0349d 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -2,7 +2,7 @@
config CLK_RENESAS
bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS
- default y if ARCH_RENESAS
+ default y if ARCH_RENESAS || SUPERH
select CLK_EMEV2 if ARCH_EMEV2
select CLK_RZA1 if ARCH_R7S72100
select CLK_R7S9210 if ARCH_R7S9210
@@ -39,6 +39,11 @@ config CLK_RENESAS
select CLK_R9A07G054 if ARCH_R9A07G054
select CLK_R9A09G011 if ARCH_R9A09G011
select CLK_SH73A0 if ARCH_SH73A0
+ select CLK_SH7750 if CPU_SUBTYPE_SH7750
+ select CLK_SH7750 if CPU_SUBTYPE_SH7750S
+ select CLK_SH7750 if CPU_SUBTYPE_SH7750R
+ select CLK_SH7750 if CPU_SUBTYPE_SH7751
+ select CLK_SH7750 if CPU_SUBTYPE_SH7751R
if CLK_RENESAS
@@ -218,6 +223,14 @@ config CLK_RZG2L
bool "Renesas RZ/{G2L,G2UL,V2L} family clock support" if COMPILE_TEST
select RESET_CONTROLLER
+config CLK_SH7750
+ bool "Renesas SH7750/7751 family clock support"
+ depends on CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7750S || \
+ CPU_SUBTYPE_SH7750R || \
+ CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R || COMPILE_TEST
+ help
+ This is a driver for SH7750 / SH7751 CPG.
+
# Generic
config CLK_RENESAS_CPG_MSSR
bool "CPG/MSSR clock support" if COMPILE_TEST
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index de907623fe3f..3f896cf31dc4 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
+obj-$(CONFIG_CLK_SH7750) += clk-sh7750.o clk-shdiv.o
# Family
obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 13/30] Documentation/devicetree: Add renesas,sh7751-cpg binding document.
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (11 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 12/30] drivers/clk: Add SH7750 CPG drivers entry Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-13 10:44 ` Krzysztof Kozlowski
` (2 more replies)
2023-09-13 9:23 ` [RFC PATCH v2 14/30] drivers/irqchip: Add SH7751 Internal INTC drivers Yoshinori Sato
` (16 subsequent siblings)
29 siblings, 3 replies; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz, linux-clk
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
.../bindings/clock/renesas,sh7750-cpg.yaml | 58 +++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
diff --git a/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
new file mode 100644
index 000000000000..bf10a09440ac
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7750 / SH7751 Clock Pulse Generator (CPG)
+
+maintainers:
+ - Yoshinori Sato <ysato@users.sourceforge.jp>
+
+description:
+ The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
+ includes PLLs, and fixed and variable ratio dividers.
+
+ The CPG may also provide a Clock Domain for SoC devices,
+
+properties:
+ compatible:
+ - const: renesas,sh7750-cpg # SH7750 / 7750S / 7751
+ - items:
+ - const: renesas,sh7750r-cpg # SH7750R / 7751R
+
+ reg:
+ maxItems: 2
+ items:
+ - description: FRQCR register
+ - description: WDT registers
+
+ clocks: true
+
+ '#clock-cells':
+ const: 1
+
+ renesas,mode:
+ description: Board-specific settings of the MD0 - MD2 bits
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 6
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7740-clock.h>
+ cpg: cpg@ffc00000 {
+ #clock-cells = <1>;
+ compatible = "renesas,sh7750r-cpg","renesas,sh7750-cpg";
+ clocks = <&xtal>;
+ reg = <0xffc00000 2>, <0xffc00008 4>;
+ renesas,mode = <0x05>
+ };
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 14/30] drivers/irqchip: Add SH7751 Internal INTC drivers.
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (12 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 13/30] Documentation/devicetree: Add renesas,sh7751-cpg binding document Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-19 11:50 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 15/30] Documentation/devicetree: Add renesas,sh7751-intc binding document Yoshinori Sato
` (15 subsequent siblings)
29 siblings, 1 reply; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/irqchip/Kconfig | 9 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-renesas-sh7751.c | 232 +++++++++++++++++++++++++++
3 files changed, 242 insertions(+)
create mode 100644 drivers/irqchip/irq-renesas-sh7751.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index f7149d0f3d45..167832daa903 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -679,4 +679,13 @@ config SUNPLUS_SP7021_INTC
chained controller, routing all interrupt source in P-Chip to
the primary controller on C-Chip.
+config RENESAS_SH7751_INTC
+ bool "Renesas SH7751 Interrupt Controller"
+ depends on SH_DEVICE_TREE
+ select IRQ_DOMAIN
+ select IRQ_DOMAIN_HIERARCHY
+ help
+ Support for the Renesas SH7751 On-chip interrupt controller.
+ And external interrupt encoder for some targets.
+
endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index ffd945fe71aa..26c91d075e25 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -120,3 +120,4 @@ obj-$(CONFIG_IRQ_IDT3243X) += irq-idt3243x.o
obj-$(CONFIG_APPLE_AIC) += irq-apple-aic.o
obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o
obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o
+obj-$(CONFIG_RENESAS_SH7751_INTC) += irq-renesas-sh7751.o
diff --git a/drivers/irqchip/irq-renesas-sh7751.c b/drivers/irqchip/irq-renesas-sh7751.c
new file mode 100644
index 000000000000..1ce0851e35cd
--- /dev/null
+++ b/drivers/irqchip/irq-renesas-sh7751.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas SH7751 interrupt controller driver
+ *
+ * Copyright 2023 Yoshinori Sato <ysato@users.sourceforge.jp>
+ */
+
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of.h>
+#include <linux/bsearch.h>
+#include <linux/io.h>
+
+static struct sh7751_intc_regs {
+ void *icr;
+ void *ipr;
+ void *intpri00;
+ void *intreq00;
+ void *intmsk00;
+ void *intmskclr00;
+} sh7751_regs;
+
+#define ICR_IRLM BIT(7)
+
+/* Bitmap of IRQ masked */
+#define IMASK_PRIORITY 15
+
+static DECLARE_BITMAP(imask_mask, IMASK_PRIORITY);
+static int interrupt_priority;
+
+static inline void set_interrupt_registers(int ip)
+{
+ unsigned long __dummy;
+
+ asm volatile(
+#ifdef CONFIG_CPU_HAS_SR_RB
+ "ldc %2, r6_bank\n\t"
+#endif
+ "stc sr, %0\n\t"
+ "and #0xf0, %0\n\t"
+ "shlr2 %0\n\t"
+ "cmp/eq #0x3c, %0\n\t"
+ "bt/s 1f ! CLI-ed\n\t"
+ " stc sr, %0\n\t"
+ "and %1, %0\n\t"
+ "or %2, %0\n\t"
+ "ldc %0, sr\n"
+ "1:"
+ : "=&z" (__dummy)
+ : "r" (~0xf0), "r" (ip << 4)
+ : "t");
+}
+
+#define IPRA 0
+#define IPRB 4
+#define IPRC 8
+#define IPRD 12
+#define INTPRI00 128
+#define IPR_B12 12
+#define IPR_B8 8
+#define IPR_B4 4
+#define IPR_B0 0
+
+/* INTEVT to IPR mapping */
+static const struct iprmap {
+ int intevt;
+ int off;
+ int bit;
+} iprmaps[] = {
+#define IPRDEF(e, o, b) { .intevt = evt2irq(e), .off = o, .bit = b }
+ IPRDEF(0x240, IPRD, IPR_B12), /* IRL0 */
+ IPRDEF(0x2a0, IPRD, IPR_B8), /* IRL1 */
+ IPRDEF(0x300, IPRD, IPR_B4), /* IRL2 */
+ IPRDEF(0x360, IPRD, IPR_B0), /* IRL3 */
+ IPRDEF(0x400, IPRA, IPR_B12), /* TMU0 */
+ IPRDEF(0x420, IPRA, IPR_B8), /* TMU1 */
+ IPRDEF(0x440, IPRA, IPR_B4), /* TMU2 TNUI */
+ IPRDEF(0x460, IPRA, IPR_B4), /* TMU2 TICPI */
+ IPRDEF(0x480, IPRA, IPR_B0), /* RTC ATI */
+ IPRDEF(0x4a0, IPRA, IPR_B0), /* RTC PRI */
+ IPRDEF(0x4c0, IPRA, IPR_B0), /* RTC CUI */
+ IPRDEF(0x4e0, IPRB, IPR_B4), /* SCI ERI */
+ IPRDEF(0x500, IPRB, IPR_B4), /* SCI RXI */
+ IPRDEF(0x520, IPRB, IPR_B4), /* SCI TXI */
+ IPRDEF(0x540, IPRB, IPR_B4), /* SCI TEI */
+ IPRDEF(0x560, IPRB, IPR_B12), /* WDT */
+ IPRDEF(0x580, IPRB, IPR_B8), /* REF RCMI */
+ IPRDEF(0x5a0, IPRB, IPR_B4), /* REF ROVI */
+ IPRDEF(0x600, IPRC, IPR_B0), /* H-UDI */
+ IPRDEF(0x620, IPRC, IPR_B12), /* GPIO */
+ IPRDEF(0x640, IPRC, IPR_B8), /* DMAC DMTE0 */
+ IPRDEF(0x660, IPRC, IPR_B8), /* DMAC DMTE1 */
+ IPRDEF(0x680, IPRC, IPR_B8), /* DMAC DMTE2 */
+ IPRDEF(0x6a0, IPRC, IPR_B8), /* DMAC DMTE3 */
+ IPRDEF(0x6c0, IPRC, IPR_B8), /* DMAC DMAE */
+ IPRDEF(0x700, IPRC, IPR_B4), /* SCIF ERI */
+ IPRDEF(0x720, IPRC, IPR_B4), /* SCIF RXI */
+ IPRDEF(0x740, IPRC, IPR_B4), /* SCIF BRI */
+ IPRDEF(0x760, IPRC, IPR_B4), /* SCIF TXI */
+ IPRDEF(0x780, IPRC, IPR_B8), /* DMAC DMTE4 */
+ IPRDEF(0x7a0, IPRC, IPR_B8), /* DMAC DMTE5 */
+ IPRDEF(0x7c0, IPRC, IPR_B8), /* DMAC DMTE6 */
+ IPRDEF(0x7e0, IPRC, IPR_B8), /* DMAC DMTE7 */
+ IPRDEF(0xa00, INTPRI00, IPR_B0), /* PCIC PCISERR */
+ IPRDEF(0xa20, INTPRI00, IPR_B4), /* PCIC PCIDMA3 */
+ IPRDEF(0xa40, INTPRI00, IPR_B4), /* PCIC PCIDMA2 */
+ IPRDEF(0xa60, INTPRI00, IPR_B4), /* PCIC PCIDMA1 */
+ IPRDEF(0xa80, INTPRI00, IPR_B4), /* PCIC PCIDMA0 */
+ IPRDEF(0xaa0, INTPRI00, IPR_B4), /* PCIC PCIPWON */
+ IPRDEF(0xac0, INTPRI00, IPR_B4), /* PCIC PCIPWDWN */
+ IPRDEF(0xae0, INTPRI00, IPR_B4), /* PCIC PCIERR */
+ IPRDEF(0xb00, INTPRI00, IPR_B8), /* TMU3 */
+ IPRDEF(0xb80, INTPRI00, IPR_B12), /* TMU4 */
+};
+
+static int ipr_compare(const void *a, const void *b)
+{
+ return (int)a - ((struct iprmap *)b)->intevt;
+}
+
+static void update_ipr(struct sh7751_intc_regs *reg, int irq, int pval)
+{
+ void *prireg;
+ struct iprmap *p;
+ u16 pri;
+
+ p = bsearch((void *)irq, iprmaps, ARRAY_SIZE(iprmaps),
+ sizeof(struct iprmap), ipr_compare);
+ if (p) {
+ prireg = (p->off < INTPRI00) ? reg->ipr + p->off : reg->intpri00;
+ pri = ~(0x000f << p->bit);
+ pri &= __raw_readw(prireg);
+ pri |= (pval & 0x0f) << p->bit;
+ __raw_writew(pri, prireg);
+ }
+}
+
+static void sh7751_disable_irq(struct irq_data *data)
+{
+ unsigned int irq = data->irq;
+ struct sh7751_intc_regs *reg = data->chip_data;
+ uint16_t icr = __raw_readw(reg->icr);
+
+ if (irq < 16 && (icr & ICR_IRLM) == 0) {
+ /* IRL encoded externel interrupt */
+ /* disable for SR.IMASK */
+ clear_bit(irq, imask_mask);
+ if (interrupt_priority < IMASK_PRIORITY - irq)
+ interrupt_priority = IMASK_PRIORITY - irq;
+ set_interrupt_registers(interrupt_priority);
+ } else
+ /* Internal periphreal interrupt */
+ /* IPR priority is 0 */
+ update_ipr(reg, irq, 0);
+}
+
+static void sh7751_enable_irq(struct irq_data *data)
+{
+ unsigned int irq = data->irq;
+ struct sh7751_intc_regs *reg = data->chip_data;
+ uint16_t icr = __raw_readw(reg->icr);
+
+ if (irq < 16 && (icr & ICR_IRLM) == 0) {
+ set_bit(irq, imask_mask);
+ interrupt_priority = IMASK_PRIORITY -
+ find_first_bit(imask_mask, IMASK_PRIORITY);
+ set_interrupt_registers(interrupt_priority);
+ } else
+ update_ipr(reg, irq, 1);
+}
+
+static const struct irq_chip sh7751_irq_chip = {
+ .name = "SH7751-INTC",
+ .irq_unmask = sh7751_enable_irq,
+ .irq_mask = sh7751_disable_irq,
+};
+
+static int irq_sh7751_map(struct irq_domain *h, unsigned int virq,
+ irq_hw_number_t hw_irq_num)
+{
+ irq_set_chip_and_handler(virq, &sh7751_irq_chip, handle_level_irq);
+ irq_get_irq_data(virq)->chip_data = h->host_data;
+ irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOPROBE);
+ return 0;
+}
+static const struct irq_domain_ops irq_ops = {
+ .map = irq_sh7751_map,
+ .xlate = irq_domain_xlate_onecell,
+};
+
+static int __init sh7751_intc_of_init(struct device_node *intc,
+ struct device_node *parent)
+{
+ u16 icr;
+ struct irq_domain *domain;
+ void *intc_baseaddr;
+ void *intc_baseaddr2;
+
+ intc_baseaddr = of_iomap(intc, 0);
+ intc_baseaddr2 = of_iomap(intc, 1);
+ if (IS_ERR(intc_baseaddr)) {
+ pr_err("%s: Invalid register definition\n", intc->name);
+ return -EINVAL;
+ }
+
+ sh7751_regs.icr = intc_baseaddr;
+ sh7751_regs.ipr = intc_baseaddr + 4;
+ sh7751_regs.intpri00 = intc_baseaddr2;
+ sh7751_regs.intreq00 = intc_baseaddr2 + 0x20;
+ sh7751_regs.intmsk00 = intc_baseaddr2 + 0x40;
+ sh7751_regs.intmskclr00 = intc_baseaddr2 + 0x60;
+
+ if (of_property_read_bool(intc, "sh7751,irlm")) {
+ icr = __raw_readw(sh7751_regs.icr);
+ icr |= ICR_IRLM;
+ __raw_writew(icr, sh7751_regs.icr);
+ }
+
+ domain = irq_domain_add_linear(intc, NR_IRQS, &irq_ops, &sh7751_regs);
+ if (domain == NULL) {
+ pr_err("%s: cannot initialize irq domain\n", intc->name);
+ return -ENOMEM;
+ }
+
+ irq_set_default_host(domain);
+ return 0;
+}
+
+IRQCHIP_DECLARE(sh_7751_intc,
+ "renesas,sh7751-intc", sh7751_intc_of_init);
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 15/30] Documentation/devicetree: Add renesas,sh7751-intc binding document.
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (13 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 14/30] drivers/irqchip: Add SH7751 Internal INTC drivers Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-13 10:44 ` Krzysztof Kozlowski
2023-09-19 11:56 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 16/30] drivers/irqchip: SH7751 IRL external encoder with enable gate Yoshinori Sato
` (14 subsequent siblings)
29 siblings, 2 replies; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
.../renesas,sh7751-intc.yaml | 45 +++++++++++++++++++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
new file mode 100644
index 000000000000..0f0139545d77
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7751 Interrupt Controller
+
+maintainers:
+ - Yoshinori Sato <ysato@users.sourceforge.jp>
+
+properties:
+ compatible:
+ items:
+ - const: renesas,sh7751-intc
+
+ '#interrupt-cells':
+ # an interrupt index and flags, as defined in interrupts.txt in
+ # this directory
+ const: 2
+
+ interrupt-controller: true
+
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ sh7751,irlm:
+ description: If this value true. ICR.IRLM is 1.
+ $ref: /schemas/types.yaml#/definitions/bool
+
+required:
+ - compatible
+ - '#interrupt-cells'
+ - interrupt-controller
+ - reg
+
+examples:
+ - |
+ shintc: interrupt-controller@ffd00000 {
+ compatible = "renesas,sh7751-intc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0xffd00000 14>, <0xfe080000 128>;
+ };
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 16/30] drivers/irqchip: SH7751 IRL external encoder with enable gate.
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (14 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 15/30] Documentation/devicetree: Add renesas,sh7751-intc binding document Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-19 12:10 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 17/30] Documentation/devicetree: Add renesas,sh7751-irl-ext binding document Yoshinori Sato
` (13 subsequent siblings)
29 siblings, 1 reply; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
SH7751 have 15 level external interrupt.
It is typically connected to the CPU through a priority encoder
that can suppress requests.
This driver provides a way to control those hardware with irqchip.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/irqchip/Kconfig | 7 +
drivers/irqchip/Makefile | 2 +
drivers/irqchip/irq-renesas-sh7751irl.c | 183 ++++++++++++++++++++++++
3 files changed, 192 insertions(+)
create mode 100644 drivers/irqchip/irq-renesas-sh7751irl.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 167832daa903..9ea7fd49d7cb 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -688,4 +688,11 @@ config RENESAS_SH7751_INTC
Support for the Renesas SH7751 On-chip interrupt controller.
And external interrupt encoder for some targets.
+config RENESAS_SH7751IRL_INTC
+ bool "Renesas SH7751 based target IRL encoder support."
+ depends on RENESAS_SH7751_INTC
+ help
+ Support for External Interrupt encoder
+ on the some Renesas SH7751 based target.
+
endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 26c91d075e25..91df16726b1f 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -121,3 +121,5 @@ obj-$(CONFIG_APPLE_AIC) += irq-apple-aic.o
obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o
obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o
obj-$(CONFIG_RENESAS_SH7751_INTC) += irq-renesas-sh7751.o
+obj-$(CONFIG_RENESAS_SH7751IRL_INTC) += irq-renesas-sh7751irl.o
+
diff --git a/drivers/irqchip/irq-renesas-sh7751irl.c b/drivers/irqchip/irq-renesas-sh7751irl.c
new file mode 100644
index 000000000000..3aadf9336115
--- /dev/null
+++ b/drivers/irqchip/irq-renesas-sh7751irl.c
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SH7751 based board IRL encoder driver
+ * (Renesas RTS7751R2D / IO DATA DEVICE LANDISK, USL-5P)
+ *
+ * Copyright (C) 2023 Yoshinori Sato
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irqdomain.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+
+#define NUM_IRQ 15
+#define EXTIRQ_BASE 16
+
+struct sh7751irl_intc_priv {
+ void __iomem *base;
+ struct irq_domain *irq_domain;
+ int width;
+ int pol;
+ int nr_irq;
+ u32 enable_map[NUM_IRQ];
+};
+
+static inline u32 get_reg(void *addr, int w)
+{
+ switch (w) {
+ case 8:
+ return __raw_readb(addr);
+ case 16:
+ return __raw_readw(addr);
+ case 32:
+ return __raw_readl(addr);
+ }
+ return 0;
+}
+
+static inline void set_reg(void *addr, int w, u32 val)
+{
+ switch (w) {
+ case 8:
+ __raw_writeb(val, addr);
+ break;
+ case 16:
+ __raw_writew(val, addr);
+ break;
+ case 32:
+ __raw_writel(val, addr);
+ break;
+ }
+}
+
+static inline struct sh7751irl_intc_priv *irq_data_to_priv(struct irq_data *data)
+{
+ return data->domain->host_data;
+}
+
+static inline u32 set_reset_bit(int val, u32 in, int bit, int pol)
+{
+ val &= 1;
+ if (pol)
+ val ^= 1;
+ in &= ~(1 << bit);
+ return in | (val << bit);
+}
+
+static inline void mask_unmask(struct irq_data *data, int en)
+{
+ struct sh7751irl_intc_priv *priv = irq_data_to_priv(data);
+ int irq = data->irq - EXTIRQ_BASE;
+ u32 val;
+
+ if (priv->nr_irq > irq && priv->enable_map[irq] < priv->width) {
+ val = get_reg(priv->base, priv->width);
+ val = set_reset_bit(en, val, priv->enable_map[irq], priv->pol);
+ set_reg(priv->base, priv->width, val);
+ }
+}
+
+static void sh7751irl_intc_mask_irq(struct irq_data *data)
+{
+ mask_unmask(data, 0);
+}
+
+static void sh7751irl_intc_unmask_irq(struct irq_data *data)
+{
+ mask_unmask(data, 1);
+}
+
+static struct irq_chip sh7751irl_intc_chip = {
+ .name = "SH7751IRL-INTC",
+ .irq_unmask = sh7751irl_intc_unmask_irq,
+ .irq_mask = sh7751irl_intc_mask_irq,
+};
+
+static int sh7751irl_intc_map(struct irq_domain *h, unsigned int virq,
+ irq_hw_number_t hw_irq_num)
+{
+ irq_set_chip_and_handler(virq, &sh7751irl_intc_chip, handle_level_irq);
+ irq_get_irq_data(virq)->chip_data = h->host_data;
+ irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOPROBE);
+ return 0;
+}
+
+static int sh7751irl_intc_translate(struct irq_domain *domain,
+ struct irq_fwspec *fwspec, unsigned long *hwirq,
+ unsigned int *type)
+{
+ if (fwspec->param[0] >= NUM_IRQ)
+ return -EINVAL;
+
+ switch (fwspec->param_count) {
+ case 2:
+ *type = fwspec->param[1];
+ fallthrough;
+ case 1:
+ *hwirq = fwspec->param[0] + EXTIRQ_BASE;
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static const struct irq_domain_ops sh7751irl_intc_domain_ops = {
+ .map = sh7751irl_intc_map,
+ .translate = sh7751irl_intc_translate,
+};
+
+static int sh7751irl_init(struct device_node *node, struct device_node *parent)
+{
+ struct sh7751irl_intc_priv *priv;
+ struct irq_domain *d;
+ int ret = 0;
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->base = of_iomap(node, 0);
+ if (IS_ERR(priv->base)) {
+ ret = PTR_ERR(priv->base);
+ goto error;
+ }
+ of_property_read_u32(node, "sh7751irl,width", &priv->width);
+ if (priv->width != 8 && priv->width != 16 && priv->width != 32) {
+ pr_err("%s Invalid register width.\n", node->name);
+ ret = -EINVAL;
+ goto error;
+ }
+ of_property_read_u32(node, "sh7751irl,polarity", &priv->pol);
+ priv->nr_irq = of_property_count_u32_elems(node, "sh7751irl,irqbit");
+ if (priv->nr_irq <= 0 || priv->nr_irq >= NUM_IRQ) {
+ pr_err("%s sh7751irl: Invalid register definition.\n", node->name);
+ ret = -EINVAL;
+ goto error;
+ }
+ of_property_read_u32_array(node, "sh7751irl,irqbit", priv->enable_map, priv->nr_irq);
+
+ d = irq_domain_add_tree(node, &sh7751irl_intc_domain_ops, priv);
+ if (d == NULL) {
+ pr_err("%s: cannot initialize irq domain\n", node->name);
+ ret = -ENOMEM;
+ goto error;
+ }
+ priv->irq_domain = d;
+ irq_domain_update_bus_token(d, DOMAIN_BUS_WIRED);
+
+ return 0;
+error:
+ kfree(priv);
+ return ret;
+}
+
+IRQCHIP_DECLARE(renesas_sh7751_irl, "renesas,sh7751-irl-ext", sh7751irl_init);
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 17/30] Documentation/devicetree: Add renesas,sh7751-irl-ext binding document.
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (15 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 16/30] drivers/irqchip: SH7751 IRL external encoder with enable gate Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-13 10:45 ` Krzysztof Kozlowski
2023-09-19 12:08 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 18/30] drivers/clocksource: sh_tmu clocks property support Yoshinori Sato
` (12 subsequent siblings)
29 siblings, 2 replies; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
.../renesas,sh7751-irl-ext.yaml | 77 +++++++++++++++++++
1 file changed, 77 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
new file mode 100644
index 000000000000..dfc35717b92a
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-irl-ext.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7751 IRL external encoder with enable regs.
+
+maintainers:
+ - Yoshinori Sato <ysato@users.sourceforge.jp>
+
+description: |
+ This is the general used external interrupt encoder on SH7751 based boards.
+
+properties:
+ compatible:
+ items:
+ - const: renesas,sh7751-irl-ext
+
+ '#interrupt-cells':
+ # an interrupt index and flags, as defined in interrupts.txt in
+ # this directory
+ const: 2
+
+ interrupt-controller: true
+
+ reg:
+ minItems: 1
+
+ sh7751irl,width:
+ description: Enable register width
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ sh7751irl,polarity:
+ description: Enable register polarity
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ sh7751irl,irqbit:
+ description: IRQ to enable register bit mapping
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
+
+required:
+ - compatible
+ - '#interrupt-cells'
+ - interrupt-controller
+ - reg
+ - sh7751irl,width
+ - sh7751irl,polarity
+ - sh7751,irqbit
+
+additionalProperties: false
+
+examples:
+ - |
+ r2dintc: sh7751irl_encoder@a4000000 {
+ compatible = "renesas,sh7751-irl-ext";
+ reg = <0xa4000000 0x02>;
+ interrupt-controller;
+ #address-cells = <1>;
+ #interrupt-cells = <2>;
+ sh7751irl,width = <16>;
+ sh7751irl,polarity = <0>;
+ sh7751irl,irqbit =<11>, /* PCI INTD */
+ <9>, /* CF IDE */
+ <8>, /* CF CD */
+ <12>, /* PCI INTC */
+ <10>, /* SM501 */
+ <6>, /* KEY */
+ <5>, /* RTC ALARM */
+ <4>, /* RTC T */
+ <7>, /* SDCARD */
+ <14>, /* PCI INTA */
+ <13>, /* PCI INTB */
+ <0>, /* EXT */
+ <15>; /* TP */
+ };
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 18/30] drivers/clocksource: sh_tmu clocks property support.
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (16 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 17/30] Documentation/devicetree: Add renesas,sh7751-irl-ext binding document Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-19 12:15 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 19/30] drivers/tty: sh-sci fix SH4 OF support Yoshinori Sato
` (11 subsequent siblings)
29 siblings, 1 reply; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/clocksource/sh_tmu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c
index beffff81c00f..878324986f49 100644
--- a/drivers/clocksource/sh_tmu.c
+++ b/drivers/clocksource/sh_tmu.c
@@ -537,6 +537,9 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
/* Get hold of clock. */
tmu->clk = clk_get(&tmu->pdev->dev, "fck");
+ if (IS_ERR(tmu->clk) && IS_ENABLED(CONFIG_OF) && pdev->dev.of_node)
+ /* use DeviceTree clocks property */
+ tmu->clk = devm_clk_get(&tmu->pdev->dev, NULL);
if (IS_ERR(tmu->clk)) {
dev_err(&tmu->pdev->dev, "cannot get clock\n");
return PTR_ERR(tmu->clk);
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 19/30] drivers/tty: sh-sci fix SH4 OF support.
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (17 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 18/30] drivers/clocksource: sh_tmu clocks property support Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-19 12:25 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 20/30] drivers/mfd: sm501 add some properties Yoshinori Sato
` (10 subsequent siblings)
29 siblings, 1 reply; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
- fix earlycon name.
- fix earlyprintk hung (NULL pointer reference).
- clocks property support.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/tty/serial/sh-sci.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index a560b729fa3b..7ff1733d3368 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -2720,7 +2720,7 @@ static int sci_remap_port(struct uart_port *port)
if (port->membase)
return 0;
- if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
+ if ((port->dev && port->dev->of_node) || (port->flags & UPF_IOREMAP)) {
port->membase = ioremap(port->mapbase, sport->reg_size);
if (unlikely(!port->membase)) {
dev_err(port->dev, "can't remap port#%d\n", port->line);
@@ -2842,6 +2842,8 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
* global "peripheral_clk" clock.
*/
clk = devm_clk_get(dev, "peripheral_clk");
+ if (IS_ERR(clk))
+ clk = devm_clk_get(dev, NULL);
if (IS_ERR(clk))
return dev_err_probe(dev, PTR_ERR(clk),
"failed to get %s\n",
@@ -3555,8 +3557,8 @@ static int __init hscif_early_console_setup(struct earlycon_device *device,
OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
-OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
-OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
+OF_EARLYCON_DECLARE(rzscif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
+OF_EARLYCON_DECLARE(rzscif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 20/30] drivers/mfd: sm501 add some properties.
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (18 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 19/30] drivers/tty: sh-sci fix SH4 OF support Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-20 12:25 ` Lee Jones
2023-09-13 9:23 ` [RFC PATCH v2 21/30] Documentation/devicetree: sm501fb add properies Yoshinori Sato
` (9 subsequent siblings)
29 siblings, 1 reply; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz, lee
SM501's OF support is not enough parameter in platform device.
This change adds the missing parameter.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/mfd/sm501.c | 113 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 113 insertions(+)
diff --git a/drivers/mfd/sm501.c b/drivers/mfd/sm501.c
index 28027982cf69..82508f6d96da 100644
--- a/drivers/mfd/sm501.c
+++ b/drivers/mfd/sm501.c
@@ -1370,6 +1370,113 @@ static int sm501_init_dev(struct sm501_devdata *sm)
return 0;
}
+#if defined(CONFIG_OF)
+static unsigned int sm501_parse_devices_str(struct device_node *np)
+{
+ unsigned int device = 0;
+ unsigned int i, j;
+ unsigned int nstr;
+ const char *devstr;
+ static const struct {
+ char *devname;
+ unsigned int devid;
+ } devlist[] = {
+ { "usb-host", SM501_USE_USB_HOST },
+ { "usb-gadget", SM501_USE_USB_SLAVE },
+ { "ssp0", SM501_USE_SSP0 },
+ { "ssp1", SM501_USE_SSP1 },
+ { "uart0", SM501_USE_UART0 },
+ { "uart1", SM501_USE_UART1 },
+ { "accel", SM501_USE_FBACCEL },
+ { "ac97", SM501_USE_AC97 },
+ { "i2s", SM501_USE_I2S },
+ { "gpio", SM501_USE_GPIO },
+ { "all", SM501_USE_ALL },
+ };
+
+ nstr = of_property_count_strings(np, "sm501,devices");
+ for (i = 0; i < nstr; i++) {
+ if (of_property_read_string_index(np, "sm501,devices", i, &devstr))
+ break;
+ for (j = 0; j < ARRAY_SIZE(devlist); j++) {
+ if (strcmp(devstr, devlist[j].devname) == 0) {
+ device |= devlist[j].devid;
+ goto next;
+ }
+ }
+next:
+ }
+ return device;
+}
+
+static void sm501_of_read_reg_init(struct device_node *np,
+ const char *propname, struct sm501_reg_init *val)
+{
+ u32 u32_val[2];
+
+ if (!of_property_read_u32_array(np, propname, u32_val, sizeof(u32_val))) {
+ val->set = u32_val[0];
+ val->mask = u32_val[1];
+ } else {
+ val->set = 0;
+ val->mask = 0;
+ }
+}
+
+static int sm501_parse_dt(struct sm501_devdata *sm, struct device_node *np)
+{
+ struct sm501_platdata *plat;
+ u32 u32_val;
+
+ plat = devm_kzalloc(sm->dev, sizeof(struct sm501_platdata), GFP_KERNEL);
+ if (plat == NULL)
+ return -ENOMEM;
+
+ plat->init = devm_kzalloc(sm->dev, sizeof(struct sm501_initdata), GFP_KERNEL);
+ if (plat->init == NULL)
+ return -ENOMEM;
+
+ plat->init->devices = sm501_parse_devices_str(np);
+
+ if (!of_property_read_u32_index(np, "sm501,mclk", 0, &u32_val))
+ plat->init->mclk = u32_val;
+ else
+ plat->init->mclk = 0;
+
+ if (!of_property_read_u32_index(np, "sm501,m1xclk", 0, &u32_val))
+ plat->init->m1xclk = u32_val;
+ else
+ plat->init->m1xclk = 0;
+
+ sm501_of_read_reg_init(np, "sm501,misc-timing", &plat->init->misc_timing);
+ sm501_of_read_reg_init(np, "sm501,misc-control", &plat->init->misc_control);
+ sm501_of_read_reg_init(np, "sm501,gpio-low", &plat->init->gpio_low);
+ sm501_of_read_reg_init(np, "sm501,gpio-high", &plat->init->gpio_high);
+
+#ifdef CONFIG_MFD_SM501_GPIO
+ if (plat->init->devices & SM501_USE_GPIO) {
+ if (!of_property_read_u32_index(np, "sm501,num-i2c", 0, &u32_val))
+ plat->gpio_i2c_nr = u32_val;
+ else
+ plat->gpio_i2c_nr = 0;
+ }
+ if (plat->gpio_i2c_nr > 0) {
+ int sz_gpio;
+
+ sz_gpio = sizeof(struct sm501_platdata_gpio_i2c) * plat->gpio_i2c_nr;
+ plat->gpio_i2c = devm_kzalloc(sm->dev, sz_gpio, GFP_KERNEL);
+ if (plat->gpio_i2c == NULL)
+ return -ENOMEM;
+
+ of_property_read_variable_u32(np, "sm501,gpio-i2c",
+ plat->gpio_i2c, plat->gpio_i2c_nr * 5);
+ }
+#endif
+ sm->platdata = plat;
+ return 0;
+}
+#endif
+
static int sm501_plat_probe(struct platform_device *dev)
{
struct sm501_devdata *sm;
@@ -1406,6 +1513,12 @@ static int sm501_plat_probe(struct platform_device *dev)
goto err_res;
}
+ if (IS_ENABLED(CONFIG_OF) && dev->dev.of_node) {
+ ret = sm501_parse_dt(sm, dev->dev.of_node);
+ if (ret)
+ goto err_res;
+ }
+
platform_set_drvdata(dev, sm);
sm->regs = ioremap(sm->io_res->start, resource_size(sm->io_res));
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 21/30] Documentation/devicetree: sm501fb add properies.
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (19 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 20/30] drivers/mfd: sm501 add some properties Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-13 10:45 ` Krzysztof Kozlowski
2023-09-13 9:23 ` [RFC PATCH v2 22/30] arch/sh: Add dtbs target support Yoshinori Sato
` (8 subsequent siblings)
29 siblings, 1 reply; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
SM501's OF support is not enough parameter in platform device.
This change adds the missing parameter.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
Documentation/devicetree/bindings/display/sm501fb.txt | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/sm501fb.txt b/Documentation/devicetree/bindings/display/sm501fb.txt
index 1c79c267a57f..4c4920394431 100644
--- a/Documentation/devicetree/bindings/display/sm501fb.txt
+++ b/Documentation/devicetree/bindings/display/sm501fb.txt
@@ -20,6 +20,17 @@ Optional properties:
set different foreign endian.
- big-endian: available on little endian systems, to
set different foreign endian.
+- sm501,devices: select peripheral functions.
+ available usb-host, usb-gadget, ssp0, ssp,1 uart0, uart1, accel,
+ ac97, i2s, gpio and all.
+- sm501,mclk: SM501 mclk frequency.
+- sm501,m1xclk: SM501 m1xclk frequency.
+- sm501,misc-timing: SM501 Miscellaneous Timing reg value.
+- sm501,misc-control: SM501 Miscellaneous Control reg value.
+- sm501,gpio-low: SM501 GPIO31-0 Control reg value.
+- sm501,gpio-high: SM501 GPIO63-32 Control reg value.
+- sm501,num-i2c: I2C channel number.
+- sm501,gpio-i2c: I2C assigned GPIO.
Example for MPC5200:
display@1,0 {
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 22/30] arch/sh: Add dtbs target support.
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (20 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 21/30] Documentation/devicetree: sm501fb add properies Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-19 12:28 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 23/30] arch/sh: Add SH7751 SoC Internal periphreal devicetree Yoshinori Sato
` (7 subsequent siblings)
29 siblings, 1 reply; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/boot/dts/Makefile | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/sh/boot/dts/Makefile b/arch/sh/boot/dts/Makefile
index 4a6dec9714a9..e6b93360c213 100644
--- a/arch/sh/boot/dts/Makefile
+++ b/arch/sh/boot/dts/Makefile
@@ -1,2 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_USE_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_SOURCE))
+
+dtb-$(CONFIG_CPU_J2) += j2_mimas_v2.dtb
+dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += landisk.dtb
+dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += rts7751r2dplus.dtb
+dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += usl-5p.dtb
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 23/30] arch/sh: Add SH7751 SoC Internal periphreal devicetree.
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (21 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 22/30] arch/sh: Add dtbs target support Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-13 10:49 ` Krzysztof Kozlowski
` (2 more replies)
2023-09-13 9:23 ` [RFC PATCH v2 24/30] include/dt-bindings: Add SH7750 CPG header Yoshinori Sato
` (6 subsequent siblings)
29 siblings, 3 replies; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/boot/dts/sh7751.dtsi | 76 ++++++++++++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
create mode 100644 arch/sh/boot/dts/sh7751.dtsi
diff --git a/arch/sh/boot/dts/sh7751.dtsi b/arch/sh/boot/dts/sh7751.dtsi
new file mode 100644
index 000000000000..749eab3bce9f
--- /dev/null
+++ b/arch/sh/boot/dts/sh7751.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the SH7751 SoC
+ */
+
+#include <dt-bindings/interrupt-controller/sh_intc.h>
+#include <dt-bindings/clock/sh7750.h>
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ compatible = "renesas,sh7751r","renesas,sh4", "renesas,sh";
+ };
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ cpg: cpg@ffc00000 {
+ #clock-cells = <1>;
+ compatible = "renesas,sh7750-cpg";
+ clocks = <&xtal>;
+ reg = <0xffc00000 2>, <0xffc00008 4>;
+ };
+
+ };
+
+ shintc: interrupt-controller@ffd00000 {
+ compatible = "renesas,sh7751-intc";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0xffd00000 14>, <0xfe080000 128>;
+ };
+
+ /* sci0 is rarely used, so it is not defined here. */
+ scif1: serial@ffe80000 {
+ compatible = "renesas,scif";
+ reg = <0xffe80000 0x100>;
+ interrupts = <evt2irq(0x700) 0>,
+ <evt2irq(0x720) 0>,
+ <evt2irq(0x760) 0>,
+ <evt2irq(0x740) 0>;
+ interrupt-names = "eri", "rxi", "bri", "txi";
+ clocks = <&cpg SH7750_CPG_FCK>;
+ };
+
+ /* Normally ch0 and ch1 are used, so we will define ch0 to ch2 here. */
+ tmu0: timer@ffd80008 {
+ compatible = "renesas,tmu";
+ reg = <0xffd80000 12>;
+ interrupts = <evt2irq(0x400) 0>,
+ <evt2irq(0x420) 0>,
+ <evt2irq(0x440) 0>,
+ <evt2irq(0x460) 0>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
+ clocks = <&cpg SH7750_CPG_FCK>;
+ renesas,channels = <3>;
+ };
+
+ pci@fe200000 {
+ compatible = "renesas,sh7751-pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0 0xfd000000 0xfd000000 0 0x01000000>,
+ <0x01000000 0 0xfe240000 0xfe240000 0 0x00040000>;
+ reg = <0xfe200000 0x0400>,
+ <0x0c000000 0x04000000>,
+ <0xff800000 0x0030>;
+ #interrupt-cells = <1>;
+ };
+};
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 24/30] include/dt-bindings: Add SH7750 CPG header.
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (22 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 23/30] arch/sh: Add SH7751 SoC Internal periphreal devicetree Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-13 10:46 ` Krzysztof Kozlowski
2023-09-19 12:46 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 25/30] include/dt-bindings: Add sh_intc IRQ - EVT conversion helper Yoshinori Sato
` (5 subsequent siblings)
29 siblings, 2 replies; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
include/dt-bindings/clock/sh7750.h | 13 +++++++++++++
1 file changed, 13 insertions(+)
create mode 100644 include/dt-bindings/clock/sh7750.h
diff --git a/include/dt-bindings/clock/sh7750.h b/include/dt-bindings/clock/sh7750.h
new file mode 100644
index 000000000000..88e60a9a01df
--- /dev/null
+++ b/include/dt-bindings/clock/sh7750.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright 2023 Yoshinori Sato
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_SH7750_H__
+#define __DT_BINDINGS_CLOCK_SH7750_H__
+
+#define SH7750_CPG_FCK 0
+#define SH7750_CPG_BCK 1
+#define SH7750_CPG_ICK 2
+
+#endif
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 25/30] include/dt-bindings: Add sh_intc IRQ - EVT conversion helper
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (23 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 24/30] include/dt-bindings: Add SH7750 CPG header Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-13 10:47 ` Krzysztof Kozlowski
2023-09-19 13:05 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 26/30] arch/sh: RTS7751R2D Plus DeviceTree Yoshinori Sato
` (4 subsequent siblings)
29 siblings, 2 replies; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/boot/dts/include/dt-bindings | 1 +
include/dt-bindings/interrupt-controller/sh_intc.h | 7 +++++++
2 files changed, 8 insertions(+)
create mode 120000 arch/sh/boot/dts/include/dt-bindings
create mode 100644 include/dt-bindings/interrupt-controller/sh_intc.h
diff --git a/arch/sh/boot/dts/include/dt-bindings b/arch/sh/boot/dts/include/dt-bindings
new file mode 120000
index 000000000000..08c00e4972fa
--- /dev/null
+++ b/arch/sh/boot/dts/include/dt-bindings
@@ -0,0 +1 @@
+../../../../../include/dt-bindings
\ No newline at end of file
diff --git a/include/dt-bindings/interrupt-controller/sh_intc.h b/include/dt-bindings/interrupt-controller/sh_intc.h
new file mode 100644
index 000000000000..cab546fba396
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/sh_intc.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * SH3/4 INTC EVT - IRQ conversion
+ */
+
+#define evt2irq(evt) ((evt) >> 5)
+#define irq2evt(irq) ((irq) << 5)
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 26/30] arch/sh: RTS7751R2D Plus DeviceTree.
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (24 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 25/30] include/dt-bindings: Add sh_intc IRQ - EVT conversion helper Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-13 10:49 ` Krzysztof Kozlowski
` (2 more replies)
2023-09-13 9:23 ` [RFC PATCH v2 27/30] arch/sh: LANDISK DeviceTree Yoshinori Sato
` (3 subsequent siblings)
29 siblings, 3 replies; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/boot/dts/rts7751r2dplus.dts | 124 ++++++++++++++++++++++++++++
1 file changed, 124 insertions(+)
create mode 100644 arch/sh/boot/dts/rts7751r2dplus.dts
diff --git a/arch/sh/boot/dts/rts7751r2dplus.dts b/arch/sh/boot/dts/rts7751r2dplus.dts
new file mode 100644
index 000000000000..a08061133841
--- /dev/null
+++ b/arch/sh/boot/dts/rts7751r2dplus.dts
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Renesas RTS7751R2D Plus
+ */
+
+/dts-v1/;
+
+#include "sh7751.dtsi"
+
+/ {
+ model = "Renesas RTS7715R2D Plus";
+ compatible = "renesas,r2dplus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&shintc>;
+
+ aliases {
+ serial0 = &scif1;
+ };
+
+ chosen {
+ };
+
+ clocks {
+ xtal: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <22222222>;
+ };
+
+ cpg: cpg@ffc00000 {
+ compatible = "renesas,sh7750r-cpg",
+ "renesas,sh7750-cpg";
+ renesas,mode = <5>;
+ };
+ };
+
+ cpus {
+ cpu@0 {
+ clock-frequency = <266666666>;
+ };
+ };
+
+ memory@c000000 {
+ device_type = "memory";
+ reg = <0x0c000000 0x4000000>;
+ };
+
+ r2dintc: sh7751irl_encoder@a4000000 {
+ compatible = "renesas,sh7751-irl-ext";
+ reg = <0xa4000000 0x02>;
+ interrupt-controller;
+ #address-cells = <1>;
+ #interrupt-cells = <2>;
+ sh7751irl,width = <16>;
+ sh7751irl,polarity = <0>;
+ sh7751irl,irqbit =<11>, /* PCI INTD */
+ <9>, /* CF IDE */
+ <8>, /* CF CD */
+ <12>, /* PCI INTC */
+ <10>, /* SM501 */
+ <6>, /* KEY */
+ <5>, /* RTC ALARM */
+ <4>, /* RTC T */
+ <7>, /* SDCARD */
+ <14>, /* PCI INTA */
+ <13>, /* PCI INTB */
+ <0>, /* EXT */
+ <15>; /* TP */
+ };
+
+ display@1,0 {
+ compatible = "smi,sm501";
+ reg = <0x10000000 0x03e00000
+ 0x13e00000 0x00200000>;
+ interrupt-parent = <&r2dintc>;
+ interrupts = <4 0>;
+ mode = "640x480-16@60";
+ little-endian;
+ sm501,devices = "usb-host","uart0";
+ };
+
+ compact-flash@b4001000 {
+ compatible = "ata-generic";
+ reg = <0xb4001000 0x0e>, <0xb400080c 2>;
+ reg-shift = <1>;
+ interrupt-parent = <&r2dintc>;
+ interrupts = <1 0>;
+ };
+
+ flash@0 {
+ compatible = "cfi-flash";
+ reg = <0x00000000 0x02000000>;
+ device-width = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "U-Boot";
+ reg = <0x00000000 0x00040000>;
+ };
+ partition@1 {
+ label = "Environemt";
+ reg = <0x00040000 0x00040000>;
+ };
+ partition@2 {
+ label = "Kernel";
+ reg = <0x00080000 0x001c0000>;
+ };
+ partition@3 {
+ label = "Flash_FS";
+ reg = <0x00240000 0x00dc0000>;
+ };
+ };
+
+ pci@fe200000 {
+ compatible = "renesas,r2d-pci", "renesas,sh7751-pci";
+ #interrupt-cells = <1>;
+ interrupt-parent = <&r2dintc>;
+ eth@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ interrupts = <3 0>;
+ };
+ };
+};
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 27/30] arch/sh: LANDISK DeviceTree.
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (25 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 26/30] arch/sh: RTS7751R2D Plus DeviceTree Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-13 9:23 ` [RFC PATCH v2 28/30] arch/sh: USL-5P DeviceTree Yoshinori Sato
` (2 subsequent siblings)
29 siblings, 0 replies; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/boot/dts/landisk.dts | 103 +++++++++++++++++++++++++++++++++++
1 file changed, 103 insertions(+)
create mode 100644 arch/sh/boot/dts/landisk.dts
diff --git a/arch/sh/boot/dts/landisk.dts b/arch/sh/boot/dts/landisk.dts
new file mode 100644
index 000000000000..1d76fbd6923b
--- /dev/null
+++ b/arch/sh/boot/dts/landisk.dts
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the IO DATA DEVICE LANDISK
+ */
+
+
+/dts-v1/;
+
+#include "sh7751.dtsi"
+
+/ {
+ model = "IO-DATA Device LANDISK";
+ compatible = "iodata,landisk", "renesas,sh7751r";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&shintc>;
+
+ aliases {
+ serial0 = &scif1;
+ };
+
+ chosen {
+ stdout-path = "serial0:9600n8";
+ };
+
+ clocks {
+ xtal: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <22222222>;
+ };
+
+ cpg: cpg@ffc00000 {
+ compatible = "renesas,sh7750r-cpg",
+ "renesas,sh7750-cpg";
+ renesas,mode = <5>;
+ };
+ };
+
+ cpus {
+ cpu@0 {
+ clock-frequency = <266666666>;
+ };
+ };
+ memory@c000000 {
+ device_type = "memory";
+ reg = <0x0c000000 0x4000000>;
+ };
+
+ julianintc: sh7751irl_encoder@a4000000 {
+ compatible = "renesas,sh7751-irl-ext";
+ reg = <0xb0000005 0x01>;
+ interrupt-controller;
+ #address-cells = <1>;
+ #interrupt-cells = <2>;
+ sh7751irl,width = <8>;
+ sh7751irl,polarity = <0>;
+ sh7751irl,irqbit = <0xffffffff>, /* Not use */
+ <0xffffffff>,
+ <0xffffffff>,
+ <0xffffffff>,
+ <0xffffffff>,
+ <0>, /* PCI INTA */
+ <1>, /* PCI INTB */
+ <2>, /* PCI INTC */
+ <3>, /* PCI INTD */
+ <4>, /* ATA */
+ <5>, /* CF */
+ <6>, /* Power Switch */
+ <7>; /* Button */
+ };
+
+ pci@fe200000 {
+ compatible = "iodata,julian-pci", "renesas,sh7751-pci";
+ #interrupt-cells = <1>;
+ interrupt-parent = <&julianintc>;
+ eth@0,0 {
+ reg = <0x0000 0 0 0 0>;
+ interrupts = <5 0>;
+ interrupt-names = "eth";
+ };
+ ata@1,0 {
+ reg = <0x0800 0 0 0 0>;
+ interrupts = <6 0>;
+ interrupt-names = "ata";
+ };
+ usb@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ interrupts = <7 0>;
+ interrupt-names = "ochi";
+ };
+ usb@2,1 {
+ reg = <0x1100 0 0 0 0>;
+ interrupts = <8 0>;
+ interrupt-names = "ohci";
+ };
+ usb@2,2 {
+ reg = <0x1200 0 0 0 0>;
+ interrupts = <5 0>;
+ interrupt-names = "ehci";
+ };
+ };
+};
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 28/30] arch/sh: USL-5P DeviceTree.
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (26 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 27/30] arch/sh: LANDISK DeviceTree Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-13 9:23 ` [RFC PATCH v2 29/30] arch/sh: RTS7751R2D Plus OF defconfig Yoshinori Sato
2023-09-13 9:23 ` [RFC PATCH v2 30/30] arch/sh: LANDISK " Yoshinori Sato
29 siblings, 0 replies; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/boot/dts/usl-5p.dts | 106 ++++++++++++++++++++++++++++++++++++
1 file changed, 106 insertions(+)
create mode 100644 arch/sh/boot/dts/usl-5p.dts
diff --git a/arch/sh/boot/dts/usl-5p.dts b/arch/sh/boot/dts/usl-5p.dts
new file mode 100644
index 000000000000..574e26cc6191
--- /dev/null
+++ b/arch/sh/boot/dts/usl-5p.dts
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the IO DATA DEVICE USL-5P
+ */
+
+/dts-v1/;
+
+#include "sh7751.dtsi"
+
+/ {
+ model = "IO-DATA Device USL-5P";
+ compatible = "iodata,usl-5p";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&shintc>;
+
+ aliases {
+ serial0 = &scif1;
+ };
+
+ chosen {
+ stdout-path = "serial0:9600n8";
+ };
+
+ clocks {
+ xtal: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <22222222>;
+ };
+
+ cpg: cpg@ffc00000 {
+ compatible = "renesas,sh7750r-cpg",
+ "renesas,sh7750-cpg";
+ renesas,mode = <5>;
+ };
+ };
+
+ cpus {
+ cpu@0 {
+ clock-frequency = <266666666>;
+ };
+ };
+
+ memory@c000000 {
+ device_type = "memory";
+ reg = <0x0c000000 0x4000000>;
+ };
+
+ julianintc: sh7751irl_encoder@a4000000 {
+ compatible ="renesas,sh7751-irl-ext";
+ reg = <0xb0000005 0x01>;
+ interrupt-controller;
+ #address-cells = <1>;
+ #interrupt-cells = <2>;
+ sh7751irl,width = <8>;
+ sh7751irl,polarity = <0>;
+ sh7751irl,irqbit = <0xffffffff>, /* Not use */
+ <0xffffffff>,
+ <0xffffffff>,
+ <0xffffffff>,
+ <0xffffffff>,
+ <0>, /* PCI INTA */
+ <1>, /* PCI INTB */
+ <2>, /* PCI INTC */
+ <3>, /* PCI INTD */
+ <4>, /* ATA */
+ <5>, /* CF */
+ <6>, /* Power Switch */
+ <7>; /* Button */
+ };
+
+ compact-flash@b4001000 {
+ compatible = "ata-generic";
+ reg = <0xb4000040 0x0e>, <0xb400002c 2>;
+ reg-shift = <1>;
+ interrupt-parent = <&julianintc>;
+ interrupts = <10 0>;
+ };
+
+ pci@fe200000 {
+ compatible = "iodata,julian-pci", "renesas,sh7751-pci";
+ #interrupt-cells = <1>;
+ interrupt-parent = <&julianintc>;
+ eth@0,0 {
+ reg = <0x0000 0 0 0 0>;
+ interrupts = <5 0>;
+ interrupt-names = "eth";
+ };
+ usb@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ interrupts = <7 0>;
+ interrupt-names = "ochi";
+ };
+ usb@2,1 {
+ reg = <0x1100 0 0 0 0>;
+ interrupts = <8 0>;
+ interrupt-names = "ohci";
+ };
+ usb@2,2 {
+ reg = <0x1200 0 0 0 0>;
+ interrupts = <5 0>;
+ interrupt-names = "ehci";
+ };
+ };
+};
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 29/30] arch/sh: RTS7751R2D Plus OF defconfig
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (27 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 28/30] arch/sh: USL-5P DeviceTree Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
2023-09-13 9:23 ` [RFC PATCH v2 30/30] arch/sh: LANDISK " Yoshinori Sato
29 siblings, 0 replies; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/configs/rts7751r2dplus-of_defconfig | 93 +++++++++++++++++++++
1 file changed, 93 insertions(+)
create mode 100644 arch/sh/configs/rts7751r2dplus-of_defconfig
diff --git a/arch/sh/configs/rts7751r2dplus-of_defconfig b/arch/sh/configs/rts7751r2dplus-of_defconfig
new file mode 100644
index 000000000000..0313009433bd
--- /dev/null
+++ b/arch/sh/configs/rts7751r2dplus-of_defconfig
@@ -0,0 +1,93 @@
+CONFIG_SYSVIPC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_NAMESPACES=y
+CONFIG_EXPERT=y
+CONFIG_PROFILING=y
+CONFIG_CPU_SUBTYPE_SH7751R=y
+CONFIG_MEMORY_START=0x0c000000
+CONFIG_SH_OF_BOARD=y
+CONFIG_HEARTBEAT=y
+CONFIG_CMDLINE_OVERWRITE=y
+CONFIG_CMDLINE="console=tty0 console=ttySC1,115200 root=/dev/sda1"
+CONFIG_MODULES=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IPV6 is not set
+CONFIG_PCI=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_UEVENT_HELPER=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_ATA=y
+CONFIG_PATA_OF_PLATFORM=y
+CONFIG_NETDEVICES=y
+CONFIG_8139TOO=y
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_EARLYCON=y
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+CONFIG_SPI_SH_SCI=y
+CONFIG_MFD_SM501=y
+CONFIG_FB=y
+CONFIG_FB_SH_MOBILE_LCDC=m
+CONFIG_FB_SM501=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+# CONFIG_LOGO_LINUX_CLUT224 is not set
+# CONFIG_LOGO_SUPERH_MONO is not set
+# CONFIG_LOGO_SUPERH_VGA16 is not set
+CONFIG_SOUND=y
+CONFIG_SND=m
+CONFIG_SND_YMFPCI=m
+CONFIG_HID_A4TECH=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_ITE=y
+CONFIG_HID_KENSINGTON=y
+CONFIG_HID_REDRAGON=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_PANTHERLORD=y
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SUNPLUS=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_R9701=y
+CONFIG_RENESAS_SH7751_INTC=y
+CONFIG_RENESAS_SH7751IRL_INTC=y
+CONFIG_EXT2_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_MINIX_FS=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_INIT_STACK_NONE=y
+CONFIG_CRC_T10DIF=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_FTRACE is not set
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH v2 30/30] arch/sh: LANDISK OF defconfig
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
` (28 preceding siblings ...)
2023-09-13 9:23 ` [RFC PATCH v2 29/30] arch/sh: RTS7751R2D Plus OF defconfig Yoshinori Sato
@ 2023-09-13 9:23 ` Yoshinori Sato
29 siblings, 0 replies; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-13 9:23 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/configs/landisk-of_defconfig | 110 +++++++++++++++++++++++++++
1 file changed, 110 insertions(+)
create mode 100644 arch/sh/configs/landisk-of_defconfig
diff --git a/arch/sh/configs/landisk-of_defconfig b/arch/sh/configs/landisk-of_defconfig
new file mode 100644
index 000000000000..f7c9b7d756e3
--- /dev/null
+++ b/arch/sh/configs/landisk-of_defconfig
@@ -0,0 +1,110 @@
+CONFIG_SYSVIPC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_NAMESPACES=y
+CONFIG_EXPERT=y
+CONFIG_CPU_SUBTYPE_SH7751R=y
+CONFIG_MEMORY_START=0x0c000000
+CONFIG_SH_OF_BOARD=y
+CONFIG_HEARTBEAT=y
+CONFIG_KEXEC=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_PNP=y
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+CONFIG_ATALK=m
+CONFIG_PCI=y
+CONFIG_PCCARD=y
+CONFIG_YENTA=y
+CONFIG_UEVENT_HELPER=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_ATA=y
+CONFIG_PATA_ATP867X=y
+CONFIG_PATA_OF_PLATFORM=y
+CONFIG_ATA_GENERIC=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_NETDEVICES=y
+CONFIG_TUN=m
+CONFIG_8139CP=y
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_EARLYCON=y
+CONFIG_HW_RANDOM=y
+CONFIG_SOUND=m
+CONFIG_HID_A4TECH=m
+CONFIG_HID_BELKIN=m
+CONFIG_HID_CHERRY=m
+CONFIG_HID_CHICONY=m
+CONFIG_HID_CYPRESS=m
+CONFIG_HID_EZKEY=m
+CONFIG_HID_GYRATION=m
+CONFIG_HID_ITE=y
+CONFIG_HID_KENSINGTON=y
+CONFIG_HID_REDRAGON=y
+CONFIG_HID_MICROSOFT=m
+CONFIG_HID_MONTEREY=m
+CONFIG_HID_PANTHERLORD=m
+CONFIG_HID_PETALYNX=m
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SUNPLUS=m
+CONFIG_USB_HID=m
+CONFIG_USB=y
+CONFIG_USB_MON=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_PRINTER=m
+CONFIG_USB_STORAGE=m
+CONFIG_USB_STORAGE_DATAFAB=m
+CONFIG_USB_STORAGE_FREECOM=m
+CONFIG_USB_STORAGE_ISD200=m
+CONFIG_USB_STORAGE_SDDR09=m
+CONFIG_USB_STORAGE_SDDR55=m
+CONFIG_USB_STORAGE_JUMPSHOT=m
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_EMI62=m
+CONFIG_USB_EMI26=m
+CONFIG_USB_SISUSBVGA=m
+CONFIG_RENESAS_SH7751_INTC=y
+CONFIG_RENESAS_SH7751IRL_INTC=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+CONFIG_REISERFS_FS=y
+CONFIG_ISO9660_FS=m
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=m
+CONFIG_NTFS_RW=y
+CONFIG_TMPFS=y
+CONFIG_ROMFS_FS=y
+CONFIG_UFS_FS=m
+CONFIG_NFS_FS=m
+CONFIG_NFSD=m
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_INIT_STACK_NONE=y
+CONFIG_CRC_T10DIF=y
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_FTRACE is not set
+CONFIG_SH_STANDARD_BIOS=y
--
2.39.2
^ permalink raw reply related [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 09/30] Documentation/devicetree: Add renesas,sh7751-pci binding document.
2023-09-13 9:23 ` [RFC PATCH v2 09/30] Documentation/devicetree: Add renesas,sh7751-pci binding document Yoshinori Sato
@ 2023-09-13 10:42 ` Krzysztof Kozlowski
2023-09-18 15:41 ` Geert Uytterhoeven
1 sibling, 0 replies; 83+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-13 10:42 UTC (permalink / raw)
To: Yoshinori Sato, linux-sh; +Cc: glaubitz, linux-pci
On 13/09/2023 11:23, Yoshinori Sato wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
You did not resolve several comments from previous version. I don't
understand why, so I just assume this is not ready for review. Just
quick look tells this wasn't tested and has multiple issues. Maybe that
was the intention, but nothing is described in commit log confirming
such intention.
Therefore to be clear: that's a NAK.
Also, standard template:
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC. It might happen, that command when run on an older
kernel, gives you outdated entries. Therefore please be sure you base
your patches on recent Linux kernel.
You missed at least devicetree list (maybe more), so this won't be
tested by automated tooling. Performing review on untested code might be
a waste of time, thus I will skip this patch entirely till you follow
the process allowing the patch to be tested.
Please kindly resend and include all necessary To/Cc entries.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 10/30] drivers/clk: SH7750 / SH7751 CPG Driver
2023-09-13 9:23 ` [RFC PATCH v2 10/30] drivers/clk: SH7750 / SH7751 CPG Driver Yoshinori Sato
@ 2023-09-13 10:43 ` Krzysztof Kozlowski
2023-09-18 16:05 ` Geert Uytterhoeven
1 sibling, 0 replies; 83+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-13 10:43 UTC (permalink / raw)
To: Yoshinori Sato, linux-sh; +Cc: glaubitz, linux-clk
On 13/09/2023 11:23, Yoshinori Sato wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
1. Commit msg did not improve.
2. Please use subject prefixes matching the subsystem. You can get them
for example with `git log --oneline -- DIRECTORY_OR_FILE` on the
directory your patch is touching. There is no "drivers" (except few
subsystems, but not this one).
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 13/30] Documentation/devicetree: Add renesas,sh7751-cpg binding document.
2023-09-13 9:23 ` [RFC PATCH v2 13/30] Documentation/devicetree: Add renesas,sh7751-cpg binding document Yoshinori Sato
@ 2023-09-13 10:44 ` Krzysztof Kozlowski
2023-09-18 19:21 ` Geert Uytterhoeven
2023-10-03 9:16 ` Geert Uytterhoeven
2 siblings, 0 replies; 83+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-13 10:44 UTC (permalink / raw)
To: Yoshinori Sato, linux-sh; +Cc: glaubitz, linux-clk
On 13/09/2023 11:23, Yoshinori Sato wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Same problems as before. Also:
1. Please use subject prefixes matching the subsystem. You can get them
for example with `git log --oneline -- DIRECTORY_OR_FILE` on the
directory your patch is touching.
2. Drop redundant "binding document." Drop full-stop from subject.
Subjects do not have full stops, unlike commit msg which here is missing.
3. Please use scripts/get_maintainers.pl to get a list of necessary
people and lists to CC. It might happen, that command when run on an
older kernel, gives you outdated entries. Therefore please be sure you
base your patches on recent Linux kernel.
You missed at least devicetree list (maybe more), so this won't be
tested by automated tooling. Performing review on untested code might be
a waste of time, thus I will skip this patch entirely till you follow
the process allowing the patch to be tested.
Please kindly resend and include all necessary To/Cc entries.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 15/30] Documentation/devicetree: Add renesas,sh7751-intc binding document.
2023-09-13 9:23 ` [RFC PATCH v2 15/30] Documentation/devicetree: Add renesas,sh7751-intc binding document Yoshinori Sato
@ 2023-09-13 10:44 ` Krzysztof Kozlowski
2023-09-19 11:56 ` Geert Uytterhoeven
1 sibling, 0 replies; 83+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-13 10:44 UTC (permalink / raw)
To: Yoshinori Sato, linux-sh; +Cc: glaubitz
On 13/09/2023 11:23, Yoshinori Sato wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> ---
> .../renesas,sh7751-intc.yaml | 45 +++++++++++++++++++
> 1 file changed, 45 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
> new file mode 100644
> index 000000000000..0f0139545d77
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
> @@ -0,0 +1,45 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-intc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas SH7751 Interrupt Controller
> +
> +maintainers:
> + - Yoshinori Sato <ysato@users.sourceforge.jp>
> +
> +properties:
> + compatible:
> + items:
> + - const: renesas,sh7751-intc
> +
> + '#interrupt-cells':
> + # an interrupt index and flags, as defined in interrupts.txt in
> + # this directory
> + const: 2
> +
> + interrupt-controller: true
> +
> + reg:
> + minItems: 2
> + maxItems: 2
> +
> + sh7751,irlm:
This was absolutely never tested. That's not a valid vendor prefix.
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC. It might happen, that command when run on an older
kernel, gives you outdated entries. Therefore please be sure you base
your patches on recent Linux kernel.
You missed at least devicetree list (maybe more), so this won't be
tested by automated tooling. Performing review on untested code might be
a waste of time, thus I will skip this patch entirely till you follow
the process allowing the patch to be tested.
Please kindly resend and include all necessary To/Cc entries.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 17/30] Documentation/devicetree: Add renesas,sh7751-irl-ext binding document.
2023-09-13 9:23 ` [RFC PATCH v2 17/30] Documentation/devicetree: Add renesas,sh7751-irl-ext binding document Yoshinori Sato
@ 2023-09-13 10:45 ` Krzysztof Kozlowski
2023-09-19 12:08 ` Geert Uytterhoeven
1 sibling, 0 replies; 83+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-13 10:45 UTC (permalink / raw)
To: Yoshinori Sato, linux-sh; +Cc: glaubitz
On 13/09/2023 11:23, Yoshinori Sato wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> ---
Same comments as for other patches :(
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 21/30] Documentation/devicetree: sm501fb add properies.
2023-09-13 9:23 ` [RFC PATCH v2 21/30] Documentation/devicetree: sm501fb add properies Yoshinori Sato
@ 2023-09-13 10:45 ` Krzysztof Kozlowski
0 siblings, 0 replies; 83+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-13 10:45 UTC (permalink / raw)
To: Yoshinori Sato, linux-sh; +Cc: glaubitz
On 13/09/2023 11:23, Yoshinori Sato wrote:
> SM501's OF support is not enough parameter in platform device.
> This change adds the missing parameter.
>
NAK, nothing improved here.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 24/30] include/dt-bindings: Add SH7750 CPG header.
2023-09-13 9:23 ` [RFC PATCH v2 24/30] include/dt-bindings: Add SH7750 CPG header Yoshinori Sato
@ 2023-09-13 10:46 ` Krzysztof Kozlowski
2023-09-19 12:43 ` Geert Uytterhoeven
2023-09-19 12:46 ` Geert Uytterhoeven
1 sibling, 1 reply; 83+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-13 10:46 UTC (permalink / raw)
To: Yoshinori Sato, linux-sh; +Cc: glaubitz
On 13/09/2023 11:23, Yoshinori Sato wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Empty commit msgs are not acceptable.
> ---
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC. It might happen, that command when run on an older
kernel, gives you outdated entries. Therefore please be sure you base
your patches on recent Linux kernel.
You missed at least devicetree list (maybe more), so this won't be
tested by automated tooling. Performing review on untested code might be
a waste of time, thus I will skip this patch entirely till you follow
the process allowing the patch to be tested.
Please kindly resend and include all necessary To/Cc entries.
Please use subject prefixes matching the subsystem. You can get them for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching.
> include/dt-bindings/clock/sh7750.h | 13 +++++++++++++
Missing vendor prefix.
> 1 file changed, 13 insertions(+)
> create mode 100644 include/dt-bindings/clock/sh7750.h
>
> diff --git a/include/dt-bindings/clock/sh7750.h b/include/dt-bindings/clock/sh7750.h
> new file mode 100644
> index 000000000000..88e60a9a01df
> --- /dev/null
> +++ b/include/dt-bindings/clock/sh7750.h
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> + *
> + * Copyright 2023 Yoshinori Sato
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_SH7750_H__
> +#define __DT_BINDINGS_CLOCK_SH7750_H__
> +
> +#define SH7750_CPG_FCK 0
> +#define SH7750_CPG_BCK 1
> +#define SH7750_CPG_ICK 2
This should be squashed with the patch bringing bindings for this
device. It does not make sense on its own.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 25/30] include/dt-bindings: Add sh_intc IRQ - EVT conversion helper
2023-09-13 9:23 ` [RFC PATCH v2 25/30] include/dt-bindings: Add sh_intc IRQ - EVT conversion helper Yoshinori Sato
@ 2023-09-13 10:47 ` Krzysztof Kozlowski
2023-09-19 13:02 ` Geert Uytterhoeven
2023-09-19 13:05 ` Geert Uytterhoeven
1 sibling, 1 reply; 83+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-13 10:47 UTC (permalink / raw)
To: Yoshinori Sato, linux-sh; +Cc: glaubitz
On 13/09/2023 11:23, Yoshinori Sato wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> ---
> arch/sh/boot/dts/include/dt-bindings | 1 +
> include/dt-bindings/interrupt-controller/sh_intc.h | 7 +++++++
> 2 files changed, 8 insertions(+)
> create mode 120000 arch/sh/boot/dts/include/dt-bindings
> create mode 100644 include/dt-bindings/interrupt-controller/sh_intc.h
>
> diff --git a/arch/sh/boot/dts/include/dt-bindings b/arch/sh/boot/dts/include/dt-bindings
> new file mode 120000
> index 000000000000..08c00e4972fa
> --- /dev/null
> +++ b/arch/sh/boot/dts/include/dt-bindings
> @@ -0,0 +1 @@
> +../../../../../include/dt-bindings
> \ No newline at end of file
Nothing improved here.
This is a friendly reminder during the review process.
It seems my previous comments were not fully addressed. Maybe my
feedback got lost between the quotes, maybe you just forgot to apply it.
Please go back to the previous discussion and either implement all
requested changes or keep discussing them.
Thank you.
> diff --git a/include/dt-bindings/interrupt-controller/sh_intc.h b/include/dt-bindings/interrupt-controller/sh_intc.h
> new file mode 100644
> index 000000000000..cab546fba396
> --- /dev/null
> +++ b/include/dt-bindings/interrupt-controller/sh_intc.h
> @@ -0,0 +1,7 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> + *
> + * SH3/4 INTC EVT - IRQ conversion
> + */
> +
> +#define evt2irq(evt) ((evt) >> 5)
> +#define irq2evt(irq) ((irq) << 5)
No, that's not a binding. Drop entire file.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 23/30] arch/sh: Add SH7751 SoC Internal periphreal devicetree.
2023-09-13 9:23 ` [RFC PATCH v2 23/30] arch/sh: Add SH7751 SoC Internal periphreal devicetree Yoshinori Sato
@ 2023-09-13 10:49 ` Krzysztof Kozlowski
2023-09-19 12:41 ` Geert Uytterhoeven
2023-09-19 13:11 ` Geert Uytterhoeven
2 siblings, 0 replies; 83+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-13 10:49 UTC (permalink / raw)
To: Yoshinori Sato, linux-sh; +Cc: glaubitz
On 13/09/2023 11:23, Yoshinori Sato wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> ---
> arch/sh/boot/dts/sh7751.dtsi | 76 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 76 insertions(+)
> create mode 100644 arch/sh/boot/dts/sh7751.dtsi
>
> diff --git a/arch/sh/boot/dts/sh7751.dtsi b/arch/sh/boot/dts/sh7751.dtsi
> new file mode 100644
> index 000000000000..749eab3bce9f
> --- /dev/null
> +++ b/arch/sh/boot/dts/sh7751.dtsi
> @@ -0,0 +1,76 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the SH7751 SoC
> + */
> +
> +#include <dt-bindings/interrupt-controller/sh_intc.h>
> +#include <dt-bindings/clock/sh7750.h>
> +
> +/ {
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cpu@0 {
> + compatible = "renesas,sh7751r","renesas,sh4", "renesas,sh";
Except missing spaces and incorrect indentation, where is this
documented? Anyway it looks really odd to use such compatibles for CPUs.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 26/30] arch/sh: RTS7751R2D Plus DeviceTree.
2023-09-13 9:23 ` [RFC PATCH v2 26/30] arch/sh: RTS7751R2D Plus DeviceTree Yoshinori Sato
@ 2023-09-13 10:49 ` Krzysztof Kozlowski
2023-09-15 15:43 ` Geert Uytterhoeven
2023-09-19 13:25 ` Geert Uytterhoeven
2 siblings, 0 replies; 83+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-13 10:49 UTC (permalink / raw)
To: Yoshinori Sato, linux-sh; +Cc: glaubitz
On 13/09/2023 11:23, Yoshinori Sato wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
No improvements in commit msg. No improvements in subject.
> ---
> arch/sh/boot/dts/rts7751r2dplus.dts | 124 ++++++++++++++++++++++++++++
> 1 file changed, 124 insertions(+)
> create mode 100644 arch/sh/boot/dts/rts7751r2dplus.dts
>
> diff --git a/arch/sh/boot/dts/rts7751r2dplus.dts b/arch/sh/boot/dts/rts7751r2dplus.dts
> new file mode 100644
> index 000000000000..a08061133841
> --- /dev/null
> +++ b/arch/sh/boot/dts/rts7751r2dplus.dts
> @@ -0,0 +1,124 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the Renesas RTS7751R2D Plus
> + */
> +
> +/dts-v1/;
> +
> +#include "sh7751.dtsi"
> +
> +/ {
> + model = "Renesas RTS7715R2D Plus";
> + compatible = "renesas,r2dplus";
Missing bindings documentation. Incomplete compatible - missing SoC.
Sorry, but this is nowhere ready for review. There are so many trivial
issues to fix.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 26/30] arch/sh: RTS7751R2D Plus DeviceTree.
2023-09-13 9:23 ` [RFC PATCH v2 26/30] arch/sh: RTS7751R2D Plus DeviceTree Yoshinori Sato
2023-09-13 10:49 ` Krzysztof Kozlowski
@ 2023-09-15 15:43 ` Geert Uytterhoeven
2023-09-19 13:25 ` Geert Uytterhoeven
2 siblings, 0 replies; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-15 15:43 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Hi Sato-san,
On Wed, Sep 13, 2023 at 11:24 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> --- /dev/null
> +++ b/arch/sh/boot/dts/rts7751r2dplus.dts
> @@ -0,0 +1,124 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the Renesas RTS7751R2D Plus
> + */
> +
> +/dts-v1/;
> +
> +#include "sh7751.dtsi"
> +
> +/ {
> + model = "Renesas RTS7715R2D Plus";
> + compatible = "renesas,r2dplus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + interrupt-parent = <&shintc>;
> +
> + aliases {
> + serial0 = &scif1;
> + };
> +
> + chosen {
I had to add
stdout-path = "serial0:115200n8";
to get serial console output on qemu/r2d.
> + };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 02/30] arch/sh: boards/Kconfig unified OF supported targets.
2023-09-13 9:23 ` [RFC PATCH v2 02/30] arch/sh: boards/Kconfig unified OF supported targets Yoshinori Sato
@ 2023-09-18 15:05 ` Geert Uytterhoeven
0 siblings, 0 replies; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-18 15:05 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Hi Sato-san,
On Wed, Sep 13, 2023 at 11:24 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Targets that support OF should be treated as one board.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> --- a/arch/sh/boards/Kconfig
> +++ b/arch/sh/boards/Kconfig
> @@ -376,6 +371,17 @@ config SH_APSH4AD0A
> help
> Select AP-SH4AD-0A if configuring for an ALPHAPROJECT AP-SH4AD-0A.
>
> +config SH_OF_BOARD
> + bool "General Open Firmware boards"
> + select SH_DEVICE_TREE
> + select CLKSRC_JCORE_PIT if CPU_J2
> + select JCORE_AIC if CPU_J2
> + select HAVE_PCI if CPU_SUBTYPE_SH7751R
> + help
> + This board means general OF supported targets.
> + Currentry supported.
Currently supported:
> + J-Core, RTS7751R2DPlus and LANDISK.
Although it's usually a bad idea to have such a list, as (hopefully)
it becomes outdated soon ;-)
> +
> source "arch/sh/boards/mach-r2d/Kconfig"
> source "arch/sh/boards/mach-highlander/Kconfig"
> source "arch/sh/boards/mach-sdk7780/Kconfig"
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 03/30] arch/sh: Disable SH specific drivers in OF enabled.
2023-09-13 9:23 ` [RFC PATCH v2 03/30] arch/sh: Disable SH specific drivers in OF enabled Yoshinori Sato
@ 2023-09-18 15:14 ` Geert Uytterhoeven
0 siblings, 0 replies; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-18 15:14 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Hi Sato-san,
On Wed, Sep 13, 2023 at 11:35 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> OF uses a common framework.
> Avoid using clk, irq and PCI SH-specific drivers.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> --- a/arch/sh/Kconfig
> +++ b/arch/sh/Kconfig
> @@ -379,6 +379,7 @@ config CPU_SUBTYPE_SH7751
> config CPU_SUBTYPE_SH7751R
> bool "Support SH7751R processor"
> select CPU_SH4
> + select PCI_SH7751 if SH_DEVICE_TREE
Is PCI a hard requirement for using SH7751?
It not, it should not be auto-enabled by default.
> --- a/arch/sh/boards/of-generic.c
> +++ b/arch/sh/boards/of-generic.c
> @@ -116,6 +117,8 @@ static void __init sh_of_mem_reserve(void)
> static void __init sh_of_setup(char **cmdline_p)
> {
> struct device_node *root;
> + struct device_node *cpu;
> + int freq;
u32
>
> sh_mv.mv_name = "Unknown SH model";
> root = of_find_node_by_path("/");
> @@ -125,6 +128,9 @@ static void __init sh_of_setup(char **cmdline_p)
> }
>
> sh_of_smp_probe();
> + cpu = of_find_node_by_name(NULL, "cpu");
> + if (!of_property_read_u32(cpu, "clock-frequency", &freq))
> + preset_lpj = freq / 500;
> }
>
> static int sh_of_irq_demux(int irq)
> @@ -140,25 +146,14 @@ static void __init sh_of_init_irq(void)
> irqchip_init();
> }
>
> -static int __init sh_of_clk_init(void)
> -{
> -#ifdef CONFIG_COMMON_CLK
> - /* Disabled pending move to COMMON_CLK framework. */
> - pr_info("SH generic board support: scanning for clk providers\n");
> - of_clk_init(NULL);
> -#endif
> - return 0;
> -}
> -
> static struct sh_machine_vector __initmv sh_of_generic_mv = {
> .mv_setup = sh_of_setup,
> .mv_name = "devicetree", /* replaced by DT root's model */
> .mv_irq_demux = sh_of_irq_demux,
> .mv_init_irq = sh_of_init_irq,
> - .mv_clk_init = sh_of_clk_init,
> + .mv_clk_init = noopi,
> .mv_mode_pins = noopi,
> - .mv_mem_init = noop,
warning: ‘noop’ defined but not used [-Wunused-function]
> - .mv_mem_reserve = sh_of_mem_reserve,
> + .mv_mem_init = sh_of_mem_init,
> };
>
> struct sh_clk_ops;
> --- a/drivers/sh/Makefile
> +++ b/drivers/sh/Makefile
> @@ -2,7 +2,9 @@
> #
> # Makefile for the SuperH specific drivers.
> #
> +ifneq ($(CONFIG_SH_DEVICE_TREE),y)
> obj-$(CONFIG_SH_INTC) += intc/
> +endif
> ifneq ($(CONFIG_COMMON_CLK),y)
> obj-$(CONFIG_HAVE_CLK) += clk/
> endif
The above three lines can be simplified to
obj-$(CONFIG_HAVE_LEGACY_CLK) += clk
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 01/30] arch/sh: head_32.S passing FDT address to initialize function.
2023-09-13 9:23 ` [RFC PATCH v2 01/30] arch/sh: head_32.S passing FDT address to initialize function Yoshinori Sato
@ 2023-09-18 15:16 ` Geert Uytterhoeven
0 siblings, 0 replies; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-18 15:16 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
On Wed, Sep 13, 2023 at 11:24 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> R4 is caller saved in SH ABI.
> Save it so it doesn't get corrupted until it's needed for initialization.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 04/30] include: sh_intc.h Add stub function "intc_finalize".
2023-09-13 9:23 ` [RFC PATCH v2 04/30] include: sh_intc.h Add stub function "intc_finalize" Yoshinori Sato
@ 2023-09-18 15:16 ` Geert Uytterhoeven
0 siblings, 0 replies; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-18 15:16 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
On Wed, Sep 13, 2023 at 11:35 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> This function not use in OF.
This function is not used with OF.
> avoid unneeded call.
Using a static inline function avoids an external call.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 07/30] drivers/pci: SH7751 PCI Host bridge controller driver.
2023-09-13 9:23 ` [RFC PATCH v2 07/30] drivers/pci: SH7751 PCI Host bridge controller driver Yoshinori Sato
@ 2023-09-18 15:32 ` Geert Uytterhoeven
2023-09-20 12:15 ` Yoshinori Sato
2023-09-18 19:30 ` Bjorn Helgaas
1 sibling, 1 reply; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-18 15:32 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz, linux-pci
Hi Sato-san,
On Wed, Sep 13, 2023 at 11:35 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> --- /dev/null
> +++ b/drivers/pci/controller/pci-sh7751.c
> @@ -0,0 +1,338 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * SH7751 PCI driver
> + * Copyright (C) 2023 Yoshinori Sato
> + *
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/of_pci.h>
> +#include <linux/of_platform.h>
> +#include <linux/pci-ecam.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +#include <asm-generic/pci.h>
> +#include "pci-sh7751.h"
> +
> +#define pcic_writel(val, reg) __raw_writel(val, pci_reg_base + (reg))
> +#define pcic_readl(reg) __raw_readl(pci_reg_base + (reg))
> +
> +DEFINE_RAW_SPINLOCK(pci_config_lock);
> +
> +/*
> + * PCIC fixups
> + */
> +
> +#define PCIMCR_MRSET 0x40000000
> +#define PCIMCR_RFSH 0x00000004
> +
> +/* board depend PCI bus fixups */
> +static void __init julian_fixup(void __iomem *pci_reg_base, void __iomem *bcr)
Please drop all the __init* annotations.
Although I no longer see invalid section warnings, all symbols tagged
with __init* are still referenced from sh7751_pci_probe(), eventually.
> +{
> + unsigned long bcr1, mcr;
> +
> + bcr1 = __raw_readl(bcr + SH7751_BCR1);
> + bcr1 |= 0x00080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
> + pcic_writel(bcr1, SH4_PCIBCR1);
> +
> + mcr = __raw_readl(bcr + SH7751_MCR);
> + mcr &= (~PCIMCR_MRSET) & (~PCIMCR_RFSH);
> + pcic_writel(mcr, SH4_PCIMCR);
> +
> + pcic_writel(0x0c000000, SH7751_PCICONF5);
> + pcic_writel(0xd0000000, SH7751_PCICONF6);
> + pcic_writel(0x0c000000, SH4_PCILAR0);
> + pcic_writel(0x00000000, SH4_PCILAR1);
> +}
> +
> +static void __init r2d_fixup(void __iomem *pci_reg_base, void __iomem *bcr)
> +{
> + unsigned long bcr1, mcr;
> +
> + bcr1 = ioread32(bcr + SH7751_BCR1);
> + bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
> + pcic_writel(bcr1, SH4_PCIBCR1);
> +
> + /* Enable all interrupts, so we known what to fix */
> + pcic_writel(0x0000c3ff, SH4_PCIINTM);
> + pcic_writel(0x0000380f, SH4_PCIAINTM);
> +
> + pcic_writel(0xfb900047, SH7751_PCICONF1);
> + pcic_writel(0xab000001, SH7751_PCICONF4);
> +
> + mcr = ioread32(bcr + SH7751_MCR);
> + mcr &= (~PCIMCR_MRSET) & (~PCIMCR_RFSH);
> + pcic_writel(mcr, SH4_PCIMCR);
> +
> + pcic_writel(0x0c000000, SH7751_PCICONF5);
> + pcic_writel(0xd0000000, SH7751_PCICONF6);
> + pcic_writel(0x0c000000, SH4_PCILAR0);
> + pcic_writel(0x00000000, SH4_PCILAR1);
> +}
> +
> +static const __initconst struct fixups {
> + char *compatible;
> + void (*fixup)(void __iomem *pci_reg_base, void __iomem *bcr);
> +} fixup_list[] = {
> + {
> + .compatible = "iodata,julian-pci",
> + .fixup = julian_fixup,
> + },
> + {
> + .compatible = "renesas,r2d-pci",
> + .fixup = r2d_fixup,
> + },
> +};
These fixups seem to be board-specific instead of specific to the
PCI block in the SoCs on these boards.
I see three options to handle this in a more appropriate way:
1. Handle this in the bootloader.
Not an attractive solution, as not everyone can/wants to update
the bootloader,
2. Use of_machine_is_compatible() in a platform-specific quirk
handler, outside the PCI driver,
3. Move the common parts into sh7751_pci_probe(), and the
handle the differences through DT topology analysis and/or
properties in DT.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 08/30] drivers/pci: Add SH7751 Host bridge controller
2023-09-13 9:23 ` [RFC PATCH v2 08/30] drivers/pci: Add SH7751 Host bridge controller Yoshinori Sato
@ 2023-09-18 15:34 ` Geert Uytterhoeven
2023-09-18 19:33 ` Bjorn Helgaas
2023-10-12 7:16 ` Geert Uytterhoeven
2 siblings, 0 replies; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-18 15:34 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz, linux-pci
Hi Sato-san,
On Wed, Sep 13, 2023 at 11:24 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> ---
> drivers/pci/controller/Kconfig | 9 +++++++++
> drivers/pci/controller/Makefile | 1 +
Please combine this with "[RFC PATCH v2 07/30] drivers/pci: SH7751
PCI Host bridge controller driver.".
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 09/30] Documentation/devicetree: Add renesas,sh7751-pci binding document.
2023-09-13 9:23 ` [RFC PATCH v2 09/30] Documentation/devicetree: Add renesas,sh7751-pci binding document Yoshinori Sato
2023-09-13 10:42 ` Krzysztof Kozlowski
@ 2023-09-18 15:41 ` Geert Uytterhoeven
1 sibling, 0 replies; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-18 15:41 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz, linux-pci
Hi Sato-san,
On Wed, Sep 13, 2023 at 11:24 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml
> @@ -0,0 +1,57 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/renesas,sh7751-pci.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas SH7751 PCI Host controller
> +
> +maintainers:
> + - Yoshinori Sato <ysato@users.sourceforge.jp>
> +
> +properties:
> + compatible:
> + - items:
make dt_binding_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml:
Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml:14:7:
[warning] wrong indentation: expected 4 but found 6 (indentation)
> + - enum:
> + - renesas,r2d-pci # Renesas RTS7751R2D board
Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml:16:32:
[error] syntax error: found character '\t' that cannot start any token
(syntax)
> + - iodata,julian-pci # IO DATA DEVICE Julian board
Please drop the two board-specific compatible values, they do not
represent different implementations of the PCI core in the SH7751 SoC.
> + - const: renesas,sh7751-pci
> +
> + reg:
> + minItems: 3
> +
> + interrupt-cells:
> + const: 1
> +
> + address-cells:
> + const: 3
> +
> + size-cells:
> + const: 2;
> +
> + range:
> + description: |
> + The PCI bus memory area and I/O area.
> +
> +
> +required:
> + - compatible
> + - reg
> + - interrupt-cells
> + - address-cells
> + - size-cells
> + - range
> +
> +examples:
> + - |
> + pci@fe200000 {
Please align "pci" with the "|" above
> + compatible = "renesas,sh7751-pci";
Please indent by 4 spaces
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges = <0x02000000 0 0xfd000000 0xfd000000 0 0x01000000>,
> + <0x01000000 0 0xfe240000 0xfe240000 0 0x00040000>;
> + reg = <0xfe200000 0x0400>,
> + <0x0c000000 0x04000000>,
> + <0xff800000 0x0030>;
> + #interrupt-cells = <1>;
Documentation/devicetree/bindings/pci/renesas,sh7751-pci.example.dtb:
pci@fe200000: 'device_type' is a required property
from schema $id: http://devicetree.org/schemas/pci/pci-bus.yaml#
> + };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 10/30] drivers/clk: SH7750 / SH7751 CPG Driver
2023-09-13 9:23 ` [RFC PATCH v2 10/30] drivers/clk: SH7750 / SH7751 CPG Driver Yoshinori Sato
2023-09-13 10:43 ` Krzysztof Kozlowski
@ 2023-09-18 16:05 ` Geert Uytterhoeven
1 sibling, 0 replies; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-18 16:05 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz, linux-clk
Hi Sato-san,
On Wed, Sep 13, 2023 at 11:25 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> drivers/clk/renesas/clk-sh7750.c | 236 +++++++++++++++++++++++++++++++
Patch prefix should be "clk: renesas: ".
> --- /dev/null
> +++ b/drivers/clk/renesas/clk-sh7750.c
> @@ -0,0 +1,236 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Renesas SH7750/51 CPG driver
> + *
> + * Copyright 2023 Yoshinori Sato <ysato@users.sourceforge.jp>
> + */
> +
> +#include <linux/clkdev.h>
> +#include <linux/clk-provider.h>
> +#include <linux/err.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/io.h>
Please add a blank line.
> +#include "clk-shdiv.h"
This doesn't exist until "[RFC PATCH v2 11/30] drivers/clk: SuperH
generai clock divider helper", so please move that patch up in the
series.
> +#include <dt-bindings/clock/sh7750.h>
This doesn't exist until "[RFC PATCH v2 24/30] include/dt-bindings:
Add SH7750 CPG header.", so please move that patch up in the series.
> +
> +static DEFINE_SPINLOCK(clklock);
I think it would make sense to move this into struct cpg_priv.
> +struct cpg_priv {
> + struct clk_hw hw;
> + void __iomem *frqcr;
> + void __iomem *wdt;
> + u32 mode;
> + bool have_div1;
> +};
> +
> +#define to_priv(_hw) container_of(_hw, struct cpg_priv, hw)
> +
> +#define FRQCR_PLL1EN BIT(10)
> +static const int pll1mult[] = { 12, 12, 6, 12, 6, 12, 1};
unsigned int
> +
> +static unsigned long pll_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct cpg_priv *cpg = to_priv(hw);
> + unsigned long rate = parent_rate;
> + uint16_t frqcr;
u16
Please don't mix uint<n>_t and u<n> in the same driver.
> +static int pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
> +{
> + struct cpg_priv *cpg = to_priv(hw);
> +
> + get_round_rate(cpg, &req->rate, NULL, req->rate, req->best_parent_rate);
> + return 0;
> +}
> +
> +static int pll_set_rate(struct clk_hw *hw,
> + unsigned long rate, unsigned long prate)
> +{
> + struct cpg_priv *cpg = to_priv(hw);
> + bool oldpll, newpll;
> + uint16_t frqcr;
u16
> +static void __init register_div(struct device_node *node, struct cpg_priv *cpg)
> +{
> + static const char * const divout[] = {
> + [SH7750_CPG_FCK] = "fck",
> + [SH7750_CPG_BCK] = "bck",
> + [SH7750_CPG_ICK] = "ick",
> + };
> + struct clk *clk;
> + int i;
unsigned int
> +
> + for (i = 0; i < ARRAY_SIZE(divout); i++) {
> + if (sh_div_clk_register(node, divout[i], PLLOUT,
> + cpg->frqcr, i * 3, 3,
> + (i == 0) ? pdiv_table : div_table,
> + &clklock) < 0)
> + pr_err("%s: failed to register %s div clock (%ld)\n",
> + __func__, divout[i], PTR_ERR(clk));
> + }
> +}
> +
> +
> +static void __init sh7750_cpg_setup(struct device_node *node)
> +{
> + unsigned int num_parents;
> + struct cpg_priv *cpg;
> +
> + num_parents = of_clk_get_parent_count(node);
> + if (num_parents < 1) {
> + pr_err("%s: no parent found", node->name);
> + return;
> + }
> +
> + cpg = kzalloc(sizeof(struct cpg_priv), GFP_KERNEL);
> + if (!cpg) {
> + pr_err("%s: failed to alloc memory", node->name);
> + return;
> + }
> +
> + of_property_read_u32_index(node, "renesas,mode", 0, &cpg->mode);
> + if (cpg->mode >= 7) {
> + pr_err("%s: Invalid clock mode setting (%u)\n",
> + node->name, cpg->mode);
> + goto cpg_free;
> + }
> + cpg->have_div1 = (of_device_is_compatible(node, "renesas,sh7750r-pll-clk") == 0);
What is this for? There are no users of "renesas,sh7750r-pll-clk".
> +
> + cpg->frqcr = of_iomap(node, 0);
> + if (cpg->frqcr == NULL) {
> + pr_err("%s: failed to map divide register", node->name);
> + goto cpg_free;
> + }
> +
> + cpg->wdt = of_iomap(node, 1);
> + if (cpg->wdt == NULL) {
> + pr_err("%s: failed to map watchdog register", node->name);
> + goto unmap_frqcr;
> + }
> +
> + if (!register_pll(node, cpg))
> + goto unmap_wdt;
> +
> + register_div(node, cpg);
> +
> +unmap_wdt:
> + iounmap(cpg->wdt);
> +unmap_frqcr:
> + iounmap(cpg->frqcr);
> +cpg_free:
> + kfree(cpg);
> +}
> +
> +CLK_OF_DECLARE(sh7750_cpg, "renesas,sh7750-cpg",
> + sh7750_cpg_setup);
Probably you want a second entry for "renesas,sh7751-cpg"?
Is there a good reason to use CLK_OF_DECLARE()?
Perhaps because you need it early for the timer?
Most modern clock drivers use a platform_driver, registered from
e.g. subsys_initcall(). When you need an early initialization phase,
you can use CLK_OF_DECLARE_DRIVER() for the early part.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 11/30] drivers/clk: SuperH generai clock divider helper
2023-09-13 9:23 ` [RFC PATCH v2 11/30] drivers/clk: SuperH generai clock divider helper Yoshinori Sato
@ 2023-09-18 18:59 ` Geert Uytterhoeven
0 siblings, 0 replies; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-18 18:59 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz, linux-clk
Hi Sato-san,
On Wed, Sep 13, 2023 at 11:26 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
Patch prefix should be "clk: renesas: ".
s/generai/general/
> --- /dev/null
> +++ b/drivers/clk/renesas/clk-shdiv.c
> @@ -0,0 +1,346 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * SuperH divider clock driver
> + */
> +
> +#include <linux/clkdev.h>
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +#include <linux/string.h>
> +#include "clk-shdiv.h"
> +
> +#define div_mask(width) ((1 << (width)) - 1)
"1U << ...", so you can use min() below.
> +
> +static unsigned int _get_table_maxdiv(const struct clk_div_table *table,
> + u8 width)
> +{
> + unsigned int maxdiv = 0, mask = div_mask(width);
> + const struct clk_div_table *clkt;
> +
> + for (clkt = table; clkt->div; clkt++)
> + if (clkt->div > maxdiv && clkt->val <= mask)
> + maxdiv = clkt->div;
> + return maxdiv;
> +}
> +
> +static unsigned int _get_maxdiv(const struct clk_div_table *table, u8 width)
> +{
> + if (table)
> + return _get_table_maxdiv(table, width);
> + return div_mask(width) + 1;
> +}
> +
> +static unsigned int _get_table_div(const struct clk_div_table *table,
> + unsigned int val)
> +{
> + const struct clk_div_table *clkt;
> +
> + for (clkt = table; clkt->div; clkt++)
> + if (clkt->val == val)
> + return clkt->div;
> + return 0;
> +}
> +
> +static unsigned int _get_div(const struct clk_div_table *table,
> + unsigned int val, u8 width)
> +{
> + if (table)
> + return _get_table_div(table, val);
> + return val + 1;
> +}
> +
> +static unsigned int _get_table_val(const struct clk_div_table *table,
> + unsigned int div)
> +{
> + const struct clk_div_table *clkt;
> +
> + for (clkt = table; clkt->div; clkt++)
> + if (clkt->div == div)
> + return clkt->val;
> + return 0;
> +}
> +
> +static unsigned int _get_val(const struct clk_div_table *table,
> + unsigned int div, u8 width)
> +{
> + if (table)
> + return _get_table_val(table, div);
> + return div - 1;
> +}
Lots of functions named "_<foo>()" are called only once.
Please inline them manually.
> +
> +static unsigned long sh_divider_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate,
> + unsigned int val,
> + const struct clk_div_table *table)
> +{
> + struct clk_divider *divider = to_clk_divider(hw);
> + unsigned int div;
> +
> + div = _get_div(table, val, divider->width);
> +
> + return DIV_ROUND_UP_ULL((u64)parent_rate, div);
> +}
> +
> +static unsigned long sh_clk_divider_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct clk_divider *divider = to_clk_divider(hw);
> + unsigned int val;
> +
> + val = __raw_readw(divider->reg) >> divider->shift;
> + val &= div_mask(divider->width);
> +
> + return sh_divider_recalc_rate(hw, parent_rate, val, divider->table);
> +}
> +
> +static bool _is_valid_table_div(const struct clk_div_table *table,
> + unsigned int div)
> +{
> + const struct clk_div_table *clkt;
> +
> + for (clkt = table; clkt->div; clkt++)
> + if (clkt->div == div)
> + return true;
> + return false;
> +}
> +
> +static bool _is_valid_div(const struct clk_div_table *table, unsigned int div)
> +{
> + if (table)
> + return _is_valid_table_div(table, div);
> + return true;
> +}
> +
> +static int _round_up_table(const struct clk_div_table *table, int div)
> +{
> + const struct clk_div_table *clkt;
> + int up = INT_MAX;
> +
> + for (clkt = table; clkt->div; clkt++) {
> + if (clkt->div == div)
> + return clkt->div;
> + else if (clkt->div < div)
> + continue;
> +
> + if ((clkt->div - div) < (up - div))
> + up = clkt->div;
> + }
> +
> + return up;
> +}
> +
> +static int _div_round_up(const struct clk_div_table *table,
> + unsigned long parent_rate, unsigned long rate)
> +{
> + int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
unsigned int (everywhere)
> +
> + if (table)
> + div = _round_up_table(table, div);
> +
> + return div;
> +}
> +
> +static int _div_round(const struct clk_div_table *table,
> + unsigned long parent_rate, unsigned long rate)
> +{
> + return _div_round_up(table, parent_rate, rate);
> +}
> +
> +static bool _is_best_div(unsigned long rate, unsigned long now,
> + unsigned long best)
> +{
> + return now <= rate && now > best;
> +}
> +
> +static int _next_div(const struct clk_div_table *table, int div)
> +{
> + div++;
> +
> + if (table)
> + return _round_up_table(table, div);
> +
> + return div;
> +}
> +
> +static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
> + unsigned long *best_parent_rate,
> + const struct clk_div_table *table, u8 width)
> +{
> + int i, bestdiv = 0;
unsigned int;
> + unsigned long parent_rate, best = 0, now, maxdiv;
> + unsigned long parent_rate_saved = *best_parent_rate;
> +
> + if (!rate)
> + rate = 1;
> +
> + maxdiv = _get_maxdiv(table, width);
> +
> + if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
> + parent_rate = *best_parent_rate;
> + bestdiv = _div_round(table, parent_rate, rate);
> + bestdiv = bestdiv == 0 ? 1 : bestdiv;
> + bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
> + return bestdiv;
> + }
> +
> + /*
> + * The maximum divider we can use without overflowing
> + * unsigned long in rate * i below
> + */
> + maxdiv = min(ULONG_MAX / rate, maxdiv);
> +
> + for (i = _next_div(table, 0); i <= maxdiv;
> + i = _next_div(table, i)) {
> + if (rate * i == parent_rate_saved) {
> + /*
> + * It's the most ideal case if the requested rate can be
> + * divided from parent clock without needing to change
> + * parent rate, so return the divider immediately.
> + */
> + *best_parent_rate = parent_rate_saved;
> + return i;
> + }
> + parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
> + rate * i);
> + now = DIV_ROUND_UP_ULL((u64)parent_rate, i);
> + if (_is_best_div(rate, now, best)) {
> + bestdiv = i;
> + best = now;
> + *best_parent_rate = parent_rate;
> + }
> + }
> +
> + if (!bestdiv) {
> + bestdiv = _get_maxdiv(table, width);
> + *best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), 1);
> + }
> +
> + return bestdiv;
> +}
> +
> +static long sh_divider_round_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long *prate, const struct clk_div_table *table,
> + u8 width)
> +{
> + int div;
> +
> + div = clk_divider_bestdiv(hw, rate, prate, table, width);
> +
> + return DIV_ROUND_UP_ULL((u64)*prate, div);
> +}
> +
> +static int sh_clk_divider_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> +{
> + struct clk_divider *divider = to_clk_divider(hw);
> + long rate, prate;
> +
> + prate = req->best_parent_rate;
> + rate = sh_divider_round_rate(hw, req->rate, &prate, divider->table,
> + divider->width);
> + if (rate < 0)
> + return rate;
> + req->rate = rate;
> + req->best_parent_rate = prate;
> + return 0;
> +}
> +
> +static int sh_divider_get_val(unsigned long rate, unsigned long parent_rate,
> + const struct clk_div_table *table, u8 width)
> +{
> + unsigned int div, value;
> +
> + div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
> +
> + if (!_is_valid_div(table, div))
> + return -EINVAL;
> +
> + value = _get_val(table, div, width);
> +
> + return min_t(unsigned int, value, div_mask(width));
min() (once div_mask() is unsigned)
> +}
> +static int _register_divider(struct device_node *node, const char *name,
> + const char *parent_name,
> + void __iomem *reg, u8 shift, u8 width,
> + const struct clk_div_table *table,
> + spinlock_t *lock)
> +{
> + struct clk_divider *div;
> + struct clk_init_data init;
> +
> + /* allocate the divider */
> + div = kzalloc(sizeof(*div), GFP_KERNEL);
> + if (!div)
> + return -ENOMEM;
> +
> + init.name = name;
> + init.ops = &sh_clk_divider_ops;
> + init.flags = 0;
> + init.parent_names = (parent_name ? &parent_name : NULL);
> + init.num_parents = (parent_name ? 1 : 0);
> +
> + /* struct clk_divider assignments */
> + div->reg = reg;
> + div->shift = shift;
> + div->width = width;
> + div->lock = lock;
> + div->hw.init = &init;
> + div->table = table;
> +
> + /* register the clock */
> + if (of_clk_hw_register(node, &div->hw) < 0)
> + kfree(div);
> + of_clk_add_hw_provider(node, of_clk_hw_simple_get, &div->hw);
> +
> + return 0;
Please propagate the error in case of failure.
> +}
> +
> +int sh_div_clk_register(struct device_node *node, const char *name,
> + const char *parent_name,
> + void __iomem *reg, u8 shift, u8 width,
> + const struct clk_div_table *table,
> + spinlock_t *lock)
> +{
> + return _register_divider(node, name, parent_name, reg, shift,
> + width, table, lock);
Is there a reason why you made _register_divider() a separate function?
> +}
> +EXPORT_SYMBOL_GPL(sh_div_clk_register);
> diff --git a/drivers/clk/renesas/clk-shdiv.h b/drivers/clk/renesas/clk-shdiv.h
> new file mode 100644
> index 000000000000..fd49c06da9ff
> --- /dev/null
> +++ b/drivers/clk/renesas/clk-shdiv.h
> @@ -0,0 +1,18 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +
> +#ifndef __CLK_SHDIV_H__
> +#define __CLK_SHDIV_H__
> +/*
> + * SuperH divider clock driver
> + */
> +
> +#include <linux/of.h>
> +#include <linux/clk-provider.h>
There is no need to include these headers.
You do need to include <linux/compiler_types.h> for __iomem;
You can use forward declarations:
struct device_node;
struct clk_div_table;
struct spinlock;
> +
> +int sh_div_clk_register(struct device_node *node, const char *name,
> + const char *parent_name,
> + void __iomem *reg, u8 shift, u8 width,
> + const struct clk_div_table *table,
> + spinlock_t *lock);
struct spinlock *lock
> +
> +#endif
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 12/30] drivers/clk: Add SH7750 CPG drivers entry.
2023-09-13 9:23 ` [RFC PATCH v2 12/30] drivers/clk: Add SH7750 CPG drivers entry Yoshinori Sato
@ 2023-09-18 19:05 ` Geert Uytterhoeven
0 siblings, 0 replies; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-18 19:05 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz, linux-clk
Hi Sato-san,
On Wed, Sep 13, 2023 at 11:24 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
Patch prefix should be "clk: renesas: ".
> drivers/clk/renesas/Kconfig | 15 ++++++++++++++-
> drivers/clk/renesas/Makefile | 1 +
Please combine this patch with "[RFC PATCH v2 10/30] drivers/clk:
SH7750 / SH7751 CPG Driver".
> --- a/drivers/clk/renesas/Kconfig
> +++ b/drivers/clk/renesas/Kconfig
> @@ -2,7 +2,7 @@
>
> config CLK_RENESAS
> bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS
... && !SUPERH
> - default y if ARCH_RENESAS
> + default y if ARCH_RENESAS || SUPERH
> select CLK_EMEV2 if ARCH_EMEV2
> select CLK_RZA1 if ARCH_R7S72100
> select CLK_R7S9210 if ARCH_R7S9210
> @@ -39,6 +39,11 @@ config CLK_RENESAS
> select CLK_R9A07G054 if ARCH_R9A07G054
> select CLK_R9A09G011 if ARCH_R9A09G011
> select CLK_SH73A0 if ARCH_SH73A0
> + select CLK_SH7750 if CPU_SUBTYPE_SH7750
> + select CLK_SH7750 if CPU_SUBTYPE_SH7750S
> + select CLK_SH7750 if CPU_SUBTYPE_SH7750R
> + select CLK_SH7750 if CPU_SUBTYPE_SH7751
> + select CLK_SH7750 if CPU_SUBTYPE_SH7751R
>
> if CLK_RENESAS
>
> @@ -218,6 +223,14 @@ config CLK_RZG2L
> bool "Renesas RZ/{G2L,G2UL,V2L} family clock support" if COMPILE_TEST
> select RESET_CONTROLLER
>
> +config CLK_SH7750
Probably you want to move this below CLK_SH73A0...
> + bool "Renesas SH7750/7751 family clock support"
... and drop the "Renesas" part?
Please add "if COMPILE_TEST" like all other clock drivers in this file.
> + depends on CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7750S || \
> + CPU_SUBTYPE_SH7750R || \
> + CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R || COMPILE_TEST
There is no need for a dependency rule.
> + help
> + This is a driver for SH7750 / SH7751 CPG.
> +
> # Generic
> config CLK_RENESAS_CPG_MSSR
> bool "CPG/MSSR clock support" if COMPILE_TEST
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 06/30] drivers/pci: SH7751 PCI Host bridge header.
2023-09-13 9:23 ` [RFC PATCH v2 06/30] drivers/pci: SH7751 PCI Host bridge header Yoshinori Sato
@ 2023-09-18 19:16 ` Bjorn Helgaas
0 siblings, 0 replies; 83+ messages in thread
From: Bjorn Helgaas @ 2023-09-18 19:16 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, linux-pci, glaubitz
On Wed, Sep 13, 2023 at 06:23:31PM +0900, Yoshinori Sato wrote:
> This file move from SH specific directory "arch/sh/drivers/pci/pci-sh7751.h"
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> ---
> drivers/pci/controller/pci-sh7751.h | 270 ++++++++++++++++++++++++++++
> 1 file changed, 270 insertions(+)
> create mode 100644 drivers/pci/controller/pci-sh7751.h
If this is a move from arch/sh/drivers/pci/, shouldn't this diff show
both the removal and the addition? Or even better, if you use "git
mv", won't it show the move directly, without a diff at all?
This file is only used in one place, so please just incorporate it
directly into pci-sh7751.c. I think the git history would be a little
cleaner if you did this as a separate patch before moving it to
drivers/pci/.
If you're moving things into drivers/pci/, follow the subject line
conventions (see "git log --oneline drivers/pci/controller/"):
- No period at end of subject line
- Subject line begins with "PCI: <driver-tag>: <Verb> ...", e.g.,
PCI: sh7751: Add SH7751 driver
> diff --git a/drivers/pci/controller/pci-sh7751.h b/drivers/pci/controller/pci-sh7751.h
> new file mode 100644
> index 000000000000..9b7de8243e92
> --- /dev/null
> +++ b/drivers/pci/controller/pci-sh7751.h
> @@ -0,0 +1,270 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Low-Level PCI Support for SH7751 targets
> + *
> + * Dustin McIntire (dustin@sensoria.com) (c) 2001
> + * Paul Mundt (lethal@linux-sh.org) (c) 2003
> + *
> + * May be copied or modified under the terms of the GNU General Public
> + * License. See linux/COPYING for more information.
Unnecessary text, given the SPDX header above.
> + *
Spurious blank line.
> +/* Platform Specific Values */
> +#define SH7751_VENDOR_ID 0x1054
> +#define SH7751_DEVICE_ID 0x3505
> +#define SH7751R_DEVICE_ID 0x350e
Most of this file uses upper-case hex, so use it consistently.
Bjorn
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 13/30] Documentation/devicetree: Add renesas,sh7751-cpg binding document.
2023-09-13 9:23 ` [RFC PATCH v2 13/30] Documentation/devicetree: Add renesas,sh7751-cpg binding document Yoshinori Sato
2023-09-13 10:44 ` Krzysztof Kozlowski
@ 2023-09-18 19:21 ` Geert Uytterhoeven
2023-10-03 9:16 ` Geert Uytterhoeven
2 siblings, 0 replies; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-18 19:21 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz, linux-clk
Hi Sato-san,
On Wed, Sep 13, 2023 at 11:26 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
Patch prefix should be "dt-bindings: clock: renesas:".
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
> @@ -0,0 +1,58 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas SH7750 / SH7751 Clock Pulse Generator (CPG)
> +
> +maintainers:
> + - Yoshinori Sato <ysato@users.sourceforge.jp>
> +
> +description:
> + The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
> + includes PLLs, and fixed and variable ratio dividers.
> +
> + The CPG may also provide a Clock Domain for SoC devices,
That functionality would require '#power-domain-cells'.
> +
> +properties:
> + compatible:
> + - const: renesas,sh7750-cpg # SH7750 / 7750S / 7751
make dt_binding_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml:
Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml:20:7:
[warning] wrong indentation: expected 4 but found 6 (indentation)
Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml:20:34:
[error] syntax error: found character '\t' that cannot start any token
(syntax)
> + - items:
> + - const: renesas,sh7750r-cpg # SH7750R / 7751R
This is the wrong order for compatible values: they should be ordered
from most-specific to least-specific.
However, given the small but significant differences between the
different variants, I think you need to define all five:
compatible:
enum:
- renesas,sh7750-cpg
- renesas,sh7750r-cpg
- renesas,sh7750s-cpg
- renesas,sh7751-cpg
- renesas,sh7751r-cpg
> + reg:
> + maxItems: 2
> + items:
> + - description: FRQCR register
> + - description: WDT registers
I think the above should be combined into one larger block, containing
the CPG, standby control, and watchdog registers.
A second block would contain the clock stop registers. Even although
the driver doesn't support these yet, it would be good to have them
in DT.
And probably you want to specify "reg-names", too.
> +
> + clocks: true
maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
> + renesas,mode:
> + description: Board-specific settings of the MD0 - MD2 bits
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 6
> +
> +required:
> + - compatible
> + - reg
+ reg-names
> + - clocks
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/r8a7740-clock.h>
> + cpg: cpg@ffc00000 {
Please align "cpg:" with "#include" above, using spaces as indentation.
> + #clock-cells = <1>;
> + compatible = "renesas,sh7750r-cpg","renesas,sh7750-cpg";
> + clocks = <&xtal>;
> + reg = <0xffc00000 2>, <0xffc00008 4>;
> + renesas,mode = <0x05>
> + };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 07/30] drivers/pci: SH7751 PCI Host bridge controller driver.
2023-09-13 9:23 ` [RFC PATCH v2 07/30] drivers/pci: SH7751 PCI Host bridge controller driver Yoshinori Sato
2023-09-18 15:32 ` Geert Uytterhoeven
@ 2023-09-18 19:30 ` Bjorn Helgaas
1 sibling, 0 replies; 83+ messages in thread
From: Bjorn Helgaas @ 2023-09-18 19:30 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz, linux-pci
On Wed, Sep 13, 2023 at 06:23:32PM +0900, Yoshinori Sato wrote:
See subject line comments at
https://lore.kernel.org/r/20230918191602.GA201859@bhelgaas
Please add a commit log. Repeating the subject line is fine, but
there's a little more detail that could be included here, e.g., a hint
about what platforms this is useful for.
> + * SH7751 PCI driver
> + * Copyright (C) 2023 Yoshinori Sato
> + *
Spurious blank line.
> +#define pcic_writel(val, reg) __raw_writel(val, pci_reg_base + (reg))
> +#define pcic_readl(reg) __raw_readl(pci_reg_base + (reg))
Best to include a pointer to a struct in the macro arguments so this
doesn't depend on local variable names in the users. See advk_readl()
and advk_writel(), for example.
> +DEFINE_RAW_SPINLOCK(pci_config_lock);
Should be static.
> + pcic_writel(0x0c000000, SH7751_PCICONF5);
> + pcic_writel(0xd0000000, SH7751_PCICONF6);
> + pcic_writel(0x0c000000, SH4_PCILAR0);
> + pcic_writel(0x00000000, SH4_PCILAR1);
The header file uses upper-case hex, but this file looks like mostly
lower-case. Maybe make them consistent?
> + * Since SH4 only does 32bit access we'll have to do a read,
> + * mask,write operation.
This RMW corrupts some registers; see comments and warning in
pci_generic_config_write32(). A comment here is probably enough.
> + * We'll allow an odd byte offset, though it should be illegal.
> + */
> +static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn,
> + int where, int size, u32 val)
> +static int area_sdram_check(void __iomem *pci_reg_base,
> + void __iomem *bcr,
> + unsigned int area)
> +{
> + unsigned long word;
> +
> + word = __raw_readl(bcr + SH7751_BCR1);
> + /* check BCR for SDRAM in area */
> + if (((word >> area) & 1) == 0) {
> + pr_info("PCI: Area %d is not configured for SDRAM. BCR1=0x%lx\n",
Use dev_info(). Will require passing a controller struct around,
which is common style in drivers/pci/controller/.
> + dev_info(&pdev->dev, "PCI core found at %p\n",
> + pci_reg_base);
Use %pR.
> + /* use round robin mode to stop a device starving/overruning */
overrunning
Bjorn
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 08/30] drivers/pci: Add SH7751 Host bridge controller
2023-09-13 9:23 ` [RFC PATCH v2 08/30] drivers/pci: Add SH7751 Host bridge controller Yoshinori Sato
2023-09-18 15:34 ` Geert Uytterhoeven
@ 2023-09-18 19:33 ` Bjorn Helgaas
2023-10-12 7:16 ` Geert Uytterhoeven
2 siblings, 0 replies; 83+ messages in thread
From: Bjorn Helgaas @ 2023-09-18 19:33 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz, linux-pci
On Wed, Sep 13, 2023 at 06:23:33PM +0900, Yoshinori Sato wrote:
Update subject line and include a commit log.
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> ---
> drivers/pci/controller/Kconfig | 9 +++++++++
> drivers/pci/controller/Makefile | 1 +
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> index c0c3f2824990..037ff44bd1e8 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -342,6 +342,15 @@ config PCIE_XILINX_CPM
> Say 'Y' here if you want kernel support for the
> Xilinx Versal CPM host bridge.
>
> +config PCI_SH7751
> + bool "Renesas SH7751 PCI controller"
> + depends on OF
> + depends on CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R || COMPILE_TEST
> + select PCI_HOST_COMMON
> + help
> + Say 'Y' here if you want kernel to support the Renesas SH7751 PCI
> + Host Bridge driver.
Sort this so it appears in alpha order by vendor, device in
menuconfig, etc.
Since I didn't get the entire series, here are the whitespace errors
from git-am:
Applying: arch/sh: head_32.S passing FDT address to initialize function.
.git/rebase-apply/patch:25: trailing whitespace.
Applying: Documentation/devicetree: Add renesas,sh7751-cpg binding document.
.git/rebase-apply/patch:66: space before tab in indent.
clocks = <&xtal>;
Applying: drivers/irqchip: SH7751 IRL external encoder with enable gate.
.git/rebase-apply/patch:33: new blank line at EOF.
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 14/30] drivers/irqchip: Add SH7751 Internal INTC drivers.
2023-09-13 9:23 ` [RFC PATCH v2 14/30] drivers/irqchip: Add SH7751 Internal INTC drivers Yoshinori Sato
@ 2023-09-19 11:50 ` Geert Uytterhoeven
2023-09-22 10:12 ` Yoshinori Sato
0 siblings, 1 reply; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-19 11:50 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Hi Sato-san,
On Wed, Sep 13, 2023 at 11:24 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -679,4 +679,13 @@ config SUNPLUS_SP7021_INTC
> chained controller, routing all interrupt source in P-Chip to
> the primary controller on C-Chip.
>
> +config RENESAS_SH7751_INTC
> + bool "Renesas SH7751 Interrupt Controller"
> + depends on SH_DEVICE_TREE
"|| COMPILE_TEST"?
> + select IRQ_DOMAIN
> + select IRQ_DOMAIN_HIERARCHY
> + help
> + Support for the Renesas SH7751 On-chip interrupt controller.
> + And external interrupt encoder for some targets.
Inconsistent indentation
> --- /dev/null
> +++ b/drivers/irqchip/irq-renesas-sh7751.c
> +/* INTEVT to IPR mapping */
> +static const struct iprmap {
> + int intevt;
irq, as you're storing the irq number not the event number?
> + int off;
> + int bit;
All unsigned int ...
> +} iprmaps[] = {
> +#define IPRDEF(e, o, b) { .intevt = evt2irq(e), .off = o, .bit = b }
> + IPRDEF(0x240, IPRD, IPR_B12), /* IRL0 */
> + IPRDEF(0x2a0, IPRD, IPR_B8), /* IRL1 */
> + IPRDEF(0x300, IPRD, IPR_B4), /* IRL2 */
> + IPRDEF(0x360, IPRD, IPR_B0), /* IRL3 */
> + IPRDEF(0x400, IPRA, IPR_B12), /* TMU0 */
> + IPRDEF(0x420, IPRA, IPR_B8), /* TMU1 */
> + IPRDEF(0x440, IPRA, IPR_B4), /* TMU2 TNUI */
> + IPRDEF(0x460, IPRA, IPR_B4), /* TMU2 TICPI */
> + IPRDEF(0x480, IPRA, IPR_B0), /* RTC ATI */
> + IPRDEF(0x4a0, IPRA, IPR_B0), /* RTC PRI */
> + IPRDEF(0x4c0, IPRA, IPR_B0), /* RTC CUI */
> + IPRDEF(0x4e0, IPRB, IPR_B4), /* SCI ERI */
> + IPRDEF(0x500, IPRB, IPR_B4), /* SCI RXI */
> + IPRDEF(0x520, IPRB, IPR_B4), /* SCI TXI */
> + IPRDEF(0x540, IPRB, IPR_B4), /* SCI TEI */
> + IPRDEF(0x560, IPRB, IPR_B12), /* WDT */
> + IPRDEF(0x580, IPRB, IPR_B8), /* REF RCMI */
> + IPRDEF(0x5a0, IPRB, IPR_B4), /* REF ROVI */
> + IPRDEF(0x600, IPRC, IPR_B0), /* H-UDI */
> + IPRDEF(0x620, IPRC, IPR_B12), /* GPIO */
> + IPRDEF(0x640, IPRC, IPR_B8), /* DMAC DMTE0 */
> + IPRDEF(0x660, IPRC, IPR_B8), /* DMAC DMTE1 */
> + IPRDEF(0x680, IPRC, IPR_B8), /* DMAC DMTE2 */
> + IPRDEF(0x6a0, IPRC, IPR_B8), /* DMAC DMTE3 */
> + IPRDEF(0x6c0, IPRC, IPR_B8), /* DMAC DMAE */
> + IPRDEF(0x700, IPRC, IPR_B4), /* SCIF ERI */
> + IPRDEF(0x720, IPRC, IPR_B4), /* SCIF RXI */
> + IPRDEF(0x740, IPRC, IPR_B4), /* SCIF BRI */
> + IPRDEF(0x760, IPRC, IPR_B4), /* SCIF TXI */
> + IPRDEF(0x780, IPRC, IPR_B8), /* DMAC DMTE4 */
> + IPRDEF(0x7a0, IPRC, IPR_B8), /* DMAC DMTE5 */
> + IPRDEF(0x7c0, IPRC, IPR_B8), /* DMAC DMTE6 */
> + IPRDEF(0x7e0, IPRC, IPR_B8), /* DMAC DMTE7 */
> + IPRDEF(0xa00, INTPRI00, IPR_B0), /* PCIC PCISERR */
> + IPRDEF(0xa20, INTPRI00, IPR_B4), /* PCIC PCIDMA3 */
> + IPRDEF(0xa40, INTPRI00, IPR_B4), /* PCIC PCIDMA2 */
> + IPRDEF(0xa60, INTPRI00, IPR_B4), /* PCIC PCIDMA1 */
> + IPRDEF(0xa80, INTPRI00, IPR_B4), /* PCIC PCIDMA0 */
> + IPRDEF(0xaa0, INTPRI00, IPR_B4), /* PCIC PCIPWON */
> + IPRDEF(0xac0, INTPRI00, IPR_B4), /* PCIC PCIPWDWN */
> + IPRDEF(0xae0, INTPRI00, IPR_B4), /* PCIC PCIERR */
> + IPRDEF(0xb00, INTPRI00, IPR_B8), /* TMU3 */
> + IPRDEF(0xb80, INTPRI00, IPR_B12), /* TMU4 */
Probably the same or a very similar interrupt controller is present
on other SoCs? Then the comments don't make much sense, as the actual
interrupt mapping is specified in the DTS anyway.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 15/30] Documentation/devicetree: Add renesas,sh7751-intc binding document.
2023-09-13 9:23 ` [RFC PATCH v2 15/30] Documentation/devicetree: Add renesas,sh7751-intc binding document Yoshinori Sato
2023-09-13 10:44 ` Krzysztof Kozlowski
@ 2023-09-19 11:56 ` Geert Uytterhoeven
1 sibling, 0 replies; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-19 11:56 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Hi Sato-san,
On Wed, Sep 13, 2023 at 11:26 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
> @@ -0,0 +1,45 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-intc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas SH7751 Interrupt Controller
> +
> +maintainers:
> + - Yoshinori Sato <ysato@users.sourceforge.jp>
> +
> +properties:
> + compatible:
> + items:
> + - const: renesas,sh7751-intc
> +
> + '#interrupt-cells':
> + # an interrupt index and flags, as defined in interrupts.txt in
> + # this directory
> + const: 2
> +
> + interrupt-controller: true
> +
> + reg:
> + minItems: 2
> + maxItems: 2
Please explain the meaning of each register bank, using
"description".
Perhaps reg-names, as there are two register banks?
> +
> + sh7751,irlm:
The vendor prefix should be "renesas".
> + description: If this value true. ICR.IRLM is 1.
This does not explain why you need this.
Is this hardware description, or software configuration?
> + $ref: /schemas/types.yaml#/definitions/bool
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 17/30] Documentation/devicetree: Add renesas,sh7751-irl-ext binding document.
2023-09-13 9:23 ` [RFC PATCH v2 17/30] Documentation/devicetree: Add renesas,sh7751-irl-ext binding document Yoshinori Sato
2023-09-13 10:45 ` Krzysztof Kozlowski
@ 2023-09-19 12:08 ` Geert Uytterhoeven
1 sibling, 0 replies; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-19 12:08 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Hi Sato-san,
On Wed, Sep 13, 2023 at 11:27 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> ---
> .../renesas,sh7751-irl-ext.yaml | 77 +++++++++++++++++++
> 1 file changed, 77 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
> new file mode 100644
> index 000000000000..dfc35717b92a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
> @@ -0,0 +1,77 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-irl-ext.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas SH7751 IRL external encoder with enable regs.
> +
> +maintainers:
> + - Yoshinori Sato <ysato@users.sourceforge.jp>
> +
> +description: |
> + This is the general used external interrupt encoder on SH7751 based boards.
generally
> +
> +properties:
> + compatible:
> + items:
> + - const: renesas,sh7751-irl-ext
> +
> + '#interrupt-cells':
> + # an interrupt index and flags, as defined in interrupts.txt in
> + # this directory
> + const: 2
> +
> + interrupt-controller: true
> +
> + reg:
> + minItems: 1
> +
> + sh7751irl,width:
Vendor prefix should be "renesas" (everywhere).
> + description: Enable register width
Specify
> + $ref: /schemas/types.yaml#/definitions/uint32
Perhaps this should be specified implicitly, by using a
different compatible value depending on the register width?
> +
> + sh7751irl,polarity:
> + description: Enable register polarity
Specify
> + $ref: /schemas/types.yaml#/definitions/uint32
Is this the interrupt polarity? If yes, that should be specified
by the consumer through the last cell of the interrupts property
(IRQ_TYPE_*).
> +
> + sh7751irl,irqbit:
> + description: IRQ to enable register bit mapping
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> +
> +
> +required:
> + - compatible
> + - '#interrupt-cells'
> + - interrupt-controller
> + - reg
> + - sh7751irl,width
> + - sh7751irl,polarity
> + - sh7751,irqbit
Vendor prefix does not match above.
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + r2dintc: sh7751irl_encoder@a4000000 {
Please align "r2dintc" with the "|" above.
> + compatible = "renesas,sh7751-irl-ext";
> + reg = <0xa4000000 0x02>;
> + interrupt-controller;
> + #address-cells = <1>;
make dt_binding_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
sh7751irl_encoder@a4000000: '#address-cells' does not match any of
the regexes: 'pinctrl-[0-9]+'
> + #interrupt-cells = <2>;
> + sh7751irl,width = <16>;
> + sh7751irl,polarity = <0>;
> + sh7751irl,irqbit =<11>, /* PCI INTD */
> + <9>, /* CF IDE */
> + <8>, /* CF CD */
> + <12>, /* PCI INTC */
> + <10>, /* SM501 */
> + <6>, /* KEY */
> + <5>, /* RTC ALARM */
> + <4>, /* RTC T */
> + <7>, /* SDCARD */
> + <14>, /* PCI INTA */
> + <13>, /* PCI INTB */
> + <0>, /* EXT */
> + <15>; /* TP */
'sh7751irl,irqbit', 'sh7751irl,polarity', 'sh7751irl,width' do not
match any of the regexes ...
> + };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 16/30] drivers/irqchip: SH7751 IRL external encoder with enable gate.
2023-09-13 9:23 ` [RFC PATCH v2 16/30] drivers/irqchip: SH7751 IRL external encoder with enable gate Yoshinori Sato
@ 2023-09-19 12:10 ` Geert Uytterhoeven
0 siblings, 0 replies; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-19 12:10 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Hi Sato-san,
On Wed, Sep 13, 2023 at 11:27 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> SH7751 have 15 level external interrupt.
> It is typically connected to the CPU through a priority encoder
> that can suppress requests.
> This driver provides a way to control those hardware with irqchip.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -688,4 +688,11 @@ config RENESAS_SH7751_INTC
> Support for the Renesas SH7751 On-chip interrupt controller.
> And external interrupt encoder for some targets.
>
> +config RENESAS_SH7751IRL_INTC
> + bool "Renesas SH7751 based target IRL encoder support."
> + depends on RENESAS_SH7751_INTC
> + help
Inconsistent indentation
> + Support for External Interrupt encoder
> + on the some Renesas SH7751 based target.
> +
> endmenu
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 18/30] drivers/clocksource: sh_tmu clocks property support.
2023-09-13 9:23 ` [RFC PATCH v2 18/30] drivers/clocksource: sh_tmu clocks property support Yoshinori Sato
@ 2023-09-19 12:15 ` Geert Uytterhoeven
0 siblings, 0 replies; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-19 12:15 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Hi Sato-san,
On Wed, Sep 13, 2023 at 11:29 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> --- a/drivers/clocksource/sh_tmu.c
> +++ b/drivers/clocksource/sh_tmu.c
> @@ -537,6 +537,9 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
>
> /* Get hold of clock. */
> tmu->clk = clk_get(&tmu->pdev->dev, "fck");
> + if (IS_ERR(tmu->clk) && IS_ENABLED(CONFIG_OF) && pdev->dev.of_node)
> + /* use DeviceTree clocks property */
> + tmu->clk = devm_clk_get(&tmu->pdev->dev, NULL);
This should not be needed.
I guess this is a workaround for the missing
clock-names = "fck";
in arch/sh/boot/dts/sh7751.dtsi?
"make dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/timer/renesas,tmu.yaml"
would have told you ;-)
timer@ffd80008: 'clock-names' is a required property
> if (IS_ERR(tmu->clk)) {
> dev_err(&tmu->pdev->dev, "cannot get clock\n");
> return PTR_ERR(tmu->clk);
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 19/30] drivers/tty: sh-sci fix SH4 OF support.
2023-09-13 9:23 ` [RFC PATCH v2 19/30] drivers/tty: sh-sci fix SH4 OF support Yoshinori Sato
@ 2023-09-19 12:25 ` Geert Uytterhoeven
2023-10-02 12:56 ` Yoshinori Sato
0 siblings, 1 reply; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-19 12:25 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Hi Sato-san,
Thanks for your patch!
On Wed, Sep 13, 2023 at 11:26 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> - fix earlycon name.
I guess you mean earlyprintk?
"Earlyprintk expects that all names used in OF_EARLYCON_DECLARE()
are unique".
> - fix earlyprintk hung (NULL pointer reference).
> - clocks property support.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c
> @@ -2842,6 +2842,8 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
> * global "peripheral_clk" clock.
> */
> clk = devm_clk_get(dev, "peripheral_clk");
> + if (IS_ERR(clk))
> + clk = devm_clk_get(dev, NULL);
This should not be needed.
I guess this is a workaround for the lack of
clock-names = "fck";
in arch/sh/boot/dts/sh7751.dtsi?
"make dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/serial/renesas,scif.yaml"
would have told you ;-)
serial@ffe80000: 'clock-names' is a required property
> if (IS_ERR(clk))
> return dev_err_probe(dev, PTR_ERR(clk),
> "failed to get %s\n",
> @@ -3555,8 +3557,8 @@ static int __init hscif_early_console_setup(struct earlycon_device *device,
>
> OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
> OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
> -OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
> -OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
> +OF_EARLYCON_DECLARE(rzscif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
> +OF_EARLYCON_DECLARE(rzscif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
Perhaps "rzscifa", to match the setup function prefix?
> OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
> OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
> OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 22/30] arch/sh: Add dtbs target support.
2023-09-13 9:23 ` [RFC PATCH v2 22/30] arch/sh: Add dtbs target support Yoshinori Sato
@ 2023-09-19 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-19 12:28 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Hi Sato-san,
On Wed, Sep 13, 2023 at 11:24 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> --- a/arch/sh/boot/dts/Makefile
> +++ b/arch/sh/boot/dts/Makefile
> @@ -1,2 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0-only
> obj-$(CONFIG_USE_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_SOURCE))
> +
> +dtb-$(CONFIG_CPU_J2) += j2_mimas_v2.dtb
Until here, everything is fine.
> +dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += landisk.dtb
> +dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += rts7751r2dplus.dtb
> +dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += usl-5p.dtb
These DTS files do not exist yet.
Please update the Makefile in each patch that adds a new DTS file.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 23/30] arch/sh: Add SH7751 SoC Internal periphreal devicetree.
2023-09-13 9:23 ` [RFC PATCH v2 23/30] arch/sh: Add SH7751 SoC Internal periphreal devicetree Yoshinori Sato
2023-09-13 10:49 ` Krzysztof Kozlowski
@ 2023-09-19 12:41 ` Geert Uytterhoeven
2023-09-19 13:11 ` Geert Uytterhoeven
2 siblings, 0 replies; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-19 12:41 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Hi Sato-san,
On Wed, Sep 13, 2023 at 11:24 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> --- /dev/null
> +++ b/arch/sh/boot/dts/sh7751.dtsi
> @@ -0,0 +1,76 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the SH7751 SoC
> + */
> +
> +#include <dt-bindings/interrupt-controller/sh_intc.h>
> +#include <dt-bindings/clock/sh7750.h>
> +
> +/ {
Missing top-level compatible property:
compatible = "renesas,sh7751r";
And of course this compatible value should be documented in
Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
Please add a blank line between properties and subnodes.
> + cpu@0 {
> + compatible = "renesas,sh7751r","renesas,sh4", "renesas,sh";
> + };
> + };
> +
> + clocks {
s/clocks/soc/, and move everything below inside the "soc" container.
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + cpg: cpg@ffc00000 {
Please use generic node names: clock-controller@ffc00000;
> + #clock-cells = <1>;
> + compatible = "renesas,sh7750-cpg";
> + clocks = <&xtal>;
> + reg = <0xffc00000 2>, <0xffc00008 4>;
> + };
> +
> + };
> +
> + shintc: interrupt-controller@ffd00000 {
> + compatible = "renesas,sh7751-intc";
> + #interrupt-cells = <2>;
> + #address-cells = <0>;
> + interrupt-controller;
> + reg = <0xffd00000 14>, <0xfe080000 128>;
> + };
> +
> + /* sci0 is rarely used, so it is not defined here. */
> + scif1: serial@ffe80000 {
> + compatible = "renesas,scif";
Please add (and document!) "renesas,scif-sh7751".
> + reg = <0xffe80000 0x100>;
> + interrupts = <evt2irq(0x700) 0>,
> + <evt2irq(0x720) 0>,
> + <evt2irq(0x760) 0>,
> + <evt2irq(0x740) 0>;
> + interrupt-names = "eri", "rxi", "bri", "txi";
make dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/serial/renesas,scif.yaml
serial@ffe80000: interrupt-names: 'oneOf' conditional failed, one
must be fixed:
['eri', 'rxi', 'bri', 'txi'] is too short
'txi' was expected
'bri' was expected
The "bri" and "txi" entries must be exchanged, both in the
"interrupts" and "interrupt-names" properties.
> + clocks = <&cpg SH7750_CPG_FCK>;
clock-names = "fck";
> + };
> +
> + /* Normally ch0 and ch1 are used, so we will define ch0 to ch2 here. */
> + tmu0: timer@ffd80008 {
> + compatible = "renesas,tmu";
Please add (and document!) "renesas,tmu-sh7751".
> + reg = <0xffd80000 12>;
> + interrupts = <evt2irq(0x400) 0>,
> + <evt2irq(0x420) 0>,
> + <evt2irq(0x440) 0>,
> + <evt2irq(0x460) 0>;
> + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
This will need an update to the bindings, and the driver, too.
> + clocks = <&cpg SH7750_CPG_FCK>;
clock-names = "fck";
> + renesas,channels = <3>;
> + };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 24/30] include/dt-bindings: Add SH7750 CPG header.
2023-09-13 10:46 ` Krzysztof Kozlowski
@ 2023-09-19 12:43 ` Geert Uytterhoeven
2023-09-20 11:52 ` Krzysztof Kozlowski
0 siblings, 1 reply; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-19 12:43 UTC (permalink / raw)
To: Krzysztof Kozlowski; +Cc: Yoshinori Sato, linux-sh, glaubitz
Hi Krzysztof,
On Wed, Sep 13, 2023 at 12:49 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> On 13/09/2023 11:23, Yoshinori Sato wrote:
> > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
>
> > include/dt-bindings/clock/sh7750.h | 13 +++++++++++++
>
> Missing vendor prefix.
None of the clock binding definitions for Renesas SoCs use a
vendor prefix. The same is true for various other vendors.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 24/30] include/dt-bindings: Add SH7750 CPG header.
2023-09-13 9:23 ` [RFC PATCH v2 24/30] include/dt-bindings: Add SH7750 CPG header Yoshinori Sato
2023-09-13 10:46 ` Krzysztof Kozlowski
@ 2023-09-19 12:46 ` Geert Uytterhoeven
1 sibling, 0 replies; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-19 12:46 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Hi Sato-san,
On Wed, Sep 13, 2023 at 11:29 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> include/dt-bindings/clock/sh7750.h | 13 +++++++++++++
This is a dependency for both the clock driver and the various
DTS files, so it should be moved up in the series.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 25/30] include/dt-bindings: Add sh_intc IRQ - EVT conversion helper
2023-09-13 10:47 ` Krzysztof Kozlowski
@ 2023-09-19 13:02 ` Geert Uytterhoeven
2023-09-20 11:51 ` Krzysztof Kozlowski
0 siblings, 1 reply; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-19 13:02 UTC (permalink / raw)
To: Krzysztof Kozlowski; +Cc: Yoshinori Sato, linux-sh, glaubitz
Hi Krzysztof,
On Wed, Sep 13, 2023 at 12:50 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> On 13/09/2023 11:23, Yoshinori Sato wrote:
> > --- /dev/null
> > +++ b/include/dt-bindings/interrupt-controller/sh_intc.h
> > @@ -0,0 +1,7 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > + *
> > + * SH3/4 INTC EVT - IRQ conversion
> > + */
> > +
> > +#define evt2irq(evt) ((evt) >> 5)
> > +#define irq2evt(irq) ((irq) << 5)
>
> No, that's not a binding. Drop entire file.
The issue is that the hardware documentation does not list interrupt
numbers, but event codes. The latter is a sparse address space.
As the "interrupts" property needs interrupt numbers, we have two
options:
1. Use hardcoded event codes and evt2irq() in DTS files.
This is the approach Sato-san took,
2. Use hardcoded interrupt numbers in DTS files.
This would avoids the need for the evt2irq() macro in the DT bindings,
but would make life slightly harder for the DTS writer and
for the casual reader, as the conversion needs to be done in
one's head.
Note that the documentation for later SoCs that contain both a SuperH
and an ARM CPU core, usually lists both the event code and the interrupt
number, although the latter may be offset by 32 due to the SPI
interrupt base.
I agree we do not need irq2evt() in DTS, though.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 25/30] include/dt-bindings: Add sh_intc IRQ - EVT conversion helper
2023-09-13 9:23 ` [RFC PATCH v2 25/30] include/dt-bindings: Add sh_intc IRQ - EVT conversion helper Yoshinori Sato
2023-09-13 10:47 ` Krzysztof Kozlowski
@ 2023-09-19 13:05 ` Geert Uytterhoeven
1 sibling, 0 replies; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-19 13:05 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Hi Sato-san,
On Wed, Sep 13, 2023 at 11:27 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> arch/sh/boot/dts/include/dt-bindings | 1 +
> include/dt-bindings/interrupt-controller/sh_intc.h | 7 +++++++
> 2 files changed, 8 insertions(+)
> create mode 120000 arch/sh/boot/dts/include/dt-bindings
> create mode 100644 include/dt-bindings/interrupt-controller/sh_intc.h
>
> diff --git a/arch/sh/boot/dts/include/dt-bindings b/arch/sh/boot/dts/include/dt-bindings
> new file mode 120000
> index 000000000000..08c00e4972fa
> --- /dev/null
> +++ b/arch/sh/boot/dts/include/dt-bindings
> @@ -0,0 +1 @@
> +../../../../../include/dt-bindings
Do you need this symlink? All other architectures do without.
> --- /dev/null
> +++ b/include/dt-bindings/interrupt-controller/sh_intc.h
This is used by the DTS files, so this patch should be moved up in
this series.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 23/30] arch/sh: Add SH7751 SoC Internal periphreal devicetree.
2023-09-13 9:23 ` [RFC PATCH v2 23/30] arch/sh: Add SH7751 SoC Internal periphreal devicetree Yoshinori Sato
2023-09-13 10:49 ` Krzysztof Kozlowski
2023-09-19 12:41 ` Geert Uytterhoeven
@ 2023-09-19 13:11 ` Geert Uytterhoeven
2 siblings, 0 replies; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-19 13:11 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Hi Sato-san,
On Wed, Sep 13, 2023 at 11:24 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> --- /dev/null
> +++ b/arch/sh/boot/dts/sh7751.dtsi
> @@ -0,0 +1,76 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the SH7751 SoC
> + */
> +
> +#include <dt-bindings/interrupt-controller/sh_intc.h>
> +#include <dt-bindings/clock/sh7750.h>
> +
> +/ {
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cpu@0 {
> + compatible = "renesas,sh7751r","renesas,sh4", "renesas,sh";
> + };
> + };
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + cpg: cpg@ffc00000 {
> + #clock-cells = <1>;
> + compatible = "renesas,sh7750-cpg";
renesas,sh7751-cpg?
> + clocks = <&xtal>;
Please provide an xtal (or extal) fixed-clock placeholder, to be
filled in by the board DTS.
(cfr. extal_clk in arch/arm64/boot/dts/renesas/r8a77951.dtsi)
> + reg = <0xffc00000 2>, <0xffc00008 4>;
> + };
> +
> + };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 26/30] arch/sh: RTS7751R2D Plus DeviceTree.
2023-09-13 9:23 ` [RFC PATCH v2 26/30] arch/sh: RTS7751R2D Plus DeviceTree Yoshinori Sato
2023-09-13 10:49 ` Krzysztof Kozlowski
2023-09-15 15:43 ` Geert Uytterhoeven
@ 2023-09-19 13:25 ` Geert Uytterhoeven
2023-10-02 13:21 ` Yoshinori Sato
2 siblings, 1 reply; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-19 13:25 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Hi Sato-san,
On Wed, Sep 13, 2023 at 11:24 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> --- /dev/null
> +++ b/arch/sh/boot/dts/rts7751r2dplus.dts
> @@ -0,0 +1,124 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the Renesas RTS7751R2D Plus
> + */
> +
> +/dts-v1/;
> +
> +#include "sh7751.dtsi"
#include "sh7751r.dtsi"?
To make that work, you can create "sh7751.dtsi" that includes
"sh7751.dtsi" and overrides the parts that are different.
> +
> +/ {
> + model = "Renesas RTS7715R2D Plus";
> + compatible = "renesas,r2dplus";
compatible = "renesas,r2dplus", "renesas,sh7751r", "renesas,sh7751".
And all these compatible values must be documented in the DT
binding documentation.
> + #address-cells = <1>;
> + #size-cells = <1>;
> + interrupt-parent = <&shintc>;
> +
> + aliases {
> + serial0 = &scif1;
> + };
> +
> + chosen {
> + };
> +
> + clocks {
> + xtal: oscillator {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <22222222>;
> + };
Please
> +
> + cpg: cpg@ffc00000 {
"&cpg"?
> + compatible = "renesas,sh7750r-cpg",
> + "renesas,sh7750-cpg";
There should be no need to override the cpg's compatible value.
> + renesas,mode = <5>;
> + };
> + };
> +
> + cpus {
> + cpu@0 {
> + clock-frequency = <266666666>;
As the CPU clock is programmable, the "clock-frequency"
property should probably be replaced by a "clocks" property in the
base sh7751.dtsi.
> + };
> + };
> +
> + memory@c000000 {
> + device_type = "memory";
> + reg = <0x0c000000 0x4000000>;
> + };
> +
> + r2dintc: sh7751irl_encoder@a4000000 {
> + compatible = "renesas,sh7751-irl-ext";
> + reg = <0xa4000000 0x02>;
> + interrupt-controller;
> + #address-cells = <1>;
> + #interrupt-cells = <2>;
> + sh7751irl,width = <16>;
> + sh7751irl,polarity = <0>;
> + sh7751irl,irqbit =<11>, /* PCI INTD */
> + <9>, /* CF IDE */
> + <8>, /* CF CD */
> + <12>, /* PCI INTC */
> + <10>, /* SM501 */
> + <6>, /* KEY */
> + <5>, /* RTC ALARM */
> + <4>, /* RTC T */
> + <7>, /* SDCARD */
> + <14>, /* PCI INTA */
> + <13>, /* PCI INTB */
> + <0>, /* EXT */
> + <15>; /* TP */
> + };
> +
> + display@1,0 {
> + compatible = "smi,sm501";
> + reg = <0x10000000 0x03e00000
> + 0x13e00000 0x00200000>;
> + interrupt-parent = <&r2dintc>;
> + interrupts = <4 0>;
> + mode = "640x480-16@60";
> + little-endian;
> + sm501,devices = "usb-host","uart0";
> + };
> +
> + compact-flash@b4001000 {
> + compatible = "ata-generic";
compact-flash@b4001000: compatible:0: 'ata-generic' is not one of
['arm,vexpress-cf', 'fsl,mpc8349emitx-pata']
from schema $id: http://devicetree.org/schemas/ata/ata-generic.yaml#
> + reg = <0xb4001000 0x0e>, <0xb400080c 2>;
> + reg-shift = <1>;
> + interrupt-parent = <&r2dintc>;
> + interrupts = <1 0>;
> + };
> +
> + flash@0 {
> + compatible = "cfi-flash";
> + reg = <0x00000000 0x02000000>;
> + device-width = <2>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + partition@0 {
> + label = "U-Boot";
> + reg = <0x00000000 0x00040000>;
> + };
> + partition@1 {
> + label = "Environemt";
Environment
> + reg = <0x00040000 0x00040000>;
> + };
Several of the above comments apply to "[RFC PATCH v2 27/30]
arch/sh: LANDISK DeviceTree." and "[RFC PATCH v2 28/30] arch/sh:
USL-5P DeviceTree.", too.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 25/30] include/dt-bindings: Add sh_intc IRQ - EVT conversion helper
2023-09-19 13:02 ` Geert Uytterhoeven
@ 2023-09-20 11:51 ` Krzysztof Kozlowski
2023-09-20 12:30 ` Geert Uytterhoeven
0 siblings, 1 reply; 83+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-20 11:51 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Yoshinori Sato, linux-sh, glaubitz
On 19/09/2023 15:02, Geert Uytterhoeven wrote:
> Hi Krzysztof,
>
> On Wed, Sep 13, 2023 at 12:50 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>> On 13/09/2023 11:23, Yoshinori Sato wrote:
>>> --- /dev/null
>>> +++ b/include/dt-bindings/interrupt-controller/sh_intc.h
>>> @@ -0,0 +1,7 @@
>>> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> + *
>>> + * SH3/4 INTC EVT - IRQ conversion
>>> + */
>>> +
>>> +#define evt2irq(evt) ((evt) >> 5)
>>> +#define irq2evt(irq) ((irq) << 5)
>>
>> No, that's not a binding. Drop entire file.
>
> The issue is that the hardware documentation does not list interrupt
> numbers, but event codes. The latter is a sparse address space.
> As the "interrupts" property needs interrupt numbers, we have two
> options:
> 1. Use hardcoded event codes and evt2irq() in DTS files.
> This is the approach Sato-san took,
> 2. Use hardcoded interrupt numbers in DTS files.
> This would avoids the need for the evt2irq() macro in the DT bindings,
> but would make life slightly harder for the DTS writer and
> for the casual reader, as the conversion needs to be done in
> one's head.
>
> Note that the documentation for later SoCs that contain both a SuperH
> and an ARM CPU core, usually lists both the event code and the interrupt
> number, although the latter may be offset by 32 due to the SPI
> interrupt base.
>
> I agree we do not need irq2evt() in DTS, though.
Is the macro used by the drivers? I have a feeling that not, so it would
not be suitable for the bindings, but rather as a header included in the
DTS.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 24/30] include/dt-bindings: Add SH7750 CPG header.
2023-09-19 12:43 ` Geert Uytterhoeven
@ 2023-09-20 11:52 ` Krzysztof Kozlowski
0 siblings, 0 replies; 83+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-20 11:52 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Yoshinori Sato, linux-sh, glaubitz
On 19/09/2023 14:43, Geert Uytterhoeven wrote:
> Hi Krzysztof,
>
> On Wed, Sep 13, 2023 at 12:49 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>> On 13/09/2023 11:23, Yoshinori Sato wrote:
>>> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
>>
>>> include/dt-bindings/clock/sh7750.h | 13 +++++++++++++
>>
>> Missing vendor prefix.
>
> None of the clock binding definitions for Renesas SoCs use a
> vendor prefix. The same is true for various other vendors.
So how about start using them for new bindings. :)
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 07/30] drivers/pci: SH7751 PCI Host bridge controller driver.
2023-09-18 15:32 ` Geert Uytterhoeven
@ 2023-09-20 12:15 ` Yoshinori Sato
0 siblings, 0 replies; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-20 12:15 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: linux-sh, glaubitz, linux-pci
On Tue, 19 Sep 2023 00:32:46 +0900,
Geert Uytterhoeven wrote:
>
> Hi Sato-san,
>
> On Wed, Sep 13, 2023 at 11:35 AM Yoshinori Sato
> <ysato@users.sourceforge.jp> wrote:
> > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/drivers/pci/controller/pci-sh7751.c
> > @@ -0,0 +1,338 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * SH7751 PCI driver
> > + * Copyright (C) 2023 Yoshinori Sato
> > + *
> > + */
> > +
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_pci.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/pci-ecam.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/io.h>
> > +#include <asm-generic/pci.h>
> > +#include "pci-sh7751.h"
> > +
> > +#define pcic_writel(val, reg) __raw_writel(val, pci_reg_base + (reg))
> > +#define pcic_readl(reg) __raw_readl(pci_reg_base + (reg))
> > +
> > +DEFINE_RAW_SPINLOCK(pci_config_lock);
> > +
> > +/*
> > + * PCIC fixups
> > + */
> > +
> > +#define PCIMCR_MRSET 0x40000000
> > +#define PCIMCR_RFSH 0x00000004
> > +
> > +/* board depend PCI bus fixups */
> > +static void __init julian_fixup(void __iomem *pci_reg_base, void __iomem *bcr)
>
> Please drop all the __init* annotations.
> Although I no longer see invalid section warnings, all symbols tagged
> with __init* are still referenced from sh7751_pci_probe(), eventually.
>
> > +{
> > + unsigned long bcr1, mcr;
> > +
> > + bcr1 = __raw_readl(bcr + SH7751_BCR1);
> > + bcr1 |= 0x00080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
> > + pcic_writel(bcr1, SH4_PCIBCR1);
> > +
> > + mcr = __raw_readl(bcr + SH7751_MCR);
> > + mcr &= (~PCIMCR_MRSET) & (~PCIMCR_RFSH);
> > + pcic_writel(mcr, SH4_PCIMCR);
> > +
> > + pcic_writel(0x0c000000, SH7751_PCICONF5);
> > + pcic_writel(0xd0000000, SH7751_PCICONF6);
> > + pcic_writel(0x0c000000, SH4_PCILAR0);
> > + pcic_writel(0x00000000, SH4_PCILAR1);
> > +}
> > +
> > +static void __init r2d_fixup(void __iomem *pci_reg_base, void __iomem *bcr)
> > +{
> > + unsigned long bcr1, mcr;
> > +
> > + bcr1 = ioread32(bcr + SH7751_BCR1);
> > + bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
> > + pcic_writel(bcr1, SH4_PCIBCR1);
> > +
> > + /* Enable all interrupts, so we known what to fix */
> > + pcic_writel(0x0000c3ff, SH4_PCIINTM);
> > + pcic_writel(0x0000380f, SH4_PCIAINTM);
> > +
> > + pcic_writel(0xfb900047, SH7751_PCICONF1);
> > + pcic_writel(0xab000001, SH7751_PCICONF4);
> > +
> > + mcr = ioread32(bcr + SH7751_MCR);
> > + mcr &= (~PCIMCR_MRSET) & (~PCIMCR_RFSH);
> > + pcic_writel(mcr, SH4_PCIMCR);
> > +
> > + pcic_writel(0x0c000000, SH7751_PCICONF5);
> > + pcic_writel(0xd0000000, SH7751_PCICONF6);
> > + pcic_writel(0x0c000000, SH4_PCILAR0);
> > + pcic_writel(0x00000000, SH4_PCILAR1);
> > +}
> > +
> > +static const __initconst struct fixups {
> > + char *compatible;
> > + void (*fixup)(void __iomem *pci_reg_base, void __iomem *bcr);
> > +} fixup_list[] = {
> > + {
> > + .compatible = "iodata,julian-pci",
> > + .fixup = julian_fixup,
> > + },
> > + {
> > + .compatible = "renesas,r2d-pci",
> > + .fixup = r2d_fixup,
> > + },
> > +};
>
> These fixups seem to be board-specific instead of specific to the
> PCI block in the SoCs on these boards.
>
> I see three options to handle this in a more appropriate way:
> 1. Handle this in the bootloader.
> Not an attractive solution, as not everyone can/wants to update
> the bootloader,
> 2. Use of_machine_is_compatible() in a platform-specific quirk
> handler, outside the PCI driver,
> 3. Move the common parts into sh7751_pci_probe(), and the
> handle the differences through DT topology analysis and/or
> properties in DT.
I think the bootloader is not initialized on targets that do not use
a PCI device for booting.
I think it's better to use option 2 or 3.
I looked at the current fixup, but the only difference is the PCIC setting,
so I will try plan 3.
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
--
Yosinori Sato
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 20/30] drivers/mfd: sm501 add some properties.
2023-09-13 9:23 ` [RFC PATCH v2 20/30] drivers/mfd: sm501 add some properties Yoshinori Sato
@ 2023-09-20 12:25 ` Lee Jones
0 siblings, 0 replies; 83+ messages in thread
From: Lee Jones @ 2023-09-20 12:25 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Subject line is wrong in many of your commits.
Use `git log --online -- <subsystem>` to help you.
On Wed, 13 Sep 2023, Yoshinori Sato wrote:
> SM501's OF support is not enough parameter in platform device.
> This change adds the missing parameter.
You need more information.
What currently doesn't work? How does this help?
How does it work? What will happen if it's not applied?
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> ---
> drivers/mfd/sm501.c | 113 ++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 113 insertions(+)
Please resubmit this set and Cc it to everyone.
I would like to see all of the changes please, since they are related.
> diff --git a/drivers/mfd/sm501.c b/drivers/mfd/sm501.c
> index 28027982cf69..82508f6d96da 100644
> --- a/drivers/mfd/sm501.c
> +++ b/drivers/mfd/sm501.c
> @@ -1370,6 +1370,113 @@ static int sm501_init_dev(struct sm501_devdata *sm)
> return 0;
> }
>
> +#if defined(CONFIG_OF)
Avoid #ifery as much as possible.
> +static unsigned int sm501_parse_devices_str(struct device_node *np)
> +{
> + unsigned int device = 0;
> + unsigned int i, j;
> + unsigned int nstr;
> + const char *devstr;
> + static const struct {
> + char *devname;
> + unsigned int devid;
> + } devlist[] = {
> + { "usb-host", SM501_USE_USB_HOST },
> + { "usb-gadget", SM501_USE_USB_SLAVE },
> + { "ssp0", SM501_USE_SSP0 },
> + { "ssp1", SM501_USE_SSP1 },
> + { "uart0", SM501_USE_UART0 },
> + { "uart1", SM501_USE_UART1 },
> + { "accel", SM501_USE_FBACCEL },
> + { "ac97", SM501_USE_AC97 },
> + { "i2s", SM501_USE_I2S },
> + { "gpio", SM501_USE_GPIO },
> + { "all", SM501_USE_ALL },
> + };
> +
> + nstr = of_property_count_strings(np, "sm501,devices");
> + for (i = 0; i < nstr; i++) {
> + if (of_property_read_string_index(np, "sm501,devices", i, &devstr))
Not a lot I can do without seeing the DT binding.
> + break;
> + for (j = 0; j < ARRAY_SIZE(devlist); j++) {
> + if (strcmp(devstr, devlist[j].devname) == 0) {
> + device |= devlist[j].devid;
> + goto next;
> + }
> + }
> +next:
> + }
> + return device;
> +}
> +
> +static void sm501_of_read_reg_init(struct device_node *np,
> + const char *propname, struct sm501_reg_init *val)
> +{
> + u32 u32_val[2];
> +
> + if (!of_property_read_u32_array(np, propname, u32_val, sizeof(u32_val))) {
> + val->set = u32_val[0];
> + val->mask = u32_val[1];
> + } else {
> + val->set = 0;
> + val->mask = 0;
> + }
> +}
> +
> +static int sm501_parse_dt(struct sm501_devdata *sm, struct device_node *np)
> +{
> + struct sm501_platdata *plat;
> + u32 u32_val;
> +
> + plat = devm_kzalloc(sm->dev, sizeof(struct sm501_platdata), GFP_KERNEL);
sizeof(*plat)
> + if (plat == NULL)
if (!plat)
> + return -ENOMEM;
> +
> + plat->init = devm_kzalloc(sm->dev, sizeof(struct sm501_initdata), GFP_KERNEL);
> + if (plat->init == NULL)
> + return -ENOMEM;
> +
> + plat->init->devices = sm501_parse_devices_str(np);
> +
> + if (!of_property_read_u32_index(np, "sm501,mclk", 0, &u32_val))
> + plat->init->mclk = u32_val;
> + else
> + plat->init->mclk = 0;
> +
> + if (!of_property_read_u32_index(np, "sm501,m1xclk", 0, &u32_val))
> + plat->init->m1xclk = u32_val;
> + else
> + plat->init->m1xclk = 0;
> +
> + sm501_of_read_reg_init(np, "sm501,misc-timing", &plat->init->misc_timing);
> + sm501_of_read_reg_init(np, "sm501,misc-control", &plat->init->misc_control);
> + sm501_of_read_reg_init(np, "sm501,gpio-low", &plat->init->gpio_low);
> + sm501_of_read_reg_init(np, "sm501,gpio-high", &plat->init->gpio_high);
> +
> +#ifdef CONFIG_MFD_SM501_GPIO
> + if (plat->init->devices & SM501_USE_GPIO) {
> + if (!of_property_read_u32_index(np, "sm501,num-i2c", 0, &u32_val))
> + plat->gpio_i2c_nr = u32_val;
> + else
> + plat->gpio_i2c_nr = 0;
> + }
> + if (plat->gpio_i2c_nr > 0) {
> + int sz_gpio;
> +
> + sz_gpio = sizeof(struct sm501_platdata_gpio_i2c) * plat->gpio_i2c_nr;
> + plat->gpio_i2c = devm_kzalloc(sm->dev, sz_gpio, GFP_KERNEL);
> + if (plat->gpio_i2c == NULL)
> + return -ENOMEM;
> +
> + of_property_read_variable_u32(np, "sm501,gpio-i2c",
> + plat->gpio_i2c, plat->gpio_i2c_nr * 5);
> + }
> +#endif
> + sm->platdata = plat;
> + return 0;
> +}
> +#endif
> +
> static int sm501_plat_probe(struct platform_device *dev)
> {
> struct sm501_devdata *sm;
> @@ -1406,6 +1513,12 @@ static int sm501_plat_probe(struct platform_device *dev)
> goto err_res;
> }
>
> + if (IS_ENABLED(CONFIG_OF) && dev->dev.of_node) {
> + ret = sm501_parse_dt(sm, dev->dev.of_node);
> + if (ret)
> + goto err_res;
> + }
> +
> platform_set_drvdata(dev, sm);
>
> sm->regs = ioremap(sm->io_res->start, resource_size(sm->io_res));
> --
> 2.39.2
>
--
Lee Jones [李琼斯]
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 25/30] include/dt-bindings: Add sh_intc IRQ - EVT conversion helper
2023-09-20 11:51 ` Krzysztof Kozlowski
@ 2023-09-20 12:30 ` Geert Uytterhoeven
0 siblings, 0 replies; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-20 12:30 UTC (permalink / raw)
To: Krzysztof Kozlowski; +Cc: Yoshinori Sato, linux-sh, glaubitz
Hi Krzysztof,
On Wed, Sep 20, 2023 at 1:51 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> On 19/09/2023 15:02, Geert Uytterhoeven wrote:
> > On Wed, Sep 13, 2023 at 12:50 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >> On 13/09/2023 11:23, Yoshinori Sato wrote:
> >>> --- /dev/null
> >>> +++ b/include/dt-bindings/interrupt-controller/sh_intc.h
> >>> @@ -0,0 +1,7 @@
> >>> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >>> + *
> >>> + * SH3/4 INTC EVT - IRQ conversion
> >>> + */
> >>> +
> >>> +#define evt2irq(evt) ((evt) >> 5)
> >>> +#define irq2evt(irq) ((irq) << 5)
> >>
> >> No, that's not a binding. Drop entire file.
> >
> > The issue is that the hardware documentation does not list interrupt
> > numbers, but event codes. The latter is a sparse address space.
> > As the "interrupts" property needs interrupt numbers, we have two
> > options:
> > 1. Use hardcoded event codes and evt2irq() in DTS files.
> > This is the approach Sato-san took,
> > 2. Use hardcoded interrupt numbers in DTS files.
> > This would avoids the need for the evt2irq() macro in the DT bindings,
> > but would make life slightly harder for the DTS writer and
> > for the casual reader, as the conversion needs to be done in
> > one's head.
> >
> > Note that the documentation for later SoCs that contain both a SuperH
> > and an ARM CPU core, usually lists both the event code and the interrupt
> > number, although the latter may be offset by 32 due to the SPI
> > interrupt base.
> >
> > I agree we do not need irq2evt() in DTS, though.
>
> Is the macro used by the drivers? I have a feeling that not, so it would
> not be suitable for the bindings, but rather as a header included in the
> DTS.
You mean irq2evt()? No, the new DT-aware drivers avoid the conversion
from IRQ numbers to events codes by storing evt2irq() values in the
interrupt table (see drivers/irqchip/irq-renesas-sh7751.c:iprmaps[]).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 14/30] drivers/irqchip: Add SH7751 Internal INTC drivers.
2023-09-19 11:50 ` Geert Uytterhoeven
@ 2023-09-22 10:12 ` Yoshinori Sato
2023-09-25 7:38 ` Geert Uytterhoeven
0 siblings, 1 reply; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-22 10:12 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: linux-sh, glaubitz
On Tue, 19 Sep 2023 20:50:14 +0900,
Geert Uytterhoeven wrote:
>
> Hi Sato-san,
>
> On Wed, Sep 13, 2023 at 11:24 AM Yoshinori Sato
> <ysato@users.sourceforge.jp> wrote:
> > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
>
> Thanks for your patch!
>
> > --- a/drivers/irqchip/Kconfig
> > +++ b/drivers/irqchip/Kconfig
> > @@ -679,4 +679,13 @@ config SUNPLUS_SP7021_INTC
> > chained controller, routing all interrupt source in P-Chip to
> > the primary controller on C-Chip.
> >
> > +config RENESAS_SH7751_INTC
> > + bool "Renesas SH7751 Interrupt Controller"
> > + depends on SH_DEVICE_TREE
>
> "|| COMPILE_TEST"?
>
> > + select IRQ_DOMAIN
> > + select IRQ_DOMAIN_HIERARCHY
> > + help
> > + Support for the Renesas SH7751 On-chip interrupt controller.
> > + And external interrupt encoder for some targets.
>
> Inconsistent indentation
>
> > --- /dev/null
> > +++ b/drivers/irqchip/irq-renesas-sh7751.c
>
> > +/* INTEVT to IPR mapping */
> > +static const struct iprmap {
> > + int intevt;
>
> irq, as you're storing the irq number not the event number?
>
> > + int off;
> > + int bit;
>
> All unsigned int ...
>
> > +} iprmaps[] = {
> > +#define IPRDEF(e, o, b) { .intevt = evt2irq(e), .off = o, .bit = b }
> > + IPRDEF(0x240, IPRD, IPR_B12), /* IRL0 */
> > + IPRDEF(0x2a0, IPRD, IPR_B8), /* IRL1 */
> > + IPRDEF(0x300, IPRD, IPR_B4), /* IRL2 */
> > + IPRDEF(0x360, IPRD, IPR_B0), /* IRL3 */
> > + IPRDEF(0x400, IPRA, IPR_B12), /* TMU0 */
> > + IPRDEF(0x420, IPRA, IPR_B8), /* TMU1 */
> > + IPRDEF(0x440, IPRA, IPR_B4), /* TMU2 TNUI */
> > + IPRDEF(0x460, IPRA, IPR_B4), /* TMU2 TICPI */
> > + IPRDEF(0x480, IPRA, IPR_B0), /* RTC ATI */
> > + IPRDEF(0x4a0, IPRA, IPR_B0), /* RTC PRI */
> > + IPRDEF(0x4c0, IPRA, IPR_B0), /* RTC CUI */
> > + IPRDEF(0x4e0, IPRB, IPR_B4), /* SCI ERI */
> > + IPRDEF(0x500, IPRB, IPR_B4), /* SCI RXI */
> > + IPRDEF(0x520, IPRB, IPR_B4), /* SCI TXI */
> > + IPRDEF(0x540, IPRB, IPR_B4), /* SCI TEI */
> > + IPRDEF(0x560, IPRB, IPR_B12), /* WDT */
> > + IPRDEF(0x580, IPRB, IPR_B8), /* REF RCMI */
> > + IPRDEF(0x5a0, IPRB, IPR_B4), /* REF ROVI */
> > + IPRDEF(0x600, IPRC, IPR_B0), /* H-UDI */
> > + IPRDEF(0x620, IPRC, IPR_B12), /* GPIO */
> > + IPRDEF(0x640, IPRC, IPR_B8), /* DMAC DMTE0 */
> > + IPRDEF(0x660, IPRC, IPR_B8), /* DMAC DMTE1 */
> > + IPRDEF(0x680, IPRC, IPR_B8), /* DMAC DMTE2 */
> > + IPRDEF(0x6a0, IPRC, IPR_B8), /* DMAC DMTE3 */
> > + IPRDEF(0x6c0, IPRC, IPR_B8), /* DMAC DMAE */
> > + IPRDEF(0x700, IPRC, IPR_B4), /* SCIF ERI */
> > + IPRDEF(0x720, IPRC, IPR_B4), /* SCIF RXI */
> > + IPRDEF(0x740, IPRC, IPR_B4), /* SCIF BRI */
> > + IPRDEF(0x760, IPRC, IPR_B4), /* SCIF TXI */
> > + IPRDEF(0x780, IPRC, IPR_B8), /* DMAC DMTE4 */
> > + IPRDEF(0x7a0, IPRC, IPR_B8), /* DMAC DMTE5 */
> > + IPRDEF(0x7c0, IPRC, IPR_B8), /* DMAC DMTE6 */
> > + IPRDEF(0x7e0, IPRC, IPR_B8), /* DMAC DMTE7 */
> > + IPRDEF(0xa00, INTPRI00, IPR_B0), /* PCIC PCISERR */
> > + IPRDEF(0xa20, INTPRI00, IPR_B4), /* PCIC PCIDMA3 */
> > + IPRDEF(0xa40, INTPRI00, IPR_B4), /* PCIC PCIDMA2 */
> > + IPRDEF(0xa60, INTPRI00, IPR_B4), /* PCIC PCIDMA1 */
> > + IPRDEF(0xa80, INTPRI00, IPR_B4), /* PCIC PCIDMA0 */
> > + IPRDEF(0xaa0, INTPRI00, IPR_B4), /* PCIC PCIPWON */
> > + IPRDEF(0xac0, INTPRI00, IPR_B4), /* PCIC PCIPWDWN */
> > + IPRDEF(0xae0, INTPRI00, IPR_B4), /* PCIC PCIERR */
> > + IPRDEF(0xb00, INTPRI00, IPR_B8), /* TMU3 */
> > + IPRDEF(0xb80, INTPRI00, IPR_B12), /* TMU4 */
>
> Probably the same or a very similar interrupt controller is present
> on other SoCs? Then the comments don't make much sense, as the actual
> interrupt mapping is specified in the DTS anyway.
This interrupt controller design is quite old, so there doesn't seem to be
any SoC with a similar design.
Since the SH interrupt controllers have almost the same design,
I think this driver can be used for other devices besides the SH7751.
I think a good way to write IPR mapping is to use dts.
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
--
Yosinori Sato
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 14/30] drivers/irqchip: Add SH7751 Internal INTC drivers.
2023-09-22 10:12 ` Yoshinori Sato
@ 2023-09-25 7:38 ` Geert Uytterhoeven
2023-09-30 15:14 ` Yoshinori Sato
0 siblings, 1 reply; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-09-25 7:38 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Hi Sato-san,
On Fri, Sep 22, 2023 at 12:12 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> On Tue, 19 Sep 2023 20:50:14 +0900,
> Geert Uytterhoeven wrote:
> > On Wed, Sep 13, 2023 at 11:24 AM Yoshinori Sato
> > <ysato@users.sourceforge.jp> wrote:
> > > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> >
> > Thanks for your patch!
> >
> > > --- a/drivers/irqchip/Kconfig
> > > +++ b/drivers/irqchip/Kconfig
> > > @@ -679,4 +679,13 @@ config SUNPLUS_SP7021_INTC
> > > chained controller, routing all interrupt source in P-Chip to
> > > the primary controller on C-Chip.
> > >
> > > +config RENESAS_SH7751_INTC
> > > + bool "Renesas SH7751 Interrupt Controller"
> > > + depends on SH_DEVICE_TREE
> >
> > "|| COMPILE_TEST"?
> >
> > > + select IRQ_DOMAIN
> > > + select IRQ_DOMAIN_HIERARCHY
> > > + help
> > > + Support for the Renesas SH7751 On-chip interrupt controller.
> > > + And external interrupt encoder for some targets.
> >
> > Inconsistent indentation
> >
> > > --- /dev/null
> > > +++ b/drivers/irqchip/irq-renesas-sh7751.c
> >
> > > +/* INTEVT to IPR mapping */
> > > +static const struct iprmap {
> > > + int intevt;
> >
> > irq, as you're storing the irq number not the event number?
> >
> > > + int off;
> > > + int bit;
> >
> > All unsigned int ...
> >
> > > +} iprmaps[] = {
> > > +#define IPRDEF(e, o, b) { .intevt = evt2irq(e), .off = o, .bit = b }
> > > + IPRDEF(0x240, IPRD, IPR_B12), /* IRL0 */
> > > + IPRDEF(0x2a0, IPRD, IPR_B8), /* IRL1 */
> > > + IPRDEF(0x300, IPRD, IPR_B4), /* IRL2 */
> > > + IPRDEF(0x360, IPRD, IPR_B0), /* IRL3 */
> > > + IPRDEF(0x400, IPRA, IPR_B12), /* TMU0 */
> > > + IPRDEF(0x420, IPRA, IPR_B8), /* TMU1 */
> > > + IPRDEF(0x440, IPRA, IPR_B4), /* TMU2 TNUI */
> > > + IPRDEF(0x460, IPRA, IPR_B4), /* TMU2 TICPI */
> > > + IPRDEF(0x480, IPRA, IPR_B0), /* RTC ATI */
> > > + IPRDEF(0x4a0, IPRA, IPR_B0), /* RTC PRI */
> > > + IPRDEF(0x4c0, IPRA, IPR_B0), /* RTC CUI */
> > > + IPRDEF(0x4e0, IPRB, IPR_B4), /* SCI ERI */
> > > + IPRDEF(0x500, IPRB, IPR_B4), /* SCI RXI */
> > > + IPRDEF(0x520, IPRB, IPR_B4), /* SCI TXI */
> > > + IPRDEF(0x540, IPRB, IPR_B4), /* SCI TEI */
> > > + IPRDEF(0x560, IPRB, IPR_B12), /* WDT */
> > > + IPRDEF(0x580, IPRB, IPR_B8), /* REF RCMI */
> > > + IPRDEF(0x5a0, IPRB, IPR_B4), /* REF ROVI */
> > > + IPRDEF(0x600, IPRC, IPR_B0), /* H-UDI */
> > > + IPRDEF(0x620, IPRC, IPR_B12), /* GPIO */
> > > + IPRDEF(0x640, IPRC, IPR_B8), /* DMAC DMTE0 */
> > > + IPRDEF(0x660, IPRC, IPR_B8), /* DMAC DMTE1 */
> > > + IPRDEF(0x680, IPRC, IPR_B8), /* DMAC DMTE2 */
> > > + IPRDEF(0x6a0, IPRC, IPR_B8), /* DMAC DMTE3 */
> > > + IPRDEF(0x6c0, IPRC, IPR_B8), /* DMAC DMAE */
> > > + IPRDEF(0x700, IPRC, IPR_B4), /* SCIF ERI */
> > > + IPRDEF(0x720, IPRC, IPR_B4), /* SCIF RXI */
> > > + IPRDEF(0x740, IPRC, IPR_B4), /* SCIF BRI */
> > > + IPRDEF(0x760, IPRC, IPR_B4), /* SCIF TXI */
> > > + IPRDEF(0x780, IPRC, IPR_B8), /* DMAC DMTE4 */
> > > + IPRDEF(0x7a0, IPRC, IPR_B8), /* DMAC DMTE5 */
> > > + IPRDEF(0x7c0, IPRC, IPR_B8), /* DMAC DMTE6 */
> > > + IPRDEF(0x7e0, IPRC, IPR_B8), /* DMAC DMTE7 */
> > > + IPRDEF(0xa00, INTPRI00, IPR_B0), /* PCIC PCISERR */
> > > + IPRDEF(0xa20, INTPRI00, IPR_B4), /* PCIC PCIDMA3 */
> > > + IPRDEF(0xa40, INTPRI00, IPR_B4), /* PCIC PCIDMA2 */
> > > + IPRDEF(0xa60, INTPRI00, IPR_B4), /* PCIC PCIDMA1 */
> > > + IPRDEF(0xa80, INTPRI00, IPR_B4), /* PCIC PCIDMA0 */
> > > + IPRDEF(0xaa0, INTPRI00, IPR_B4), /* PCIC PCIPWON */
> > > + IPRDEF(0xac0, INTPRI00, IPR_B4), /* PCIC PCIPWDWN */
> > > + IPRDEF(0xae0, INTPRI00, IPR_B4), /* PCIC PCIERR */
> > > + IPRDEF(0xb00, INTPRI00, IPR_B8), /* TMU3 */
> > > + IPRDEF(0xb80, INTPRI00, IPR_B12), /* TMU4 */
> >
> > Probably the same or a very similar interrupt controller is present
> > on other SoCs? Then the comments don't make much sense, as the actual
> > interrupt mapping is specified in the DTS anyway.
>
> This interrupt controller design is quite old, so there doesn't seem to be
> any SoC with a similar design.
OK.
> Since the SH interrupt controllers have almost the same design,
> I think this driver can be used for other devices besides the SH7751.
Wait, this contradicts your sentence above?
> I think a good way to write IPR mapping is to use dts.
If there is one thing we learned from putting full clock controller and PM
Domain hierarchies in DT, it is that that turned out to be very fragile.
It is hard not to make mistakes in the description, and easy to miss
a critical aspect of the hardware that needs changes later.
So that's why it's better to differentiate through the compatible value,
instead of through (lots of) properties: you can always fix the driver,
while DT is a stable ABI.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 14/30] drivers/irqchip: Add SH7751 Internal INTC drivers.
2023-09-25 7:38 ` Geert Uytterhoeven
@ 2023-09-30 15:14 ` Yoshinori Sato
0 siblings, 0 replies; 83+ messages in thread
From: Yoshinori Sato @ 2023-09-30 15:14 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: linux-sh, glaubitz
On Mon, 25 Sep 2023 16:38:37 +0900,
Geert Uytterhoeven wrote:
>
> Hi Sato-san,
>
> On Fri, Sep 22, 2023 at 12:12 PM Yoshinori Sato
> <ysato@users.sourceforge.jp> wrote:
> > On Tue, 19 Sep 2023 20:50:14 +0900,
> > Geert Uytterhoeven wrote:
> > > On Wed, Sep 13, 2023 at 11:24 AM Yoshinori Sato
> > > <ysato@users.sourceforge.jp> wrote:
> > > > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> > >
> > > Thanks for your patch!
> > >
> > > > --- a/drivers/irqchip/Kconfig
> > > > +++ b/drivers/irqchip/Kconfig
> > > > @@ -679,4 +679,13 @@ config SUNPLUS_SP7021_INTC
> > > > chained controller, routing all interrupt source in P-Chip to
> > > > the primary controller on C-Chip.
> > > >
> > > > +config RENESAS_SH7751_INTC
> > > > + bool "Renesas SH7751 Interrupt Controller"
> > > > + depends on SH_DEVICE_TREE
> > >
> > > "|| COMPILE_TEST"?
> > >
> > > > + select IRQ_DOMAIN
> > > > + select IRQ_DOMAIN_HIERARCHY
> > > > + help
> > > > + Support for the Renesas SH7751 On-chip interrupt controller.
> > > > + And external interrupt encoder for some targets.
> > >
> > > Inconsistent indentation
> > >
> > > > --- /dev/null
> > > > +++ b/drivers/irqchip/irq-renesas-sh7751.c
> > >
> > > > +/* INTEVT to IPR mapping */
> > > > +static const struct iprmap {
> > > > + int intevt;
> > >
> > > irq, as you're storing the irq number not the event number?
> > >
> > > > + int off;
> > > > + int bit;
> > >
> > > All unsigned int ...
> > >
> > > > +} iprmaps[] = {
> > > > +#define IPRDEF(e, o, b) { .intevt = evt2irq(e), .off = o, .bit = b }
> > > > + IPRDEF(0x240, IPRD, IPR_B12), /* IRL0 */
> > > > + IPRDEF(0x2a0, IPRD, IPR_B8), /* IRL1 */
> > > > + IPRDEF(0x300, IPRD, IPR_B4), /* IRL2 */
> > > > + IPRDEF(0x360, IPRD, IPR_B0), /* IRL3 */
> > > > + IPRDEF(0x400, IPRA, IPR_B12), /* TMU0 */
> > > > + IPRDEF(0x420, IPRA, IPR_B8), /* TMU1 */
> > > > + IPRDEF(0x440, IPRA, IPR_B4), /* TMU2 TNUI */
> > > > + IPRDEF(0x460, IPRA, IPR_B4), /* TMU2 TICPI */
> > > > + IPRDEF(0x480, IPRA, IPR_B0), /* RTC ATI */
> > > > + IPRDEF(0x4a0, IPRA, IPR_B0), /* RTC PRI */
> > > > + IPRDEF(0x4c0, IPRA, IPR_B0), /* RTC CUI */
> > > > + IPRDEF(0x4e0, IPRB, IPR_B4), /* SCI ERI */
> > > > + IPRDEF(0x500, IPRB, IPR_B4), /* SCI RXI */
> > > > + IPRDEF(0x520, IPRB, IPR_B4), /* SCI TXI */
> > > > + IPRDEF(0x540, IPRB, IPR_B4), /* SCI TEI */
> > > > + IPRDEF(0x560, IPRB, IPR_B12), /* WDT */
> > > > + IPRDEF(0x580, IPRB, IPR_B8), /* REF RCMI */
> > > > + IPRDEF(0x5a0, IPRB, IPR_B4), /* REF ROVI */
> > > > + IPRDEF(0x600, IPRC, IPR_B0), /* H-UDI */
> > > > + IPRDEF(0x620, IPRC, IPR_B12), /* GPIO */
> > > > + IPRDEF(0x640, IPRC, IPR_B8), /* DMAC DMTE0 */
> > > > + IPRDEF(0x660, IPRC, IPR_B8), /* DMAC DMTE1 */
> > > > + IPRDEF(0x680, IPRC, IPR_B8), /* DMAC DMTE2 */
> > > > + IPRDEF(0x6a0, IPRC, IPR_B8), /* DMAC DMTE3 */
> > > > + IPRDEF(0x6c0, IPRC, IPR_B8), /* DMAC DMAE */
> > > > + IPRDEF(0x700, IPRC, IPR_B4), /* SCIF ERI */
> > > > + IPRDEF(0x720, IPRC, IPR_B4), /* SCIF RXI */
> > > > + IPRDEF(0x740, IPRC, IPR_B4), /* SCIF BRI */
> > > > + IPRDEF(0x760, IPRC, IPR_B4), /* SCIF TXI */
> > > > + IPRDEF(0x780, IPRC, IPR_B8), /* DMAC DMTE4 */
> > > > + IPRDEF(0x7a0, IPRC, IPR_B8), /* DMAC DMTE5 */
> > > > + IPRDEF(0x7c0, IPRC, IPR_B8), /* DMAC DMTE6 */
> > > > + IPRDEF(0x7e0, IPRC, IPR_B8), /* DMAC DMTE7 */
> > > > + IPRDEF(0xa00, INTPRI00, IPR_B0), /* PCIC PCISERR */
> > > > + IPRDEF(0xa20, INTPRI00, IPR_B4), /* PCIC PCIDMA3 */
> > > > + IPRDEF(0xa40, INTPRI00, IPR_B4), /* PCIC PCIDMA2 */
> > > > + IPRDEF(0xa60, INTPRI00, IPR_B4), /* PCIC PCIDMA1 */
> > > > + IPRDEF(0xa80, INTPRI00, IPR_B4), /* PCIC PCIDMA0 */
> > > > + IPRDEF(0xaa0, INTPRI00, IPR_B4), /* PCIC PCIPWON */
> > > > + IPRDEF(0xac0, INTPRI00, IPR_B4), /* PCIC PCIPWDWN */
> > > > + IPRDEF(0xae0, INTPRI00, IPR_B4), /* PCIC PCIERR */
> > > > + IPRDEF(0xb00, INTPRI00, IPR_B8), /* TMU3 */
> > > > + IPRDEF(0xb80, INTPRI00, IPR_B12), /* TMU4 */
> > >
> > > Probably the same or a very similar interrupt controller is present
> > > on other SoCs? Then the comments don't make much sense, as the actual
> > > interrupt mapping is specified in the DTS anyway.
> >
> > This interrupt controller design is quite old, so there doesn't seem to be
> > any SoC with a similar design.
>
> OK.
>
> > Since the SH interrupt controllers have almost the same design,
> > I think this driver can be used for other devices besides the SH7751.
>
> Wait, this contradicts your sentence above?
I'm referring to other SH3/4 CPUs.
The only difference is the correspondence between registers and
interrupt sources, so it can be used universally not only for the
SH7751 but also for the other SH3 and 4.
I don't think it fits the philosophy of dt to embed information about
each CPU in the code and switch it with compatible.
> > I think a good way to write IPR mapping is to use dts.
>
> If there is one thing we learned from putting full clock controller and PM
> Domain hierarchies in DT, it is that that turned out to be very fragile.
> It is hard not to make mistakes in the description, and easy to miss
> a critical aspect of the hardware that needs changes later.
> So that's why it's better to differentiate through the compatible value,
> instead of through (lots of) properties: you can always fix the driver,
> while DT is a stable ABI.
I tried defining it like this.
I think this format is easy to maintain.
renesas,ipr-map = IPRDEF(0x240, IPRD, IPR_B12), /* IRL0 */
IPRDEF(0x2a0, IPRD, IPR_B8), /* IRL1 */
IPRDEF(0x300, IPRD, IPR_B4), /* IRL2 */
IPRDEF(0x360, IPRD, IPR_B0), /* IRL3
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
--
Yosinori Sato
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 19/30] drivers/tty: sh-sci fix SH4 OF support.
2023-09-19 12:25 ` Geert Uytterhoeven
@ 2023-10-02 12:56 ` Yoshinori Sato
0 siblings, 0 replies; 83+ messages in thread
From: Yoshinori Sato @ 2023-10-02 12:56 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: linux-sh, glaubitz
On Tue, 19 Sep 2023 21:25:06 +0900,
Geert Uytterhoeven wrote:
>
> Hi Sato-san,
>
> Thanks for your patch!
>
> On Wed, Sep 13, 2023 at 11:26 AM Yoshinori Sato
> <ysato@users.sourceforge.jp> wrote:
> > - fix earlycon name.
>
> I guess you mean earlyprintk?
>
> "Earlyprintk expects that all names used in OF_EARLYCON_DECLARE()
> are unique".
>
> > - fix earlyprintk hung (NULL pointer reference).
> > - clocks property support.
> >
> > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
>
> > --- a/drivers/tty/serial/sh-sci.c
> > +++ b/drivers/tty/serial/sh-sci.c
>
> > @@ -2842,6 +2842,8 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
> > * global "peripheral_clk" clock.
> > */
> > clk = devm_clk_get(dev, "peripheral_clk");
> > + if (IS_ERR(clk))
> > + clk = devm_clk_get(dev, NULL);
>
> This should not be needed.
> I guess this is a workaround for the lack of
>
> clock-names = "fck";
>
> in arch/sh/boot/dts/sh7751.dtsi?
>
> "make dtbs_check
> DT_SCHEMA_FILES=Documentation/devicetree/bindings/serial/renesas,scif.yaml"
> would have told you ;-)
>
> serial@ffe80000: 'clock-names' is a required property
>
> > if (IS_ERR(clk))
> > return dev_err_probe(dev, PTR_ERR(clk),
> > "failed to get %s\n",
> > @@ -3555,8 +3557,8 @@ static int __init hscif_early_console_setup(struct earlycon_device *device,
> >
> > OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
> > OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
> > -OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
> > -OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
> > +OF_EARLYCON_DECLARE(rzscif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
> > +OF_EARLYCON_DECLARE(rzscif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
>
> Perhaps "rzscifa", to match the setup function prefix?
With this change, specifying "earlycon=rzscif,0xe8007000" in
the boot parameter will call rzscifa_early_console_setup.
But it would be confusing if the names were not unified, so use "rzscifa"
I'll make it.
> > OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
> > OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
> > OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
--
Yosinori Sato
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 26/30] arch/sh: RTS7751R2D Plus DeviceTree.
2023-09-19 13:25 ` Geert Uytterhoeven
@ 2023-10-02 13:21 ` Yoshinori Sato
2023-10-02 13:51 ` Geert Uytterhoeven
0 siblings, 1 reply; 83+ messages in thread
From: Yoshinori Sato @ 2023-10-02 13:21 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: linux-sh, glaubitz
On Tue, 19 Sep 2023 22:25:19 +0900,
Geert Uytterhoeven wrote:
>
> Hi Sato-san,
>
> On Wed, Sep 13, 2023 at 11:24 AM Yoshinori Sato
> <ysato@users.sourceforge.jp> wrote:
> > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/arch/sh/boot/dts/rts7751r2dplus.dts
> > @@ -0,0 +1,124 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Device Tree Source for the Renesas RTS7751R2D Plus
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "sh7751.dtsi"
>
> #include "sh7751r.dtsi"?
>
> To make that work, you can create "sh7751.dtsi" that includes
> "sh7751.dtsi" and overrides the parts that are different.
The only difference between 7751 and 7751R is CPG,
so I don't differentiate between them.
Shall we write the CPG differences in sh7751r.dtsi?
> > +
> > +/ {
> > + model = "Renesas RTS7715R2D Plus";
> > + compatible = "renesas,r2dplus";
>
> compatible = "renesas,r2dplus", "renesas,sh7751r", "renesas,sh7751".
>
> And all these compatible values must be documented in the DT
> binding documentation.
>
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + interrupt-parent = <&shintc>;
> > +
> > + aliases {
> > + serial0 = &scif1;
> > + };
> > +
> > + chosen {
> > + };
> > +
> > + clocks {
> > + xtal: oscillator {
> > + #clock-cells = <0>;
> > + compatible = "fixed-clock";
> > + clock-frequency = <22222222>;
> > + };
>
> Please
> > +
> > + cpg: cpg@ffc00000 {
>
> "&cpg"?
>
> > + compatible = "renesas,sh7750r-cpg",
> > + "renesas,sh7750-cpg";
>
> There should be no need to override the cpg's compatible value.
>
> > + renesas,mode = <5>;
> > + };
> > + };
> > +
> > + cpus {
> > + cpu@0 {
> > + clock-frequency = <266666666>;
>
> As the CPU clock is programmable, the "clock-frequency"
> property should probably be replaced by a "clocks" property in the
> base sh7751.dtsi.
>
> > + };
> > + };
> > +
> > + memory@c000000 {
> > + device_type = "memory";
> > + reg = <0x0c000000 0x4000000>;
> > + };
> > +
> > + r2dintc: sh7751irl_encoder@a4000000 {
> > + compatible = "renesas,sh7751-irl-ext";
> > + reg = <0xa4000000 0x02>;
> > + interrupt-controller;
> > + #address-cells = <1>;
> > + #interrupt-cells = <2>;
> > + sh7751irl,width = <16>;
> > + sh7751irl,polarity = <0>;
> > + sh7751irl,irqbit =<11>, /* PCI INTD */
> > + <9>, /* CF IDE */
> > + <8>, /* CF CD */
> > + <12>, /* PCI INTC */
> > + <10>, /* SM501 */
> > + <6>, /* KEY */
> > + <5>, /* RTC ALARM */
> > + <4>, /* RTC T */
> > + <7>, /* SDCARD */
> > + <14>, /* PCI INTA */
> > + <13>, /* PCI INTB */
> > + <0>, /* EXT */
> > + <15>; /* TP */
> > + };
> > +
> > + display@1,0 {
> > + compatible = "smi,sm501";
> > + reg = <0x10000000 0x03e00000
> > + 0x13e00000 0x00200000>;
> > + interrupt-parent = <&r2dintc>;
> > + interrupts = <4 0>;
> > + mode = "640x480-16@60";
> > + little-endian;
> > + sm501,devices = "usb-host","uart0";
> > + };
> > +
> > + compact-flash@b4001000 {
> > + compatible = "ata-generic";
>
> compact-flash@b4001000: compatible:0: 'ata-generic' is not one of
> ['arm,vexpress-cf', 'fsl,mpc8349emitx-pata']
> from schema $id: http://devicetree.org/schemas/ata/ata-generic.yaml#
>
> > + reg = <0xb4001000 0x0e>, <0xb400080c 2>;
> > + reg-shift = <1>;
> > + interrupt-parent = <&r2dintc>;
> > + interrupts = <1 0>;
> > + };
> > +
> > + flash@0 {
> > + compatible = "cfi-flash";
> > + reg = <0x00000000 0x02000000>;
> > + device-width = <2>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + partition@0 {
> > + label = "U-Boot";
> > + reg = <0x00000000 0x00040000>;
> > + };
> > + partition@1 {
> > + label = "Environemt";
>
> Environment
>
> > + reg = <0x00040000 0x00040000>;
> > + };
>
> Several of the above comments apply to "[RFC PATCH v2 27/30]
> arch/sh: LANDISK DeviceTree." and "[RFC PATCH v2 28/30] arch/sh:
> USL-5P DeviceTree.", too.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
--
Yosinori Sato
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 26/30] arch/sh: RTS7751R2D Plus DeviceTree.
2023-10-02 13:21 ` Yoshinori Sato
@ 2023-10-02 13:51 ` Geert Uytterhoeven
0 siblings, 0 replies; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-10-02 13:51 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Hi Sato-san,
On Mon, Oct 2, 2023 at 3:22 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> On Tue, 19 Sep 2023 22:25:19 +0900,
> Geert Uytterhoeven wrote:
> > On Wed, Sep 13, 2023 at 11:24 AM Yoshinori Sato
> > <ysato@users.sourceforge.jp> wrote:
> > > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> >
> > Thanks for your patch!
> >
> > > --- /dev/null
> > > +++ b/arch/sh/boot/dts/rts7751r2dplus.dts
> > > @@ -0,0 +1,124 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> > > + * Device Tree Source for the Renesas RTS7751R2D Plus
> > > + */
> > > +
> > > +/dts-v1/;
> > > +
> > > +#include "sh7751.dtsi"
> >
> > #include "sh7751r.dtsi"?
> >
> > To make that work, you can create "sh7751.dtsi" that includes
> > "sh7751.dtsi" and overrides the parts that are different.
>
> The only difference between 7751 and 7751R is CPG,
> so I don't differentiate between them.
>
> Shall we write the CPG differences in sh7751r.dtsi?
Yes please.
That way the .dts board file for a board with SH7751 can include sh7751.dtsi,
and the .dts board file for a board with SH7751R can include sh7751r.dtsi.
All common parts should be put in sh7751.dtsi, to avoid duplication.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 13/30] Documentation/devicetree: Add renesas,sh7751-cpg binding document.
2023-09-13 9:23 ` [RFC PATCH v2 13/30] Documentation/devicetree: Add renesas,sh7751-cpg binding document Yoshinori Sato
2023-09-13 10:44 ` Krzysztof Kozlowski
2023-09-18 19:21 ` Geert Uytterhoeven
@ 2023-10-03 9:16 ` Geert Uytterhoeven
2 siblings, 0 replies; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-10-03 9:16 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz, linux-clk
On Wed, Sep 13, 2023 at 11:26 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> ---
> .../bindings/clock/renesas,sh7750-cpg.yaml | 58 +++++++++++++++++++
> 1 file changed, 58 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
> new file mode 100644
> index 000000000000..bf10a09440ac
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
> @@ -0,0 +1,58 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
warning: ignoring duplicate '$id' value
'http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#'
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH v2 08/30] drivers/pci: Add SH7751 Host bridge controller
2023-09-13 9:23 ` [RFC PATCH v2 08/30] drivers/pci: Add SH7751 Host bridge controller Yoshinori Sato
2023-09-18 15:34 ` Geert Uytterhoeven
2023-09-18 19:33 ` Bjorn Helgaas
@ 2023-10-12 7:16 ` Geert Uytterhoeven
2 siblings, 0 replies; 83+ messages in thread
From: Geert Uytterhoeven @ 2023-10-12 7:16 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz, linux-pci
Hi Sato-san,
On Wed, Sep 13, 2023 at 11:24 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -342,6 +342,15 @@ config PCIE_XILINX_CPM
> Say 'Y' here if you want kernel support for the
> Xilinx Versal CPM host bridge.
>
> +config PCI_SH7751
> + bool "Renesas SH7751 PCI controller"
> + depends on OF
> + depends on CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R || COMPILE_TEST
> + select PCI_HOST_COMMON
> + help
> + Say 'Y' here if you want kernel to support the Renesas SH7751 PCI
> + Host Bridge driver.
> +
When compile-testing:
drivers/pci/controller/pci-sh7751.c: In function ‘sh7751_pci_probe’:
drivers/pci/controller/pci-sh7751.c:276:16: error: implicit
declaration of function ‘P2SEGADDR’
[-Werror=implicit-function-declaration]
276 | word = P2SEGADDR(wres->start);
| ^~~~~~~~~
P2SEGADDR() depends on the SH-specific CONFIG_29BIT.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 83+ messages in thread
end of thread, other threads:[~2023-10-12 7:16 UTC | newest]
Thread overview: 83+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-09-13 9:23 [RFC PATCH v2 00/30] Device Tree support for SH7751 based board Yoshinori Sato
2023-09-13 9:23 ` [RFC PATCH v2 01/30] arch/sh: head_32.S passing FDT address to initialize function Yoshinori Sato
2023-09-18 15:16 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 02/30] arch/sh: boards/Kconfig unified OF supported targets Yoshinori Sato
2023-09-18 15:05 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 03/30] arch/sh: Disable SH specific drivers in OF enabled Yoshinori Sato
2023-09-18 15:14 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 04/30] include: sh_intc.h Add stub function "intc_finalize" Yoshinori Sato
2023-09-18 15:16 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 05/30] arch/sh: setup.c update DeviceTree support Yoshinori Sato
2023-09-13 9:23 ` [RFC PATCH v2 06/30] drivers/pci: SH7751 PCI Host bridge header Yoshinori Sato
2023-09-18 19:16 ` Bjorn Helgaas
2023-09-13 9:23 ` [RFC PATCH v2 07/30] drivers/pci: SH7751 PCI Host bridge controller driver Yoshinori Sato
2023-09-18 15:32 ` Geert Uytterhoeven
2023-09-20 12:15 ` Yoshinori Sato
2023-09-18 19:30 ` Bjorn Helgaas
2023-09-13 9:23 ` [RFC PATCH v2 08/30] drivers/pci: Add SH7751 Host bridge controller Yoshinori Sato
2023-09-18 15:34 ` Geert Uytterhoeven
2023-09-18 19:33 ` Bjorn Helgaas
2023-10-12 7:16 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 09/30] Documentation/devicetree: Add renesas,sh7751-pci binding document Yoshinori Sato
2023-09-13 10:42 ` Krzysztof Kozlowski
2023-09-18 15:41 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 10/30] drivers/clk: SH7750 / SH7751 CPG Driver Yoshinori Sato
2023-09-13 10:43 ` Krzysztof Kozlowski
2023-09-18 16:05 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 11/30] drivers/clk: SuperH generai clock divider helper Yoshinori Sato
2023-09-18 18:59 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 12/30] drivers/clk: Add SH7750 CPG drivers entry Yoshinori Sato
2023-09-18 19:05 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 13/30] Documentation/devicetree: Add renesas,sh7751-cpg binding document Yoshinori Sato
2023-09-13 10:44 ` Krzysztof Kozlowski
2023-09-18 19:21 ` Geert Uytterhoeven
2023-10-03 9:16 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 14/30] drivers/irqchip: Add SH7751 Internal INTC drivers Yoshinori Sato
2023-09-19 11:50 ` Geert Uytterhoeven
2023-09-22 10:12 ` Yoshinori Sato
2023-09-25 7:38 ` Geert Uytterhoeven
2023-09-30 15:14 ` Yoshinori Sato
2023-09-13 9:23 ` [RFC PATCH v2 15/30] Documentation/devicetree: Add renesas,sh7751-intc binding document Yoshinori Sato
2023-09-13 10:44 ` Krzysztof Kozlowski
2023-09-19 11:56 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 16/30] drivers/irqchip: SH7751 IRL external encoder with enable gate Yoshinori Sato
2023-09-19 12:10 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 17/30] Documentation/devicetree: Add renesas,sh7751-irl-ext binding document Yoshinori Sato
2023-09-13 10:45 ` Krzysztof Kozlowski
2023-09-19 12:08 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 18/30] drivers/clocksource: sh_tmu clocks property support Yoshinori Sato
2023-09-19 12:15 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 19/30] drivers/tty: sh-sci fix SH4 OF support Yoshinori Sato
2023-09-19 12:25 ` Geert Uytterhoeven
2023-10-02 12:56 ` Yoshinori Sato
2023-09-13 9:23 ` [RFC PATCH v2 20/30] drivers/mfd: sm501 add some properties Yoshinori Sato
2023-09-20 12:25 ` Lee Jones
2023-09-13 9:23 ` [RFC PATCH v2 21/30] Documentation/devicetree: sm501fb add properies Yoshinori Sato
2023-09-13 10:45 ` Krzysztof Kozlowski
2023-09-13 9:23 ` [RFC PATCH v2 22/30] arch/sh: Add dtbs target support Yoshinori Sato
2023-09-19 12:28 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 23/30] arch/sh: Add SH7751 SoC Internal periphreal devicetree Yoshinori Sato
2023-09-13 10:49 ` Krzysztof Kozlowski
2023-09-19 12:41 ` Geert Uytterhoeven
2023-09-19 13:11 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 24/30] include/dt-bindings: Add SH7750 CPG header Yoshinori Sato
2023-09-13 10:46 ` Krzysztof Kozlowski
2023-09-19 12:43 ` Geert Uytterhoeven
2023-09-20 11:52 ` Krzysztof Kozlowski
2023-09-19 12:46 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 25/30] include/dt-bindings: Add sh_intc IRQ - EVT conversion helper Yoshinori Sato
2023-09-13 10:47 ` Krzysztof Kozlowski
2023-09-19 13:02 ` Geert Uytterhoeven
2023-09-20 11:51 ` Krzysztof Kozlowski
2023-09-20 12:30 ` Geert Uytterhoeven
2023-09-19 13:05 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 26/30] arch/sh: RTS7751R2D Plus DeviceTree Yoshinori Sato
2023-09-13 10:49 ` Krzysztof Kozlowski
2023-09-15 15:43 ` Geert Uytterhoeven
2023-09-19 13:25 ` Geert Uytterhoeven
2023-10-02 13:21 ` Yoshinori Sato
2023-10-02 13:51 ` Geert Uytterhoeven
2023-09-13 9:23 ` [RFC PATCH v2 27/30] arch/sh: LANDISK DeviceTree Yoshinori Sato
2023-09-13 9:23 ` [RFC PATCH v2 28/30] arch/sh: USL-5P DeviceTree Yoshinori Sato
2023-09-13 9:23 ` [RFC PATCH v2 29/30] arch/sh: RTS7751R2D Plus OF defconfig Yoshinori Sato
2023-09-13 9:23 ` [RFC PATCH v2 30/30] arch/sh: LANDISK " Yoshinori Sato
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