Updates Renesas OF-DMA code

Updates Renesas OF-DMA code

[Ben Dooks]

This is an update of the previous series to remove the "renesas,slaves"
property and move the CHCR register defintions into the references to
the dma node.

This requires a change to the shdma-of code as the slave-ids array is
now dynamically built, which means that we need to keep updating it
with each lookup we have not seen before. I /think/ the DMA locking
in the OF code should keep the list from getting damaged.

This is slighly more code than the original version, but it is much
easier to add devices that are DMA slaves as the dma nodes no longer
need to be updated.

Updates Renesas OF-DMA code

[Ben Dooks]

This is an update of the previous series to remove the "renesas,slaves"
property and move the CHCR register defintions into the references to
the dma node.

This requires a change to the shdma-of code as the slave-ids array is
now dynamically built, which means that we need to keep updating it
with each lookup we have not seen before. I /think/ the DMA locking
in the OF code should keep the list from getting damaged.

This is slighly more code than the original version, but it is much
easier to add devices that are DMA slaves as the dma nodes no longer
need to be updated.

[PATCH v2 1/9] ARM: shmobile: r8a7790: add dmac0,dmac1 clocks

[Ben Dooks]

Add clocks for the SYS-DMAC0 and SYS-DMAC1 hardware blocks.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/arm/boot/dts/r8a7790.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index a1e7c39..f98b01d 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -671,16 +671,17 @@
 			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 			reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 			clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
-				 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>;
+				 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&hp_clk>, <&hp_clk>;
 			#clock-cells = <1>;
 			renesas,clock-indices = <
 				R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
 				R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
 				R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
+				R8A7790_CLK_SYS_DMAC0 R8A7790_CLK_SYS_DMAC1
 			>;
 			clock-output-names  				"scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
-				"scifb1", "msiof1", "msiof3", "scifb2";
+				"scifb1", "msiof1", "msiof3", "scifb2", "dmac0", "dmac1";
 		};
 		mstp3_clks: mstp3_clks@e615013c {
 			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
-- 
1.9.1

[PATCH v2 1/9] ARM: shmobile: r8a7790: add dmac0,dmac1 clocks

[Ben Dooks]

Add clocks for the SYS-DMAC0 and SYS-DMAC1 hardware blocks.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/arm/boot/dts/r8a7790.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index a1e7c39..f98b01d 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -671,16 +671,17 @@
 			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 			reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 			clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
-				 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>;
+				 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&hp_clk>, <&hp_clk>;
 			#clock-cells = <1>;
 			renesas,clock-indices = <
 				R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
 				R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
 				R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
+				R8A7790_CLK_SYS_DMAC0 R8A7790_CLK_SYS_DMAC1
 			>;
 			clock-output-names =
 				"scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
-				"scifb1", "msiof1", "msiof3", "scifb2";
+				"scifb1", "msiof1", "msiof3", "scifb2", "dmac0", "dmac1";
 		};
 		mstp3_clks: mstp3_clks@e615013c {
 			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
-- 
1.9.1

Re: [PATCH v2 1/9] ARM: shmobile: r8a7790: add dmac0,dmac1 clocks

[Geert Uytterhoeven]

Hi Ben,

On Mon, Apr 14, 2014 at 11:35 PM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
> --- a/arch/arm/boot/dts/r8a7790.dtsi
> +++ b/arch/arm/boot/dts/r8a7790.dtsi
> @@ -671,16 +671,17 @@
>                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
>                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
>                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
> -                                <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>;
> +                                <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&hp_clk>, <&hp_clk>;

According to the docs, the parent clock of SYS-DMAC[01] is the ZS clock
(at 260 MHz), not the HP clock (at 130 MHz).

>                         #clock-cells = <1>;
>                         renesas,clock-indices = <
>                                 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
>                                 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
>                                 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
> +                               R8A7790_CLK_SYS_DMAC0 R8A7790_CLK_SYS_DMAC1

I know order doesn't really matter, but all other members are sorted by
value, so R8A7790_CLK_SYS_DMAC1 should come before
R8A7790_CLK_SYS_DMAC0.

>                         >;
>                         clock-output-names >                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
> -                               "scifb1", "msiof1", "msiof3", "scifb2";
> +                               "scifb1", "msiof1", "msiof3", "scifb2", "dmac0", "dmac1";

"sys-dmac0", "sys-dmac1" (and order changes, cfr. my comment above),
to match the documentation?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 1/9] ARM: shmobile: r8a7790: add dmac0,dmac1 clocks

[Geert Uytterhoeven]

Hi Ben,

On Mon, Apr 14, 2014 at 11:35 PM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
> --- a/arch/arm/boot/dts/r8a7790.dtsi
> +++ b/arch/arm/boot/dts/r8a7790.dtsi
> @@ -671,16 +671,17 @@
>                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
>                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
>                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
> -                                <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>;
> +                                <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&hp_clk>, <&hp_clk>;

According to the docs, the parent clock of SYS-DMAC[01] is the ZS clock
(at 260 MHz), not the HP clock (at 130 MHz).

>                         #clock-cells = <1>;
>                         renesas,clock-indices = <
>                                 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
>                                 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
>                                 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
> +                               R8A7790_CLK_SYS_DMAC0 R8A7790_CLK_SYS_DMAC1

I know order doesn't really matter, but all other members are sorted by
value, so R8A7790_CLK_SYS_DMAC1 should come before
R8A7790_CLK_SYS_DMAC0.

>                         >;
>                         clock-output-names =
>                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
> -                               "scifb1", "msiof1", "msiof3", "scifb2";
> +                               "scifb1", "msiof1", "msiof3", "scifb2", "dmac0", "dmac1";

"sys-dmac0", "sys-dmac1" (and order changes, cfr. my comment above),
to match the documentation?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 1/9] ARM: shmobile: r8a7790: add dmac0,dmac1 clocks

[Ben Dooks]

On 13/05/14 10:23, Geert Uytterhoeven wrote:
> Hi Ben,
> 
> On Mon, Apr 14, 2014 at 11:35 PM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
>> --- a/arch/arm/boot/dts/r8a7790.dtsi
>> +++ b/arch/arm/boot/dts/r8a7790.dtsi
>> @@ -671,16 +671,17 @@
>>                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
>>                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
>>                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
>> -                                <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>;
>> +                                <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&hp_clk>, <&hp_clk>;
> 
> According to the docs, the parent clock of SYS-DMAC[01] is the ZS clock
> (at 260 MHz), not the HP clock (at 130 MHz).
> 
>>                         #clock-cells = <1>;
>>                         renesas,clock-indices = <
>>                                 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
>>                                 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
>>                                 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
>> +                               R8A7790_CLK_SYS_DMAC0 R8A7790_CLK_SYS_DMAC1
> 
> I know order doesn't really matter, but all other members are sorted by
> value, so R8A7790_CLK_SYS_DMAC1 should come before
> R8A7790_CLK_SYS_DMAC0.
> 
>>                         >;
>>                         clock-output-names >>                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
>> -                               "scifb1", "msiof1", "msiof3", "scifb2";
>> +                               "scifb1", "msiof1", "msiof3", "scifb2", "dmac0", "dmac1";
> 
> "sys-dmac0", "sys-dmac1" (and order changes, cfr. my comment above),
> to match the documentation?

ok, thanks.


-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

Re: [PATCH v2 1/9] ARM: shmobile: r8a7790: add dmac0,dmac1 clocks

[Ben Dooks]

On 13/05/14 10:23, Geert Uytterhoeven wrote:
> Hi Ben,
> 
> On Mon, Apr 14, 2014 at 11:35 PM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
>> --- a/arch/arm/boot/dts/r8a7790.dtsi
>> +++ b/arch/arm/boot/dts/r8a7790.dtsi
>> @@ -671,16 +671,17 @@
>>                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
>>                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
>>                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
>> -                                <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>;
>> +                                <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&hp_clk>, <&hp_clk>;
> 
> According to the docs, the parent clock of SYS-DMAC[01] is the ZS clock
> (at 260 MHz), not the HP clock (at 130 MHz).
> 
>>                         #clock-cells = <1>;
>>                         renesas,clock-indices = <
>>                                 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
>>                                 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
>>                                 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
>> +                               R8A7790_CLK_SYS_DMAC0 R8A7790_CLK_SYS_DMAC1
> 
> I know order doesn't really matter, but all other members are sorted by
> value, so R8A7790_CLK_SYS_DMAC1 should come before
> R8A7790_CLK_SYS_DMAC0.
> 
>>                         >;
>>                         clock-output-names =
>>                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
>> -                               "scifb1", "msiof1", "msiof3", "scifb2";
>> +                               "scifb1", "msiof1", "msiof3", "scifb2", "dmac0", "dmac1";
> 
> "sys-dmac0", "sys-dmac1" (and order changes, cfr. my comment above),
> to match the documentation?

ok, thanks.


-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

[PATCH v2 2/9] ARM: shmobile: r8a7790: add dma defines for sys and audio dmacs

[Ben Dooks]

Add the DMA resource IDs for the R8A7790 Audio and SYS DMA controllers
for use when specifying DMA handles.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 include/dt-bindings/dma/r8a7790-dma.h | 228 ++++++++++++++++++++++++++++++++++
 1 file changed, 228 insertions(+)
 create mode 100644 include/dt-bindings/dma/r8a7790-dma.h

diff --git a/include/dt-bindings/dma/r8a7790-dma.h b/include/dt-bindings/dma/r8a7790-dma.h
new file mode 100644
index 0000000..732422a
--- /dev/null
+++ b/include/dt-bindings/dma/r8a7790-dma.h
@@ -0,0 +1,228 @@
+/*
+ * R8A7790 System and Audio DMA channel resource identifiers
+ *
+ * Copyirght (c) 2014 Codethink Ltd.
+ *	Ben Dooks <ben.dooks@codethink.co.uk>
+ *
+ * Licensed under GPLv2
+*/
+
+/* System DMAC */
+
+#define R8A7790_DMA_SCIFA0_TX	(0x21)
+#define R8A7790_DMA_SCIFA0_RX	(0x22)
+#define R8A7790_DMA_SCIFA1_TX	(0x25)
+#define R8A7790_DMA_SCIFA1_RX	(0x26)
+#define R8A7790_DMA_SCIFA2_TX	(0x27)
+#define R8A7790_DMA_SCIFA2_RX	(0x28)
+
+#define R8A7790_DMA_SCIFB0_TX	(0x3D)
+#define R8A7790_DMA_SCIFB0_RX	(0x3E)
+#define R8A7790_DMA_SCIFB1_TX	(0x19)
+#define R8A7790_DMA_SCIFB1_RX	(0x1A)
+#define R8A7790_DMA_SCIFB2_TX	(0x1D)
+#define R8A7790_DMA_SCIFB2_RX	(0x1E)
+
+#define R8A7790_DMA_HSCIF0_TX	(0x39)
+#define R8A7790_DMA_HSCIF0_RX	(0x3A)
+#define R8A7790_DMA_HSCIF1_TX	(0x4D)
+#define R8A7790_DMA_HSCIF1_RX	(0x4E)
+
+#define R8A7790_DMA_SCIF0_TX	(0x29)
+#define R8A7790_DMA_SCIF0_RX	(0x2A)
+#define R8A7790_DMA_SCIF1_TX	(0x2D)
+#define R8A7790_DMA_SCIF1_RX	(0x2E)
+
+#define R8A7790_DMA_MSIOF0_TX	(0x81)
+#define R8A7790_DMA_MSIOF0_RX	(0x82)
+#define R8A7790_DMA_MSIOF1_TX	(0x85)
+#define R8A7790_DMA_MSIOF1_RX	(0x86)
+#define R8A7790_DMA_MSIOF2_TX	(0x41)
+#define R8A7790_DMA_MSIOF2_RX	(0x42)
+#define R8A7790_DMA_MSIOF3_TX	(0x45)
+#define R8A7790_DMA_MSIOF3_RX	(0x46)
+
+#define R8A7790_DMA_QSPI_TX	(0x17)
+#define R8A7790_DMA_QSPI_RX	(0x18)
+
+#define R8A7790_DMA_SIM_TX	(0xA1)
+#define R8A7790_DMA_SIM_RX	(0xA2)
+
+#define R8A7790_DMA_IIC0_TX	(0x61)
+#define R8A7790_DMA_IIC0_RX	(0x62)
+#define R8A7790_DMA_IIC1_TX	(0x65)
+#define R8A7790_DMA_IIC1_RX	(0x66)
+#define R8A7790_DMA_IIC2_TX	(0x69)
+#define R8A7790_DMA_IIC2_RX	(0x6A)
+#define R8A7790_DMA_IIC3_TX	(0x77)
+#define R8A7790_DMA_IIC3_RX	(0x78)
+
+#define R8A7790_DMA_SDHI0_TX	(0xCD)
+#define R8A7790_DMA_SDHI0_RX	(0xCE)
+#define R8A7790_DMA_SDHI1_TX	(0xC9)
+#define R8A7790_DMA_SDHI1_RX	(0xCA)
+#define R8A7790_DMA_SDHI2_TX	(0xC1)
+#define R8A7790_DMA_SDHI2_RX	(0xC2)
+#define R8A7790_DMA_SDHI2C2_TX	(0xC5)
+#define R8A7790_DMA_SDHI2C2_RX	(0xC6)
+#define R8A7790_DMA_SDHI3_TX	(0xD3)
+#define R8A7790_DMA_SDHI3_RX	(0xD4)
+#define R8A7790_DMA_SDHI3C2_TX	(0xDF)
+#define R8A7790_DMA_SDHI3C2_RX	(0xDE)
+
+#define R8A7790_DMA_TPU0	(0xF1)
+#define R8A7790_DMA_TSIF0	(0xEA)
+#define R8A7790_DMA_TSIF1	(0xF0)
+
+#define R8A7790_DMA_AXISTATR	(0xA6)
+#define R8A7790_DMA_AXISTATS0	(0xAC)
+#define R8A7790_DMA_AXISTATS1	(0xAA)
+#define R8A7790_DMA_AXISTATS2	(0xA8)
+#define R8A7790_DMA_AXISTATS3	(0xA4)
+
+#define R8A7790_DMA_MMCIF0_TX	(0xD1)
+#define R8A7790_DMA_MMCIF0_RX	(0xD2)
+#define R8A7790_DMA_MMCIF1_TX	(0xE1)
+#define R8A7790_DMA_MMCIF1_RX	(0xE2)
+
+/* Audio DMAC */
+
+#define R8A7790_DMA_DTCPC0_TX	(0xD7)
+#define R8A7790_DMA_DTCPC0_RX	(0xD8)
+#define R8A7790_DMA_DTCPC1_TX	(0xD9)
+#define R8A7790_DMA_DTCPC1_RX	(0xDA)
+#define R8A7790_DMA_DTCPP0_TX	(0xBF)
+#define R8A7790_DMA_DTCPP0_RX	(0xC0)
+#define R8A7790_DMA_DTCPP1_TX	(0xD5)
+#define R8A7790_DMA_DTCPP1_RX	(0xD6)
+
+#define R8A7790_DMA_MLM0_TX	(0xDB)
+#define R8A7790_DMA_MLM0_RX	(0xDC)
+#define R8A7790_DMA_MLM1_TX	(0xE3)
+#define R8A7790_DMA_MLM1_RX	(0xE4)
+#define R8A7790_DMA_MLM2_TX	(0xE5)
+#define R8A7790_DMA_MLM2_RX	(0xE6)
+#define R8A7790_DMA_MLM3_TX	(0xE7)
+#define R8A7790_DMA_MLM3_RX	(0xE8)
+#define R8A7790_DMA_MLM4_TX	(0xF3)
+#define R8A7790_DMA_MLM4_RX	(0xF4)
+#define R8A7790_DMA_MLM5_TX	(0xF5)
+#define R8A7790_DMA_MLM5_RX	(0xF6)
+#define R8A7790_DMA_MLM6_TX	(0xF7)
+#define R8A7790_DMA_MLM6_RX	(0xF8)
+#define R8A7790_DMA_MLM7_TX	(0xF9)
+#define R8A7790_DMA_MLM7_RX	(0xFA)
+
+#define R8A7790_DMA_SCU0	(0x85)
+#define R8A7790_DMA_SCU1	(0x87)
+#define R8A7790_DMA_SCU2	(0x89)
+#define R8A7790_DMA_SCU3	(0x8B)
+#define R8A7790_DMA_SCU4	(0x8D)
+#define R8A7790_DMA_SCU5	(0x8F)
+#define R8A7790_DMA_SCU6	(0x91)
+#define R8A7790_DMA_SCU7	(0x93)
+#define R8A7790_DMA_SCU8	(0x95)
+#define R8A7790_DMA_SCU9	(0x97)
+
+#define R8A7790_DMA_SCUCMD0	(0xBC)
+#define R8A7790_DMA_SCUCMD1	(0xBE)
+
+#define R8A7790_DMA_SCUOUT0	(0x9A)
+#define R8A7790_DMA_SCUOUT1	(0x9C)
+#define R8A7790_DMA_SCUOUT2	(0x9E)
+#define R8A7790_DMA_SCUOUT3	(0xA0)
+#define R8A7790_DMA_SCUOUT4	(0xB0)
+#define R8A7790_DMA_SCUOUT5	(0xB2)
+#define R8A7790_DMA_SCUOUT6	(0xB4)
+#define R8A7790_DMA_SCUOUT7	(0xB6)
+#define R8A7790_DMA_SCUOUT8	(0xB8)
+#define R8A7790_DMA_SCUOUT9	(0xBA)
+
+#define R8A7790_DMA_SSCI00_TX	(0x15)
+#define R8A7790_DMA_SSCI00_RX	(0x16)
+#define R8A7790_DMA_SSCI01_TX	(0x35)
+#define R8A7790_DMA_SSCI01_RX	(0x36)
+#define R8A7790_DMA_SSCI02_TX	(0x37)
+#define R8A7790_DMA_SSCI02_RX	(0x38)
+#define R8A7790_DMA_SSCI03_TX	(0x47)
+#define R8A7790_DMA_SSCI03_RX	(0x48)
+
+#define R8A7790_DMA_SSCI10_TX	(0x49)
+#define R8A7790_DMA_SSCI10_RX	(0x4A)
+#define R8A7790_DMA_SSCI11_TX	(0x4B)
+#define R8A7790_DMA_SSCI11_RX	(0x4C)
+#define R8A7790_DMA_SSCI12_TX	(0x57)
+#define R8A7790_DMA_SSCI12_RX	(0x58)
+#define R8A7790_DMA_SSCI13_TX	(0x59)
+#define R8A7790_DMA_SSCI13_RX	(0x5A)
+
+#define R8A7790_DMA_SSCI20_TX	(0x63)
+#define R8A7790_DMA_SSCI20_RX	(0x64)
+#define R8A7790_DMA_SSCI21_TX	(0x67)
+#define R8A7790_DMA_SSCI21_RX	(0x68)
+#define R8A7790_DMA_SSCI22_TX	(0x6B)
+#define R8A7790_DMA_SSCI22_RX	(0x6C)
+#define R8A7790_DMA_SSCI23_TX	(0x6D)
+#define R8A7790_DMA_SSCI23_RX	(0x6E)
+
+#define R8A7790_DMA_SSCI20_TX	(0x63)
+#define R8A7790_DMA_SSCI20_RX	(0x64)
+#define R8A7790_DMA_SSCI21_TX	(0x67)
+#define R8A7790_DMA_SSCI21_RX	(0x68)
+#define R8A7790_DMA_SSCI22_TX	(0x6B)
+#define R8A7790_DMA_SSCI22_RX	(0x6C)
+#define R8A7790_DMA_SSCI23_TX	(0x6D)
+#define R8A7790_DMA_SSCI23_RX	(0x6E)
+
+#define R8A7790_DMA_SSCI3_TX	(0x6F)
+#define R8A7790_DMA_SSCI3_RX	(0x70)
+
+#define R8A7790_DMA_SSCI4_TX	(0x71)
+#define R8A7790_DMA_SSCI4_RX	(0x72)
+
+#define R8A7790_DMA_SSCI5_TX	(0x73)
+#define R8A7790_DMA_SSCI5_RX	(0x74)
+
+#define R8A7790_DMA_SSCI6_TX	(0x75)
+#define R8A7790_DMA_SSCI6_RX	(0x76)
+
+#define R8A7790_DMA_SSCI7_TX	(0x79)
+#define R8A7790_DMA_SSCI7_RX	(0x7A)
+
+#define R8A7790_DMA_SSCI8_TX	(0x7B)
+#define R8A7790_DMA_SSCI8_RX	(0x7C)
+
+#define R8A7790_DMA_SSCI90_TX	(0x7D)
+#define R8A7790_DMA_SSCI90_RX	(0x7E)
+#define R8A7790_DMA_SSCI91_TX	(0x7F)
+#define R8A7790_DMA_SSCI91_RX	(0x80)
+#define R8A7790_DMA_SSCI92_TX	(0x81)
+#define R8A7790_DMA_SSCI92_RX	(0x82)
+#define R8A7790_DMA_SSCI93_TX	(0x83)
+#define R8A7790_DMA_SSCI93_RX	(0x84)
+
+#define R8A7790_DMA_SSIND0_TX	(0x01)
+#define R8A7790_DMA_SSIND0_RX	(0x02)
+#define R8A7790_DMA_SSIND1_TX	(0x03)
+#define R8A7790_DMA_SSIND1_RX	(0x04)
+#define R8A7790_DMA_SSIND2_TX	(0x05)
+#define R8A7790_DMA_SSIND2_RX	(0x06)
+#define R8A7790_DMA_SSIND3_TX	(0x07)
+#define R8A7790_DMA_SSIND3_RX	(0x08)
+#define R8A7790_DMA_SSIND4_TX	(0x09)
+#define R8A7790_DMA_SSIND4_RX	(0x0A)
+#define R8A7790_DMA_SSIND5_TX	(0x0B)
+#define R8A7790_DMA_SSIND5_RX	(0x0C)
+#define R8A7790_DMA_SSIND6_TX	(0x0D)
+#define R8A7790_DMA_SSIND6_RX	(0x0E)
+#define R8A7790_DMA_SSIND7_TX	(0x0F)
+#define R8A7790_DMA_SSIND7_RX	(0x10)
+#define R8A7790_DMA_SSIND8_TX	(0x11)
+#define R8A7790_DMA_SSIND8_RX	(0x12)
+#define R8A7790_DMA_SSIND9_TX	(0x13)
+#define R8A7790_DMA_SSIND9_RX	(0x14)
+
+#define CHCR_RX_32BIT	SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_32BIT)
+#define CHCR_TX_32BIT	SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_32BIT)
+#define CHCR_RX_256BIT	SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_256BIT)
+#define CHCR_TX_256BIT	SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_256BIT)
-- 
1.9.1

[PATCH v2 2/9] ARM: shmobile: r8a7790: add dma defines for sys and audio dmacs

[Ben Dooks]

Add the DMA resource IDs for the R8A7790 Audio and SYS DMA controllers
for use when specifying DMA handles.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 include/dt-bindings/dma/r8a7790-dma.h | 228 ++++++++++++++++++++++++++++++++++
 1 file changed, 228 insertions(+)
 create mode 100644 include/dt-bindings/dma/r8a7790-dma.h

diff --git a/include/dt-bindings/dma/r8a7790-dma.h b/include/dt-bindings/dma/r8a7790-dma.h
new file mode 100644
index 0000000..732422a
--- /dev/null
+++ b/include/dt-bindings/dma/r8a7790-dma.h
@@ -0,0 +1,228 @@
+/*
+ * R8A7790 System and Audio DMA channel resource identifiers
+ *
+ * Copyirght (c) 2014 Codethink Ltd.
+ *	Ben Dooks <ben.dooks@codethink.co.uk>
+ *
+ * Licensed under GPLv2
+*/
+
+/* System DMAC */
+
+#define R8A7790_DMA_SCIFA0_TX	(0x21)
+#define R8A7790_DMA_SCIFA0_RX	(0x22)
+#define R8A7790_DMA_SCIFA1_TX	(0x25)
+#define R8A7790_DMA_SCIFA1_RX	(0x26)
+#define R8A7790_DMA_SCIFA2_TX	(0x27)
+#define R8A7790_DMA_SCIFA2_RX	(0x28)
+
+#define R8A7790_DMA_SCIFB0_TX	(0x3D)
+#define R8A7790_DMA_SCIFB0_RX	(0x3E)
+#define R8A7790_DMA_SCIFB1_TX	(0x19)
+#define R8A7790_DMA_SCIFB1_RX	(0x1A)
+#define R8A7790_DMA_SCIFB2_TX	(0x1D)
+#define R8A7790_DMA_SCIFB2_RX	(0x1E)
+
+#define R8A7790_DMA_HSCIF0_TX	(0x39)
+#define R8A7790_DMA_HSCIF0_RX	(0x3A)
+#define R8A7790_DMA_HSCIF1_TX	(0x4D)
+#define R8A7790_DMA_HSCIF1_RX	(0x4E)
+
+#define R8A7790_DMA_SCIF0_TX	(0x29)
+#define R8A7790_DMA_SCIF0_RX	(0x2A)
+#define R8A7790_DMA_SCIF1_TX	(0x2D)
+#define R8A7790_DMA_SCIF1_RX	(0x2E)
+
+#define R8A7790_DMA_MSIOF0_TX	(0x81)
+#define R8A7790_DMA_MSIOF0_RX	(0x82)
+#define R8A7790_DMA_MSIOF1_TX	(0x85)
+#define R8A7790_DMA_MSIOF1_RX	(0x86)
+#define R8A7790_DMA_MSIOF2_TX	(0x41)
+#define R8A7790_DMA_MSIOF2_RX	(0x42)
+#define R8A7790_DMA_MSIOF3_TX	(0x45)
+#define R8A7790_DMA_MSIOF3_RX	(0x46)
+
+#define R8A7790_DMA_QSPI_TX	(0x17)
+#define R8A7790_DMA_QSPI_RX	(0x18)
+
+#define R8A7790_DMA_SIM_TX	(0xA1)
+#define R8A7790_DMA_SIM_RX	(0xA2)
+
+#define R8A7790_DMA_IIC0_TX	(0x61)
+#define R8A7790_DMA_IIC0_RX	(0x62)
+#define R8A7790_DMA_IIC1_TX	(0x65)
+#define R8A7790_DMA_IIC1_RX	(0x66)
+#define R8A7790_DMA_IIC2_TX	(0x69)
+#define R8A7790_DMA_IIC2_RX	(0x6A)
+#define R8A7790_DMA_IIC3_TX	(0x77)
+#define R8A7790_DMA_IIC3_RX	(0x78)
+
+#define R8A7790_DMA_SDHI0_TX	(0xCD)
+#define R8A7790_DMA_SDHI0_RX	(0xCE)
+#define R8A7790_DMA_SDHI1_TX	(0xC9)
+#define R8A7790_DMA_SDHI1_RX	(0xCA)
+#define R8A7790_DMA_SDHI2_TX	(0xC1)
+#define R8A7790_DMA_SDHI2_RX	(0xC2)
+#define R8A7790_DMA_SDHI2C2_TX	(0xC5)
+#define R8A7790_DMA_SDHI2C2_RX	(0xC6)
+#define R8A7790_DMA_SDHI3_TX	(0xD3)
+#define R8A7790_DMA_SDHI3_RX	(0xD4)
+#define R8A7790_DMA_SDHI3C2_TX	(0xDF)
+#define R8A7790_DMA_SDHI3C2_RX	(0xDE)
+
+#define R8A7790_DMA_TPU0	(0xF1)
+#define R8A7790_DMA_TSIF0	(0xEA)
+#define R8A7790_DMA_TSIF1	(0xF0)
+
+#define R8A7790_DMA_AXISTATR	(0xA6)
+#define R8A7790_DMA_AXISTATS0	(0xAC)
+#define R8A7790_DMA_AXISTATS1	(0xAA)
+#define R8A7790_DMA_AXISTATS2	(0xA8)
+#define R8A7790_DMA_AXISTATS3	(0xA4)
+
+#define R8A7790_DMA_MMCIF0_TX	(0xD1)
+#define R8A7790_DMA_MMCIF0_RX	(0xD2)
+#define R8A7790_DMA_MMCIF1_TX	(0xE1)
+#define R8A7790_DMA_MMCIF1_RX	(0xE2)
+
+/* Audio DMAC */
+
+#define R8A7790_DMA_DTCPC0_TX	(0xD7)
+#define R8A7790_DMA_DTCPC0_RX	(0xD8)
+#define R8A7790_DMA_DTCPC1_TX	(0xD9)
+#define R8A7790_DMA_DTCPC1_RX	(0xDA)
+#define R8A7790_DMA_DTCPP0_TX	(0xBF)
+#define R8A7790_DMA_DTCPP0_RX	(0xC0)
+#define R8A7790_DMA_DTCPP1_TX	(0xD5)
+#define R8A7790_DMA_DTCPP1_RX	(0xD6)
+
+#define R8A7790_DMA_MLM0_TX	(0xDB)
+#define R8A7790_DMA_MLM0_RX	(0xDC)
+#define R8A7790_DMA_MLM1_TX	(0xE3)
+#define R8A7790_DMA_MLM1_RX	(0xE4)
+#define R8A7790_DMA_MLM2_TX	(0xE5)
+#define R8A7790_DMA_MLM2_RX	(0xE6)
+#define R8A7790_DMA_MLM3_TX	(0xE7)
+#define R8A7790_DMA_MLM3_RX	(0xE8)
+#define R8A7790_DMA_MLM4_TX	(0xF3)
+#define R8A7790_DMA_MLM4_RX	(0xF4)
+#define R8A7790_DMA_MLM5_TX	(0xF5)
+#define R8A7790_DMA_MLM5_RX	(0xF6)
+#define R8A7790_DMA_MLM6_TX	(0xF7)
+#define R8A7790_DMA_MLM6_RX	(0xF8)
+#define R8A7790_DMA_MLM7_TX	(0xF9)
+#define R8A7790_DMA_MLM7_RX	(0xFA)
+
+#define R8A7790_DMA_SCU0	(0x85)
+#define R8A7790_DMA_SCU1	(0x87)
+#define R8A7790_DMA_SCU2	(0x89)
+#define R8A7790_DMA_SCU3	(0x8B)
+#define R8A7790_DMA_SCU4	(0x8D)
+#define R8A7790_DMA_SCU5	(0x8F)
+#define R8A7790_DMA_SCU6	(0x91)
+#define R8A7790_DMA_SCU7	(0x93)
+#define R8A7790_DMA_SCU8	(0x95)
+#define R8A7790_DMA_SCU9	(0x97)
+
+#define R8A7790_DMA_SCUCMD0	(0xBC)
+#define R8A7790_DMA_SCUCMD1	(0xBE)
+
+#define R8A7790_DMA_SCUOUT0	(0x9A)
+#define R8A7790_DMA_SCUOUT1	(0x9C)
+#define R8A7790_DMA_SCUOUT2	(0x9E)
+#define R8A7790_DMA_SCUOUT3	(0xA0)
+#define R8A7790_DMA_SCUOUT4	(0xB0)
+#define R8A7790_DMA_SCUOUT5	(0xB2)
+#define R8A7790_DMA_SCUOUT6	(0xB4)
+#define R8A7790_DMA_SCUOUT7	(0xB6)
+#define R8A7790_DMA_SCUOUT8	(0xB8)
+#define R8A7790_DMA_SCUOUT9	(0xBA)
+
+#define R8A7790_DMA_SSCI00_TX	(0x15)
+#define R8A7790_DMA_SSCI00_RX	(0x16)
+#define R8A7790_DMA_SSCI01_TX	(0x35)
+#define R8A7790_DMA_SSCI01_RX	(0x36)
+#define R8A7790_DMA_SSCI02_TX	(0x37)
+#define R8A7790_DMA_SSCI02_RX	(0x38)
+#define R8A7790_DMA_SSCI03_TX	(0x47)
+#define R8A7790_DMA_SSCI03_RX	(0x48)
+
+#define R8A7790_DMA_SSCI10_TX	(0x49)
+#define R8A7790_DMA_SSCI10_RX	(0x4A)
+#define R8A7790_DMA_SSCI11_TX	(0x4B)
+#define R8A7790_DMA_SSCI11_RX	(0x4C)
+#define R8A7790_DMA_SSCI12_TX	(0x57)
+#define R8A7790_DMA_SSCI12_RX	(0x58)
+#define R8A7790_DMA_SSCI13_TX	(0x59)
+#define R8A7790_DMA_SSCI13_RX	(0x5A)
+
+#define R8A7790_DMA_SSCI20_TX	(0x63)
+#define R8A7790_DMA_SSCI20_RX	(0x64)
+#define R8A7790_DMA_SSCI21_TX	(0x67)
+#define R8A7790_DMA_SSCI21_RX	(0x68)
+#define R8A7790_DMA_SSCI22_TX	(0x6B)
+#define R8A7790_DMA_SSCI22_RX	(0x6C)
+#define R8A7790_DMA_SSCI23_TX	(0x6D)
+#define R8A7790_DMA_SSCI23_RX	(0x6E)
+
+#define R8A7790_DMA_SSCI20_TX	(0x63)
+#define R8A7790_DMA_SSCI20_RX	(0x64)
+#define R8A7790_DMA_SSCI21_TX	(0x67)
+#define R8A7790_DMA_SSCI21_RX	(0x68)
+#define R8A7790_DMA_SSCI22_TX	(0x6B)
+#define R8A7790_DMA_SSCI22_RX	(0x6C)
+#define R8A7790_DMA_SSCI23_TX	(0x6D)
+#define R8A7790_DMA_SSCI23_RX	(0x6E)
+
+#define R8A7790_DMA_SSCI3_TX	(0x6F)
+#define R8A7790_DMA_SSCI3_RX	(0x70)
+
+#define R8A7790_DMA_SSCI4_TX	(0x71)
+#define R8A7790_DMA_SSCI4_RX	(0x72)
+
+#define R8A7790_DMA_SSCI5_TX	(0x73)
+#define R8A7790_DMA_SSCI5_RX	(0x74)
+
+#define R8A7790_DMA_SSCI6_TX	(0x75)
+#define R8A7790_DMA_SSCI6_RX	(0x76)
+
+#define R8A7790_DMA_SSCI7_TX	(0x79)
+#define R8A7790_DMA_SSCI7_RX	(0x7A)
+
+#define R8A7790_DMA_SSCI8_TX	(0x7B)
+#define R8A7790_DMA_SSCI8_RX	(0x7C)
+
+#define R8A7790_DMA_SSCI90_TX	(0x7D)
+#define R8A7790_DMA_SSCI90_RX	(0x7E)
+#define R8A7790_DMA_SSCI91_TX	(0x7F)
+#define R8A7790_DMA_SSCI91_RX	(0x80)
+#define R8A7790_DMA_SSCI92_TX	(0x81)
+#define R8A7790_DMA_SSCI92_RX	(0x82)
+#define R8A7790_DMA_SSCI93_TX	(0x83)
+#define R8A7790_DMA_SSCI93_RX	(0x84)
+
+#define R8A7790_DMA_SSIND0_TX	(0x01)
+#define R8A7790_DMA_SSIND0_RX	(0x02)
+#define R8A7790_DMA_SSIND1_TX	(0x03)
+#define R8A7790_DMA_SSIND1_RX	(0x04)
+#define R8A7790_DMA_SSIND2_TX	(0x05)
+#define R8A7790_DMA_SSIND2_RX	(0x06)
+#define R8A7790_DMA_SSIND3_TX	(0x07)
+#define R8A7790_DMA_SSIND3_RX	(0x08)
+#define R8A7790_DMA_SSIND4_TX	(0x09)
+#define R8A7790_DMA_SSIND4_RX	(0x0A)
+#define R8A7790_DMA_SSIND5_TX	(0x0B)
+#define R8A7790_DMA_SSIND5_RX	(0x0C)
+#define R8A7790_DMA_SSIND6_TX	(0x0D)
+#define R8A7790_DMA_SSIND6_RX	(0x0E)
+#define R8A7790_DMA_SSIND7_TX	(0x0F)
+#define R8A7790_DMA_SSIND7_RX	(0x10)
+#define R8A7790_DMA_SSIND8_TX	(0x11)
+#define R8A7790_DMA_SSIND8_RX	(0x12)
+#define R8A7790_DMA_SSIND9_TX	(0x13)
+#define R8A7790_DMA_SSIND9_RX	(0x14)
+
+#define CHCR_RX_32BIT	SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_32BIT)
+#define CHCR_TX_32BIT	SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_32BIT)
+#define CHCR_RX_256BIT	SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_256BIT)
+#define CHCR_TX_256BIT	SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_256BIT)
-- 
1.9.1

Re: [PATCH v2 2/9] ARM: shmobile: r8a7790: add dma defines for sys and audio dmacs

[Arnd Bergmann]

On Monday 14 April 2014 22:35:05 Ben Dooks wrote:
> Add the DMA resource IDs for the R8A7790 Audio and SYS DMA controllers
> for use when specifying DMA handles.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>

I really hate these lists in bindings:

> +#define R8A7790_DMA_SCIFA0_TX	(0x21)
> +#define R8A7790_DMA_SCIFA0_RX	(0x22)
> +#define R8A7790_DMA_SCIFA1_TX	(0x25)
> +#define R8A7790_DMA_SCIFA1_RX	(0x26)
> +#define R8A7790_DMA_SCIFA2_TX	(0x27)
> +#define R8A7790_DMA_SCIFA2_RX	(0x28)
> +
> +#define R8A7790_DMA_SCIFB0_TX	(0x3D)
> +#define R8A7790_DMA_SCIFB0_RX	(0x3E)
> +#define R8A7790_DMA_SCIFB1_TX	(0x19)
> +#define R8A7790_DMA_SCIFB1_RX	(0x1A)
> +#define R8A7790_DMA_SCIFB2_TX	(0x1D)
> +#define R8A7790_DMA_SCIFB2_RX	(0x1E)

These are all hardware constants, they should come from the data sheet and
get put into the dtsi file. The driver doesn't care what they are, and
the binding doesn't care, this only serves to make the binding less
generic.

> +#define CHCR_RX_32BIT	SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_32BIT)
> +#define CHCR_TX_32BIT	SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_32BIT)
> +#define CHCR_RX_256BIT	SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_256BIT)
> +#define CHCR_TX_256BIT	SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_256BIT)

For these, it's different: There is nothing wrong putting macros like
these into DT, because they will be the same across all SoCs.

However, as I mentioned in my reply to patch 8, I don't think that information
belongs into DT, and it should be in the device driver instead, because
that already knows the direction and transfer width and has to set it
through the slave config interface anyway.

	Arnd

Re: [PATCH v2 2/9] ARM: shmobile: r8a7790: add dma defines for sys and audio dmacs

[Arnd Bergmann]

On Monday 14 April 2014 22:35:05 Ben Dooks wrote:
> Add the DMA resource IDs for the R8A7790 Audio and SYS DMA controllers
> for use when specifying DMA handles.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>

I really hate these lists in bindings:

> +#define R8A7790_DMA_SCIFA0_TX	(0x21)
> +#define R8A7790_DMA_SCIFA0_RX	(0x22)
> +#define R8A7790_DMA_SCIFA1_TX	(0x25)
> +#define R8A7790_DMA_SCIFA1_RX	(0x26)
> +#define R8A7790_DMA_SCIFA2_TX	(0x27)
> +#define R8A7790_DMA_SCIFA2_RX	(0x28)
> +
> +#define R8A7790_DMA_SCIFB0_TX	(0x3D)
> +#define R8A7790_DMA_SCIFB0_RX	(0x3E)
> +#define R8A7790_DMA_SCIFB1_TX	(0x19)
> +#define R8A7790_DMA_SCIFB1_RX	(0x1A)
> +#define R8A7790_DMA_SCIFB2_TX	(0x1D)
> +#define R8A7790_DMA_SCIFB2_RX	(0x1E)

These are all hardware constants, they should come from the data sheet and
get put into the dtsi file. The driver doesn't care what they are, and
the binding doesn't care, this only serves to make the binding less
generic.

> +#define CHCR_RX_32BIT	SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_32BIT)
> +#define CHCR_TX_32BIT	SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_32BIT)
> +#define CHCR_RX_256BIT	SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_256BIT)
> +#define CHCR_TX_256BIT	SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_256BIT)

For these, it's different: There is nothing wrong putting macros like
these into DT, because they will be the same across all SoCs.

However, as I mentioned in my reply to patch 8, I don't think that information
belongs into DT, and it should be in the device driver instead, because
that already knows the direction and transfer width and has to set it
through the slave config interface anyway.

	Arnd

Re: [PATCH v2 2/9] ARM: shmobile: r8a7790: add dma defines for sys and audio dmacs

[Simon Horman]

On Tue, Apr 15, 2014 at 12:10:00AM +0200, Arnd Bergmann wrote:
> On Monday 14 April 2014 22:35:05 Ben Dooks wrote:
> > Add the DMA resource IDs for the R8A7790 Audio and SYS DMA controllers
> > for use when specifying DMA handles.
> > 
> > Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> 
> I really hate these lists in bindings:
> 
> > +#define R8A7790_DMA_SCIFA0_TX	(0x21)
> > +#define R8A7790_DMA_SCIFA0_RX	(0x22)
> > +#define R8A7790_DMA_SCIFA1_TX	(0x25)
> > +#define R8A7790_DMA_SCIFA1_RX	(0x26)
> > +#define R8A7790_DMA_SCIFA2_TX	(0x27)
> > +#define R8A7790_DMA_SCIFA2_RX	(0x28)
> > +
> > +#define R8A7790_DMA_SCIFB0_TX	(0x3D)
> > +#define R8A7790_DMA_SCIFB0_RX	(0x3E)
> > +#define R8A7790_DMA_SCIFB1_TX	(0x19)
> > +#define R8A7790_DMA_SCIFB1_RX	(0x1A)
> > +#define R8A7790_DMA_SCIFB2_TX	(0x1D)
> > +#define R8A7790_DMA_SCIFB2_RX	(0x1E)
> 
> These are all hardware constants, they should come from the data sheet and
> get put into the dtsi file. The driver doesn't care what they are, and
> the binding doesn't care, this only serves to make the binding less
> generic.

They serve to make the dts file significantly more readable and
give some small level of compile-time checking to the dts file.

I am entirely in favour of them and its the direction that we
have been moving in for shmobile bindings.

> > +#define CHCR_RX_32BIT	SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_32BIT)
> > +#define CHCR_TX_32BIT	SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_32BIT)
> > +#define CHCR_RX_256BIT	SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_256BIT)
> > +#define CHCR_TX_256BIT	SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_256BIT)
> 
> For these, it's different: There is nothing wrong putting macros like
> these into DT, because they will be the same across all SoCs.
> 
> However, as I mentioned in my reply to patch 8, I don't think that information
> belongs into DT, and it should be in the device driver instead, because
> that already knows the direction and transfer width and has to set it
> through the slave config interface anyway.
> 
> 	Arnd
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

Re: [PATCH v2 2/9] ARM: shmobile: r8a7790: add dma defines for sys and audio dmacs

[Simon Horman]

On Tue, Apr 15, 2014 at 12:10:00AM +0200, Arnd Bergmann wrote:
> On Monday 14 April 2014 22:35:05 Ben Dooks wrote:
> > Add the DMA resource IDs for the R8A7790 Audio and SYS DMA controllers
> > for use when specifying DMA handles.
> > 
> > Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> 
> I really hate these lists in bindings:
> 
> > +#define R8A7790_DMA_SCIFA0_TX	(0x21)
> > +#define R8A7790_DMA_SCIFA0_RX	(0x22)
> > +#define R8A7790_DMA_SCIFA1_TX	(0x25)
> > +#define R8A7790_DMA_SCIFA1_RX	(0x26)
> > +#define R8A7790_DMA_SCIFA2_TX	(0x27)
> > +#define R8A7790_DMA_SCIFA2_RX	(0x28)
> > +
> > +#define R8A7790_DMA_SCIFB0_TX	(0x3D)
> > +#define R8A7790_DMA_SCIFB0_RX	(0x3E)
> > +#define R8A7790_DMA_SCIFB1_TX	(0x19)
> > +#define R8A7790_DMA_SCIFB1_RX	(0x1A)
> > +#define R8A7790_DMA_SCIFB2_TX	(0x1D)
> > +#define R8A7790_DMA_SCIFB2_RX	(0x1E)
> 
> These are all hardware constants, they should come from the data sheet and
> get put into the dtsi file. The driver doesn't care what they are, and
> the binding doesn't care, this only serves to make the binding less
> generic.

They serve to make the dts file significantly more readable and
give some small level of compile-time checking to the dts file.

I am entirely in favour of them and its the direction that we
have been moving in for shmobile bindings.

> > +#define CHCR_RX_32BIT	SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_32BIT)
> > +#define CHCR_TX_32BIT	SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_32BIT)
> > +#define CHCR_RX_256BIT	SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_256BIT)
> > +#define CHCR_TX_256BIT	SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_256BIT)
> 
> For these, it's different: There is nothing wrong putting macros like
> these into DT, because they will be the same across all SoCs.
> 
> However, as I mentioned in my reply to patch 8, I don't think that information
> belongs into DT, and it should be in the device driver instead, because
> that already knows the direction and transfer width and has to set it
> through the slave config interface anyway.
> 
> 	Arnd
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

Re: [PATCH v2 2/9] ARM: shmobile: r8a7790: add dma defines for sys and audio dmacs

[Ben Dooks]

On 14/04/14 23:51, Simon Horman wrote:
> On Tue, Apr 15, 2014 at 12:10:00AM +0200, Arnd Bergmann wrote:
>> On Monday 14 April 2014 22:35:05 Ben Dooks wrote:
>>> Add the DMA resource IDs for the R8A7790 Audio and SYS DMA controllers
>>> for use when specifying DMA handles.
>>>
>>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>>
>> I really hate these lists in bindings:
>>
>>> +#define R8A7790_DMA_SCIFA0_TX	(0x21)
>>> +#define R8A7790_DMA_SCIFA0_RX	(0x22)
>>> +#define R8A7790_DMA_SCIFA1_TX	(0x25)
>>> +#define R8A7790_DMA_SCIFA1_RX	(0x26)
>>> +#define R8A7790_DMA_SCIFA2_TX	(0x27)
>>> +#define R8A7790_DMA_SCIFA2_RX	(0x28)
>>> +
>>> +#define R8A7790_DMA_SCIFB0_TX	(0x3D)
>>> +#define R8A7790_DMA_SCIFB0_RX	(0x3E)
>>> +#define R8A7790_DMA_SCIFB1_TX	(0x19)
>>> +#define R8A7790_DMA_SCIFB1_RX	(0x1A)
>>> +#define R8A7790_DMA_SCIFB2_TX	(0x1D)
>>> +#define R8A7790_DMA_SCIFB2_RX	(0x1E)
>>
>> These are all hardware constants, they should come from the data sheet and
>> get put into the dtsi file. The driver doesn't care what they are, and
>> the binding doesn't care, this only serves to make the binding less
>> generic.
>
> They serve to make the dts file significantly more readable and
> give some small level of compile-time checking to the dts file.
>
> I am entirely in favour of them and its the direction that we
> have been moving in for shmobile bindings.

I don't really mind either way on these, when we had the
configuration for each slave in the dma-controller node
then having defines was very sensible.

>>> +#define CHCR_RX_32BIT	SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_32BIT)
>>> +#define CHCR_TX_32BIT	SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_32BIT)
>>> +#define CHCR_RX_256BIT	SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_256BIT)
>>> +#define CHCR_TX_256BIT	SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_256BIT)
>>
>> For these, it's different: There is nothing wrong putting macros like
>> these into DT, because they will be the same across all SoCs.
>>
>> However, as I mentioned in my reply to patch 8, I don't think that information
>> belongs into DT, and it should be in the device driver instead, because
>> that already knows the direction and transfer width and has to set it
>> through the slave config interface anyway.

There are a couple of issues here, firstly is that I have no idea if
any other SoCs have control bits that are not currently configurable
from the information supplied by a driver when it is bound.

The second is that the DMA for some peripherals do not match the size
of the registers, for example the SDHI blocks can do 256bit DMA to
what is specified to be a 32bit register.

I also prefer these to be in one place, to avoid the following

- Altering every $OS run on the system when you add a new dma peripheral
- Having to cross merge adding to DTS/DTSI and a driver for the same.


-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

Re: [PATCH v2 2/9] ARM: shmobile: r8a7790: add dma defines for sys and audio dmacs

[Ben Dooks]

On 14/04/14 23:51, Simon Horman wrote:
> On Tue, Apr 15, 2014 at 12:10:00AM +0200, Arnd Bergmann wrote:
>> On Monday 14 April 2014 22:35:05 Ben Dooks wrote:
>>> Add the DMA resource IDs for the R8A7790 Audio and SYS DMA controllers
>>> for use when specifying DMA handles.
>>>
>>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>>
>> I really hate these lists in bindings:
>>
>>> +#define R8A7790_DMA_SCIFA0_TX	(0x21)
>>> +#define R8A7790_DMA_SCIFA0_RX	(0x22)
>>> +#define R8A7790_DMA_SCIFA1_TX	(0x25)
>>> +#define R8A7790_DMA_SCIFA1_RX	(0x26)
>>> +#define R8A7790_DMA_SCIFA2_TX	(0x27)
>>> +#define R8A7790_DMA_SCIFA2_RX	(0x28)
>>> +
>>> +#define R8A7790_DMA_SCIFB0_TX	(0x3D)
>>> +#define R8A7790_DMA_SCIFB0_RX	(0x3E)
>>> +#define R8A7790_DMA_SCIFB1_TX	(0x19)
>>> +#define R8A7790_DMA_SCIFB1_RX	(0x1A)
>>> +#define R8A7790_DMA_SCIFB2_TX	(0x1D)
>>> +#define R8A7790_DMA_SCIFB2_RX	(0x1E)
>>
>> These are all hardware constants, they should come from the data sheet and
>> get put into the dtsi file. The driver doesn't care what they are, and
>> the binding doesn't care, this only serves to make the binding less
>> generic.
>
> They serve to make the dts file significantly more readable and
> give some small level of compile-time checking to the dts file.
>
> I am entirely in favour of them and its the direction that we
> have been moving in for shmobile bindings.

I don't really mind either way on these, when we had the
configuration for each slave in the dma-controller node
then having defines was very sensible.

>>> +#define CHCR_RX_32BIT	SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_32BIT)
>>> +#define CHCR_TX_32BIT	SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_32BIT)
>>> +#define CHCR_RX_256BIT	SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_256BIT)
>>> +#define CHCR_TX_256BIT	SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_256BIT)
>>
>> For these, it's different: There is nothing wrong putting macros like
>> these into DT, because they will be the same across all SoCs.
>>
>> However, as I mentioned in my reply to patch 8, I don't think that information
>> belongs into DT, and it should be in the device driver instead, because
>> that already knows the direction and transfer width and has to set it
>> through the slave config interface anyway.

There are a couple of issues here, firstly is that I have no idea if
any other SoCs have control bits that are not currently configurable
from the information supplied by a driver when it is bound.

The second is that the DMA for some peripherals do not match the size
of the registers, for example the SDHI blocks can do 256bit DMA to
what is specified to be a 32bit register.

I also prefer these to be in one place, to avoid the following

- Altering every $OS run on the system when you add a new dma peripheral
- Having to cross merge adding to DTS/DTSI and a driver for the same.


-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

Re: [PATCH v2 2/9] ARM: shmobile: r8a7790: add dma defines for sys and audio dmacs

[Geert Uytterhoeven]

On Mon, Apr 14, 2014 at 11:35 PM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
> --- /dev/null
> +++ b/include/dt-bindings/dma/r8a7790-dma.h
> @@ -0,0 +1,228 @@
> +/*
> + * R8A7790 System and Audio DMA channel resource identifiers
> + *
> + * Copyirght (c) 2014 Codethink Ltd.

Copyright.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 2/9] ARM: shmobile: r8a7790: add dma defines for sys and audio dmacs

[Geert Uytterhoeven]

On Mon, Apr 14, 2014 at 11:35 PM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
> --- /dev/null
> +++ b/include/dt-bindings/dma/r8a7790-dma.h
> @@ -0,0 +1,228 @@
> +/*
> + * R8A7790 System and Audio DMA channel resource identifiers
> + *
> + * Copyirght (c) 2014 Codethink Ltd.

Copyright.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 2/9] ARM: shmobile: r8a7790: add dma defines for sys and audio dmacs

[Geert Uytterhoeven]

Hi Ben,

On Mon, Apr 14, 2014 at 11:35 PM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
> +*/
> +
> +/* System DMAC */

Missing include guards.

> +#define R8A7790_DMA_MSIOF0_TX  (0x81)
> +#define R8A7790_DMA_MSIOF0_RX  (0x82)
> +#define R8A7790_DMA_MSIOF1_TX  (0x85)
> +#define R8A7790_DMA_MSIOF1_RX  (0x86)

These are the only ones that se different for r8a7791 (0x51 etc.
compared to 0x81).
Wondering whether someone mixed up decimal and hexadecimal...

Are the System DMAC and Audio DMAC ID spaces separate
or unified? We also have in the audio section:

#define R8A7790_DMA_SSCI92_TX   (0x81)
#define R8A7790_DMA_SSCI92_RX   (0x82)
#define R8A7790_DMA_SCU0        (0x85)

> +#define R8A7790_DMA_IIC3_TX    (0x77)
> +#define R8A7790_DMA_IIC3_RX    (0x78)

In all other places, we call this "IICDVFS" instead of "IIC3".
The docs aren't always that consistent, though.

> +#define R8A7790_DMA_AXISTATR   (0xA6)
> +#define R8A7790_DMA_AXISTATS0  (0xAC)
> +#define R8A7790_DMA_AXISTATS1  (0xAA)
> +#define R8A7790_DMA_AXISTATS2  (0xA8)
> +#define R8A7790_DMA_AXISTATS3  (0xA4)

R8A7790_DMA_AXISTATS3C, to match the docs?

> +#define R8A7790_DMA_MMCIF0_TX  (0xD1)
> +#define R8A7790_DMA_MMCIF0_RX  (0xD2)
> +#define R8A7790_DMA_MMCIF1_TX  (0xE1)
> +#define R8A7790_DMA_MMCIF1_RX  (0xE2)

AXSTM is missing at the end:

#define R8A7790_DMA_AXSTM      (0xAE)

> +#define R8A7790_DMA_SSCI20_TX  (0x63)
> +#define R8A7790_DMA_SSCI20_RX  (0x64)
> +#define R8A7790_DMA_SSCI21_TX  (0x67)
> +#define R8A7790_DMA_SSCI21_RX  (0x68)
> +#define R8A7790_DMA_SSCI22_TX  (0x6B)
> +#define R8A7790_DMA_SSCI22_RX  (0x6C)
> +#define R8A7790_DMA_SSCI23_TX  (0x6D)
> +#define R8A7790_DMA_SSCI23_RX  (0x6E)
> +
> +#define R8A7790_DMA_SSCI20_TX  (0x63)
> +#define R8A7790_DMA_SSCI20_RX  (0x64)
> +#define R8A7790_DMA_SSCI21_TX  (0x67)
> +#define R8A7790_DMA_SSCI21_RX  (0x68)
> +#define R8A7790_DMA_SSCI22_TX  (0x6B)
> +#define R8A7790_DMA_SSCI22_RX  (0x6C)
> +#define R8A7790_DMA_SSCI23_TX  (0x6D)
> +#define R8A7790_DMA_SSCI23_RX  (0x6E)

This section is duplicated.

> +#define CHCR_RX_32BIT  SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_32BIT)
> +#define CHCR_TX_32BIT  SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_32BIT)
> +#define CHCR_RX_256BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_256BIT)
> +#define CHCR_TX_256BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_256BIT)

From my (still-limited) understanding of the shdma driver, these look like
pure register values, not descriptions of the hardware?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 2/9] ARM: shmobile: r8a7790: add dma defines for sys and audio dmacs

[Geert Uytterhoeven]

Hi Ben,

On Mon, Apr 14, 2014 at 11:35 PM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
> +*/
> +
> +/* System DMAC */

Missing include guards.

> +#define R8A7790_DMA_MSIOF0_TX  (0x81)
> +#define R8A7790_DMA_MSIOF0_RX  (0x82)
> +#define R8A7790_DMA_MSIOF1_TX  (0x85)
> +#define R8A7790_DMA_MSIOF1_RX  (0x86)

These are the only ones that se different for r8a7791 (0x51 etc.
compared to 0x81).
Wondering whether someone mixed up decimal and hexadecimal...

Are the System DMAC and Audio DMAC ID spaces separate
or unified? We also have in the audio section:

#define R8A7790_DMA_SSCI92_TX   (0x81)
#define R8A7790_DMA_SSCI92_RX   (0x82)
#define R8A7790_DMA_SCU0        (0x85)

> +#define R8A7790_DMA_IIC3_TX    (0x77)
> +#define R8A7790_DMA_IIC3_RX    (0x78)

In all other places, we call this "IICDVFS" instead of "IIC3".
The docs aren't always that consistent, though.

> +#define R8A7790_DMA_AXISTATR   (0xA6)
> +#define R8A7790_DMA_AXISTATS0  (0xAC)
> +#define R8A7790_DMA_AXISTATS1  (0xAA)
> +#define R8A7790_DMA_AXISTATS2  (0xA8)
> +#define R8A7790_DMA_AXISTATS3  (0xA4)

R8A7790_DMA_AXISTATS3C, to match the docs?

> +#define R8A7790_DMA_MMCIF0_TX  (0xD1)
> +#define R8A7790_DMA_MMCIF0_RX  (0xD2)
> +#define R8A7790_DMA_MMCIF1_TX  (0xE1)
> +#define R8A7790_DMA_MMCIF1_RX  (0xE2)

AXSTM is missing at the end:

#define R8A7790_DMA_AXSTM      (0xAE)

> +#define R8A7790_DMA_SSCI20_TX  (0x63)
> +#define R8A7790_DMA_SSCI20_RX  (0x64)
> +#define R8A7790_DMA_SSCI21_TX  (0x67)
> +#define R8A7790_DMA_SSCI21_RX  (0x68)
> +#define R8A7790_DMA_SSCI22_TX  (0x6B)
> +#define R8A7790_DMA_SSCI22_RX  (0x6C)
> +#define R8A7790_DMA_SSCI23_TX  (0x6D)
> +#define R8A7790_DMA_SSCI23_RX  (0x6E)
> +
> +#define R8A7790_DMA_SSCI20_TX  (0x63)
> +#define R8A7790_DMA_SSCI20_RX  (0x64)
> +#define R8A7790_DMA_SSCI21_TX  (0x67)
> +#define R8A7790_DMA_SSCI21_RX  (0x68)
> +#define R8A7790_DMA_SSCI22_TX  (0x6B)
> +#define R8A7790_DMA_SSCI22_RX  (0x6C)
> +#define R8A7790_DMA_SSCI23_TX  (0x6D)
> +#define R8A7790_DMA_SSCI23_RX  (0x6E)

This section is duplicated.

> +#define CHCR_RX_32BIT  SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_32BIT)
> +#define CHCR_TX_32BIT  SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_32BIT)
> +#define CHCR_RX_256BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_256BIT)
> +#define CHCR_TX_256BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_256BIT)

>From my (still-limited) understanding of the shdma driver, these look like
pure register values, not descriptions of the hardware?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 2/9] ARM: shmobile: r8a7790: add dma defines for sys and audio dmacs

[Geert Uytterhoeven]

Hi Ben,

On Tue, May 13, 2014 at 12:46 PM, Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
>> +#define R8A7790_DMA_MSIOF0_TX  (0x81)
>> +#define R8A7790_DMA_MSIOF0_RX  (0x82)
>> +#define R8A7790_DMA_MSIOF1_TX  (0x85)
>> +#define R8A7790_DMA_MSIOF1_RX  (0x86)
>
> These are the only ones that se different for r8a7791 (0x51 etc.
> compared to 0x81).
> Wondering whether someone mixed up decimal and hexadecimal...

Confirmed. They should be 0x51, 0x52, 0x55, 0x56.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 2/9] ARM: shmobile: r8a7790: add dma defines for sys and audio dmacs

[Geert Uytterhoeven]

Hi Ben,

On Tue, May 13, 2014 at 12:46 PM, Geert Uytterhoeven
<geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org> wrote:
>> +#define R8A7790_DMA_MSIOF0_TX  (0x81)
>> +#define R8A7790_DMA_MSIOF0_RX  (0x82)
>> +#define R8A7790_DMA_MSIOF1_TX  (0x85)
>> +#define R8A7790_DMA_MSIOF1_RX  (0x86)
>
> These are the only ones that se different for r8a7791 (0x51 etc.
> compared to 0x81).
> Wondering whether someone mixed up decimal and hexadecimal...

Confirmed. They should be 0x51, 0x52, 0x55, 0x56.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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[PATCH v2 2/9] ARM: shmobile: r8a7790: Add DU node to device tree

[Laurent Pinchart]

Add the DU device with a disabled state. Boards that want to enable the
DU need to specify the output topology.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
 arch/arm/boot/dts/r8a7790.dtsi | 39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index d0e1773..4c2deb4 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -600,6 +600,45 @@
 		status = "disabled";
 	};
 
+	du: display@feb00000 {
+		compatible = "renesas,du-r8a7790";
+		reg = <0 0xfeb00000 0 0x70000>,
+		      <0 0xfeb90000 0 0x1c>,
+		      <0 0xfeb94000 0 0x1c>;
+		reg-names = "du", "lvds.0", "lvds.1";
+		interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 268 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 269 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7790_CLK_DU0>,
+		         <&mstp7_clks R8A7790_CLK_DU1>,
+		         <&mstp7_clks R8A7790_CLK_DU2>,
+		         <&mstp7_clks R8A7790_CLK_LVDS0>,
+		         <&mstp7_clks R8A7790_CLK_LVDS1>;
+		clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				du_out_rgb: endpoint {
+				};
+			};
+			port@1 {
+				reg = <1>;
+				du_out_lvds0: endpoint {
+				};
+			};
+			port@2 {
+				reg = <2>;
+				du_out_lvds1: endpoint {
+				};
+			};
+		};
+	};
+
 	clocks {
 		#address-cells = <2>;
 		#size-cells = <2>;
-- 
1.8.5.5

[PATCH v2 3/9] ARM: shmobile: r8a7790: add dmac0 dmac1 nodes

[Ben Dooks]

Add nodes for the SYS-DMA controllers, SYS-DMAC0 and SYS-DMAC1. These
both share the same device sources, so are wrapped in the shdma-mux
node to allow both to be used.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>

---
v2:
	- fix indentation
	- remove extra channel on dmac1
v3:
	- updated to use include files
---
 arch/arm/boot/dts/r8a7790.dtsi | 72 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index f98b01d..e85e354 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -8,6 +8,8 @@
  * kind, whether express or implied.
  */
 
+#include <dt-bindings/dma/shdma.h>
+#include <dt-bindings/dma/r8a7790-dma.h>
 #include <dt-bindings/clock/r8a7790-clock.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -86,6 +88,76 @@
 		};
 	};
 
+	dma0: dma-mux@0 {
+		compatible = "renesas,shdma-mux";
+		#dma-cells = <2>;
+		dma-channels = <20>;
+		dma-requests = <256>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		sysdma0: dma-controller@e6700000 {
+			compatible = "renesas,shdma-r8a7790";
+			clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
+			dma-channels = <15>;
+			status = "disabled";
+			reg = <0 0xe6700020 0 0xffc0>;
+
+			interrupts =	<0 197 IRQ_TYPE_LEVEL_HIGH>, /* error */
+					<0 200 IRQ_TYPE_LEVEL_HIGH>, /* ch0 */
+					<0 201 IRQ_TYPE_LEVEL_HIGH>,
+					<0 202 IRQ_TYPE_LEVEL_HIGH>,
+					<0 203 IRQ_TYPE_LEVEL_HIGH>,
+					<0 204 IRQ_TYPE_LEVEL_HIGH>,
+					<0 205 IRQ_TYPE_LEVEL_HIGH>,
+					<0 206 IRQ_TYPE_LEVEL_HIGH>,
+					<0 207 IRQ_TYPE_LEVEL_HIGH>,
+					<0 208 IRQ_TYPE_LEVEL_HIGH>,
+					<0 209 IRQ_TYPE_LEVEL_HIGH>,
+					<0 210 IRQ_TYPE_LEVEL_HIGH>,
+					<0 211 IRQ_TYPE_LEVEL_HIGH>,
+					<0 212 IRQ_TYPE_LEVEL_HIGH>,
+					<0 213 IRQ_TYPE_LEVEL_HIGH>,
+					<0 214 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					"ch0", "ch1", "ch2", "ch3",
+					"ch4", "ch5", "ch6", "ch7",
+					"ch8", "ch9", "ch10", "ch11",
+					"ch12", "ch13", "ch14";
+		};
+
+		sysdma1: dma-controller@e6720000 {
+			compatible = "renesas,shdma-r8a7790";
+			clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
+			dma-channels = <15>;
+			reg = <0 0xe6720020 0 0xffc0>;
+			status = "disabled";
+
+			interrupts =  <0 220 IRQ_TYPE_LEVEL_HIGH>,
+					<0 216 IRQ_TYPE_LEVEL_HIGH>,
+					<0 217 IRQ_TYPE_LEVEL_HIGH>,
+					<0 218 IRQ_TYPE_LEVEL_HIGH>,
+					<0 219 IRQ_TYPE_LEVEL_HIGH>,
+					<0 308 IRQ_TYPE_LEVEL_HIGH>,
+					<0 309 IRQ_TYPE_LEVEL_HIGH>,
+					<0 310 IRQ_TYPE_LEVEL_HIGH>,
+					<0 311 IRQ_TYPE_LEVEL_HIGH>,
+					<0 312 IRQ_TYPE_LEVEL_HIGH>,
+					<0 313 IRQ_TYPE_LEVEL_HIGH>,
+					<0 314 IRQ_TYPE_LEVEL_HIGH>,
+					<0 315 IRQ_TYPE_LEVEL_HIGH>,
+					<0 316 IRQ_TYPE_LEVEL_HIGH>,
+					<0 317 IRQ_TYPE_LEVEL_HIGH>,
+					<0 318 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					"ch0", "ch1", "ch2", "ch3",
+					"ch4", "ch5", "ch6", "ch7",
+					"ch8", "ch9", "ch10", "ch11",
+					"ch12", "ch13", "ch14";
+		};
+	};
+
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,cortex-a15-gic";
 		#interrupt-cells = <3>;
-- 
1.9.1

[PATCH v2 3/9] ARM: shmobile: r8a7790: add dmac0 dmac1 nodes

[Ben Dooks]

Add nodes for the SYS-DMA controllers, SYS-DMAC0 and SYS-DMAC1. These
both share the same device sources, so are wrapped in the shdma-mux
node to allow both to be used.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>

---
v2:
	- fix indentation
	- remove extra channel on dmac1
v3:
	- updated to use include files
---
 arch/arm/boot/dts/r8a7790.dtsi | 72 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index f98b01d..e85e354 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -8,6 +8,8 @@
  * kind, whether express or implied.
  */
 
+#include <dt-bindings/dma/shdma.h>
+#include <dt-bindings/dma/r8a7790-dma.h>
 #include <dt-bindings/clock/r8a7790-clock.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -86,6 +88,76 @@
 		};
 	};
 
+	dma0: dma-mux@0 {
+		compatible = "renesas,shdma-mux";
+		#dma-cells = <2>;
+		dma-channels = <20>;
+		dma-requests = <256>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		sysdma0: dma-controller@e6700000 {
+			compatible = "renesas,shdma-r8a7790";
+			clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
+			dma-channels = <15>;
+			status = "disabled";
+			reg = <0 0xe6700020 0 0xffc0>;
+
+			interrupts =	<0 197 IRQ_TYPE_LEVEL_HIGH>, /* error */
+					<0 200 IRQ_TYPE_LEVEL_HIGH>, /* ch0 */
+					<0 201 IRQ_TYPE_LEVEL_HIGH>,
+					<0 202 IRQ_TYPE_LEVEL_HIGH>,
+					<0 203 IRQ_TYPE_LEVEL_HIGH>,
+					<0 204 IRQ_TYPE_LEVEL_HIGH>,
+					<0 205 IRQ_TYPE_LEVEL_HIGH>,
+					<0 206 IRQ_TYPE_LEVEL_HIGH>,
+					<0 207 IRQ_TYPE_LEVEL_HIGH>,
+					<0 208 IRQ_TYPE_LEVEL_HIGH>,
+					<0 209 IRQ_TYPE_LEVEL_HIGH>,
+					<0 210 IRQ_TYPE_LEVEL_HIGH>,
+					<0 211 IRQ_TYPE_LEVEL_HIGH>,
+					<0 212 IRQ_TYPE_LEVEL_HIGH>,
+					<0 213 IRQ_TYPE_LEVEL_HIGH>,
+					<0 214 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					"ch0", "ch1", "ch2", "ch3",
+					"ch4", "ch5", "ch6", "ch7",
+					"ch8", "ch9", "ch10", "ch11",
+					"ch12", "ch13", "ch14";
+		};
+
+		sysdma1: dma-controller@e6720000 {
+			compatible = "renesas,shdma-r8a7790";
+			clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
+			dma-channels = <15>;
+			reg = <0 0xe6720020 0 0xffc0>;
+			status = "disabled";
+
+			interrupts =  <0 220 IRQ_TYPE_LEVEL_HIGH>,
+					<0 216 IRQ_TYPE_LEVEL_HIGH>,
+					<0 217 IRQ_TYPE_LEVEL_HIGH>,
+					<0 218 IRQ_TYPE_LEVEL_HIGH>,
+					<0 219 IRQ_TYPE_LEVEL_HIGH>,
+					<0 308 IRQ_TYPE_LEVEL_HIGH>,
+					<0 309 IRQ_TYPE_LEVEL_HIGH>,
+					<0 310 IRQ_TYPE_LEVEL_HIGH>,
+					<0 311 IRQ_TYPE_LEVEL_HIGH>,
+					<0 312 IRQ_TYPE_LEVEL_HIGH>,
+					<0 313 IRQ_TYPE_LEVEL_HIGH>,
+					<0 314 IRQ_TYPE_LEVEL_HIGH>,
+					<0 315 IRQ_TYPE_LEVEL_HIGH>,
+					<0 316 IRQ_TYPE_LEVEL_HIGH>,
+					<0 317 IRQ_TYPE_LEVEL_HIGH>,
+					<0 318 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					"ch0", "ch1", "ch2", "ch3",
+					"ch4", "ch5", "ch6", "ch7",
+					"ch8", "ch9", "ch10", "ch11",
+					"ch12", "ch13", "ch14";
+		};
+	};
+
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,cortex-a15-gic";
 		#interrupt-cells = <3>;
-- 
1.9.1

Re: [PATCH v2 3/9] ARM: shmobile: r8a7790: add dmac0 dmac1 nodes

[Geert Uytterhoeven]

Hi Ben,

On Mon, Apr 14, 2014 at 11:35 PM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
> --- a/arch/arm/boot/dts/r8a7790.dtsi
> +++ b/arch/arm/boot/dts/r8a7790.dtsi
> @@ -86,6 +88,76 @@
>                 };
>         };
>
> +       dma0: dma-mux@0 {
> +               compatible = "renesas,shdma-mux";
> +               #dma-cells = <2>;
> +               dma-channels = <20>;

Shouldn't this be 30, i.e. the sum of the properties in the child nodes?

> +               sysdma0: dma-controller@e6700000 {
> +                       compatible = "renesas,shdma-r8a7790";
> +                       clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
> +                       dma-channels = <15>;

> +               sysdma1: dma-controller@e6720000 {
> +                       compatible = "renesas,shdma-r8a7790";
> +                       clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
> +                       dma-channels = <15>;

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 3/9] ARM: shmobile: r8a7790: add dmac0 dmac1 nodes

[Geert Uytterhoeven]

Hi Ben,

On Mon, Apr 14, 2014 at 11:35 PM, Ben Dooks <ben.dooks-4yDnlxn2s6sWdaTGBSpHTA@public.gmane.org> wrote:
> --- a/arch/arm/boot/dts/r8a7790.dtsi
> +++ b/arch/arm/boot/dts/r8a7790.dtsi
> @@ -86,6 +88,76 @@
>                 };
>         };
>
> +       dma0: dma-mux@0 {
> +               compatible = "renesas,shdma-mux";
> +               #dma-cells = <2>;
> +               dma-channels = <20>;

Shouldn't this be 30, i.e. the sum of the properties in the child nodes?

> +               sysdma0: dma-controller@e6700000 {
> +                       compatible = "renesas,shdma-r8a7790";
> +                       clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
> +                       dma-channels = <15>;

> +               sysdma1: dma-controller@e6720000 {
> +                       compatible = "renesas,shdma-r8a7790";
> +                       clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
> +                       dma-channels = <15>;

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v2 3/9] ARM: shmobile: r8a7790: add dmac0 dmac1 nodes

[Ben Dooks]

On 13/05/14 13:00, Geert Uytterhoeven wrote:
> Hi Ben,
> 
> On Mon, Apr 14, 2014 at 11:35 PM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
>> --- a/arch/arm/boot/dts/r8a7790.dtsi
>> +++ b/arch/arm/boot/dts/r8a7790.dtsi
>> @@ -86,6 +88,76 @@
>>                 };
>>         };
>>
>> +       dma0: dma-mux@0 {
>> +               compatible = "renesas,shdma-mux";
>> +               #dma-cells = <2>;
>> +               dma-channels = <20>;
> 
> Shouldn't this be 30, i.e. the sum of the properties in the child nodes?

Thanks, fixed.


-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

Re: [PATCH v2 3/9] ARM: shmobile: r8a7790: add dmac0 dmac1 nodes

[Ben Dooks]

On 13/05/14 13:00, Geert Uytterhoeven wrote:
> Hi Ben,
> 
> On Mon, Apr 14, 2014 at 11:35 PM, Ben Dooks <ben.dooks-4yDnlxn2s6sWdaTGBSpHTA@public.gmane.org> wrote:
>> --- a/arch/arm/boot/dts/r8a7790.dtsi
>> +++ b/arch/arm/boot/dts/r8a7790.dtsi
>> @@ -86,6 +88,76 @@
>>                 };
>>         };
>>
>> +       dma0: dma-mux@0 {
>> +               compatible = "renesas,shdma-mux";
>> +               #dma-cells = <2>;
>> +               dma-channels = <20>;
> 
> Shouldn't this be 30, i.e. the sum of the properties in the child nodes?

Thanks, fixed.


-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius
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Re: [PATCH v2 3/9] ARM: shmobile: r8a7790: add dmac0 dmac1 nodes

[Geert Uytterhoeven]

On Mon, Apr 14, 2014 at 11:35 PM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
> --- a/arch/arm/boot/dts/r8a7790.dtsi
> +++ b/arch/arm/boot/dts/r8a7790.dtsi
> @@ -8,6 +8,8 @@
> +               sysdma0: dma-controller@e6700000 {

> +                       reg = <0 0xe6700020 0 0xffc0>;

> +               sysdma1: dma-controller@e6720000 {

> +                       reg = <0 0xe6720020 0 0xffc0>;

ePAPR: "The unit-address must match the first address specified in the reg
property of the node."

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 3/9] ARM: shmobile: r8a7790: add dmac0 dmac1 nodes

[Geert Uytterhoeven]

On Mon, Apr 14, 2014 at 11:35 PM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
> --- a/arch/arm/boot/dts/r8a7790.dtsi
> +++ b/arch/arm/boot/dts/r8a7790.dtsi
> @@ -8,6 +8,8 @@
> +               sysdma0: dma-controller@e6700000 {

> +                       reg = <0 0xe6700020 0 0xffc0>;

> +               sysdma1: dma-controller@e6720000 {

> +                       reg = <0 0xe6720020 0 0xffc0>;

ePAPR: "The unit-address must match the first address specified in the reg
property of the node."

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 4/9] ARM: shmobile: r8a7790: Add DMA for MMCIF1

[Ben Dooks]

Updated dtsi file with DMA info for MMCIF1

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/arm/boot/dts/r8a7790.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index e85e354..8b66de8 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -316,6 +316,9 @@
 		reg = <0 0xee220000 0 0x80>;
 		interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
+		dmas =  <&dma0 R8A7790_DMA_MMCIF1_RX CHCR_RX_32BIT>,
+			<&dma0 R8A7790_DMA_MMCIF1_TX CHCR_TX_32BIT>;
+		dma-names = "rx", "tx";
 		reg-io-width = <4>;
 		status = "disabled";
 	};
-- 
1.9.1

[PATCH v2 4/9] ARM: shmobile: r8a7790: Add DMA for MMCIF1

[Ben Dooks]

Updated dtsi file with DMA info for MMCIF1

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/arm/boot/dts/r8a7790.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index e85e354..8b66de8 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -316,6 +316,9 @@
 		reg = <0 0xee220000 0 0x80>;
 		interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
+		dmas =  <&dma0 R8A7790_DMA_MMCIF1_RX CHCR_RX_32BIT>,
+			<&dma0 R8A7790_DMA_MMCIF1_TX CHCR_TX_32BIT>;
+		dma-names = "rx", "tx";
 		reg-io-width = <4>;
 		status = "disabled";
 	};
-- 
1.9.1

[PATCH v2 5/9] ARM: shmobile: add Audio DMAC clocks

[Ben Dooks]

Add MSTP5 clock definitions for Audio DMAC

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/arm/boot/dts/r8a7790.dtsi            | 7 ++++---
 include/dt-bindings/clock/r8a7790-clock.h | 2 ++
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 8b66de8..de3ca15 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -777,10 +777,11 @@
 		mstp5_clks: mstp5_clks@e6150144 {
 			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 			reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
-			clocks = <&extal_clk>, <&p_clk>;
+			clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
 			#clock-cells = <1>;
-			renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
-			clock-output-names = "thermal", "pwm";
+			renesas,clock-indices = <R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
+						 R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
+			clock-output-names = "audmac0", "audamc1", "thermal", "pwm";
 		};
 		mstp7_clks: mstp7_clks@e615014c {
 			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
index 6548a5f..9e74d11 100644
--- a/include/dt-bindings/clock/r8a7790-clock.h
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -63,6 +63,8 @@
 #define R8A7790_CLK_USBDMAC1		31
 
 /* MSTP5 */
+#define R8A7790_CLK_AUDIO_DMAC1		1
+#define R8A7790_CLK_AUDIO_DMAC0		2
 #define R8A7790_CLK_THERMAL		22
 #define R8A7790_CLK_PWM			23
 
-- 
1.9.1

[PATCH v2 5/9] ARM: shmobile: add Audio DMAC clocks

[Ben Dooks]

Add MSTP5 clock definitions for Audio DMAC

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/arm/boot/dts/r8a7790.dtsi            | 7 ++++---
 include/dt-bindings/clock/r8a7790-clock.h | 2 ++
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 8b66de8..de3ca15 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -777,10 +777,11 @@
 		mstp5_clks: mstp5_clks@e6150144 {
 			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 			reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
-			clocks = <&extal_clk>, <&p_clk>;
+			clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
 			#clock-cells = <1>;
-			renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
-			clock-output-names = "thermal", "pwm";
+			renesas,clock-indices = <R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
+						 R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
+			clock-output-names = "audmac0", "audamc1", "thermal", "pwm";
 		};
 		mstp7_clks: mstp7_clks@e615014c {
 			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
index 6548a5f..9e74d11 100644
--- a/include/dt-bindings/clock/r8a7790-clock.h
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -63,6 +63,8 @@
 #define R8A7790_CLK_USBDMAC1		31
 
 /* MSTP5 */
+#define R8A7790_CLK_AUDIO_DMAC1		1
+#define R8A7790_CLK_AUDIO_DMAC0		2
 #define R8A7790_CLK_THERMAL		22
 #define R8A7790_CLK_PWM			23
 
-- 
1.9.1

[PATCH v2 6/9] ARM: shmobile: r8a7790: add audio dmac node

[Ben Dooks]

Add initial audio dmac node and resources.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/arm/boot/dts/r8a7790.dtsi | 66 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index de3ca15..582e687 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -158,6 +158,72 @@
 		};
 	};
 
+	dma1: dma-mux@1 {
+		compatible = "renesas,shdma-mux";
+		#dma-cells = <2>;
+		dma-channels = <20>;
+		dma-requests = <256>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		audiodma0: dma-contorller@ec700000 {
+			compatible = "renesas,shdma-r8a7790";
+			clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
+			dma-channels = <13>;
+			status = "disabled";
+			reg = <0 0xec700020 0 0xffc0>;
+
+			interrupts =	<0 346 IRQ_TYPE_LEVEL_HIGH>, /* error */
+					<0 320 IRQ_TYPE_LEVEL_HIGH>, /* ch0 */
+					<0 321 IRQ_TYPE_LEVEL_HIGH>,
+					<0 322 IRQ_TYPE_LEVEL_HIGH>,
+					<0 323 IRQ_TYPE_LEVEL_HIGH>,
+					<0 324 IRQ_TYPE_LEVEL_HIGH>,
+					<0 325 IRQ_TYPE_LEVEL_HIGH>,
+					<0 326 IRQ_TYPE_LEVEL_HIGH>,
+					<0 327 IRQ_TYPE_LEVEL_HIGH>,
+					<0 328 IRQ_TYPE_LEVEL_HIGH>,
+					<0 329 IRQ_TYPE_LEVEL_HIGH>,
+					<0 330 IRQ_TYPE_LEVEL_HIGH>,
+					<0 331 IRQ_TYPE_LEVEL_HIGH>,
+					<0 332 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					"ch0", "ch1", "ch2", "ch3",
+					"ch4", "ch5", "ch6", "ch7",
+					"ch8", "ch9", "ch10", "ch11",
+					"ch12";
+		};
+
+		audiodma1: dma-controller@ec720000 {
+			compatible = "renesas,shdma-r8a7790";
+			clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
+			dma-channels = <13>;
+			status = "disabled";
+			reg = <0 0xec720020 0 0xffc0>;
+
+			interrupts =	<0 347 IRQ_TYPE_LEVEL_HIGH>, /* error */
+					<0 333 IRQ_TYPE_LEVEL_HIGH>, /* ch0 */
+					<0 334 IRQ_TYPE_LEVEL_HIGH>,
+					<0 335 IRQ_TYPE_LEVEL_HIGH>,
+					<0 336 IRQ_TYPE_LEVEL_HIGH>,
+					<0 337 IRQ_TYPE_LEVEL_HIGH>,
+					<0 338 IRQ_TYPE_LEVEL_HIGH>,
+					<0 339 IRQ_TYPE_LEVEL_HIGH>,
+					<0 340 IRQ_TYPE_LEVEL_HIGH>,
+					<0 341 IRQ_TYPE_LEVEL_HIGH>,
+					<0 342 IRQ_TYPE_LEVEL_HIGH>,
+					<0 343 IRQ_TYPE_LEVEL_HIGH>,
+					<0 344 IRQ_TYPE_LEVEL_HIGH>,
+					<0 345 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					"ch0", "ch1", "ch2", "ch3",
+					"ch4", "ch5", "ch6", "ch7",
+					"ch8", "ch9", "ch10", "ch11",
+					"ch12";
+		};
+	};
+
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,cortex-a15-gic";
 		#interrupt-cells = <3>;
-- 
1.9.1

[PATCH v2 6/9] ARM: shmobile: r8a7790: add audio dmac node

[Ben Dooks]

Add initial audio dmac node and resources.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/arm/boot/dts/r8a7790.dtsi | 66 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index de3ca15..582e687 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -158,6 +158,72 @@
 		};
 	};
 
+	dma1: dma-mux@1 {
+		compatible = "renesas,shdma-mux";
+		#dma-cells = <2>;
+		dma-channels = <20>;
+		dma-requests = <256>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		audiodma0: dma-contorller@ec700000 {
+			compatible = "renesas,shdma-r8a7790";
+			clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
+			dma-channels = <13>;
+			status = "disabled";
+			reg = <0 0xec700020 0 0xffc0>;
+
+			interrupts =	<0 346 IRQ_TYPE_LEVEL_HIGH>, /* error */
+					<0 320 IRQ_TYPE_LEVEL_HIGH>, /* ch0 */
+					<0 321 IRQ_TYPE_LEVEL_HIGH>,
+					<0 322 IRQ_TYPE_LEVEL_HIGH>,
+					<0 323 IRQ_TYPE_LEVEL_HIGH>,
+					<0 324 IRQ_TYPE_LEVEL_HIGH>,
+					<0 325 IRQ_TYPE_LEVEL_HIGH>,
+					<0 326 IRQ_TYPE_LEVEL_HIGH>,
+					<0 327 IRQ_TYPE_LEVEL_HIGH>,
+					<0 328 IRQ_TYPE_LEVEL_HIGH>,
+					<0 329 IRQ_TYPE_LEVEL_HIGH>,
+					<0 330 IRQ_TYPE_LEVEL_HIGH>,
+					<0 331 IRQ_TYPE_LEVEL_HIGH>,
+					<0 332 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					"ch0", "ch1", "ch2", "ch3",
+					"ch4", "ch5", "ch6", "ch7",
+					"ch8", "ch9", "ch10", "ch11",
+					"ch12";
+		};
+
+		audiodma1: dma-controller@ec720000 {
+			compatible = "renesas,shdma-r8a7790";
+			clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
+			dma-channels = <13>;
+			status = "disabled";
+			reg = <0 0xec720020 0 0xffc0>;
+
+			interrupts =	<0 347 IRQ_TYPE_LEVEL_HIGH>, /* error */
+					<0 333 IRQ_TYPE_LEVEL_HIGH>, /* ch0 */
+					<0 334 IRQ_TYPE_LEVEL_HIGH>,
+					<0 335 IRQ_TYPE_LEVEL_HIGH>,
+					<0 336 IRQ_TYPE_LEVEL_HIGH>,
+					<0 337 IRQ_TYPE_LEVEL_HIGH>,
+					<0 338 IRQ_TYPE_LEVEL_HIGH>,
+					<0 339 IRQ_TYPE_LEVEL_HIGH>,
+					<0 340 IRQ_TYPE_LEVEL_HIGH>,
+					<0 341 IRQ_TYPE_LEVEL_HIGH>,
+					<0 342 IRQ_TYPE_LEVEL_HIGH>,
+					<0 343 IRQ_TYPE_LEVEL_HIGH>,
+					<0 344 IRQ_TYPE_LEVEL_HIGH>,
+					<0 345 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					"ch0", "ch1", "ch2", "ch3",
+					"ch4", "ch5", "ch6", "ch7",
+					"ch8", "ch9", "ch10", "ch11",
+					"ch12";
+		};
+	};
+
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,cortex-a15-gic";
 		#interrupt-cells = <3>;
-- 
1.9.1

Re: [PATCH v2 6/9] ARM: shmobile: r8a7790: add audio dmac node

[Geert Uytterhoeven]

On Mon, Apr 14, 2014 at 11:35 PM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
> diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
> index de3ca15..582e687 100644
> --- a/arch/arm/boot/dts/r8a7790.dtsi
> +++ b/arch/arm/boot/dts/r8a7790.dtsi

> +               audiodma0: dma-contorller@ec700000 {

dma-controller

(we really need better dts validation tools)

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 6/9] ARM: shmobile: r8a7790: add audio dmac node

[Geert Uytterhoeven]

On Mon, Apr 14, 2014 at 11:35 PM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
> diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
> index de3ca15..582e687 100644
> --- a/arch/arm/boot/dts/r8a7790.dtsi
> +++ b/arch/arm/boot/dts/r8a7790.dtsi

> +               audiodma0: dma-contorller@ec700000 {

dma-controller

(we really need better dts validation tools)

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 6/9] ARM: shmobile: r8a7790: add audio dmac node

[Geert Uytterhoeven]

On Mon, Apr 14, 2014 at 11:35 PM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
> --- a/arch/arm/boot/dts/r8a7790.dtsi
> +++ b/arch/arm/boot/dts/r8a7790.dtsi
> @@ -158,6 +158,72 @@
>                 };
>         };
>
> +       dma1: dma-mux@1 {
> +               compatible = "renesas,shdma-mux";
> +               #dma-cells = <2>;
> +               dma-channels = <20>;

26, cfr. the sum of the subnodes?

> +               audiodma0: dma-contorller@ec700000 {
> +                       compatible = "renesas,shdma-r8a7790";
> +                       clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
> +                       dma-channels = <13>;

> +               audiodma1: dma-controller@ec720000 {
> +                       compatible = "renesas,shdma-r8a7790";
> +                       clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
> +                       dma-channels = <13>;

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 6/9] ARM: shmobile: r8a7790: add audio dmac node

[Geert Uytterhoeven]

On Mon, Apr 14, 2014 at 11:35 PM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
> --- a/arch/arm/boot/dts/r8a7790.dtsi
> +++ b/arch/arm/boot/dts/r8a7790.dtsi
> @@ -158,6 +158,72 @@
>                 };
>         };
>
> +       dma1: dma-mux@1 {
> +               compatible = "renesas,shdma-mux";
> +               #dma-cells = <2>;
> +               dma-channels = <20>;

26, cfr. the sum of the subnodes?

> +               audiodma0: dma-contorller@ec700000 {
> +                       compatible = "renesas,shdma-r8a7790";
> +                       clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
> +                       dma-channels = <13>;

> +               audiodma1: dma-controller@ec720000 {
> +                       compatible = "renesas,shdma-r8a7790";
> +                       clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
> +                       dma-channels = <13>;

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 6/9] ARM: shmobile: r8a7790: add audio dmac node

[Geert Uytterhoeven]

Hi Ben,

On Mon, Apr 14, 2014 at 11:35 PM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
> --- a/arch/arm/boot/dts/r8a7790.dtsi
> +++ b/arch/arm/boot/dts/r8a7790.dtsi

> +               audiodma0: dma-contorller@ec700000 {

> +                       reg = <0 0xec700020 0 0xffc0>;

> +               audiodma1: dma-controller@ec720000 {

> +                       reg = <0 0xec720020 0 0xffc0>;

ePAPR: "The unit-address must match the first address specified in the reg
property of the node."

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 6/9] ARM: shmobile: r8a7790: add audio dmac node

[Geert Uytterhoeven]

Hi Ben,

On Mon, Apr 14, 2014 at 11:35 PM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
> --- a/arch/arm/boot/dts/r8a7790.dtsi
> +++ b/arch/arm/boot/dts/r8a7790.dtsi

> +               audiodma0: dma-contorller@ec700000 {

> +                       reg = <0 0xec700020 0 0xffc0>;

> +               audiodma1: dma-controller@ec720000 {

> +                       reg = <0 0xec720020 0 0xffc0>;

ePAPR: "The unit-address must match the first address specified in the reg
property of the node."

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 7/9] ARM: shmobile: lager: enable sysdma units 0 and 1

[Ben Dooks]

Add the new sysdma units to the lager board.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/arm/boot/dts/r8a7790-lager.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 26a9010..3b4f59c 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -214,3 +214,11 @@
 	cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
+
+&sysdma0 {
+	status = "okay";
+};
+
+&sysdma1 {
+	status = "okay";
+};
-- 
1.9.1

[PATCH v2 7/9] ARM: shmobile: lager: enable sysdma units 0 and 1

[Ben Dooks]

Add the new sysdma units to the lager board.

Signed-off-by: Ben Dooks <ben.dooks-4yDnlxn2s6sWdaTGBSpHTA@public.gmane.org>
---
 arch/arm/boot/dts/r8a7790-lager.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 26a9010..3b4f59c 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -214,3 +214,11 @@
 	cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
+
+&sysdma0 {
+	status = "okay";
+};
+
+&sysdma1 {
+	status = "okay";
+};
-- 
1.9.1

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[PATCH v2 7/9] ARM: shmobile: lager: Enable DU device in DT

[Laurent Pinchart]

Specify the DU output topology, enable the DU device and configure the
related pins.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
 arch/arm/boot/dts/r8a7790-lager.dts | 51 ++++++++++++++++++++++++++++++++++---
 1 file changed, 48 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 84dcafa..a036d88 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -144,6 +144,54 @@
 		states = <3300000 1
 			  1800000 0>;
 	};
+
+	adv7123 {
+		compatible = "adi,adv7123";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ports {
+			port@0 {
+				adv7123_in: endpoint {
+					remote-endpoint = <&du_out_rgb>;
+				};
+			};
+			port@1 {
+				adv7123_out: endpoint {
+					remote-endpoint = <&vga_in>;
+				};
+			};
+		};
+	};
+
+	vga {
+		compatible = "vga-connector";
+
+		port {
+			vga_in: endpoint {
+				remote-endpoint = <&adv7123_out>;
+			};
+		};
+	};
+};
+
+&du {
+	pinctrl-0 = <&du_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	ports {
+		port@0 {
+			endpoint {
+				remote-endpoint = <&adv7123_in>;
+			};
+		};
+		port@2 {
+			lvds_connector: endpoint {
+			};
+		};
+	};
 };
 
 &extal_clk {
@@ -151,9 +199,6 @@
 };
 
 &pfc {
-	pinctrl-0 = <&du_pins>;
-	pinctrl-names = "default";
-
 	du_pins: du {
 		renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
 		renesas,function = "du";
-- 
1.8.5.5

Re: [PATCH v2 7/9] ARM: shmobile: lager: Enable DU device in DT

[Sergei Shtylyov]

Hello.

On 9/24/2014 4:27 PM, Laurent Pinchart wrote:

> Specify the DU output topology, enable the DU device and configure the
> related pins.

> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
>   arch/arm/boot/dts/r8a7790-lager.dts | 51 ++++++++++++++++++++++++++++++++++---
>   1 file changed, 48 insertions(+), 3 deletions(-)

> diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
> index 84dcafa..a036d88 100644
> --- a/arch/arm/boot/dts/r8a7790-lager.dts
> +++ b/arch/arm/boot/dts/r8a7790-lager.dts
> @@ -144,6 +144,54 @@
>   		states = <3300000 1
>   			  1800000 0>;
>   	};
> +
> +	adv7123 {

    Again, ePAPR dictates using generic device node names, not just chip names.

> +		compatible = "adi,adv7123";
> +
> +		#address-cells = <1>;
> +		#size-cells = <0>;

    Er, why? I don't see the "reg" props below...

> +
> +		ports {
> +			port@0 {
> +				adv7123_in: endpoint {
> +					remote-endpoint = <&du_out_rgb>;
> +				};
> +			};
> +			port@1 {
> +				adv7123_out: endpoint {
> +					remote-endpoint = <&vga_in>;
> +				};
> +			};
> +		};
> +	};

WBR, Sergei

Re: [PATCH v2 7/9] ARM: shmobile: lager: Enable DU device in DT

[Laurent Pinchart]

Hi Sergei,

Thank you for the review.

On Wednesday 24 September 2014 17:01:30 Sergei Shtylyov wrote:
> Hello.
> 
> On 9/24/2014 4:27 PM, Laurent Pinchart wrote:
> > Specify the DU output topology, enable the DU device and configure the
> > related pins.
> > 
> > Signed-off-by: Laurent Pinchart
> > <laurent.pinchart+renesas@ideasonboard.com>
> > ---
> > 
> >  arch/arm/boot/dts/r8a7790-lager.dts | 51 ++++++++++++++++++++++++++++---
> >  1 file changed, 48 insertions(+),
> >  3 deletions(-)
> > 
> > diff --git a/arch/arm/boot/dts/r8a7790-lager.dts
> > b/arch/arm/boot/dts/r8a7790-lager.dts index 84dcafa..a036d88 100644
> > --- a/arch/arm/boot/dts/r8a7790-lager.dts
> > +++ b/arch/arm/boot/dts/r8a7790-lager.dts
> > @@ -144,6 +144,54 @@
> >   		states = <3300000 1
> >   			  1800000 0>;
> >   	};
> > 
> > +
> > +	adv7123 {
> 
> Again, ePAPR dictates using generic device node names, not just chip names.

Sure, will fix.

> > +		compatible = "adi,adv7123";
> > +
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> 
> Er, why? I don't see the "reg" props below...

The reg property is missing in the "port" nodes, and the #*-cells properties 
should be moved to the "ports" node. I'll fix that.

> > +
> > +		ports {
> > +			port@0 {
> > +				adv7123_in: endpoint {
> > +					remote-endpoint = <&du_out_rgb>;
> > +				};
> > +			};
> > +			port@1 {
> > +				adv7123_out: endpoint {
> > +					remote-endpoint = <&vga_in>;
> > +				};
> > +			};
> > +		};
> > +	};

-- 
Regards,

Laurent Pinchart

[PATCH v2 8/9] DMA: shdma: initial of common code

[Ben Dooks]

Add support for building shdma internal data from the device tree to allow
converting the driver to be device tree enabled.

It includes a helper for the of case to build the internal data used to
select and filter out the DMA channels from the ID information in the
device tree. Also updates the documentation for the DT case.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 Documentation/devicetree/bindings/dma/shdma.txt |  23 +++-
 drivers/dma/sh/shdma-of.c                       | 174 +++++++++++++++++++++++-
 drivers/dma/sh/shdma.h                          |  29 ++++
 include/dt-bindings/dma/shdma.h                 |  45 ++++++
 4 files changed, 268 insertions(+), 3 deletions(-)
 create mode 100644 include/dt-bindings/dma/shdma.h

diff --git a/Documentation/devicetree/bindings/dma/shdma.txt b/Documentation/devicetree/bindings/dma/shdma.txt
index 2a3f3b8..86d5c50 100644
--- a/Documentation/devicetree/bindings/dma/shdma.txt
+++ b/Documentation/devicetree/bindings/dma/shdma.txt
@@ -14,9 +14,9 @@ still has to be placed under such a multiplexer node.
 Required properties:
 - compatible:	should be "renesas,shdma-mux"
 - #dma-cells:	should be <1>, see "dmas" property below
+- dma-channels:	number of DMA channels
 
 Optional properties (currently unused):
-- dma-channels:	number of DMA channels
 - dma-requests:	number of DMA request signals
 
 * DMA controller
@@ -25,6 +25,7 @@ Required properties:
 - compatible:	should be of the form "renesas,shdma-<soc>", where <soc> should
 		be replaced with the desired SoC model, e.g.
 		"renesas,shdma-r8a73a4" for the system DMAC on r8a73a4 SoC
+		"renesas,shdma-r8a7790" for the DMAC on the R8A7790.
 
 Example:
 	dmac: dma-multiplexer@0 {
@@ -70,15 +71,33 @@ Example:
 		};
 	};
 
+For r8a7790 and newer implementations, the information for the channel
+controll register is found in the dma phandle and #dma-cells is set to 2.
+
+	dma0: dma-mux@0 {
+		compatible = "renesas,shdma-mux";
+		#dma-cells = <2>;
+		dma-channels = <20>;
+		dma-requests = <256>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+	}
+
 * DMA client
 
 Required properties:
 - dmas:		a list of <[DMA multiplexer phandle] [MID/RID value]> pairs,
 		where MID/RID values are fixed handles, specified in the SoC
-		manual
+		manual as the value that would be written into the DMASR.
+
+		If the #dma-cells is 2, then the second value is the CHCR
+		register configuration for the channel.
+
 - dma-names:	a list of DMA channel names, one per "dmas" entry
 
 Example:
 	dmas = <&dmac 0xd1
 		&dmac 0xd2>;
 	dma-names = "tx", "rx";
+
diff --git a/drivers/dma/sh/shdma-of.c b/drivers/dma/sh/shdma-of.c
index 06473a0..661ac77 100644
--- a/drivers/dma/sh/shdma-of.c
+++ b/drivers/dma/sh/shdma-of.c
@@ -3,12 +3,15 @@
  *
  * Copyright (C) 2013 Renesas Electronics Inc.
  * Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+ * Copyright (c) 2014 Codethink Limited
+ *	Ben Dooks <ben.dooks@codethink.co.uk>
  *
  * This is free software; you can redistribute it and/or modify
  * it under the terms of version 2 of the GNU General Public License as
  * published by the Free Software Foundation.
  */
 
+#include <linux/slab.h>
 #include <linux/dmaengine.h>
 #include <linux/module.h>
 #include <linux/of.h>
@@ -16,17 +19,117 @@
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
 #include <linux/shdma-base.h>
+#include <linux/sh_dma.h>
+
+#include <dt-bindings/dma/shdma.h>
 
 #define to_shdma_chan(c) container_of(c, struct shdma_chan, dma_chan)
 
+#include "shdma-arm.h"
+
+static const unsigned int arm_dma_ts_shift[] = SH_DMAE_TS_SHIFT;
+
+static struct sh_dmae_pdata arm_dmae_info = {
+	.ts_low_shift	= SHDMA_ARM_TS_LOW_SHIFT,
+	.ts_low_mask	= SHDMA_ARM_TS_LOW_BIT << SHDMA_ARM_TS_LOW_SHIFT,
+	.ts_high_shift	= SHDMA_ARM_TS_HI_SHIFT,
+	.ts_high_mask	= SHDMA_ARM_TS_HI_BIT << SHDMA_ARM_TS_HI_SHIFT,
+	.ts_shift	= arm_dma_ts_shift,
+	.ts_shift_num	= ARRAY_SIZE(arm_dma_ts_shift),
+	.dmaor_init	= DMAOR_DME,
+	.chclr_present	= 1,
+	.chclr_bitwise	= 1,
+};
+
+struct sh_dmae_of_info shdma_arm_info = {
+	.pdata_template	= &arm_dmae_info,
+	.channel_offset	= 0x8000-0x20,
+	.channel_stride	= 0x80,
+	.offset		= 0x0,
+	.dmars		= 0x40,
+	.chclr_offset	= 0x80,
+};
+
+/* Need global index due to shdma_slave_used being global */
+static atomic_t of_slave_index = ATOMIC_INIT(0);
+
+struct shdma_of_client {
+	int				index;
+	struct list_head		node;
+	struct sh_dmae_slave_config	cfg;
+};
+
+struct shdma_of_pdata {
+	struct sh_dmae_pdata	pdata;
+	struct shdma_of_state	*state;
+};
+
+struct shdma_of_state {
+	struct list_head	of_slaves;
+};
+
+#define to_of_pdata(_pd) container_of(_pd, struct shdma_of_pdata, pdata)
+
+struct shdma_of_client *shdma_of_find_client(struct shdma_of_state *state, int id)
+{
+	struct shdma_of_client *client;
+
+	list_for_each_entry(client, &state->of_slaves, node) {
+		if (client->cfg.slave_id = id)
+			return client;
+	}
+
+	return NULL;
+}
+
+struct sh_dmae_slave_config *
+shdma_find_slave_of(struct sh_dmae_device *shdev, int match, int *index)
+{
+	struct shdma_of_pdata *pdata = to_of_pdata(shdev->pdata);
+	struct sh_dmae_slave_config *cfg = NULL;
+	struct shdma_of_client *client;
+
+	pr_info("looking for %02x\n", match);
+
+	client = shdma_of_find_client(pdata->state, match);
+	if (client) {
+		*index = client->index;
+		cfg = &client->cfg;
+	}
+
+	return cfg;
+}
+
 static struct dma_chan *shdma_of_xlate(struct of_phandle_args *dma_spec,
 				       struct of_dma *ofdma)
 {
+	struct platform_device *pdev = ofdma->of_dma_data;
 	u32 id = dma_spec->args[0];
 	dma_cap_mask_t mask;
 	struct dma_chan *chan;
 
-	if (dma_spec->args_count != 1)
+	if (dma_spec->args_count = 2) {
+		struct shdma_of_state *state = platform_get_drvdata(pdev);
+		struct shdma_of_client *client;
+
+		client = shdma_of_find_client(state, id);
+		if (!client) {
+			client = devm_kzalloc(&pdev->dev, sizeof(*client),
+					      GFP_KERNEL);
+			if (!client)
+				return NULL;
+
+			client->index = atomic_inc_return(&of_slave_index);
+			client->cfg.slave_id = id;
+			client->cfg.mid_rid = id;
+			client->cfg.chcr = dma_spec->args[1];
+
+			dev_dbg(&pdev->dev, "new client %d, %02x\n",
+				client->index, id);
+
+			list_add_tail(&client->node, &state->of_slaves);
+		}
+	} else if (dma_spec->args_count != 1)
 		return NULL;
 
 	dma_cap_zero(mask);
@@ -40,11 +143,80 @@ static struct dma_chan *shdma_of_xlate(struct of_phandle_args *dma_spec,
 	return chan;
 }
 
+const struct sh_dmae_pdata *
+sh_dma_probe_of(struct platform_device *pdev, const struct of_device_id *ofmatch)
+{
+	const struct device_node *np = pdev->dev.of_node;
+	const struct sh_dmae_of_info *ofinf;
+	struct device *dev = &pdev->dev;
+	struct sh_dmae_pdata *pdata;
+	struct shdma_of_pdata *ofdata;
+	struct sh_dmae_channel *chan;
+	u32 nr_chan;
+	unsigned ch;
+	int ret;
+
+	if (!ofmatch)
+		return NULL;
+
+	ofdata = devm_kzalloc(dev, sizeof(struct shdma_of_pdata), GFP_KERNEL);
+	if (!ofdata)
+		return NULL;
+
+	ofinf = ofmatch->data;
+	pdata = &ofdata->pdata;
+	*pdata = *ofinf->pdata_template;	/* copy in template first */
+	ofdata->state = dev_get_drvdata(dev->parent);
+
+	ret = of_property_read_u32(np, "dma-channels", &nr_chan);
+	if (ret < 0) {
+		dev_err(dev, "failed to get number of channels\n");
+		return NULL;
+	}
+
+	chan = devm_kcalloc(dev, nr_chan, sizeof(struct sh_dmae_channel),
+			    GFP_KERNEL);
+	if (!chan) {
+		dev_err(dev, "cannot allocate %d channels\n", nr_chan);
+		return NULL;
+	}
+
+	pdata->channel = chan;
+	pdata->channel_num = nr_chan;
+
+	dev_dbg(dev, "%d dma channels allocated\n", nr_chan);
+
+	for (ch = 0; ch < nr_chan; ch++) {
+		struct sh_dmae_channel *cp = chan + ch;
+		u32 base = ofinf->channel_offset + ofinf->channel_stride * ch;
+
+		cp->offset = base + ofinf->offset;
+		cp->dmars = base + ofinf->dmars;
+		cp->chclr_bit = ch;
+		cp->chclr_offset = ofinf->chclr_offset;
+
+		dev_dbg(dev, "ch %d: off %08x, dmars %08x, bit %d, off %d\n",
+			ch, cp->offset, cp->dmars,
+			cp->chclr_bit, cp->chclr_offset);
+	}
+
+	pdev->dev.platform_data = pdata;
+	return pdata;
+};
+
 static int shdma_of_probe(struct platform_device *pdev)
 {
 	const struct of_dev_auxdata *lookup = dev_get_platdata(&pdev->dev);
+	struct shdma_of_state *state;
 	int ret;
 
+	state = devm_kzalloc(&pdev->dev, sizeof(*state), GFP_KERNEL);
+	if (!state)
+		return -ENOMEM;
+
+	INIT_LIST_HEAD(&state->of_slaves);
+	platform_set_drvdata(pdev, state);
+
 	ret = of_dma_controller_register(pdev->dev.of_node,
 					 shdma_of_xlate, pdev);
 	if (ret < 0)
diff --git a/drivers/dma/sh/shdma.h b/drivers/dma/sh/shdma.h
index 758a57b..05b84b9 100644
--- a/drivers/dma/sh/shdma.h
+++ b/drivers/dma/sh/shdma.h
@@ -56,6 +56,26 @@ struct sh_dmae_desc {
 	struct shdma_desc shdma_desc;
 };
 
+/*
+ * Template information for building shdma data, provided as part of the
+ * data field in the of_device_id structure. This is then used to build
+ * the platform data for the dma code.
+ */
+struct sh_dmae_of_info {
+	struct sh_dmae_pdata	*pdata_template;
+	unsigned int		channel_offset;
+	unsigned int		channel_stride;
+	int			offset;
+	int			dmars;
+	int			chclr_offset;
+	int			chclr_bit;
+};
+
+extern struct sh_dmae_of_info shdma_arm_info;
+
+extern const struct sh_dmae_pdata *sh_dma_probe_of(struct platform_device *pdev,
+						   const struct of_device_id *match);
+
 #define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, shdma_chan)
 #define to_sh_desc(lh) container_of(lh, struct sh_desc, node)
 #define tx_to_sh_desc(tx) container_of(tx, struct sh_desc, async_tx)
@@ -69,4 +89,13 @@ extern const struct sh_dmae_pdata r8a73a4_dma_pdata;
 #define r8a73a4_shdma_devid NULL
 #endif
 
+#ifdef CONFIG_OF
+extern struct sh_dmae_slave_config *shdma_find_slave_of(struct sh_dmae_device *shdev, int match, int *index);
+#else
+static inline struct sh_dmae_slave_config *shdma_find_slave_of(struct sh_dmae_device *shdev, int match, int *index)
+{
+	return NULL;
+}
+#endif
+
 #endif	/* __DMA_SHDMA_H */
diff --git a/include/dt-bindings/dma/shdma.h b/include/dt-bindings/dma/shdma.h
new file mode 100644
index 0000000..0c8fc9e
--- /dev/null
+++ b/include/dt-bindings/dma/shdma.h
@@ -0,0 +1,45 @@
+/* DMA binding definitions for SH-DMAC engines.
+ *
+ * Moved from sh_dma.h to share with device tree by Ben Dooks.
+ * Orignal code from:
+ *   shdma.h: Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+ *   shdma-arm.h: Copyright (C) 2013 Renesas Electronics, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define SHDMA_DM_INC	0x00004000
+#define SHDMA_DM_DEC	0x00008000
+#define SHDMA_DM_FIX	0x0000c000
+#define SHDMA_SM_INC	0x00001000
+#define SHDMA_SM_DEC	0x00002000
+#define SHDMA_SM_FIX	0x00003000
+#define SHDMA_CHCR_DE	0x00000001
+#define SHDMA_CHCR_TE	0x00000002
+#define SHDMA_CHCR_IE	0x00000004
+
+/* ARM specific definitions */
+
+#define SHDMA_ARM_SZ_8BIT	(0)
+#define SHDMA_ARM_SZ_16BIT	(1)
+#define SHDMA_ARM_SZ_32BIT	(2)
+#define SHDMA_ARM_SZ_64BIT	(7)
+#define SHDMA_ARM_SZ_128BIT	(3)
+#define SHDMA_ARM_SZ_256BIT	(4)
+#define SHDMA_ARM_SZ_512BIT	(5)
+
+#define SHDMA_ARM_TS_LOW_BIT	(0x3)
+#define SHDMA_ARM_TS_HI_BIT	(0xc)
+
+#define SHDMA_ARM_TS_LOW_SHIFT	(3)
+#define SHDMA_ARM_TS_HI_SHIFT	(20 - 2)	/* 2 bits for shifted low TS */
+
+#define SHDMA_ARM_TS_INDEX2VAL(i) \
+	((((i) & SHDMA_ARM_TS_LOW_BIT) << SHDMA_ARM_TS_LOW_SHIFT) |\
+	 (((i) & SHDMA_ARM_TS_HI_BIT)  << SHDMA_ARM_TS_HI_SHIFT))
+
+#define SHDMA_ARM_CHCR_RX(size) (SHDMA_DM_INC | SHDMA_SM_FIX | 0x800 | SHDMA_ARM_TS_INDEX2VAL(size))
+#define SHDMA_ARM_CHCR_TX(size) (SHDMA_DM_FIX | SHDMA_SM_INC | 0x800 | SHDMA_ARM_TS_INDEX2VAL(size))
+
-- 
1.9.1

[PATCH v2 8/9] DMA: shdma: initial of common code

[Ben Dooks]

Add support for building shdma internal data from the device tree to allow
converting the driver to be device tree enabled.

It includes a helper for the of case to build the internal data used to
select and filter out the DMA channels from the ID information in the
device tree. Also updates the documentation for the DT case.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 Documentation/devicetree/bindings/dma/shdma.txt |  23 +++-
 drivers/dma/sh/shdma-of.c                       | 174 +++++++++++++++++++++++-
 drivers/dma/sh/shdma.h                          |  29 ++++
 include/dt-bindings/dma/shdma.h                 |  45 ++++++
 4 files changed, 268 insertions(+), 3 deletions(-)
 create mode 100644 include/dt-bindings/dma/shdma.h

diff --git a/Documentation/devicetree/bindings/dma/shdma.txt b/Documentation/devicetree/bindings/dma/shdma.txt
index 2a3f3b8..86d5c50 100644
--- a/Documentation/devicetree/bindings/dma/shdma.txt
+++ b/Documentation/devicetree/bindings/dma/shdma.txt
@@ -14,9 +14,9 @@ still has to be placed under such a multiplexer node.
 Required properties:
 - compatible:	should be "renesas,shdma-mux"
 - #dma-cells:	should be <1>, see "dmas" property below
+- dma-channels:	number of DMA channels
 
 Optional properties (currently unused):
-- dma-channels:	number of DMA channels
 - dma-requests:	number of DMA request signals
 
 * DMA controller
@@ -25,6 +25,7 @@ Required properties:
 - compatible:	should be of the form "renesas,shdma-<soc>", where <soc> should
 		be replaced with the desired SoC model, e.g.
 		"renesas,shdma-r8a73a4" for the system DMAC on r8a73a4 SoC
+		"renesas,shdma-r8a7790" for the DMAC on the R8A7790.
 
 Example:
 	dmac: dma-multiplexer@0 {
@@ -70,15 +71,33 @@ Example:
 		};
 	};
 
+For r8a7790 and newer implementations, the information for the channel
+controll register is found in the dma phandle and #dma-cells is set to 2.
+
+	dma0: dma-mux@0 {
+		compatible = "renesas,shdma-mux";
+		#dma-cells = <2>;
+		dma-channels = <20>;
+		dma-requests = <256>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+	}
+
 * DMA client
 
 Required properties:
 - dmas:		a list of <[DMA multiplexer phandle] [MID/RID value]> pairs,
 		where MID/RID values are fixed handles, specified in the SoC
-		manual
+		manual as the value that would be written into the DMASR.
+
+		If the #dma-cells is 2, then the second value is the CHCR
+		register configuration for the channel.
+
 - dma-names:	a list of DMA channel names, one per "dmas" entry
 
 Example:
 	dmas = <&dmac 0xd1
 		&dmac 0xd2>;
 	dma-names = "tx", "rx";
+
diff --git a/drivers/dma/sh/shdma-of.c b/drivers/dma/sh/shdma-of.c
index 06473a0..661ac77 100644
--- a/drivers/dma/sh/shdma-of.c
+++ b/drivers/dma/sh/shdma-of.c
@@ -3,12 +3,15 @@
  *
  * Copyright (C) 2013 Renesas Electronics Inc.
  * Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+ * Copyright (c) 2014 Codethink Limited
+ *	Ben Dooks <ben.dooks@codethink.co.uk>
  *
  * This is free software; you can redistribute it and/or modify
  * it under the terms of version 2 of the GNU General Public License as
  * published by the Free Software Foundation.
  */
 
+#include <linux/slab.h>
 #include <linux/dmaengine.h>
 #include <linux/module.h>
 #include <linux/of.h>
@@ -16,17 +19,117 @@
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
 #include <linux/shdma-base.h>
+#include <linux/sh_dma.h>
+
+#include <dt-bindings/dma/shdma.h>
 
 #define to_shdma_chan(c) container_of(c, struct shdma_chan, dma_chan)
 
+#include "shdma-arm.h"
+
+static const unsigned int arm_dma_ts_shift[] = SH_DMAE_TS_SHIFT;
+
+static struct sh_dmae_pdata arm_dmae_info = {
+	.ts_low_shift	= SHDMA_ARM_TS_LOW_SHIFT,
+	.ts_low_mask	= SHDMA_ARM_TS_LOW_BIT << SHDMA_ARM_TS_LOW_SHIFT,
+	.ts_high_shift	= SHDMA_ARM_TS_HI_SHIFT,
+	.ts_high_mask	= SHDMA_ARM_TS_HI_BIT << SHDMA_ARM_TS_HI_SHIFT,
+	.ts_shift	= arm_dma_ts_shift,
+	.ts_shift_num	= ARRAY_SIZE(arm_dma_ts_shift),
+	.dmaor_init	= DMAOR_DME,
+	.chclr_present	= 1,
+	.chclr_bitwise	= 1,
+};
+
+struct sh_dmae_of_info shdma_arm_info = {
+	.pdata_template	= &arm_dmae_info,
+	.channel_offset	= 0x8000-0x20,
+	.channel_stride	= 0x80,
+	.offset		= 0x0,
+	.dmars		= 0x40,
+	.chclr_offset	= 0x80,
+};
+
+/* Need global index due to shdma_slave_used being global */
+static atomic_t of_slave_index = ATOMIC_INIT(0);
+
+struct shdma_of_client {
+	int				index;
+	struct list_head		node;
+	struct sh_dmae_slave_config	cfg;
+};
+
+struct shdma_of_pdata {
+	struct sh_dmae_pdata	pdata;
+	struct shdma_of_state	*state;
+};
+
+struct shdma_of_state {
+	struct list_head	of_slaves;
+};
+
+#define to_of_pdata(_pd) container_of(_pd, struct shdma_of_pdata, pdata)
+
+struct shdma_of_client *shdma_of_find_client(struct shdma_of_state *state, int id)
+{
+	struct shdma_of_client *client;
+
+	list_for_each_entry(client, &state->of_slaves, node) {
+		if (client->cfg.slave_id == id)
+			return client;
+	}
+
+	return NULL;
+}
+
+struct sh_dmae_slave_config *
+shdma_find_slave_of(struct sh_dmae_device *shdev, int match, int *index)
+{
+	struct shdma_of_pdata *pdata = to_of_pdata(shdev->pdata);
+	struct sh_dmae_slave_config *cfg = NULL;
+	struct shdma_of_client *client;
+
+	pr_info("looking for %02x\n", match);
+
+	client = shdma_of_find_client(pdata->state, match);
+	if (client) {
+		*index = client->index;
+		cfg = &client->cfg;
+	}
+
+	return cfg;
+}
+
 static struct dma_chan *shdma_of_xlate(struct of_phandle_args *dma_spec,
 				       struct of_dma *ofdma)
 {
+	struct platform_device *pdev = ofdma->of_dma_data;
 	u32 id = dma_spec->args[0];
 	dma_cap_mask_t mask;
 	struct dma_chan *chan;
 
-	if (dma_spec->args_count != 1)
+	if (dma_spec->args_count == 2) {
+		struct shdma_of_state *state = platform_get_drvdata(pdev);
+		struct shdma_of_client *client;
+
+		client = shdma_of_find_client(state, id);
+		if (!client) {
+			client = devm_kzalloc(&pdev->dev, sizeof(*client),
+					      GFP_KERNEL);
+			if (!client)
+				return NULL;
+
+			client->index = atomic_inc_return(&of_slave_index);
+			client->cfg.slave_id = id;
+			client->cfg.mid_rid = id;
+			client->cfg.chcr = dma_spec->args[1];
+
+			dev_dbg(&pdev->dev, "new client %d, %02x\n",
+				client->index, id);
+
+			list_add_tail(&client->node, &state->of_slaves);
+		}
+	} else if (dma_spec->args_count != 1)
 		return NULL;
 
 	dma_cap_zero(mask);
@@ -40,11 +143,80 @@ static struct dma_chan *shdma_of_xlate(struct of_phandle_args *dma_spec,
 	return chan;
 }
 
+const struct sh_dmae_pdata *
+sh_dma_probe_of(struct platform_device *pdev, const struct of_device_id *ofmatch)
+{
+	const struct device_node *np = pdev->dev.of_node;
+	const struct sh_dmae_of_info *ofinf;
+	struct device *dev = &pdev->dev;
+	struct sh_dmae_pdata *pdata;
+	struct shdma_of_pdata *ofdata;
+	struct sh_dmae_channel *chan;
+	u32 nr_chan;
+	unsigned ch;
+	int ret;
+
+	if (!ofmatch)
+		return NULL;
+
+	ofdata = devm_kzalloc(dev, sizeof(struct shdma_of_pdata), GFP_KERNEL);
+	if (!ofdata)
+		return NULL;
+
+	ofinf = ofmatch->data;
+	pdata = &ofdata->pdata;
+	*pdata = *ofinf->pdata_template;	/* copy in template first */
+	ofdata->state = dev_get_drvdata(dev->parent);
+
+	ret = of_property_read_u32(np, "dma-channels", &nr_chan);
+	if (ret < 0) {
+		dev_err(dev, "failed to get number of channels\n");
+		return NULL;
+	}
+
+	chan = devm_kcalloc(dev, nr_chan, sizeof(struct sh_dmae_channel),
+			    GFP_KERNEL);
+	if (!chan) {
+		dev_err(dev, "cannot allocate %d channels\n", nr_chan);
+		return NULL;
+	}
+
+	pdata->channel = chan;
+	pdata->channel_num = nr_chan;
+
+	dev_dbg(dev, "%d dma channels allocated\n", nr_chan);
+
+	for (ch = 0; ch < nr_chan; ch++) {
+		struct sh_dmae_channel *cp = chan + ch;
+		u32 base = ofinf->channel_offset + ofinf->channel_stride * ch;
+
+		cp->offset = base + ofinf->offset;
+		cp->dmars = base + ofinf->dmars;
+		cp->chclr_bit = ch;
+		cp->chclr_offset = ofinf->chclr_offset;
+
+		dev_dbg(dev, "ch %d: off %08x, dmars %08x, bit %d, off %d\n",
+			ch, cp->offset, cp->dmars,
+			cp->chclr_bit, cp->chclr_offset);
+	}
+
+	pdev->dev.platform_data = pdata;
+	return pdata;
+};
+
 static int shdma_of_probe(struct platform_device *pdev)
 {
 	const struct of_dev_auxdata *lookup = dev_get_platdata(&pdev->dev);
+	struct shdma_of_state *state;
 	int ret;
 
+	state = devm_kzalloc(&pdev->dev, sizeof(*state), GFP_KERNEL);
+	if (!state)
+		return -ENOMEM;
+
+	INIT_LIST_HEAD(&state->of_slaves);
+	platform_set_drvdata(pdev, state);
+
 	ret = of_dma_controller_register(pdev->dev.of_node,
 					 shdma_of_xlate, pdev);
 	if (ret < 0)
diff --git a/drivers/dma/sh/shdma.h b/drivers/dma/sh/shdma.h
index 758a57b..05b84b9 100644
--- a/drivers/dma/sh/shdma.h
+++ b/drivers/dma/sh/shdma.h
@@ -56,6 +56,26 @@ struct sh_dmae_desc {
 	struct shdma_desc shdma_desc;
 };
 
+/*
+ * Template information for building shdma data, provided as part of the
+ * data field in the of_device_id structure. This is then used to build
+ * the platform data for the dma code.
+ */
+struct sh_dmae_of_info {
+	struct sh_dmae_pdata	*pdata_template;
+	unsigned int		channel_offset;
+	unsigned int		channel_stride;
+	int			offset;
+	int			dmars;
+	int			chclr_offset;
+	int			chclr_bit;
+};
+
+extern struct sh_dmae_of_info shdma_arm_info;
+
+extern const struct sh_dmae_pdata *sh_dma_probe_of(struct platform_device *pdev,
+						   const struct of_device_id *match);
+
 #define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, shdma_chan)
 #define to_sh_desc(lh) container_of(lh, struct sh_desc, node)
 #define tx_to_sh_desc(tx) container_of(tx, struct sh_desc, async_tx)
@@ -69,4 +89,13 @@ extern const struct sh_dmae_pdata r8a73a4_dma_pdata;
 #define r8a73a4_shdma_devid NULL
 #endif
 
+#ifdef CONFIG_OF
+extern struct sh_dmae_slave_config *shdma_find_slave_of(struct sh_dmae_device *shdev, int match, int *index);
+#else
+static inline struct sh_dmae_slave_config *shdma_find_slave_of(struct sh_dmae_device *shdev, int match, int *index)
+{
+	return NULL;
+}
+#endif
+
 #endif	/* __DMA_SHDMA_H */
diff --git a/include/dt-bindings/dma/shdma.h b/include/dt-bindings/dma/shdma.h
new file mode 100644
index 0000000..0c8fc9e
--- /dev/null
+++ b/include/dt-bindings/dma/shdma.h
@@ -0,0 +1,45 @@
+/* DMA binding definitions for SH-DMAC engines.
+ *
+ * Moved from sh_dma.h to share with device tree by Ben Dooks.
+ * Orignal code from:
+ *   shdma.h: Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+ *   shdma-arm.h: Copyright (C) 2013 Renesas Electronics, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define SHDMA_DM_INC	0x00004000
+#define SHDMA_DM_DEC	0x00008000
+#define SHDMA_DM_FIX	0x0000c000
+#define SHDMA_SM_INC	0x00001000
+#define SHDMA_SM_DEC	0x00002000
+#define SHDMA_SM_FIX	0x00003000
+#define SHDMA_CHCR_DE	0x00000001
+#define SHDMA_CHCR_TE	0x00000002
+#define SHDMA_CHCR_IE	0x00000004
+
+/* ARM specific definitions */
+
+#define SHDMA_ARM_SZ_8BIT	(0)
+#define SHDMA_ARM_SZ_16BIT	(1)
+#define SHDMA_ARM_SZ_32BIT	(2)
+#define SHDMA_ARM_SZ_64BIT	(7)
+#define SHDMA_ARM_SZ_128BIT	(3)
+#define SHDMA_ARM_SZ_256BIT	(4)
+#define SHDMA_ARM_SZ_512BIT	(5)
+
+#define SHDMA_ARM_TS_LOW_BIT	(0x3)
+#define SHDMA_ARM_TS_HI_BIT	(0xc)
+
+#define SHDMA_ARM_TS_LOW_SHIFT	(3)
+#define SHDMA_ARM_TS_HI_SHIFT	(20 - 2)	/* 2 bits for shifted low TS */
+
+#define SHDMA_ARM_TS_INDEX2VAL(i) \
+	((((i) & SHDMA_ARM_TS_LOW_BIT) << SHDMA_ARM_TS_LOW_SHIFT) |\
+	 (((i) & SHDMA_ARM_TS_HI_BIT)  << SHDMA_ARM_TS_HI_SHIFT))
+
+#define SHDMA_ARM_CHCR_RX(size) (SHDMA_DM_INC | SHDMA_SM_FIX | 0x800 | SHDMA_ARM_TS_INDEX2VAL(size))
+#define SHDMA_ARM_CHCR_TX(size) (SHDMA_DM_FIX | SHDMA_SM_INC | 0x800 | SHDMA_ARM_TS_INDEX2VAL(size))
+
-- 
1.9.1

Re: [PATCH v2 8/9] DMA: shdma: initial of common code

[Arnd Bergmann]

On Monday 14 April 2014 22:35:11 Ben Dooks wrote:
> Add support for building shdma internal data from the device tree to allow
> converting the driver to be device tree enabled.
> 
> It includes a helper for the of case to build the internal data used to
> select and filter out the DMA channels from the ID information in the
> device tree. Also updates the documentation for the DT case.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>

I think you should try to explain better here why you need all the logic
that other drivers don't for the DT case. 

I've tried to understand what you are doing with shdma_of_client and
couldn't quite figure it out. The driver is already different from
all the others, because it still uses the 'slave_id' field in
dma_slave_config (only for the non-DT case) that all other drivers
don't use at all.

My guess is that if you manage to clean that up first, all of this
wouldn't be necessary.

>  static struct dma_chan *shdma_of_xlate(struct of_phandle_args *dma_spec,
>  				       struct of_dma *ofdma)
>  {
> +	struct platform_device *pdev = ofdma->of_dma_data;
>  	u32 id = dma_spec->args[0];
>  	dma_cap_mask_t mask;
>  	struct dma_chan *chan;
>  
> -	if (dma_spec->args_count != 1)
> +	if (dma_spec->args_count = 2) {
> +		struct shdma_of_state *state = platform_get_drvdata(pdev);
> +		struct shdma_of_client *client;
> +
> +		client = shdma_of_find_client(state, id);
> +		if (!client) {
> +			client = devm_kzalloc(&pdev->dev, sizeof(*client),
> +					      GFP_KERNEL);
> +			if (!client)
> +				return NULL;
> +
> +			client->index = atomic_inc_return(&of_slave_index);
> +			client->cfg.slave_id = id;
> +			client->cfg.mid_rid = id;
> +			client->cfg.chcr = dma_spec->args[1];

Can you explain the purpose of setting the chcr in DT? For all I can
tell, this should come from the device driver when that calls the
dma_slave_config function, unlike the mid_rid value.

	Arnd

Re: [PATCH v2 8/9] DMA: shdma: initial of common code

[Arnd Bergmann]

On Monday 14 April 2014 22:35:11 Ben Dooks wrote:
> Add support for building shdma internal data from the device tree to allow
> converting the driver to be device tree enabled.
> 
> It includes a helper for the of case to build the internal data used to
> select and filter out the DMA channels from the ID information in the
> device tree. Also updates the documentation for the DT case.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>

I think you should try to explain better here why you need all the logic
that other drivers don't for the DT case. 

I've tried to understand what you are doing with shdma_of_client and
couldn't quite figure it out. The driver is already different from
all the others, because it still uses the 'slave_id' field in
dma_slave_config (only for the non-DT case) that all other drivers
don't use at all.

My guess is that if you manage to clean that up first, all of this
wouldn't be necessary.

>  static struct dma_chan *shdma_of_xlate(struct of_phandle_args *dma_spec,
>  				       struct of_dma *ofdma)
>  {
> +	struct platform_device *pdev = ofdma->of_dma_data;
>  	u32 id = dma_spec->args[0];
>  	dma_cap_mask_t mask;
>  	struct dma_chan *chan;
>  
> -	if (dma_spec->args_count != 1)
> +	if (dma_spec->args_count == 2) {
> +		struct shdma_of_state *state = platform_get_drvdata(pdev);
> +		struct shdma_of_client *client;
> +
> +		client = shdma_of_find_client(state, id);
> +		if (!client) {
> +			client = devm_kzalloc(&pdev->dev, sizeof(*client),
> +					      GFP_KERNEL);
> +			if (!client)
> +				return NULL;
> +
> +			client->index = atomic_inc_return(&of_slave_index);
> +			client->cfg.slave_id = id;
> +			client->cfg.mid_rid = id;
> +			client->cfg.chcr = dma_spec->args[1];

Can you explain the purpose of setting the chcr in DT? For all I can
tell, this should come from the device driver when that calls the
dma_slave_config function, unlike the mid_rid value.

	Arnd

Re: [PATCH v2 8/9] DMA: shdma: initial of common code

[Ben Dooks]

On 14/04/14 23:06, Arnd Bergmann wrote:
> On Monday 14 April 2014 22:35:11 Ben Dooks wrote:
>> Add support for building shdma internal data from the device tree to allow
>> converting the driver to be device tree enabled.
>>
>> It includes a helper for the of case to build the internal data used to
>> select and filter out the DMA channels from the ID information in the
>> device tree. Also updates the documentation for the DT case.
>>
>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>
> I think you should try to explain better here why you need all the logic
> that other drivers don't for the DT case.
>
> I've tried to understand what you are doing with shdma_of_client and
> couldn't quite figure it out. The driver is already different from
> all the others, because it still uses the 'slave_id' field in
> dma_slave_config (only for the non-DT case) that all other drivers
> don't use at all.
>
> My guess is that if you manage to clean that up first, all of this
> wouldn't be necessary.

Does anyone else have comments on this from a Renesas perspective? We
can uniquely identify a channel on a single DMAC using the MID/RID mux
control value.

If we can unify the slave-id and the MID/RID values then the driver is
simpler and we can drop part of the update and make the entire SHDMA
system simpler.

>>   static struct dma_chan *shdma_of_xlate(struct of_phandle_args *dma_spec,
>>   				       struct of_dma *ofdma)
>>   {
>> +	struct platform_device *pdev = ofdma->of_dma_data;
>>   	u32 id = dma_spec->args[0];
>>   	dma_cap_mask_t mask;
>>   	struct dma_chan *chan;
>>
>> -	if (dma_spec->args_count != 1)
>> +	if (dma_spec->args_count = 2) {
>> +		struct shdma_of_state *state = platform_get_drvdata(pdev);
>> +		struct shdma_of_client *client;
>> +
>> +		client = shdma_of_find_client(state, id);
>> +		if (!client) {
>> +			client = devm_kzalloc(&pdev->dev, sizeof(*client),
>> +					      GFP_KERNEL);
>> +			if (!client)
>> +				return NULL;
>> +
>> +			client->index = atomic_inc_return(&of_slave_index);
>> +			client->cfg.slave_id = id;
>> +			client->cfg.mid_rid = id;
>> +			client->cfg.chcr = dma_spec->args[1];
>
> Can you explain the purpose of setting the chcr in DT? For all I can
> tell, this should come from the device driver when that calls the
> dma_slave_config function, unlike the mid_rid value.

See previous note about transfer-widths and register-sizes not always
matching. I also do not have any idea about other SoCs in the series
if there are any differences between channel settings.

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

Re: [PATCH v2 8/9] DMA: shdma: initial of common code

[Ben Dooks]

On 14/04/14 23:06, Arnd Bergmann wrote:
> On Monday 14 April 2014 22:35:11 Ben Dooks wrote:
>> Add support for building shdma internal data from the device tree to allow
>> converting the driver to be device tree enabled.
>>
>> It includes a helper for the of case to build the internal data used to
>> select and filter out the DMA channels from the ID information in the
>> device tree. Also updates the documentation for the DT case.
>>
>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>
> I think you should try to explain better here why you need all the logic
> that other drivers don't for the DT case.
>
> I've tried to understand what you are doing with shdma_of_client and
> couldn't quite figure it out. The driver is already different from
> all the others, because it still uses the 'slave_id' field in
> dma_slave_config (only for the non-DT case) that all other drivers
> don't use at all.
>
> My guess is that if you manage to clean that up first, all of this
> wouldn't be necessary.

Does anyone else have comments on this from a Renesas perspective? We
can uniquely identify a channel on a single DMAC using the MID/RID mux
control value.

If we can unify the slave-id and the MID/RID values then the driver is
simpler and we can drop part of the update and make the entire SHDMA
system simpler.

>>   static struct dma_chan *shdma_of_xlate(struct of_phandle_args *dma_spec,
>>   				       struct of_dma *ofdma)
>>   {
>> +	struct platform_device *pdev = ofdma->of_dma_data;
>>   	u32 id = dma_spec->args[0];
>>   	dma_cap_mask_t mask;
>>   	struct dma_chan *chan;
>>
>> -	if (dma_spec->args_count != 1)
>> +	if (dma_spec->args_count == 2) {
>> +		struct shdma_of_state *state = platform_get_drvdata(pdev);
>> +		struct shdma_of_client *client;
>> +
>> +		client = shdma_of_find_client(state, id);
>> +		if (!client) {
>> +			client = devm_kzalloc(&pdev->dev, sizeof(*client),
>> +					      GFP_KERNEL);
>> +			if (!client)
>> +				return NULL;
>> +
>> +			client->index = atomic_inc_return(&of_slave_index);
>> +			client->cfg.slave_id = id;
>> +			client->cfg.mid_rid = id;
>> +			client->cfg.chcr = dma_spec->args[1];
>
> Can you explain the purpose of setting the chcr in DT? For all I can
> tell, this should come from the device driver when that calls the
> dma_slave_config function, unlike the mid_rid value.

See previous note about transfer-widths and register-sizes not always
matching. I also do not have any idea about other SoCs in the series
if there are any differences between channel settings.

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

Re: [PATCH v2 8/9] DMA: shdma: initial of common code

[Geert Uytterhoeven]

Hi Ben,

On Tue, Apr 15, 2014 at 11:54 AM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
>>>   static struct dma_chan *shdma_of_xlate(struct of_phandle_args
>>> *dma_spec,
>>>                                        struct of_dma *ofdma)
>>>   {
>>> +       struct platform_device *pdev = ofdma->of_dma_data;
>>>         u32 id = dma_spec->args[0];
>>>         dma_cap_mask_t mask;
>>>         struct dma_chan *chan;
>>>
>>> -       if (dma_spec->args_count != 1)
>>> +       if (dma_spec->args_count = 2) {
>>> +               struct shdma_of_state *state >>> platform_get_drvdata(pdev);
>>> +               struct shdma_of_client *client;
>>> +
>>> +               client = shdma_of_find_client(state, id);
>>> +               if (!client) {
>>> +                       client = devm_kzalloc(&pdev->dev,
>>> sizeof(*client),
>>> +                                             GFP_KERNEL);
>>> +                       if (!client)
>>> +                               return NULL;
>>> +
>>> +                       client->index >>> atomic_inc_return(&of_slave_index);
>>> +                       client->cfg.slave_id = id;
>>> +                       client->cfg.mid_rid = id;
>>> +                       client->cfg.chcr = dma_spec->args[1];
>>
>>
>> Can you explain the purpose of setting the chcr in DT? For all I can
>> tell, this should come from the device driver when that calls the
>> dma_slave_config function, unlike the mid_rid value.
>
>
> See previous note about transfer-widths and register-sizes not always
> matching. I also do not have any idea about other SoCs in the series
> if there are any differences between channel settings.

If you look for sh_dmae_slave_config in arch/arm arch/sh, you find the values
for the existing board support.

The same device always seem to use the same value, i.e. MMC always uses
32-bit, SCIF uses 8-bit, SDHI uses 16-bit. So I think it could be hardcoded
in the device driver (passed via enum dma_slave_buswidth {src,dst}_addr_width
in dma_slave_config?), and you can drop the field in the bindings.

Notes:
  - RSPI is special: on SH, it's 16-bit, while QSPI on R-Car uses 8-bit.
  - SDHI uses 32-bit according to the R-Car docs, but the (working) code
    uses 16-bit?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 8/9] DMA: shdma: initial of common code

[Geert Uytterhoeven]

Hi Ben,

On Tue, Apr 15, 2014 at 11:54 AM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
>>>   static struct dma_chan *shdma_of_xlate(struct of_phandle_args
>>> *dma_spec,
>>>                                        struct of_dma *ofdma)
>>>   {
>>> +       struct platform_device *pdev = ofdma->of_dma_data;
>>>         u32 id = dma_spec->args[0];
>>>         dma_cap_mask_t mask;
>>>         struct dma_chan *chan;
>>>
>>> -       if (dma_spec->args_count != 1)
>>> +       if (dma_spec->args_count == 2) {
>>> +               struct shdma_of_state *state =
>>> platform_get_drvdata(pdev);
>>> +               struct shdma_of_client *client;
>>> +
>>> +               client = shdma_of_find_client(state, id);
>>> +               if (!client) {
>>> +                       client = devm_kzalloc(&pdev->dev,
>>> sizeof(*client),
>>> +                                             GFP_KERNEL);
>>> +                       if (!client)
>>> +                               return NULL;
>>> +
>>> +                       client->index =
>>> atomic_inc_return(&of_slave_index);
>>> +                       client->cfg.slave_id = id;
>>> +                       client->cfg.mid_rid = id;
>>> +                       client->cfg.chcr = dma_spec->args[1];
>>
>>
>> Can you explain the purpose of setting the chcr in DT? For all I can
>> tell, this should come from the device driver when that calls the
>> dma_slave_config function, unlike the mid_rid value.
>
>
> See previous note about transfer-widths and register-sizes not always
> matching. I also do not have any idea about other SoCs in the series
> if there are any differences between channel settings.

If you look for sh_dmae_slave_config in arch/arm arch/sh, you find the values
for the existing board support.

The same device always seem to use the same value, i.e. MMC always uses
32-bit, SCIF uses 8-bit, SDHI uses 16-bit. So I think it could be hardcoded
in the device driver (passed via enum dma_slave_buswidth {src,dst}_addr_width
in dma_slave_config?), and you can drop the field in the bindings.

Notes:
  - RSPI is special: on SH, it's 16-bit, while QSPI on R-Car uses 8-bit.
  - SDHI uses 32-bit according to the R-Car docs, but the (working) code
    uses 16-bit?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 8/9] DMA: shdma: initial of common code

[Ben Dooks]

On 21/05/14 21:14, Geert Uytterhoeven wrote:
> Hi Ben,
> 
> On Tue, Apr 15, 2014 at 11:54 AM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
>>>>   static struct dma_chan *shdma_of_xlate(struct of_phandle_args
>>>> *dma_spec,
>>>>                                        struct of_dma *ofdma)
>>>>   {
>>>> +       struct platform_device *pdev = ofdma->of_dma_data;
>>>>         u32 id = dma_spec->args[0];
>>>>         dma_cap_mask_t mask;
>>>>         struct dma_chan *chan;
>>>>
>>>> -       if (dma_spec->args_count != 1)
>>>> +       if (dma_spec->args_count = 2) {
>>>> +               struct shdma_of_state *state >>>> platform_get_drvdata(pdev);
>>>> +               struct shdma_of_client *client;
>>>> +
>>>> +               client = shdma_of_find_client(state, id);
>>>> +               if (!client) {
>>>> +                       client = devm_kzalloc(&pdev->dev,
>>>> sizeof(*client),
>>>> +                                             GFP_KERNEL);
>>>> +                       if (!client)
>>>> +                               return NULL;
>>>> +
>>>> +                       client->index >>>> atomic_inc_return(&of_slave_index);
>>>> +                       client->cfg.slave_id = id;
>>>> +                       client->cfg.mid_rid = id;
>>>> +                       client->cfg.chcr = dma_spec->args[1];
>>>
>>>
>>> Can you explain the purpose of setting the chcr in DT? For all I can
>>> tell, this should come from the device driver when that calls the
>>> dma_slave_config function, unlike the mid_rid value.
>>
>>
>> See previous note about transfer-widths and register-sizes not always
>> matching. I also do not have any idea about other SoCs in the series
>> if there are any differences between channel settings.
> 
> If you look for sh_dmae_slave_config in arch/arm arch/sh, you find the values
> for the existing board support.
> 
> The same device always seem to use the same value, i.e. MMC always uses
> 32-bit, SCIF uses 8-bit, SDHI uses 16-bit. So I think it could be hardcoded
> in the device driver (passed via enum dma_slave_buswidth {src,dst}_addr_width
> in dma_slave_config?), and you can drop the field in the bindings.
> 
> Notes:
>   - RSPI is special: on SH, it's 16-bit, while QSPI on R-Car uses 8-bit.
>   - SDHI uses 32-bit according to the R-Car docs, but the (working) code
>     uses 16-bit?

I will move to using the configuration passed when the slave is used
instead of the one in the slave table.

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

Re: [PATCH v2 8/9] DMA: shdma: initial of common code

[Ben Dooks]

On 21/05/14 21:14, Geert Uytterhoeven wrote:
> Hi Ben,
> 
> On Tue, Apr 15, 2014 at 11:54 AM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
>>>>   static struct dma_chan *shdma_of_xlate(struct of_phandle_args
>>>> *dma_spec,
>>>>                                        struct of_dma *ofdma)
>>>>   {
>>>> +       struct platform_device *pdev = ofdma->of_dma_data;
>>>>         u32 id = dma_spec->args[0];
>>>>         dma_cap_mask_t mask;
>>>>         struct dma_chan *chan;
>>>>
>>>> -       if (dma_spec->args_count != 1)
>>>> +       if (dma_spec->args_count == 2) {
>>>> +               struct shdma_of_state *state =
>>>> platform_get_drvdata(pdev);
>>>> +               struct shdma_of_client *client;
>>>> +
>>>> +               client = shdma_of_find_client(state, id);
>>>> +               if (!client) {
>>>> +                       client = devm_kzalloc(&pdev->dev,
>>>> sizeof(*client),
>>>> +                                             GFP_KERNEL);
>>>> +                       if (!client)
>>>> +                               return NULL;
>>>> +
>>>> +                       client->index =
>>>> atomic_inc_return(&of_slave_index);
>>>> +                       client->cfg.slave_id = id;
>>>> +                       client->cfg.mid_rid = id;
>>>> +                       client->cfg.chcr = dma_spec->args[1];
>>>
>>>
>>> Can you explain the purpose of setting the chcr in DT? For all I can
>>> tell, this should come from the device driver when that calls the
>>> dma_slave_config function, unlike the mid_rid value.
>>
>>
>> See previous note about transfer-widths and register-sizes not always
>> matching. I also do not have any idea about other SoCs in the series
>> if there are any differences between channel settings.
> 
> If you look for sh_dmae_slave_config in arch/arm arch/sh, you find the values
> for the existing board support.
> 
> The same device always seem to use the same value, i.e. MMC always uses
> 32-bit, SCIF uses 8-bit, SDHI uses 16-bit. So I think it could be hardcoded
> in the device driver (passed via enum dma_slave_buswidth {src,dst}_addr_width
> in dma_slave_config?), and you can drop the field in the bindings.
> 
> Notes:
>   - RSPI is special: on SH, it's 16-bit, while QSPI on R-Car uses 8-bit.
>   - SDHI uses 32-bit according to the R-Car docs, but the (working) code
>     uses 16-bit?

I will move to using the configuration passed when the slave is used
instead of the one in the slave table.

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

[PATCH v2 9/9] DMA: shdma: wire r8a7790

[Ben Dooks]

Add support for R8A7790 with new device tree code.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 drivers/dma/sh/shdmac.c | 32 +++++++++++++++++++++++++-------
 1 file changed, 25 insertions(+), 7 deletions(-)

diff --git a/drivers/dma/sh/shdmac.c b/drivers/dma/sh/shdmac.c
index 0d765c0..eb57cf2 100644
--- a/drivers/dma/sh/shdmac.c
+++ b/drivers/dma/sh/shdmac.c
@@ -342,11 +342,21 @@ static const struct sh_dmae_slave_config *dmae_find_slave(
 			if (cfg->slave_id = match)
 				return cfg;
 	} else {
-		for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++)
-			if (cfg->mid_rid = match) {
+		if (!pdata->slave) {
+			cfg = shdma_find_slave_of(shdev, match, &i);
+			if (cfg) {
 				sh_chan->shdma_chan.slave_id = i;
 				return cfg;
 			}
+
+			return NULL;
+		} else
+			for (i = 0, cfg = pdata->slave; i < pdata->slave_num;
+			     i++, cfg++)
+				if (cfg->mid_rid = match) {
+					sh_chan->shdma_chan.slave_id = i;
+					return cfg;
+				}
 	}
 
 	return NULL;
@@ -677,7 +687,8 @@ static const struct shdma_ops sh_dmae_shdma_ops = {
 };
 
 static const struct of_device_id sh_dmae_of_match[] = {
-	{.compatible = "renesas,shdma-r8a73a4", .data = r8a73a4_shdma_devid,},
+	{ .compatible = "renesas,shdma-r8a73a4", .data = r8a73a4_shdma_devid },
+	{ .compatible = "renesas,dma-r8a7790", .data = &shdma_arm_info },
 	{}
 };
 MODULE_DEVICE_TABLE(of, sh_dmae_of_match);
@@ -693,10 +704,17 @@ static int sh_dmae_probe(struct platform_device *pdev)
 	struct dma_device *dma_dev;
 	struct resource *chan, *dmars, *errirq_res, *chanirq_res;
 
-	if (pdev->dev.of_node)
-		pdata = of_match_device(sh_dmae_of_match, &pdev->dev)->data;
-	else
+	if (pdev->dev.of_node) {
+		const struct of_device_id *match;
+
+		match = of_match_device(sh_dmae_of_match, &pdev->dev);
+		if (match->data = r8a73a4_shdma_devid)
+			pdata = match->data;
+		else
+			pdata = sh_dma_probe_of(pdev, match);
+	} else {
 		pdata = dev_get_platdata(&pdev->dev);
+	}
 
 	/* get platform data */
 	if (!pdata || !pdata->channel_num)
@@ -745,7 +763,7 @@ static int sh_dmae_probe(struct platform_device *pdev)
 
 	if (!pdata->slave_only)
 		dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
-	if (pdata->slave && pdata->slave_num)
+	if ((pdata->slave && pdata->slave_num) || pdev->dev.of_node)
 		dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
 
 	/* Default transfer size of 32 bytes requires 32-byte alignment */
-- 
1.9.1

[PATCH v2 9/9] DMA: shdma: wire r8a7790

[Ben Dooks]

Add support for R8A7790 with new device tree code.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 drivers/dma/sh/shdmac.c | 32 +++++++++++++++++++++++++-------
 1 file changed, 25 insertions(+), 7 deletions(-)

diff --git a/drivers/dma/sh/shdmac.c b/drivers/dma/sh/shdmac.c
index 0d765c0..eb57cf2 100644
--- a/drivers/dma/sh/shdmac.c
+++ b/drivers/dma/sh/shdmac.c
@@ -342,11 +342,21 @@ static const struct sh_dmae_slave_config *dmae_find_slave(
 			if (cfg->slave_id == match)
 				return cfg;
 	} else {
-		for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++)
-			if (cfg->mid_rid == match) {
+		if (!pdata->slave) {
+			cfg = shdma_find_slave_of(shdev, match, &i);
+			if (cfg) {
 				sh_chan->shdma_chan.slave_id = i;
 				return cfg;
 			}
+
+			return NULL;
+		} else
+			for (i = 0, cfg = pdata->slave; i < pdata->slave_num;
+			     i++, cfg++)
+				if (cfg->mid_rid == match) {
+					sh_chan->shdma_chan.slave_id = i;
+					return cfg;
+				}
 	}
 
 	return NULL;
@@ -677,7 +687,8 @@ static const struct shdma_ops sh_dmae_shdma_ops = {
 };
 
 static const struct of_device_id sh_dmae_of_match[] = {
-	{.compatible = "renesas,shdma-r8a73a4", .data = r8a73a4_shdma_devid,},
+	{ .compatible = "renesas,shdma-r8a73a4", .data = r8a73a4_shdma_devid },
+	{ .compatible = "renesas,dma-r8a7790", .data = &shdma_arm_info },
 	{}
 };
 MODULE_DEVICE_TABLE(of, sh_dmae_of_match);
@@ -693,10 +704,17 @@ static int sh_dmae_probe(struct platform_device *pdev)
 	struct dma_device *dma_dev;
 	struct resource *chan, *dmars, *errirq_res, *chanirq_res;
 
-	if (pdev->dev.of_node)
-		pdata = of_match_device(sh_dmae_of_match, &pdev->dev)->data;
-	else
+	if (pdev->dev.of_node) {
+		const struct of_device_id *match;
+
+		match = of_match_device(sh_dmae_of_match, &pdev->dev);
+		if (match->data == r8a73a4_shdma_devid)
+			pdata = match->data;
+		else
+			pdata = sh_dma_probe_of(pdev, match);
+	} else {
 		pdata = dev_get_platdata(&pdev->dev);
+	}
 
 	/* get platform data */
 	if (!pdata || !pdata->channel_num)
@@ -745,7 +763,7 @@ static int sh_dmae_probe(struct platform_device *pdev)
 
 	if (!pdata->slave_only)
 		dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
-	if (pdata->slave && pdata->slave_num)
+	if ((pdata->slave && pdata->slave_num) || pdev->dev.of_node)
 		dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
 
 	/* Default transfer size of 32 bytes requires 32-byte alignment */
-- 
1.9.1

Re: [PATCH v2 9/9] DMA: shdma: wire r8a7790

[Sergei Shtylyov]

Hello.

On 15-04-2014 1:35, Ben Dooks wrote:

> Add support for R8A7790 with new device tree code.

> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> ---
>   drivers/dma/sh/shdmac.c | 32 +++++++++++++++++++++++++-------
>   1 file changed, 25 insertions(+), 7 deletions(-)

> diff --git a/drivers/dma/sh/shdmac.c b/drivers/dma/sh/shdmac.c
> index 0d765c0..eb57cf2 100644
> --- a/drivers/dma/sh/shdmac.c
> +++ b/drivers/dma/sh/shdmac.c
> @@ -342,11 +342,21 @@ static const struct sh_dmae_slave_config *dmae_find_slave(
>   			if (cfg->slave_id = match)
>   				return cfg;
>   	} else {
> -		for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++)
> -			if (cfg->mid_rid = match) {
> +		if (!pdata->slave) {
> +			cfg = shdma_find_slave_of(shdev, match, &i);
> +			if (cfg) {
>   				sh_chan->shdma_chan.slave_id = i;
>   				return cfg;
>   			}
> +
> +			return NULL;
> +		} else

    All arms of the *if* statement should have {} if at least one arm has {}.

> +			for (i = 0, cfg = pdata->slave; i < pdata->slave_num;
> +			     i++, cfg++)
> +				if (cfg->mid_rid = match) {
> +					sh_chan->shdma_chan.slave_id = i;
> +					return cfg;
> +				}
>   	}
>
>   	return NULL;

WBR, Sergei

Re: [PATCH v2 9/9] DMA: shdma: wire r8a7790

[Sergei Shtylyov]

Hello.

On 15-04-2014 1:35, Ben Dooks wrote:

> Add support for R8A7790 with new device tree code.

> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> ---
>   drivers/dma/sh/shdmac.c | 32 +++++++++++++++++++++++++-------
>   1 file changed, 25 insertions(+), 7 deletions(-)

> diff --git a/drivers/dma/sh/shdmac.c b/drivers/dma/sh/shdmac.c
> index 0d765c0..eb57cf2 100644
> --- a/drivers/dma/sh/shdmac.c
> +++ b/drivers/dma/sh/shdmac.c
> @@ -342,11 +342,21 @@ static const struct sh_dmae_slave_config *dmae_find_slave(
>   			if (cfg->slave_id == match)
>   				return cfg;
>   	} else {
> -		for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++)
> -			if (cfg->mid_rid == match) {
> +		if (!pdata->slave) {
> +			cfg = shdma_find_slave_of(shdev, match, &i);
> +			if (cfg) {
>   				sh_chan->shdma_chan.slave_id = i;
>   				return cfg;
>   			}
> +
> +			return NULL;
> +		} else

    All arms of the *if* statement should have {} if at least one arm has {}.

> +			for (i = 0, cfg = pdata->slave; i < pdata->slave_num;
> +			     i++, cfg++)
> +				if (cfg->mid_rid == match) {
> +					sh_chan->shdma_chan.slave_id = i;
> +					return cfg;
> +				}
>   	}
>
>   	return NULL;

WBR, Sergei

Re: [PATCH v2 9/9] DMA: shdma: wire r8a7790

[Kuninori Morimoto]

Hi Ben

Thank you for your patch

> Add support for R8A7790 with new device tree code.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> ---
(snip)
>  static const struct of_device_id sh_dmae_of_match[] = {
> -	{.compatible = "renesas,shdma-r8a73a4", .data = r8a73a4_shdma_devid,},
> +	{ .compatible = "renesas,shdma-r8a73a4", .data = r8a73a4_shdma_devid },
> +	{ .compatible = "renesas,dma-r8a7790", .data = &shdma_arm_info },
>  	{}
>  };

Here, new compatible name is "renesas,dma-r8a7790"
                                      ~~~

> +		sysdma0: dma-controller@e6700000 {
> +			compatible = "renesas,shdma-r8a7790";
..
> +		sysdma1: dma-controller@e6720000 {
> +			compatible = "renesas,shdma-r8a7790";

your [PATCH v2 3/9] ARM: shmobile: r8a7790: add dmac0 dmac1 nodes
is using "renesas,shdma-r8a7790"
                  ~~~~~

Is it miss/typo ?

Re: [PATCH v2 9/9] DMA: shdma: wire r8a7790

[Kuninori Morimoto]

Hi Ben

Thank you for your patch

> Add support for R8A7790 with new device tree code.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> ---
(snip)
>  static const struct of_device_id sh_dmae_of_match[] = {
> -	{.compatible = "renesas,shdma-r8a73a4", .data = r8a73a4_shdma_devid,},
> +	{ .compatible = "renesas,shdma-r8a73a4", .data = r8a73a4_shdma_devid },
> +	{ .compatible = "renesas,dma-r8a7790", .data = &shdma_arm_info },
>  	{}
>  };

Here, new compatible name is "renesas,dma-r8a7790"
                                      ~~~

> +		sysdma0: dma-controller@e6700000 {
> +			compatible = "renesas,shdma-r8a7790";
..
> +		sysdma1: dma-controller@e6720000 {
> +			compatible = "renesas,shdma-r8a7790";

your [PATCH v2 3/9] ARM: shmobile: r8a7790: add dmac0 dmac1 nodes
is using "renesas,shdma-r8a7790"
                  ~~~~~

Is it miss/typo ?

Re: [PATCH v2 9/9] DMA: shdma: wire r8a7790

[Ben Dooks]

On 18/04/14 02:32, Kuninori Morimoto wrote:
>
> Hi Ben
>
> Thank you for your patch
>
>> Add support for R8A7790 with new device tree code.
>>
>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>> ---
> (snip)
>>   static const struct of_device_id sh_dmae_of_match[] = {
>> -	{.compatible = "renesas,shdma-r8a73a4", .data = r8a73a4_shdma_devid,},
>> +	{ .compatible = "renesas,shdma-r8a73a4", .data = r8a73a4_shdma_devid },
>> +	{ .compatible = "renesas,dma-r8a7790", .data = &shdma_arm_info },
>>   	{}
>>   };
>
> Here, new compatible name is "renesas,dma-r8a7790"
>                                        ~~~
>
>> +		sysdma0: dma-controller@e6700000 {
>> +			compatible = "renesas,shdma-r8a7790";
> ..
>> +		sysdma1: dma-controller@e6720000 {
>> +			compatible = "renesas,shdma-r8a7790";
>
> your [PATCH v2 3/9] ARM: shmobile: r8a7790: add dmac0 dmac1 nodes
> is using "renesas,shdma-r8a7790"
>                    ~~~~~
>
> Is it miss/typo ?

I think it is a missed rebase, I will be away until next week
so will check this out when I get back.


-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

Re: [PATCH v2 9/9] DMA: shdma: wire r8a7790

[Ben Dooks]

On 18/04/14 02:32, Kuninori Morimoto wrote:
>
> Hi Ben
>
> Thank you for your patch
>
>> Add support for R8A7790 with new device tree code.
>>
>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>> ---
> (snip)
>>   static const struct of_device_id sh_dmae_of_match[] = {
>> -	{.compatible = "renesas,shdma-r8a73a4", .data = r8a73a4_shdma_devid,},
>> +	{ .compatible = "renesas,shdma-r8a73a4", .data = r8a73a4_shdma_devid },
>> +	{ .compatible = "renesas,dma-r8a7790", .data = &shdma_arm_info },
>>   	{}
>>   };
>
> Here, new compatible name is "renesas,dma-r8a7790"
>                                        ~~~
>
>> +		sysdma0: dma-controller@e6700000 {
>> +			compatible = "renesas,shdma-r8a7790";
> ..
>> +		sysdma1: dma-controller@e6720000 {
>> +			compatible = "renesas,shdma-r8a7790";
>
> your [PATCH v2 3/9] ARM: shmobile: r8a7790: add dmac0 dmac1 nodes
> is using "renesas,shdma-r8a7790"
>                    ~~~~~
>
> Is it miss/typo ?

I think it is a missed rebase, I will be away until next week
so will check this out when I get back.


-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius