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* [PATCH 0/3]  Add Renesas RZ/G2LC{SoC,SMARC EVK} support
@ 2021-12-16 11:43 Biju Das
  2021-12-16 11:43 ` [PATCH 1/3] arm64: dts: renesas: rzg2l-smarc: Move pinctrl definitions Biju Das
                   ` (2 more replies)
  0 siblings, 3 replies; 9+ messages in thread
From: Biju Das @ 2021-12-16 11:43 UTC (permalink / raw)
  To: Rob Herring
  Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
	devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad

Hi All,

RZ/G2L and RZ/G2LC SoC's are similar and they share the same DEVID.
RZ/G2LC has fewer peripherals compared to RZ/G2L.

SSI (3 channels vs 4 channels)
GbEthernet (1 channel vs 2 channels)
SCIFA (4 channels vs 5 channels)
ADC is only supported in RZ/G2L.

This patch series aims to add support for Renesas RZ/G2LC SoC and
basic support for  Renesas RZ/G2L SMARC EVK (based on R9A07G044C2)
- memory
- External input clock
- SCIF
- GbEthernet
- Audio Clock

It shares the same carrier board with RZ/G2L, but the pin mapping is
different. Disable the device nodes which is not tested and
delete the corresponding pinctrl definitions.

Note:-
On the H/W manual Number of Supported SSI channels as 2 and
SCIFA as 3. I got clarification from HW team that it is 3 and 4.

Test logs:-
root@smarc-rzg2lc:~# cat /proc/cpuinfo
processor       : 0
BogoMIPS        : 48.00
Features        : fp asimd evtstrm crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x2
CPU part        : 0xd05
CPU revision    : 0

processor       : 1
BogoMIPS        : 48.00
Features        : fp asimd evtstrm crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x2
CPU part        : 0xd05
CPU revision    : 0

root@smarc-rzg2lc:~# cat /proc/meminfo
MemTotal:         868836 kB
MemFree:          745012 kB
MemAvailable:     733492 kB
Buffers:               0 kB
Cached:            28456 kB
SwapCached:            0 kB
Active:             5344 kB
Inactive:          31936 kB
Active(anon):        660 kB
Inactive(anon):    17648 kB
Active(file):       4684 kB
Inactive(file):    14288 kB
Unevictable:           0 kB
Mlocked:               0 kB
SwapTotal:             0 kB
SwapFree:              0 kB
Dirty:                 0 kB
Writeback:             0 kB
AnonPages:          8824 kB
Mapped:            11428 kB
Shmem:              9484 kB
KReclaimable:      25568 kB
Slab:              60584 kB
SReclaimable:      25568 kB
SUnreclaim:        35016 kB
KernelStack:        1424 kB
PageTables:          688 kB
NFS_Unstable:          0 kB
Bounce:                0 kB
WritebackTmp:          0 kB
CommitLimit:      434416 kB
Committed_AS:      50076 kB
VmallocTotal:   133143461888 kB
VmallocUsed:        2000 kB
VmallocChunk:          0 kB
Percpu:              504 kB
AnonHugePages:         0 kB
ShmemHugePages:        0 kB
ShmemPmdMapped:        0 kB
FileHugePages:         0 kB
FilePmdMapped:         0 kB
CmaTotal:         131072 kB
CmaFree:          130676 kB
HugePages_Total:       0
HugePages_Free:        0
HugePages_Rsvd:        0
HugePages_Surp:        0
Hugepagesize:       2048 kB
Hugetlb:               0 kB
root@smarc-rzg2lc:~# cat /proc/interrupts
           CPU0       CPU1
 11:      38819      38039     GICv3  27 Level     arch_timer
 13:          0          0     GICv3 412 Level     1004b800.serial:rx err
 14:          2          0     GICv3 414 Level     1004b800.serial:rx full
 15:       1282          0     GICv3 415 Level     1004b800.serial:tx empty
 16:          0          0     GICv3 413 Level     1004b800.serial:break
 17:         53          0     GICv3 416 Level     1004b800.serial:rx ready
 18:          0          0     GICv3 173 Edge      error
 19:          0          0     GICv3 157 Edge      11820000.dma-controller:0
 20:          0          0     GICv3 158 Edge      11820000.dma-controller:1
 21:          0          0     GICv3 159 Edge      11820000.dma-controller:2
 22:          0          0     GICv3 160 Edge      11820000.dma-controller:3
 23:          0          0     GICv3 161 Edge      11820000.dma-controller:4
 24:          0          0     GICv3 162 Edge      11820000.dma-controller:5
 25:          0          0     GICv3 163 Edge      11820000.dma-controller:6
 26:          0          0     GICv3 164 Edge      11820000.dma-controller:7
 27:          0          0     GICv3 165 Edge      11820000.dma-controller:8
 28:          0          0     GICv3 166 Edge      11820000.dma-controller:9
 29:          0          0     GICv3 167 Edge      11820000.dma-controller:10
 30:          0          0     GICv3 168 Edge      11820000.dma-controller:11
 31:          0          0     GICv3 169 Edge      11820000.dma-controller:12
 32:          0          0     GICv3 170 Edge      11820000.dma-controller:13
 33:          0          0     GICv3 171 Edge      11820000.dma-controller:14
 34:          0          0     GICv3 172 Edge      11820000.dma-controller:15
 35:      10423          0     GICv3 116 Level     eth0
IPI0:      3655       5842       Rescheduling interrupts
IPI1:       251        787       Function call interrupts
IPI2:         0          0       CPU stop interrupts
IPI3:         0          0       CPU stop (for crash dump) interrupts
IPI4:         0          0       Timer broadcast interrupts
IPI5:        20         54       IRQ work interrupts
IPI6:         0          0       CPU wake-up interrupts
Err:          0
root@smarc-rzg2lc:~#


Biju Das (3):
  arm64: dts: renesas: rzg2l-smarc: Move pinctrl definitions
  arm64: dts: renesas: Add initial DTSI for RZ/G2LC SoC
  arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK

 arch/arm64/boot/dts/renesas/Makefile          |   1 +
 arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi  |  32 ++++
 .../boot/dts/renesas/r9a07g044c2-smarc.dts    |  99 +++++++++++++
 arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi  |  20 +++
 .../boot/dts/renesas/r9a07g044l2-smarc.dts    |   1 +
 .../dts/renesas/rzg2l-smarc-pinfunction.dtsi  | 137 ++++++++++++++++++
 arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi  | 127 ----------------
 .../dts/renesas/rzg2lc-smarc-pinfunction.dtsi |  25 ++++
 .../boot/dts/renesas/rzg2lc-smarc-som.dtsi    |  76 ++++++++++
 9 files changed, 391 insertions(+), 127 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
 create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi

-- 
2.17.1


^ permalink raw reply	[flat|nested] 9+ messages in thread
* [PATCH 1/3] arm64: dts: renesas: rzg2l-smarc: Move pinctrl definitions
  2021-12-16 11:43 [PATCH 0/3] Add Renesas RZ/G2LC{SoC,SMARC EVK} support Biju Das
@ 2021-12-16 11:43 ` Biju Das
  2022-01-10 14:25   ` Geert Uytterhoeven
  2021-12-16 11:43 ` [PATCH 2/3] arm64: dts: renesas: Add initial DTSI for RZ/G2LC SoC Biju Das
  2021-12-16 11:43 ` [PATCH 3/3] arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK Biju Das
  2 siblings, 1 reply; 9+ messages in thread
From: Biju Das @ 2021-12-16 11:43 UTC (permalink / raw)
  To: Rob Herring
  Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
	devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad

RZ/G2L and RZ/G2LC SMARC EVK use same carrier board, but the pin
mapping between RZ/G2L and RZ/G2LC SMARC SoM are different.
Therefore we need to update carrier board pin definitions based
on corresponding SoM pin mapping.

Move pinctrl definitions out of RZ/G2L SMARC common file, so that
we can reuse the common file to support RZ/G2LC SMARC EVK.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../boot/dts/renesas/r9a07g044l2-smarc.dts    |   1 +
 .../dts/renesas/rzg2l-smarc-pinfunction.dtsi  | 137 ++++++++++++++++++
 arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi  | 127 ----------------
 3 files changed, 138 insertions(+), 127 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
index 247b0b3f1b58..886d38886d05 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 #include "r9a07g044l2.dtsi"
 #include "rzg2l-smarc-som.dtsi"
+#include "rzg2l-smarc-pinfunction.dtsi"
 #include "rzg2l-smarc.dtsi"
 
 / {
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
new file mode 100644
index 000000000000..71d83e447670
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L SMARC pincontrol parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+&pinctrl {
+	pinctrl-0 = <&sound_clk_pins>;
+	pinctrl-names = "default";
+
+	can0_pins: can0 {
+		pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* TX */
+			 <RZG2L_PORT_PINMUX(11, 0, 2)>; /* RX */
+	};
+
+	/* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
+	can0-stb {
+		gpio-hog;
+		gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>;
+		output-low;
+		line-name = "can0_stb";
+	};
+
+	can1_pins: can1 {
+		pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* TX */
+			 <RZG2L_PORT_PINMUX(13, 0, 2)>; /* RX */
+	};
+
+	/* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
+	can1-stb {
+		gpio-hog;
+		gpios = <RZG2L_GPIO(42, 3) GPIO_ACTIVE_HIGH>;
+		output-low;
+		line-name = "can1_stb";
+	};
+
+	i2c0_pins: i2c0 {
+		pins = "RIIC0_SDA", "RIIC0_SCL";
+		input-enable;
+	};
+
+	i2c1_pins: i2c1 {
+		pins = "RIIC1_SDA", "RIIC1_SCL";
+		input-enable;
+	};
+
+	i2c3_pins: i2c3 {
+		pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */
+			 <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
+	};
+
+	scif0_pins: scif0 {
+		pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>,	/* TxD */
+			 <RZG2L_PORT_PINMUX(38, 1, 1)>;	/* RxD */
+	};
+
+	scif2_pins: scif2 {
+		pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* TxD */
+			 <RZG2L_PORT_PINMUX(48, 1, 1)>, /* RxD */
+			 <RZG2L_PORT_PINMUX(48, 3, 1)>, /* CTS# */
+			 <RZG2L_PORT_PINMUX(48, 4, 1)>; /* RTS# */
+	};
+
+	sd1-pwr-en-hog {
+		gpio-hog;
+		gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "sd1_pwr_en";
+	};
+
+	sdhi1_pins: sd1 {
+		sd1_data {
+			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
+			power-source = <3300>;
+		};
+
+		sd1_ctrl {
+			pins = "SD1_CLK", "SD1_CMD";
+			power-source = <3300>;
+		};
+
+		sd1_mux {
+			pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
+		};
+	};
+
+	sdhi1_pins_uhs: sd1_uhs {
+		sd1_data_uhs {
+			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
+			power-source = <1800>;
+		};
+
+		sd1_ctrl_uhs {
+			pins = "SD1_CLK", "SD1_CMD";
+			power-source = <1800>;
+		};
+
+		sd1_mux_uhs {
+			pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
+		};
+	};
+
+	sound_clk_pins: sound_clk {
+		pins = "AUDIO_CLK1", "AUDIO_CLK2";
+		input-enable;
+	};
+
+	spi1_pins: spi1 {
+		pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
+			 <RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
+			 <RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
+			 <RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
+	};
+
+	ssi0_pins: ssi0 {
+		pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
+			 <RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
+			 <RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */
+			 <RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */
+	};
+
+	usb0_pins: usb0 {
+		pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */
+			 <RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */
+			 <RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */
+	};
+
+	usb1_pins: usb1 {
+		pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */
+			 <RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */
+	};
+};
+
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index 6f2a8bdfa225..46abb29718cc 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -162,133 +162,6 @@
 	status = "okay";
 };
 
-&pinctrl {
-	pinctrl-0 = <&sound_clk_pins>;
-	pinctrl-names = "default";
-
-	can0_pins: can0 {
-		pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* TX */
-			 <RZG2L_PORT_PINMUX(11, 0, 2)>; /* RX */
-	};
-
-	/* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
-	can0-stb {
-		gpio-hog;
-		gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>;
-		output-low;
-		line-name = "can0_stb";
-	};
-
-	can1_pins: can1 {
-		pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* TX */
-			 <RZG2L_PORT_PINMUX(13, 0, 2)>; /* RX */
-	};
-
-	/* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
-	can1-stb {
-		gpio-hog;
-		gpios = <RZG2L_GPIO(42, 3) GPIO_ACTIVE_HIGH>;
-		output-low;
-		line-name = "can1_stb";
-	};
-
-	i2c0_pins: i2c0 {
-		pins = "RIIC0_SDA", "RIIC0_SCL";
-		input-enable;
-	};
-
-	i2c1_pins: i2c1 {
-		pins = "RIIC1_SDA", "RIIC1_SCL";
-		input-enable;
-	};
-
-	i2c3_pins: i2c3 {
-		pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */
-			 <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
-	};
-
-	scif0_pins: scif0 {
-		pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>,	/* TxD */
-			 <RZG2L_PORT_PINMUX(38, 1, 1)>;	/* RxD */
-	};
-
-	scif2_pins: scif2 {
-		pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* TxD */
-			 <RZG2L_PORT_PINMUX(48, 1, 1)>, /* RxD */
-			 <RZG2L_PORT_PINMUX(48, 3, 1)>, /* CTS# */
-			 <RZG2L_PORT_PINMUX(48, 4, 1)>; /* RTS# */
-	};
-
-	sd1-pwr-en-hog {
-		gpio-hog;
-		gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
-		output-high;
-		line-name = "sd1_pwr_en";
-	};
-
-	sdhi1_pins: sd1 {
-		sd1_data {
-			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
-			power-source = <3300>;
-		};
-
-		sd1_ctrl {
-			pins = "SD1_CLK", "SD1_CMD";
-			power-source = <3300>;
-		};
-
-		sd1_mux {
-			pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
-		};
-	};
-
-	sdhi1_pins_uhs: sd1_uhs {
-		sd1_data_uhs {
-			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
-			power-source = <1800>;
-		};
-
-		sd1_ctrl_uhs {
-			pins = "SD1_CLK", "SD1_CMD";
-			power-source = <1800>;
-		};
-
-		sd1_mux_uhs {
-			pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
-		};
-	};
-
-	sound_clk_pins: sound_clk {
-		pins = "AUDIO_CLK1", "AUDIO_CLK2";
-		input-enable;
-	};
-
-	spi1_pins: spi1 {
-		pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
-			 <RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
-			 <RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
-			 <RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
-	};
-
-	ssi0_pins: ssi0 {
-		pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
-			 <RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
-			 <RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */
-			 <RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */
-	};
-
-	usb0_pins: usb0 {
-		pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */
-			 <RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */
-			 <RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */
-	};
-
-	usb1_pins: usb1 {
-		pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */
-			 <RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */
-	};
-};
-
 &scif0 {
 	pinctrl-0 = <&scif0_pins>;
 	pinctrl-names = "default";
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread
* [PATCH 2/3] arm64: dts: renesas: Add initial DTSI for RZ/G2LC SoC
  2021-12-16 11:43 [PATCH 0/3] Add Renesas RZ/G2LC{SoC,SMARC EVK} support Biju Das
  2021-12-16 11:43 ` [PATCH 1/3] arm64: dts: renesas: rzg2l-smarc: Move pinctrl definitions Biju Das
@ 2021-12-16 11:43 ` Biju Das
  2022-01-10 14:35   ` Geert Uytterhoeven
  2021-12-16 11:43 ` [PATCH 3/3] arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK Biju Das
  2 siblings, 1 reply; 9+ messages in thread
From: Biju Das @ 2021-12-16 11:43 UTC (permalink / raw)
  To: Rob Herring
  Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
	devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad

RZ/G2L and RZ/G2LC SoC's are similar and they share the same DEVID.
RZ/G2LC has fewer peripherals compared to RZ/G2L.

SSI (3 channels vs 4 channels)
GbEthernet (1 channel vs 2 channels)
SCIFA (4 channels vs 5 channels)
ADC is only supported in RZ/G2L.

Add initial DTSI for RZ/G2LC SoC by reusing the common r9a07g044.dtsi
file with unsupported device nodes deleted in the below SoC specific dtsi
files.

r9a07g044c1.dtsi => RZ/G2LC R9A07G044C1 SoC specific parts
r9a07g044c2.dtsi => RZ/G2LC R9A07G044C2 SoC specific parts

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi | 32 ++++++++++++++++++++
 arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi | 20 ++++++++++++
 2 files changed, 52 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi
new file mode 100644
index 000000000000..1d57df706939
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2LC R9A07G044C1 SoC specific parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g044.dtsi"
+
+/ {
+	compatible = "renesas,r9a07g044c1", "renesas,r9a07g044";
+
+	cpus {
+		/delete-node/ cpu-map;
+		/delete-node/ cpu@100;
+	};
+
+	timer {
+		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+};
+
+&soc {
+	/delete-node/ ssi@1004a800;
+	/delete-node/ serial@1004c800;
+	/delete-node/ adc@10059000;
+	/delete-node/ ethernet@11c30000;
+};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi
new file mode 100644
index 000000000000..7bb8917fe421
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2LC R9A07G044C2 SoC specific parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g044.dtsi"
+
+/ {
+	compatible = "renesas,r9a07g044c2", "renesas,r9a07g044";
+};
+
+&soc {
+	/delete-node/ ssi@1004a800;
+	/delete-node/ serial@1004c800;
+	/delete-node/ adc@10059000;
+	/delete-node/ ethernet@11c30000;
+};
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread
* [PATCH 3/3] arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK
  2021-12-16 11:43 [PATCH 0/3] Add Renesas RZ/G2LC{SoC,SMARC EVK} support Biju Das
  2021-12-16 11:43 ` [PATCH 1/3] arm64: dts: renesas: rzg2l-smarc: Move pinctrl definitions Biju Das
  2021-12-16 11:43 ` [PATCH 2/3] arm64: dts: renesas: Add initial DTSI for RZ/G2LC SoC Biju Das
@ 2021-12-16 11:43 ` Biju Das
  2022-01-10 14:53   ` Geert Uytterhoeven
  2 siblings, 1 reply; 9+ messages in thread
From: Biju Das @ 2021-12-16 11:43 UTC (permalink / raw)
  To: Rob Herring
  Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
	devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad

Add basic support for RZ/G2LC SMARC EVK (based on R9A07G044C2):
- memory
- External input clock
- SCIF
- GbEthernet
- Audio Clock

It shares the same carrier board with RZ/G2L, but the pin mapping is
different. Disable the device nodes which is not tested and
delete the corresponding pinctrl definitions.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/Makefile          |  1 +
 .../boot/dts/renesas/r9a07g044c2-smarc.dts    | 99 +++++++++++++++++++
 .../dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 25 +++++
 .../boot/dts/renesas/rzg2lc-smarc-som.dtsi    | 76 ++++++++++++++
 4 files changed, 201 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
 create mode 100644 arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 5bc8065a7864..8e696a38c560 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -76,3 +76,4 @@ dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb-kf.dtb
 dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb
 
 dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
new file mode 100644
index 000000000000..53845823d0dc
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2LC SMARC EVK board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g044c2.dtsi"
+#include "rzg2lc-smarc-som.dtsi"
+#include "rzg2lc-smarc-pinfunction.dtsi"
+#include "rzg2l-smarc.dtsi"
+
+/ {
+	model = "Renesas SMARC EVK based on r9a07g044c2";
+	compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044";
+
+};
+
+&canfd {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&ehci0 {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&ehci1 {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&hsusb {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&i2c0 {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&i2c1 {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&i2c3 {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&ohci0 {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&ohci1 {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&phyrst {
+	status = "disabled";
+};
+
+&scif2 {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&sdhi1 {
+	/delete-property/ pinctrl-0;
+	/delete-property/ pinctrl-1;
+	/delete-property/ vmmc-supply;
+	status = "disabled";
+};
+
+&spi1 {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&ssi0 {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&usb2_phy0 {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&usb2_phy1 {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
new file mode 100644
index 000000000000..5333a1f9a0e7
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2LC SMARC pincontrol parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+&pinctrl {
+	pinctrl-0 = <&sound_clk_pins>;
+	pinctrl-names = "default";
+
+	scif0_pins: scif0 {
+		pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>,	/* TxD */
+			 <RZG2L_PORT_PINMUX(38, 1, 1)>;	/* RxD */
+	};
+
+	sound_clk_pins: sound_clk {
+		pins = "AUDIO_CLK1", "AUDIO_CLK2";
+		input-enable;
+	};
+};
+
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
new file mode 100644
index 000000000000..e1d7a3a689c6
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2LC SMARC SOM common parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/ {
+	aliases {
+		ethernet0 = &eth0;
+	};
+
+	chosen {
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
+	};
+
+	memory@48000000 {
+		device_type = "memory";
+		/* first 128MB is reserved for secure area. */
+		reg = <0x0 0x48000000 0x0 0x38000000>;
+	};
+};
+
+&eth0 {
+	pinctrl-0 = <&eth0_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii-id";
+	status = "okay";
+
+	phy0: ethernet-phy@7 {
+		compatible = "ethernet-phy-id0022.1640",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <7>;
+		rxc-skew-psec = <2400>;
+		txc-skew-psec = <2400>;
+		rxdv-skew-psec = <0>;
+		txdv-skew-psec = <0>;
+		rxd0-skew-psec = <0>;
+		rxd1-skew-psec = <0>;
+		rxd2-skew-psec = <0>;
+		rxd3-skew-psec = <0>;
+		txd0-skew-psec = <0>;
+		txd1-skew-psec = <0>;
+		txd2-skew-psec = <0>;
+		txd3-skew-psec = <0>;
+	};
+};
+
+&extal_clk {
+	clock-frequency = <24000000>;
+};
+
+&pinctrl {
+	eth0_pins: eth0 {
+		pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
+			 <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
+			 <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
+			 <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
+			 <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
+			 <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
+			 <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
+			 <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
+			 <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
+			 <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
+			 <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
+			 <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
+			 <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
+			 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
+			 <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
+	};
+};
+
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] arm64: dts: renesas: rzg2l-smarc: Move pinctrl definitions
  2021-12-16 11:43 ` [PATCH 1/3] arm64: dts: renesas: rzg2l-smarc: Move pinctrl definitions Biju Das
@ 2022-01-10 14:25   ` Geert Uytterhoeven
  0 siblings, 0 replies; 9+ messages in thread
From: Geert Uytterhoeven @ 2022-01-10 14:25 UTC (permalink / raw)
  To: Biju Das
  Cc: Rob Herring, Magnus Damm, Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Chris Paterson, Biju Das, Prabhakar Mahadev Lad

On Thu, Dec 16, 2021 at 12:43 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> RZ/G2L and RZ/G2LC SMARC EVK use same carrier board, but the pin
> mapping between RZ/G2L and RZ/G2LC SMARC SoM are different.
> Therefore we need to update carrier board pin definitions based
> on corresponding SoM pin mapping.
>
> Move pinctrl definitions out of RZ/G2L SMARC common file, so that
> we can reuse the common file to support RZ/G2LC SMARC EVK.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.18.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] arm64: dts: renesas: Add initial DTSI for RZ/G2LC SoC
  2021-12-16 11:43 ` [PATCH 2/3] arm64: dts: renesas: Add initial DTSI for RZ/G2LC SoC Biju Das
@ 2022-01-10 14:35   ` Geert Uytterhoeven
  0 siblings, 0 replies; 9+ messages in thread
From: Geert Uytterhoeven @ 2022-01-10 14:35 UTC (permalink / raw)
  To: Biju Das
  Cc: Rob Herring, Magnus Damm, Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Chris Paterson, Biju Das, Prabhakar Mahadev Lad

On Thu, Dec 16, 2021 at 12:43 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> RZ/G2L and RZ/G2LC SoC's are similar and they share the same DEVID.
> RZ/G2LC has fewer peripherals compared to RZ/G2L.
>
> SSI (3 channels vs 4 channels)
> GbEthernet (1 channel vs 2 channels)
> SCIFA (4 channels vs 5 channels)
> ADC is only supported in RZ/G2L.
>
> Add initial DTSI for RZ/G2LC SoC by reusing the common r9a07g044.dtsi
> file with unsupported device nodes deleted in the below SoC specific dtsi
> files.
>
> r9a07g044c1.dtsi => RZ/G2LC R9A07G044C1 SoC specific parts
> r9a07g044c2.dtsi => RZ/G2LC R9A07G044C2 SoC specific parts
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.18.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK
  2021-12-16 11:43 ` [PATCH 3/3] arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK Biju Das
@ 2022-01-10 14:53   ` Geert Uytterhoeven
  2022-01-10 17:28     ` Biju Das
  0 siblings, 1 reply; 9+ messages in thread
From: Geert Uytterhoeven @ 2022-01-10 14:53 UTC (permalink / raw)
  To: Biju Das
  Cc: Rob Herring, Magnus Damm, Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Chris Paterson, Biju Das, Prabhakar Mahadev Lad

Hi Biju,

On Thu, Dec 16, 2021 at 12:43 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add basic support for RZ/G2LC SMARC EVK (based on R9A07G044C2):
> - memory
> - External input clock
> - SCIF
> - GbEthernet
> - Audio Clock
>
> It shares the same carrier board with RZ/G2L, but the pin mapping is
> different. Disable the device nodes which is not tested and
> delete the corresponding pinctrl definitions.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Before I queue this in renesas-devel for v5.18, I have two questions:

> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
> @@ -0,0 +1,99 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/G2LC SMARC EVK board
> + *
> + * Copyright (C) 2021 Renesas Electronics Corp.
> + */
> +
> +/dts-v1/;
> +#include "r9a07g044c2.dtsi"
> +#include "rzg2lc-smarc-som.dtsi"
> +#include "rzg2lc-smarc-pinfunction.dtsi"

1) So far it looks like the definitions in rzg2lc-smarc-pinfunction.dtsi
   do not really differ from those in rzg2l-smarc-pinfunction.dtsi,\
   there are just less. Will there be other differences?
2) Would it make sense to create rzg2*-smarc-som-pinfunction.dtsi
   files, too?

Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 9+ messages in thread
* RE: [PATCH 3/3] arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK
  2022-01-10 14:53   ` Geert Uytterhoeven
@ 2022-01-10 17:28     ` Biju Das
  2022-01-10 17:41       ` Geert Uytterhoeven
  0 siblings, 1 reply; 9+ messages in thread
From: Biju Das @ 2022-01-10 17:28 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Rob Herring, Magnus Damm, Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Chris Paterson, Biju Das, Prabhakar Mahadev Lad

Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH 3/3] arm64: dts: renesas: Add initial device tree for
> RZ/G2LC SMARC EVK
> 
> Hi Biju,
> 
> On Thu, Dec 16, 2021 at 12:43 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > Add basic support for RZ/G2LC SMARC EVK (based on R9A07G044C2):
> > - memory
> > - External input clock
> > - SCIF
> > - GbEthernet
> > - Audio Clock
> >
> > It shares the same carrier board with RZ/G2L, but the pin mapping is
> > different. Disable the device nodes which is not tested and delete the
> > corresponding pinctrl definitions.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Thanks for your patch!
> 
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> 
> Before I queue this in renesas-devel for v5.18, I have two questions:
> 
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
> > @@ -0,0 +1,99 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the RZ/G2LC SMARC EVK board
> > + *
> > + * Copyright (C) 2021 Renesas Electronics Corp.
> > + */
> > +
> > +/dts-v1/;
> > +#include "r9a07g044c2.dtsi"
> > +#include "rzg2lc-smarc-som.dtsi"
> > +#include "rzg2lc-smarc-pinfunction.dtsi"
> 
> 1) So far it looks like the definitions in rzg2lc-smarc-pinfunction.dtsi
>    do not really differ from those in rzg2l-smarc-pinfunction.dtsi,\
>    there are just less. Will there be other differences?

SoM module contains below SW for multiplex function. Same pins used for both operations.

SW1-3 : 1:CAN1, 0:SCIF1
SW1-4 : 1:CAN1, 0:RSPI1
SW1-5 : 1:I2S2 HDMI Audio, 0:I2S0 Audio code

Apart from this, there are differences w.r.to 
1) PMOD pins
2) SD0 power enable and SD0_DEV_SEL
3) IIC3
4) Only CAN1 and ETH0.

> 2) Would it make sense to create rzg2*-smarc-som-pinfunction.dtsi
>    files, too?

Only ADC, Ethernet and SD0/eMMC are defined on SoM.

Between RZ/G2L and RZ/G2LC, ADC is not present on LC
And SD0 pins are different between this as mentioned above.

Only ethernet(eth0) is common, but that also different in RZ/G2UL.
That is the reason it is not done.

If there is a value in adding, rzg2*-smarc-som-pinfunction.dtsi, I can create
rzg2*-smarc-som-pinfunction.dtsi files. 

Please let me know.

Regards,
Biju

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK
  2022-01-10 17:28     ` Biju Das
@ 2022-01-10 17:41       ` Geert Uytterhoeven
  0 siblings, 0 replies; 9+ messages in thread
From: Geert Uytterhoeven @ 2022-01-10 17:41 UTC (permalink / raw)
  To: Biju Das
  Cc: Rob Herring, Magnus Damm, Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Chris Paterson, Biju Das, Prabhakar Mahadev Lad

Hi Biju,

On Mon, Jan 10, 2022 at 6:28 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Geert,
>
> Thanks for the feedback.
>
> > Subject: Re: [PATCH 3/3] arm64: dts: renesas: Add initial device tree for
> > RZ/G2LC SMARC EVK
> >
> > Hi Biju,
> >
> > On Thu, Dec 16, 2021 at 12:43 PM Biju Das <biju.das.jz@bp.renesas.com>
> > wrote:
> > > Add basic support for RZ/G2LC SMARC EVK (based on R9A07G044C2):
> > > - memory
> > > - External input clock
> > > - SCIF
> > > - GbEthernet
> > > - Audio Clock
> > >
> > > It shares the same carrier board with RZ/G2L, but the pin mapping is
> > > different. Disable the device nodes which is not tested and delete the
> > > corresponding pinctrl definitions.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >
> > Before I queue this in renesas-devel for v5.18, I have two questions:
> >
> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
> > > @@ -0,0 +1,99 @@
> > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +/*
> > > + * Device Tree Source for the RZ/G2LC SMARC EVK board
> > > + *
> > > + * Copyright (C) 2021 Renesas Electronics Corp.
> > > + */
> > > +
> > > +/dts-v1/;
> > > +#include "r9a07g044c2.dtsi"
> > > +#include "rzg2lc-smarc-som.dtsi"
> > > +#include "rzg2lc-smarc-pinfunction.dtsi"
> >
> > 1) So far it looks like the definitions in rzg2lc-smarc-pinfunction.dtsi
> >    do not really differ from those in rzg2l-smarc-pinfunction.dtsi,\
> >    there are just less. Will there be other differences?
>
> SoM module contains below SW for multiplex function. Same pins used for both operations.
>
> SW1-3 : 1:CAN1, 0:SCIF1
> SW1-4 : 1:CAN1, 0:RSPI1
> SW1-5 : 1:I2S2 HDMI Audio, 0:I2S0 Audio code
>
> Apart from this, there are differences w.r.to
> 1) PMOD pins
> 2) SD0 power enable and SD0_DEV_SEL
> 3) IIC3
> 4) Only CAN1 and ETH0.

OK, so let's go as you proposed.

> > 2) Would it make sense to create rzg2*-smarc-som-pinfunction.dtsi
> >    files, too?
>
> Only ADC, Ethernet and SD0/eMMC are defined on SoM.
>
> Between RZ/G2L and RZ/G2LC, ADC is not present on LC
> And SD0 pins are different between this as mentioned above.
>
> Only ethernet(eth0) is common, but that also different in RZ/G2UL.
> That is the reason it is not done.
>
> If there is a value in adding, rzg2*-smarc-som-pinfunction.dtsi, I can create
> rzg2*-smarc-som-pinfunction.dtsi files.
>
> Please let me know.

Thanks, it's fine as-is.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-01-10 17:42 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-16 11:43 [PATCH 0/3] Add Renesas RZ/G2LC{SoC,SMARC EVK} support Biju Das
2021-12-16 11:43 ` [PATCH 1/3] arm64: dts: renesas: rzg2l-smarc: Move pinctrl definitions Biju Das
2022-01-10 14:25   ` Geert Uytterhoeven
2021-12-16 11:43 ` [PATCH 2/3] arm64: dts: renesas: Add initial DTSI for RZ/G2LC SoC Biju Das
2022-01-10 14:35   ` Geert Uytterhoeven
2021-12-16 11:43 ` [PATCH 3/3] arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK Biju Das
2022-01-10 14:53   ` Geert Uytterhoeven
2022-01-10 17:28     ` Biju Das
2022-01-10 17:41       ` Geert Uytterhoeven

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