* [PATCH] clk: renesas: r8a7795: Fix HDMI parent clock
@ 2016-11-04 13:58 Simon Horman
2016-11-07 10:20 ` Geert Uytterhoeven
0 siblings, 1 reply; 2+ messages in thread
From: Simon Horman @ 2016-11-04 13:58 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Magnus Damm, linux-renesas-soc, linux-clk
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Correct HDMI parent clock so that the rate of the
HDMI clock is 1/4 rather than 1/2 of the rate of PLL1
as per the v0.52 (Jun, 15) manual.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
drivers/clk/renesas/r8a7795-cpg-mssr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index f255e451e8ca..eec42c249e3a 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -97,7 +97,7 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
- DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250),
+ DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] clk: renesas: r8a7795: Fix HDMI parent clock
2016-11-04 13:58 [PATCH] clk: renesas: r8a7795: Fix HDMI parent clock Simon Horman
@ 2016-11-07 10:20 ` Geert Uytterhoeven
0 siblings, 0 replies; 2+ messages in thread
From: Geert Uytterhoeven @ 2016-11-07 10:20 UTC (permalink / raw)
To: Simon Horman; +Cc: Geert Uytterhoeven, Magnus Damm, Linux-Renesas, linux-clk
On Fri, Nov 4, 2016 at 2:58 PM, Simon Horman <horms+renesas@verge.net.au> wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> Correct HDMI parent clock so that the rate of the
> HDMI clock is 1/4 rather than 1/2 of the rate of PLL1
> as per the v0.52 (Jun, 15) manual.
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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2016-11-04 13:58 [PATCH] clk: renesas: r8a7795: Fix HDMI parent clock Simon Horman
2016-11-07 10:20 ` Geert Uytterhoeven
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