From: Baolin Wang <baolin.wang@linaro.org> To: Vinod Koul <vkoul@kernel.org> Cc: Dan Williams <dan.j.williams@intel.com>, eric.long@unisoc.com, Orson Zhai <orsonzhai@gmail.com>, Chunyan Zhang <zhang.lyra@gmail.com>, Mark Brown <broonie@kernel.org>, dmaengine@vger.kernel.org, LKML <linux-kernel@vger.kernel.org> Subject: [7/7] dmaengine: sprd: Add interrupt support for 2-stage transfer Date: Mon, 29 Apr 2019 20:11:27 +0800 [thread overview] Message-ID: <CAMz4kuJB2+6HziyDep4ctfmjFYpmZ-v_vrFQsJ9tHvwYzSJeKA@mail.gmail.com> (raw) On Mon, 29 Apr 2019 at 20:01, Vinod Koul <vkoul@kernel.org> wrote: > > On 15-04-19, 20:15, Baolin Wang wrote: > > For 2-stage transfer, some users like Audio still need transaction interrupt > > to notify when the 2-stage transfer is completed. Thus we should enable > > 2-stage transfer interrupt to support this feature. > > > > Signed-off-by: Baolin Wang <baolin.wang@linaro.org> > > --- > > drivers/dma/sprd-dma.c | 22 +++++++++++++++++++++- > > 1 file changed, 21 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/dma/sprd-dma.c b/drivers/dma/sprd-dma.c > > index cc9c24d..4c18f44 100644 > > --- a/drivers/dma/sprd-dma.c > > +++ b/drivers/dma/sprd-dma.c > > @@ -62,6 +62,8 @@ > > /* SPRD_DMA_GLB_2STAGE_GRP register definition */ > > #define SPRD_DMA_GLB_2STAGE_EN BIT(24) > > #define SPRD_DMA_GLB_CHN_INT_MASK GENMASK(23, 20) > > +#define SPRD_DMA_GLB_DEST_INT BIT(22) > > +#define SPRD_DMA_GLB_SRC_INT BIT(20) > > #define SPRD_DMA_GLB_LIST_DONE_TRG BIT(19) > > #define SPRD_DMA_GLB_TRANS_DONE_TRG BIT(18) > > #define SPRD_DMA_GLB_BLOCK_DONE_TRG BIT(17) > > @@ -135,6 +137,7 @@ > > /* define DMA channel mode & trigger mode mask */ > > #define SPRD_DMA_CHN_MODE_MASK GENMASK(7, 0) > > #define SPRD_DMA_TRG_MODE_MASK GENMASK(7, 0) > > +#define SPRD_DMA_INT_TYPE_MASK GENMASK(7, 0) > > > > /* define the DMA transfer step type */ > > #define SPRD_DMA_NONE_STEP 0 > > @@ -190,6 +193,7 @@ struct sprd_dma_chn { > > u32 dev_id; > > enum sprd_dma_chn_mode chn_mode; > > enum sprd_dma_trg_mode trg_mode; > > + enum sprd_dma_int_type int_type; > > struct sprd_dma_desc *cur_desc; > > }; > > > > @@ -429,6 +433,9 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan) > > val = chn & SPRD_DMA_GLB_SRC_CHN_MASK; > > val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET; > > val |= SPRD_DMA_GLB_2STAGE_EN; > > + if (schan->int_type != SPRD_DMA_NO_INT) > > Who configure int_type? The int_type is configured through the flags of sprd_dma_prep_slave_sg() by users, see: https://elixir.bootlin.com/linux/v5.1-rc6/source/include/linux/dma/sprd-dma.h#L9 > > > + val |= SPRD_DMA_GLB_SRC_INT; > > + > > sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val); > > break; > > > > @@ -436,6 +443,9 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan) > > val = chn & SPRD_DMA_GLB_SRC_CHN_MASK; > > val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET; > > val |= SPRD_DMA_GLB_2STAGE_EN; > > + if (schan->int_type != SPRD_DMA_NO_INT) > > + val |= SPRD_DMA_GLB_SRC_INT; > > + > > sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val); > > break; > > > > @@ -443,6 +453,9 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan) > > val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) & > > SPRD_DMA_GLB_DEST_CHN_MASK; > > val |= SPRD_DMA_GLB_2STAGE_EN; > > + if (schan->int_type != SPRD_DMA_NO_INT) > > + val |= SPRD_DMA_GLB_DEST_INT; > > + > > sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val); > > break; > > > > @@ -450,6 +463,9 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan) > > val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) & > > SPRD_DMA_GLB_DEST_CHN_MASK; > > val |= SPRD_DMA_GLB_2STAGE_EN; > > + if (schan->int_type != SPRD_DMA_NO_INT) > > + val |= SPRD_DMA_GLB_DEST_INT; > > + > > sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val); > > break; > > > > @@ -911,11 +927,15 @@ static int sprd_dma_fill_linklist_desc(struct dma_chan *chan, > > schan->linklist.virt_addr = 0; > > } > > > > - /* Set channel mode and trigger mode for 2-stage transfer */ > > + /* > > + * Set channel mode, interrupt mode and trigger mode for 2-stage > > + * transfer. > > + */ > > schan->chn_mode = > > (flags >> SPRD_DMA_CHN_MODE_SHIFT) & SPRD_DMA_CHN_MODE_MASK; > > schan->trg_mode = > > (flags >> SPRD_DMA_TRG_MODE_SHIFT) & SPRD_DMA_TRG_MODE_MASK; > > + schan->int_type = flags & SPRD_DMA_INT_TYPE_MASK; > > > > sdesc = kzalloc(sizeof(*sdesc), GFP_NOWAIT); > > if (!sdesc) > > -- > > 1.7.9.5 > > -- > ~Vinod
WARNING: multiple messages have this Message-ID (diff)
From: Baolin Wang <baolin.wang@linaro.org> To: Vinod Koul <vkoul@kernel.org> Cc: Dan Williams <dan.j.williams@intel.com>, eric.long@unisoc.com, Orson Zhai <orsonzhai@gmail.com>, Chunyan Zhang <zhang.lyra@gmail.com>, Mark Brown <broonie@kernel.org>, dmaengine@vger.kernel.org, LKML <linux-kernel@vger.kernel.org> Subject: Re: [PATCH 7/7] dmaengine: sprd: Add interrupt support for 2-stage transfer Date: Mon, 29 Apr 2019 20:11:27 +0800 [thread overview] Message-ID: <CAMz4kuJB2+6HziyDep4ctfmjFYpmZ-v_vrFQsJ9tHvwYzSJeKA@mail.gmail.com> (raw) Message-ID: <20190429121127.jyyUBaBnKwYjcG5zLk8pGn-LF-WO7OLMPqfzMr-yI88@z> (raw) In-Reply-To: <20190429120108.GL3845@vkoul-mobl.Dlink> On Mon, 29 Apr 2019 at 20:01, Vinod Koul <vkoul@kernel.org> wrote: > > On 15-04-19, 20:15, Baolin Wang wrote: > > For 2-stage transfer, some users like Audio still need transaction interrupt > > to notify when the 2-stage transfer is completed. Thus we should enable > > 2-stage transfer interrupt to support this feature. > > > > Signed-off-by: Baolin Wang <baolin.wang@linaro.org> > > --- > > drivers/dma/sprd-dma.c | 22 +++++++++++++++++++++- > > 1 file changed, 21 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/dma/sprd-dma.c b/drivers/dma/sprd-dma.c > > index cc9c24d..4c18f44 100644 > > --- a/drivers/dma/sprd-dma.c > > +++ b/drivers/dma/sprd-dma.c > > @@ -62,6 +62,8 @@ > > /* SPRD_DMA_GLB_2STAGE_GRP register definition */ > > #define SPRD_DMA_GLB_2STAGE_EN BIT(24) > > #define SPRD_DMA_GLB_CHN_INT_MASK GENMASK(23, 20) > > +#define SPRD_DMA_GLB_DEST_INT BIT(22) > > +#define SPRD_DMA_GLB_SRC_INT BIT(20) > > #define SPRD_DMA_GLB_LIST_DONE_TRG BIT(19) > > #define SPRD_DMA_GLB_TRANS_DONE_TRG BIT(18) > > #define SPRD_DMA_GLB_BLOCK_DONE_TRG BIT(17) > > @@ -135,6 +137,7 @@ > > /* define DMA channel mode & trigger mode mask */ > > #define SPRD_DMA_CHN_MODE_MASK GENMASK(7, 0) > > #define SPRD_DMA_TRG_MODE_MASK GENMASK(7, 0) > > +#define SPRD_DMA_INT_TYPE_MASK GENMASK(7, 0) > > > > /* define the DMA transfer step type */ > > #define SPRD_DMA_NONE_STEP 0 > > @@ -190,6 +193,7 @@ struct sprd_dma_chn { > > u32 dev_id; > > enum sprd_dma_chn_mode chn_mode; > > enum sprd_dma_trg_mode trg_mode; > > + enum sprd_dma_int_type int_type; > > struct sprd_dma_desc *cur_desc; > > }; > > > > @@ -429,6 +433,9 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan) > > val = chn & SPRD_DMA_GLB_SRC_CHN_MASK; > > val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET; > > val |= SPRD_DMA_GLB_2STAGE_EN; > > + if (schan->int_type != SPRD_DMA_NO_INT) > > Who configure int_type? The int_type is configured through the flags of sprd_dma_prep_slave_sg() by users, see: https://elixir.bootlin.com/linux/v5.1-rc6/source/include/linux/dma/sprd-dma.h#L9 > > > + val |= SPRD_DMA_GLB_SRC_INT; > > + > > sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val); > > break; > > > > @@ -436,6 +443,9 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan) > > val = chn & SPRD_DMA_GLB_SRC_CHN_MASK; > > val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET; > > val |= SPRD_DMA_GLB_2STAGE_EN; > > + if (schan->int_type != SPRD_DMA_NO_INT) > > + val |= SPRD_DMA_GLB_SRC_INT; > > + > > sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val); > > break; > > > > @@ -443,6 +453,9 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan) > > val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) & > > SPRD_DMA_GLB_DEST_CHN_MASK; > > val |= SPRD_DMA_GLB_2STAGE_EN; > > + if (schan->int_type != SPRD_DMA_NO_INT) > > + val |= SPRD_DMA_GLB_DEST_INT; > > + > > sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val); > > break; > > > > @@ -450,6 +463,9 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan) > > val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) & > > SPRD_DMA_GLB_DEST_CHN_MASK; > > val |= SPRD_DMA_GLB_2STAGE_EN; > > + if (schan->int_type != SPRD_DMA_NO_INT) > > + val |= SPRD_DMA_GLB_DEST_INT; > > + > > sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val); > > break; > > > > @@ -911,11 +927,15 @@ static int sprd_dma_fill_linklist_desc(struct dma_chan *chan, > > schan->linklist.virt_addr = 0; > > } > > > > - /* Set channel mode and trigger mode for 2-stage transfer */ > > + /* > > + * Set channel mode, interrupt mode and trigger mode for 2-stage > > + * transfer. > > + */ > > schan->chn_mode = > > (flags >> SPRD_DMA_CHN_MODE_SHIFT) & SPRD_DMA_CHN_MODE_MASK; > > schan->trg_mode = > > (flags >> SPRD_DMA_TRG_MODE_SHIFT) & SPRD_DMA_TRG_MODE_MASK; > > + schan->int_type = flags & SPRD_DMA_INT_TYPE_MASK; > > > > sdesc = kzalloc(sizeof(*sdesc), GFP_NOWAIT); > > if (!sdesc) > > -- > > 1.7.9.5 > > -- > ~Vinod -- Baolin Wang Best Regards
next reply other threads:[~2019-04-29 12:11 UTC|newest] Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-04-29 12:11 Baolin Wang [this message] 2019-04-29 12:11 ` [PATCH 7/7] dmaengine: sprd: Add interrupt support for 2-stage transfer Baolin Wang -- strict thread matches above, loose matches on Subject: below -- 2019-04-30 5:37 [7/7] " Baolin Wang 2019-04-30 5:37 ` [PATCH 7/7] " Baolin Wang 2019-04-29 14:10 [7/7] " Vinod Koul 2019-04-29 14:10 ` [PATCH 7/7] " Vinod Koul 2019-04-29 12:02 [1/7] dmaengine: sprd: Fix the possible crash when getting engine status Vinod Koul 2019-04-29 12:02 ` [PATCH 1/7] " Vinod Koul 2019-04-29 12:01 [7/7] dmaengine: sprd: Add interrupt support for 2-stage transfer Vinod Koul 2019-04-29 12:01 ` [PATCH 7/7] " Vinod Koul 2019-04-29 11:49 [1/7] dmaengine: sprd: Fix the possible crash when getting engine status Baolin Wang 2019-04-29 11:49 ` [PATCH 1/7] " Baolin Wang 2019-04-29 11:35 [1/7] " Vinod Koul 2019-04-29 11:35 ` [PATCH 1/7] " Vinod Koul 2019-04-15 12:15 [7/7] dmaengine: sprd: Add interrupt support for 2-stage transfer Baolin Wang 2019-04-15 12:15 ` [PATCH 7/7] " Baolin Wang 2019-04-15 12:15 [6/7] dmaengine: sprd: Fix the right place to configure " Baolin Wang 2019-04-15 12:15 ` [PATCH 6/7] " Baolin Wang 2019-04-15 12:14 [5/7] dmaengine: sprd: Fix block length overflow Baolin Wang 2019-04-15 12:14 ` [PATCH 5/7] " Baolin Wang 2019-04-15 12:14 [3/7] dmaengine: sprd: Fix the incorrect start for 2-stage destination channels Baolin Wang 2019-04-15 12:14 ` [PATCH 3/7] " Baolin Wang 2019-04-15 12:14 [2/7] dmaengine: sprd: Add validation of current descriptor in irq handler Baolin Wang 2019-04-15 12:14 ` [PATCH 2/7] " Baolin Wang 2019-04-15 12:14 [1/7] dmaengine: sprd: Fix the possible crash when getting engine status Baolin Wang 2019-04-15 12:14 ` [PATCH 1/7] " Baolin Wang 2019-04-15 12:14 [PATCH 0/7] Fix some bugs and add new feature for Spreadtrum DMA engine Baolin Wang 2019-04-15 12:14 ` [4/7] dmaengine: sprd: Add device validation to support multiple controllers Baolin Wang 2019-04-15 12:14 ` [PATCH 4/7] " Baolin Wang 2019-04-29 11:57 ` [4/7] " Vinod Koul 2019-04-29 11:57 ` [PATCH 4/7] " Vinod Koul 2019-04-29 12:20 ` [4/7] " Baolin Wang 2019-04-29 12:20 ` [PATCH 4/7] " Baolin Wang 2019-04-29 14:05 ` [4/7] " Vinod Koul 2019-04-29 14:05 ` [PATCH 4/7] " Vinod Koul 2019-04-30 5:30 ` [4/7] " Baolin Wang 2019-04-30 5:30 ` [PATCH 4/7] " Baolin Wang 2019-04-30 8:29 ` [4/7] " Vinod Koul 2019-04-30 8:29 ` [PATCH 4/7] " Vinod Koul 2019-04-30 8:34 ` [4/7] " Baolin Wang 2019-04-30 8:34 ` [PATCH 4/7] " Baolin Wang 2019-04-30 8:53 ` [4/7] " Baolin Wang 2019-04-30 8:53 ` [PATCH 4/7] " Baolin Wang 2019-05-02 6:01 ` [4/7] " Vinod Koul 2019-05-02 6:01 ` [PATCH 4/7] " Vinod Koul 2019-05-06 4:48 ` Baolin Wang
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