[RFC PATCH v6 0/2] arch: riscv: cpu: Add callback to init each core

[RFC PATCH v6 0/2] arch: riscv: cpu: Add callback to init each core

[Green Wan]

Add a callback interface, harts_early_init() to perform proprietary or
customized CRSs configuration for each hart. harts_early_init() is placed
after stack of harts are initialized and before main boot hart is picked up.
Several conditions should be aware of or avoided are listed:

  - cannot access gd
    At the moment, gd hasn't initialized yet.

  - all operations in harts_early_init() should only affect core itself
    For example, the operations for board level should be moved to mach_xxx()
    or board_init_xxx() functions instead.

  - Common resource need protection if multicore
    Since all harts might enter harts_early_init() in parallel, common
    resource need a mechanism to handle race condition.

  - A reference implementation is added in ./arch/riscv/cpu/cpu.c
    The implementation is declared with '__weak' and can be overridden.

Changelogs:
v6
  - revised the description in both of commit message and comment [1/2]
  - moved the implementation of harts_early_init() in [2/2] from
    board/sifive/unmatched/spl.c to arch/riscv/cpu/fu740/spl.c. and revised
    commit message
v5
  - rename riscv_hart_early_init to harts_early_init
  - rephrase dummy for harts_early_init() to callback but keep current
    comments not specific for customizing CSRs only.
  - Fix nit in [2/2] and add reviewed-by
v4
  - Revising the comments for riscv_hart_early_init() in [1/2]
  - Remove unnecessary braces and add reviewed-by in [2/2]

Green Wan (2):
  arch: riscv: cpu: Add callback to init each core
  board: sifive: unmatched: clear feature disable CSR

 arch/riscv/cpu/cpu.c       | 11 +++++++++++
 arch/riscv/cpu/fu740/spl.c | 15 +++++++++++++++
 arch/riscv/cpu/start.S     |  8 ++++++++
 3 files changed, 34 insertions(+)

-- 
2.31.0

[RFC PATCH v6 1/2] arch: riscv: cpu: Add callback to init each core

[Green Wan]

Add a callback harts_early_init() to start.S to allow different riscv
hart perform setup code for each hart as early as possible. Since all
the harts enter the callback, they must be able to run the same
setup.

Signed-off-by: Green Wan <green.wan@sifive.com>
---
 arch/riscv/cpu/cpu.c   | 11 +++++++++++
 arch/riscv/cpu/start.S |  8 ++++++++
 2 files changed, 19 insertions(+)

diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 85592f5bee..43c086ca19 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -140,3 +140,14 @@ int arch_early_init_r(void)
 {
 	return riscv_cpu_probe();
 }
+
+/**
+ * harts_early_init() - A callback function called by start.S to configure
+ * feature settings of each hart.
+ *
+ * In a multi-core system, memory access shall be careful here, it shall
+ * take care race conditions.
+ */
+__weak void harts_early_init(void)
+{
+}
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 8589509e01..42fc1a4406 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -117,6 +117,14 @@ call_board_init_f_0:
 	mv	sp, a0
 #endif
 
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+	/*
+	 * Configure proprietary settings and customized CRSs of harts
+	 */
+call_harts_early_init:
+	jal	harts_early_init
+#endif
+
 #ifndef CONFIG_XIP
 	/*
 	 * Pick hart to initialize global data and run U-Boot. The other harts
-- 
2.31.0

[RFC PATCH v6 2/2] arch: riscv: cpu: fu740: clear feature disable CSR

[Green Wan]

Clear feature disable CSR to turn on all features of hart. The detail
is specified at section, 'SiFive Feature Disable CSR', in user manual

https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf

Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 arch/riscv/cpu/fu740/spl.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/riscv/cpu/fu740/spl.c b/arch/riscv/cpu/fu740/spl.c
index ea0b2283a2..55e30346ff 100644
--- a/arch/riscv/cpu/fu740/spl.c
+++ b/arch/riscv/cpu/fu740/spl.c
@@ -6,6 +6,9 @@
 
 #include <dm.h>
 #include <log.h>
+#include <asm/csr.h>
+
+#define CSR_U74_FEATURE_DISABLE	0x7c1
 
 int spl_soc_init(void)
 {
@@ -21,3 +24,15 @@ int spl_soc_init(void)
 
 	return 0;
 }
+
+void harts_early_init(void)
+{
+	/*
+	 * Feature Disable CSR
+	 *
+	 * Clear feature disable CSR to '0' to turn on all features for
+	 * each core. This operation must be in M-mode.
+	 */
+	if (CONFIG_IS_ENABLED(RISCV_MMODE))
+		csr_write(CSR_U74_FEATURE_DISABLE, 0);
+}
-- 
2.31.0

[RFC PATCH v6 1/2] arch: riscv: cpu: Add callback to init each core

[Rick Chen]

> From: Green Wan [mailto:green.wan at sifive.com]
> Sent: Thursday, April 15, 2021 4:45 PM
> Cc: Green Wan; Rick Jian-Zhi Chen(???); Sean Anderson; Bin Meng; Simon Glass; Pragnesh Patel; Jagan Teki; Atish Patra; Leo Yu-Chi Liang(???); Brad Kim; u-boot at lists.denx.de
> Subject: [RFC PATCH v6 1/2] arch: riscv: cpu: Add callback to init each core

nitpicky, arch is redundant in title.

riscv: cpu: Add callback to init each core
will be fine.

>
> Add a callback harts_early_init() to start.S to allow different riscv
> hart perform setup code for each hart as early as possible. Since all
> the harts enter the callback, they must be able to run the same
> setup.
>
> Signed-off-by: Green Wan <green.wan@sifive.com>
> ---
>  arch/riscv/cpu/cpu.c   | 11 +++++++++++
>  arch/riscv/cpu/start.S |  8 ++++++++
>  2 files changed, 19 insertions(+)
>
> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> index 85592f5bee..43c086ca19 100644
> --- a/arch/riscv/cpu/cpu.c
> +++ b/arch/riscv/cpu/cpu.c
> @@ -140,3 +140,14 @@ int arch_early_init_r(void)
>  {
>         return riscv_cpu_probe();
>  }
> +
> +/**
> + * harts_early_init() - A callback function called by start.S to configure
> + * feature settings of each hart.
> + *
> + * In a multi-core system, memory access shall be careful here, it shall
> + * take care race conditions.
> + */
> +__weak void harts_early_init(void)
> +{
> +}
> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> index 8589509e01..42fc1a4406 100644
> --- a/arch/riscv/cpu/start.S
> +++ b/arch/riscv/cpu/start.S
> @@ -117,6 +117,14 @@ call_board_init_f_0:
>         mv      sp, a0
>  #endif
>
> +#if CONFIG_IS_ENABLED(RISCV_MMODE)

This M-mode check can be remove, it is a repeat confirmation in
harts_early_init() of arch/riscv/cpu/fu740/spl.c

Other than that,

Reviewed-by: Rick Chen <rick@andestech.com>

> +       /*
> +        * Configure proprietary settings and customized CRSs of harts
> +        */
> +call_harts_early_init:
> +       jal     harts_early_init
> +#endif
> +
>  #ifndef CONFIG_XIP
>         /*
>          * Pick hart to initialize global data and run U-Boot. The other harts
> --
> 2.31.0

[RFC PATCH v6 2/2] arch: riscv: cpu: fu740: clear feature disable CSR

[Rick Chen]

> From: Green Wan [mailto:green.wan at sifive.com]
> Sent: Thursday, April 15, 2021 4:45 PM
> Cc: Green Wan; Sean Anderson; Bin Meng; Rick Jian-Zhi Chen(???); Bin Meng; Simon Glass; Pragnesh Patel; Jagan Teki; Atish Patra; Leo Yu-Chi Liang(???); u-boot at lists.denx.de
> Subject: [RFC PATCH v6 2/2] arch: riscv: cpu: fu740: clear feature disable CSR
>

nitpicky: arch

> Clear feature disable CSR to turn on all features of hart. The detail
> is specified at section, 'SiFive Feature Disable CSR', in user manual
>
> https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf
>
> Signed-off-by: Green Wan <green.wan@sifive.com>
> Reviewed-by: Sean Anderson <seanga2@gmail.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>  arch/riscv/cpu/fu740/spl.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)

Reviewed-by: Rick Chen <rick@andestech.com>