[PATCH v2 00/16] riscv: k210: Enable use of AI ram bank

[PATCH v2 00/16] riscv: k210: Enable use of AI ram bank

[Sean Anderson]

This ram bank was previously unusable because PLL1 was not started correctly.
This series fixes that bug, and allows U-Boot to relocate into the AI ram. This
provides an extra 2M of space in which to load payloads.

Second time around and I realized that the bypass clock is no longer necessary
(yay). This also necessitates a few more small fixups. I've also added some
minor patches to bring the device tree and clock driver closer to what Linux has
(or will have). This should be the last round of additions to this series.

Changes in v2:
- Don't re-enable the PLL
- Remove bypass clock, which is no longer necessary
- Simplify PLL instantiation
- Modify clock tree so clint is a child of aclk
- Sync memory dts node with Linux
- Use correct aisram clock

Sean Anderson (16):
  clk: k210: Fix PLLs not being enabled
  clk: k210: Fix PLL enable always getting taken
  clk: k210: Remove bypass clock
  clk: k210: Remove k210_register_pll
  clk: k210: Move the clint clock to under aclk
  clk: Add support for the k210 clock driver pre-relocation
  riscv: Enable some devices pre-relocation
  lib: fdt: Add fdtdec_setup_mem_size_base_highest
  test: Add a test for fdtdec_setup_mem_size_base et al.
  ram: Add driver for K210 SRAM
  ram: sifive: Default to y only if compiling for fu540
  riscv: Probe ram in dram_init
  riscv: Enable AI ram on K210
  riscv: k210: Rename airam to aisram
  riscv: k210: Use AI as the parent clock of aisram, not PLL1
  riscv: Don't reserve AI ram in k210 dts

 MAINTAINERS                        |   1 +
 arch/riscv/cpu/generic/dram.c      |  26 +++
 arch/riscv/dts/k210.dtsi           |  22 +--
 arch/sandbox/dts/test.dts          |  12 ++
 board/sipeed/maix/Kconfig          |   2 +
 board/sipeed/maix/maix.c           |  26 ---
 configs/sandbox64_defconfig        |   2 +-
 configs/sandbox_defconfig          |   2 +-
 configs/sandbox_flattree_defconfig |   2 +-
 configs/sipeed_maix_bitm_defconfig |   1 +
 drivers/clk/kendryte/Makefile      |   2 +-
 drivers/clk/kendryte/bypass.c      | 273 -----------------------------
 drivers/clk/kendryte/clk.c         |  61 +++----
 drivers/clk/kendryte/pll.c         |  26 +--
 drivers/ram/Kconfig                |   7 +
 drivers/ram/Makefile               |   1 +
 drivers/ram/kendryte.c             |  56 ++++++
 drivers/ram/sifive/Kconfig         |   2 +-
 include/configs/sipeed-maix.h      |   4 -
 include/fdtdec.h                   |  19 +-
 include/kendryte/bypass.h          |  31 ----
 include/kendryte/pll.h             |   4 -
 lib/fdtdec.c                       |  34 +++-
 test/dm/fdtdec.c                   |  38 ++++
 24 files changed, 230 insertions(+), 424 deletions(-)
 delete mode 100644 drivers/clk/kendryte/bypass.c
 create mode 100644 drivers/ram/kendryte.c
 delete mode 100644 include/kendryte/bypass.h

-- 
2.28.0

[PATCH v2 01/16] clk: k210: Fix PLLs not being enabled

[Sean Anderson]

After starting or setting the rate of a PLL, the enable bit must be set.

This fixes a bug where the AI ram would not be accessible, because it
requires PLL1 to be running.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---

(no changes since v1)

 drivers/clk/kendryte/pll.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/kendryte/pll.c b/drivers/clk/kendryte/pll.c
index ab6d75d585..f198920113 100644
--- a/drivers/clk/kendryte/pll.c
+++ b/drivers/clk/kendryte/pll.c
@@ -531,6 +531,7 @@ static int k210_pll_enable(struct clk *clk)
 	k210_pll_waitfor_lock(pll);
 
 	reg &= ~K210_PLL_BYPASS;
+	reg |= K210_PLL_EN;
 	writel(reg, pll->reg);
 
 	return 0;
@@ -550,6 +551,7 @@ static int k210_pll_disable(struct clk *clk)
 	writel(reg, pll->reg);
 
 	reg &= ~K210_PLL_PWRD;
+	reg &= ~K210_PLL_EN;
 	writel(reg, pll->reg);
 	return 0;
 }
-- 
2.28.0

[PATCH v2 02/16] clk: k210: Fix PLL enable always getting taken

[Sean Anderson]

This conditional always evaluated as false, regardless of the value of reg.
Fix it so that it properly tests the bits in the PLL register. Also test
PLL_EN, now that we set it.

Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com>
Signed-off-by: Sean Anderson <seanga2@gmail.com>
---

Changes in v2:
- New

 drivers/clk/kendryte/pll.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/kendryte/pll.c b/drivers/clk/kendryte/pll.c
index f198920113..d46fd0ebbf 100644
--- a/drivers/clk/kendryte/pll.c
+++ b/drivers/clk/kendryte/pll.c
@@ -512,7 +512,8 @@ static int k210_pll_enable(struct clk *clk)
 	struct k210_pll *pll = to_k210_pll(clk);
 	u32 reg = readl(pll->reg);
 
-	if ((reg | K210_PLL_PWRD) && !(reg | K210_PLL_RESET))
+	if ((reg & K210_PLL_PWRD) && (reg & K210_PLL_EN) &&
+	    !(reg & K210_PLL_RESET))
 		return 0;
 
 	reg |= K210_PLL_PWRD;
-- 
2.28.0

[PATCH v2 03/16] clk: k210: Remove bypass clock

[Sean Anderson]

Now that the PLLs get properly enabled, the bypass clock is no longer
necessary.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---

Changes in v2:
- New

 drivers/clk/kendryte/Makefile |   2 +-
 drivers/clk/kendryte/bypass.c | 273 ----------------------------------
 drivers/clk/kendryte/clk.c    |  43 ++----
 include/kendryte/bypass.h     |  31 ----
 4 files changed, 15 insertions(+), 334 deletions(-)
 delete mode 100644 drivers/clk/kendryte/bypass.c
 delete mode 100644 include/kendryte/bypass.h

diff --git a/drivers/clk/kendryte/Makefile b/drivers/clk/kendryte/Makefile
index 6fb68253ae..d26bce954f 100644
--- a/drivers/clk/kendryte/Makefile
+++ b/drivers/clk/kendryte/Makefile
@@ -1 +1 @@
-obj-y += bypass.o clk.o pll.o
+obj-y += clk.o pll.o
diff --git a/drivers/clk/kendryte/bypass.c b/drivers/clk/kendryte/bypass.c
deleted file mode 100644
index 5f1986f2cb..0000000000
--- a/drivers/clk/kendryte/bypass.c
+++ /dev/null
@@ -1,273 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
- */
-
-#define LOG_CATEGORY UCLASS_CLK
-
-#include <common.h>
-#include <clk.h>
-#include <clk-uclass.h>
-#include <dm.h>
-#include <log.h>
-#include <kendryte/bypass.h>
-#include <linux/clk-provider.h>
-#include <linux/err.h>
-
-#define CLK_K210_BYPASS "k210_clk_bypass"
-
-/*
- * This is a small driver to do a software bypass of a clock if hardware bypass
- * is not working. I have tried to write this in a generic fashion, so that it
- * could be potentially broken out of the kendryte code at some future date.
- *
- * Say you have the following clock configuration
- *
- * +---+ +---+
- * |osc| |pll|
- * +---+ +---+
- *         ^
- *        /|
- *       / |
- *      /  |
- *     /   |
- *    /    |
- * +---+ +---+
- * |clk| |clk|
- * +---+ +---+
- *
- * But the pll does not have a bypass, so when you configure the pll, the
- * configuration needs to change to look like
- *
- * +---+ +---+
- * |osc| |pll|
- * +---+ +---+
- *   ^
- *   |\
- *   | \
- *   |  \
- *   |   \
- *   |    \
- * +---+ +---+
- * |clk| |clk|
- * +---+ +---+
- *
- * To set this up, create a bypass clock with bypassee=pll and alt=osc. When
- * creating the child clocks, set their parent to the bypass clock. After
- * creating all the children, call k210_bypass_setchildren().
- */
-
-static int k210_bypass_dobypass(struct k210_bypass *bypass)
-{
-	int ret, i;
-
-	/*
-	 * If we already have saved parents, then the children are already
-	 * bypassed
-	 */
-	if (bypass->child_count && bypass->saved_parents[0])
-		return 0;
-
-	for (i = 0; i < bypass->child_count; i++) {
-		struct clk *child = bypass->children[i];
-		struct clk *parent = clk_get_parent(child);
-
-		if (IS_ERR(parent)) {
-			for (; i; i--)
-				bypass->saved_parents[i] = NULL;
-			return PTR_ERR(parent);
-		}
-		bypass->saved_parents[i] = parent;
-	}
-
-	for (i = 0; i < bypass->child_count; i++) {
-		struct clk *child = bypass->children[i];
-
-		ret = clk_set_parent(child, bypass->alt);
-		if (ret) {
-			for (; i; i--)
-				clk_set_parent(bypass->children[i],
-					       bypass->saved_parents[i]);
-			for (i = 0; i < bypass->child_count; i++)
-				bypass->saved_parents[i] = NULL;
-			return ret;
-		}
-	}
-
-	return 0;
-}
-
-static int k210_bypass_unbypass(struct k210_bypass *bypass)
-{
-	int err, ret, i;
-
-	if (!bypass->child_count && !bypass->saved_parents[0]) {
-		log_warning("Cannot unbypass children; dobypass not called first\n");
-		return 0;
-	}
-
-	ret = 0;
-	for (i = 0; i < bypass->child_count; i++) {
-		err = clk_set_parent(bypass->children[i],
-				     bypass->saved_parents[i]);
-		if (err)
-			ret = err;
-		bypass->saved_parents[i] = NULL;
-	}
-	return ret;
-}
-
-static ulong k210_bypass_get_rate(struct clk *clk)
-{
-	struct k210_bypass *bypass = to_k210_bypass(clk);
-	const struct clk_ops *ops = bypass->bypassee_ops;
-
-	if (ops->get_rate)
-		return ops->get_rate(bypass->bypassee);
-	else
-		return clk_get_parent_rate(bypass->bypassee);
-}
-
-static ulong k210_bypass_set_rate(struct clk *clk, unsigned long rate)
-{
-	int ret;
-	struct k210_bypass *bypass = to_k210_bypass(clk);
-	const struct clk_ops *ops = bypass->bypassee_ops;
-
-	/* Don't bother bypassing if we aren't going to set the rate */
-	if (!ops->set_rate)
-		return k210_bypass_get_rate(clk);
-
-	ret = k210_bypass_dobypass(bypass);
-	if (ret)
-		return ret;
-
-	ret = ops->set_rate(bypass->bypassee, rate);
-	if (ret < 0)
-		return ret;
-
-	return k210_bypass_unbypass(bypass);
-}
-
-static int k210_bypass_set_parent(struct clk *clk, struct clk *parent)
-{
-	struct k210_bypass *bypass = to_k210_bypass(clk);
-	const struct clk_ops *ops = bypass->bypassee_ops;
-
-	if (ops->set_parent)
-		return ops->set_parent(bypass->bypassee, parent);
-	else
-		return -ENOTSUPP;
-}
-
-/*
- * For these next two functions, do the bypassing even if there is no
- * en-/-disable function, since the bypassing itself can be observed in between
- * calls.
- */
-static int k210_bypass_enable(struct clk *clk)
-{
-	int ret;
-	struct k210_bypass *bypass = to_k210_bypass(clk);
-	const struct clk_ops *ops = bypass->bypassee_ops;
-
-	ret = k210_bypass_dobypass(bypass);
-	if (ret)
-		return ret;
-
-	if (ops->enable)
-		ret = ops->enable(bypass->bypassee);
-	else
-		ret = 0;
-	if (ret)
-		return ret;
-
-	return k210_bypass_unbypass(bypass);
-}
-
-static int k210_bypass_disable(struct clk *clk)
-{
-	int ret;
-	struct k210_bypass *bypass = to_k210_bypass(clk);
-	const struct clk_ops *ops = bypass->bypassee_ops;
-
-	ret = k210_bypass_dobypass(bypass);
-	if (ret)
-		return ret;
-
-	if (ops->disable)
-		return ops->disable(bypass->bypassee);
-	else
-		return 0;
-}
-
-static const struct clk_ops k210_bypass_ops = {
-	.get_rate = k210_bypass_get_rate,
-	.set_rate = k210_bypass_set_rate,
-	.set_parent = k210_bypass_set_parent,
-	.enable = k210_bypass_enable,
-	.disable = k210_bypass_disable,
-};
-
-int k210_bypass_set_children(struct clk *clk, struct clk **children,
-			     size_t child_count)
-{
-	struct k210_bypass *bypass = to_k210_bypass(clk);
-
-	kfree(bypass->saved_parents);
-	if (child_count) {
-		bypass->saved_parents =
-			kcalloc(child_count, sizeof(struct clk *), GFP_KERNEL);
-		if (!bypass->saved_parents)
-			return -ENOMEM;
-	}
-	bypass->child_count = child_count;
-	bypass->children = children;
-
-	return 0;
-}
-
-struct clk *k210_register_bypass_struct(const char *name,
-					const char *parent_name,
-					struct k210_bypass *bypass)
-{
-	int ret;
-	struct clk *clk;
-
-	clk = &bypass->clk;
-
-	ret = clk_register(clk, CLK_K210_BYPASS, name, parent_name);
-	if (ret)
-		return ERR_PTR(ret);
-
-	bypass->bypassee->dev = clk->dev;
-	return clk;
-}
-
-struct clk *k210_register_bypass(const char *name, const char *parent_name,
-				 struct clk *bypassee,
-				 const struct clk_ops *bypassee_ops,
-				 struct clk *alt)
-{
-	struct clk *clk;
-	struct k210_bypass *bypass;
-
-	bypass = kzalloc(sizeof(*bypass), GFP_KERNEL);
-	if (!bypass)
-		return ERR_PTR(-ENOMEM);
-
-	bypass->bypassee = bypassee;
-	bypass->bypassee_ops = bypassee_ops;
-	bypass->alt = alt;
-
-	clk = k210_register_bypass_struct(name, parent_name, bypass);
-	if (IS_ERR(clk))
-		kfree(bypass);
-	return clk;
-}
-
-U_BOOT_DRIVER(k210_bypass) = {
-	.name	= CLK_K210_BYPASS,
-	.id	= UCLASS_CLK,
-	.ops	= &k210_bypass_ops,
-};
diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
index bb196961af..e657efc572 100644
--- a/drivers/clk/kendryte/clk.c
+++ b/drivers/clk/kendryte/clk.c
@@ -11,7 +11,6 @@
 #include <log.h>
 #include <mapmem.h>
 
-#include <kendryte/bypass.h>
 #include <kendryte/pll.h>
 
 /* All methods are delegated to CCF clocks */
@@ -347,10 +346,6 @@ static const struct k210_comp_params k210_comps[] = {
 #undef COMP_NOMUX_ID
 #undef COMP_LIST
 
-static struct clk *k210_bypass_children = {
-	NULL,
-};
-
 /* Helper functions to create sub-clocks */
 static struct clk_mux *k210_create_mux(const struct k210_mux_params *params,
 				       void *base)
@@ -482,7 +477,7 @@ static int k210_clk_probe(struct udevice *dev)
 {
 	int ret;
 	const char *in0;
-	struct clk *in0_clk, *bypass;
+	struct clk *in0_clk;
 	struct clk_mux *mux;
 	struct clk_divider *div;
 	struct k210_pll *pll;
@@ -516,17 +511,13 @@ static int k210_clk_probe(struct udevice *dev)
 	aclk_sels[0] = in0;
 	pll2_sels[0] = in0;
 
-	/*
-	 * All PLLs have a broken bypass, but pll0 has the CPU downstream, so we
-	 * need to manually reparent it whenever we configure pll0
-	 */
-	pll = k210_create_pll(&k210_plls[0], base);
-	if (pll) {
-		bypass = k210_register_bypass("pll0", in0, &pll->clk,
-					      &k210_pll_ops, in0_clk);
-		clk_dm(K210_CLK_PLL0, bypass);
-	} else {
-		return -ENOMEM;
+	{
+		const struct k210_pll_params *params = &k210_plls[0];
+
+		clk_dm(K210_CLK_PLL0,
+		       k210_register_pll("pll0", in0, base + params->off,
+					 base + params->lock_off, params->shift,
+					 params->width));
 	}
 
 	{
@@ -565,18 +556,12 @@ static int k210_clk_probe(struct udevice *dev)
 		free(mux);
 		free(div);
 	} else {
-		struct clk *aclk =
-			clk_register_composite(NULL, "aclk", aclk_sels,
-					       ARRAY_SIZE(aclk_sels),
-					       &mux->clk, &clk_mux_ops,
-					       &div->clk, &clk_divider_ops,
-					       NULL, NULL, 0);
-		clk_dm(K210_CLK_ACLK, aclk);
-		if (!IS_ERR(aclk)) {
-			k210_bypass_children = aclk;
-			k210_bypass_set_children(bypass,
-						 &k210_bypass_children, 1);
-		}
+		clk_dm(K210_CLK_ACLK,
+		       clk_register_composite(NULL, "aclk", aclk_sels,
+					      ARRAY_SIZE(aclk_sels),
+					      &mux->clk, &clk_mux_ops,
+					      &div->clk, &clk_divider_ops,
+					      NULL, NULL, 0));
 	}
 
 #define REGISTER_COMP(id, name) \
diff --git a/include/kendryte/bypass.h b/include/kendryte/bypass.h
deleted file mode 100644
index ab85bbcbfc..0000000000
--- a/include/kendryte/bypass.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
- */
-#ifndef K210_BYPASS_H
-#define K210_BYPASS_H
-
-struct clk;
-
-struct k210_bypass {
-	struct clk clk;
-	struct clk **children; /* Clocks to reparent */
-	struct clk **saved_parents; /* Parents saved over en-/dis-able */
-	struct clk *bypassee; /* Clock to bypass */
-	const struct clk_ops *bypassee_ops; /* Ops of the bypass clock */
-	struct clk *alt; /* Clock to set children to when bypassing */
-	size_t child_count;
-};
-
-#define to_k210_bypass(_clk) container_of(_clk, struct k210_bypass, clk)
-
-int k210_bypass_set_children(struct clk *clk, struct clk **children,
-			     size_t child_count);
-struct clk *k210_register_bypass_struct(const char *name,
-					const char *parent_name,
-					struct k210_bypass *bypass);
-struct clk *k210_register_bypass(const char *name, const char *parent_name,
-				 struct clk *bypassee,
-				 const struct clk_ops *bypassee_ops,
-				 struct clk *alt);
-#endif /* K210_BYPASS_H */
-- 
2.28.0

[PATCH v2 04/16] clk: k210: Remove k210_register_pll

[Sean Anderson]

This simplifies the PLL creation process, since we don't have to pass all
the parameters individually.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---

Changes in v2:
- New

 drivers/clk/kendryte/clk.c | 20 ++++++--------------
 drivers/clk/kendryte/pll.c | 21 ---------------------
 include/kendryte/pll.h     |  4 ----
 3 files changed, 6 insertions(+), 39 deletions(-)

diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
index e657efc572..88a997e80b 100644
--- a/drivers/clk/kendryte/clk.c
+++ b/drivers/clk/kendryte/clk.c
@@ -511,23 +511,15 @@ static int k210_clk_probe(struct udevice *dev)
 	aclk_sels[0] = in0;
 	pll2_sels[0] = in0;
 
-	{
-		const struct k210_pll_params *params = &k210_plls[0];
-
+	pll = k210_create_pll(&k210_plls[0], base);
+	if (pll)
 		clk_dm(K210_CLK_PLL0,
-		       k210_register_pll("pll0", in0, base + params->off,
-					 base + params->lock_off, params->shift,
-					 params->width));
-	}
-
-	{
-		const struct k210_pll_params *params = &k210_plls[1];
+		       k210_register_pll_struct("pll0", in0, pll));
 
+	pll = k210_create_pll(&k210_plls[1], base);
+	if (pll)
 		clk_dm(K210_CLK_PLL1,
-		       k210_register_pll("pll1", in0, base + params->off,
-					 base + params->lock_off, params->shift,
-					 params->width));
-	}
+		       k210_register_pll_struct("pll1", in0, pll));
 
 	/* PLL2 is muxed, so set up a composite clock */
 	mux = k210_create_mux(&k210_muxes[MUXIFY(K210_CLK_PLL2)], base);
diff --git a/drivers/clk/kendryte/pll.c b/drivers/clk/kendryte/pll.c
index d46fd0ebbf..184f37aaf2 100644
--- a/drivers/clk/kendryte/pll.c
+++ b/drivers/clk/kendryte/pll.c
@@ -578,27 +578,6 @@ struct clk *k210_register_pll_struct(const char *name, const char *parent_name,
 	return clk;
 }
 
-struct clk *k210_register_pll(const char *name, const char *parent_name,
-			      void __iomem *reg, void __iomem *lock, u8 shift,
-			      u8 width)
-{
-	struct clk *clk;
-	struct k210_pll *pll;
-
-	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
-	if (!pll)
-		return ERR_PTR(-ENOMEM);
-	pll->reg = reg;
-	pll->lock = lock;
-	pll->shift = shift;
-	pll->width = width;
-
-	clk = k210_register_pll_struct(name, parent_name, pll);
-	if (IS_ERR(clk))
-		kfree(pll);
-	return clk;
-}
-
 U_BOOT_DRIVER(k210_pll) = {
 	.name	= CLK_K210_PLL,
 	.id	= UCLASS_CLK,
diff --git a/include/kendryte/pll.h b/include/kendryte/pll.h
index 55a40b9c97..95b8494f40 100644
--- a/include/kendryte/pll.h
+++ b/include/kendryte/pll.h
@@ -55,8 +55,4 @@ extern const struct clk_ops k210_pll_ops;
 
 struct clk *k210_register_pll_struct(const char *name, const char *parent_name,
 				     struct k210_pll *pll);
-struct clk *k210_register_pll(const char *name, const char *parent_name,
-			      void __iomem *reg, void __iomem *lock, u8 shift,
-			      u8 width);
-
 #endif /* K210_PLL_H */
-- 
2.28.0

[PATCH v2 05/16] clk: k210: Move the clint clock to under aclk

[Sean Anderson]

No other (real) clocks have the cpu clock as their parent; instead they are
children of aclk. Move the clint clock under aclk to match them.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---

Changes in v2:
- New

 drivers/clk/kendryte/clk.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
index 88a997e80b..28e21d0bf9 100644
--- a/drivers/clk/kendryte/clk.c
+++ b/drivers/clk/kendryte/clk.c
@@ -625,7 +625,7 @@ static int k210_clk_probe(struct udevice *dev)
 
 	/* The MTIME register in CLINT runs at one 50th the CPU clock speed */
 	clk_dm(K210_CLK_CLINT,
-	       clk_register_fixed_factor(NULL, "clint", "cpu", 0, 1, 50));
+	       clk_register_fixed_factor(NULL, "clint", "aclk", 0, 1, 50));
 
 	return 0;
 }
-- 
2.28.0

[PATCH v2 06/16] clk: Add support for the k210 clock driver pre-relocation

[Sean Anderson]

Variables which had previously been stored in .bss are moved to .data. In
addition, probed needs to be reset when the clock driver is re-bound
post-relocation.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---

(no changes since v1)

 drivers/clk/kendryte/clk.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
index 28e21d0bf9..3e4818e9ef 100644
--- a/drivers/clk/kendryte/clk.c
+++ b/drivers/clk/kendryte/clk.c
@@ -471,7 +471,14 @@ cleanup_mux:
 	return comp;
 }
 
-static bool probed;
+static bool __section(.data) probed;
+
+/* reset probed so we will probe again post-relocation */
+static int k210_clk_bind(struct udevice *dev)
+{
+	probed = false;
+	return 0;
+}
 
 static int k210_clk_probe(struct udevice *dev)
 {
@@ -640,5 +647,6 @@ U_BOOT_DRIVER(k210_clk) = {
 	.id = UCLASS_CLK,
 	.of_match = k210_clk_ids,
 	.ops = &k210_clk_ops,
+	.bind = k210_clk_bind,
 	.probe = k210_clk_probe,
 };
-- 
2.28.0

[PATCH v2 07/16] riscv: Enable some devices pre-relocation

[Sean Anderson]

These devices are necessary for the clock driver, which is required by the
sram driver, to run pre-relocation.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---

(no changes since v1)

 arch/riscv/dts/k210.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi
index 7605c01f3c..86d50f14e5 100644
--- a/arch/riscv/dts/k210.dtsi
+++ b/arch/riscv/dts/k210.dtsi
@@ -91,6 +91,7 @@
 			 <&sysclk K210_CLK_SRAM1>,
 			 <&sysclk K210_CLK_PLL1>;
 		clock-names = "sram0", "sram1", "airam";
+		u-boot,dm-pre-reloc;
 	};
 
 	reserved-memory {
@@ -109,6 +110,7 @@
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <26000000>;
+			u-boot,dm-pre-reloc;
 		};
 	};
 
@@ -503,11 +505,13 @@
 					     "syscon", "simple-mfd";
 				reg = <0x50440000 0x100>;
 				reg-io-width = <4>;
+				u-boot,dm-pre-reloc;
 
 				sysclk: clock-controller {
 					#clock-cells = <1>;
 					compatible = "kendryte,k210-clk";
 					clocks = <&in0>;
+					u-boot,dm-pre-reloc;
 				};
 
 				sysrst: reset-controller {
-- 
2.28.0

[PATCH v2 08/16] lib: fdt: Add fdtdec_setup_mem_size_base_highest

[Sean Anderson]

This is very similar to fdtdec_setup_mem_size_base_lowest, except we pick
the highest ram bank, instead of the lowest. This is helpful for boards
which use separate but contiguous ram banks, as it leaves the most space
for loading programs.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---

(no changes since v1)

 include/fdtdec.h | 19 ++++++++++++++++++-
 lib/fdtdec.c     | 34 +++++++++++++++++++++++++++++-----
 2 files changed, 47 insertions(+), 6 deletions(-)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index 62d1660973..6a8e235674 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -944,7 +944,7 @@ int fdtdec_setup_mem_size_base(void);
  * gd->ram_start by lowest available memory base
  *
  * Decode the /memory 'reg' property to determine the lowest start of the memory
- * bank bank and populate the global data with it.
+ * bank and populate the global data with it.
  *
  * This function should be called from a boards dram_init(). This helper
  * function allows for boards to query the device tree for DRAM size and start
@@ -956,6 +956,23 @@ int fdtdec_setup_mem_size_base(void);
  */
 int fdtdec_setup_mem_size_base_lowest(void);
 
+/**
+ * fdtdec_setup_mem_size_base_highest() - decode and setup gd->ram_size and
+ * gd->ram_start by highest available memory top
+ *
+ * Decode the /memory 'reg' property to determine the highest end of the memory
+ * bank and populate the global data with it.
+ *
+ * This function should be called from a boards dram_init(). This helper
+ * function allows for boards to query the device tree for DRAM size and start
+ * address instead of hard coding the value in the case where the memory size
+ * and start address cannot be detected automatically.
+ *
+ * @return 0 if OK, -EINVAL if the /memory node or reg property is missing or
+ * invalid
+ */
+int fdtdec_setup_mem_size_base_highest(void);
+
 /**
  * fdtdec_setup_memory_banksize() - decode and populate gd->bd->bi_dram
  *
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index ee1bd41b08..78b34bf4da 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1123,7 +1123,7 @@ int fdtdec_setup_memory_banksize(void)
 	return 0;
 }
 
-int fdtdec_setup_mem_size_base_lowest(void)
+static int fdtdec_setup_mem_size_base_superlative(bool lowest)
 {
 	int bank, ret, reg = 0;
 	struct resource res;
@@ -1131,7 +1131,16 @@ int fdtdec_setup_mem_size_base_lowest(void)
 	phys_size_t size;
 	ofnode mem = ofnode_null();
 
-	gd->ram_base = (unsigned long)~0;
+	/*
+	 * Size must be 1 so we don't underflow when doing the subtraction below
+	 * when lowest = false. Hopefully any real ram banks will have a greater
+	 * size :)
+	 */
+	gd->ram_size = 1;
+	if (lowest)
+		gd->ram_base = (unsigned long)~0;
+	else
+		gd->ram_base = 0;
 
 	mem = get_next_memory_node(mem);
 	if (!ofnode_valid(mem)) {
@@ -1158,17 +1167,32 @@ int fdtdec_setup_mem_size_base_lowest(void)
 		base = (unsigned long)res.start;
 		size = (phys_size_t)(res.end - res.start + 1);
 
-		if (gd->ram_base > base && size) {
+		if (!size)
+			continue;
+
+		if ((lowest && gd->ram_base > base) ||
+		    (!lowest && gd->ram_base + gd->ram_size - 1 < res.end)) {
 			gd->ram_base = base;
 			gd->ram_size = size;
-			debug("%s: Initial DRAM base %lx size %lx\n",
-			      __func__, base, (unsigned long)size);
 		}
 	}
 
+	if (gd->ram_size)
+		debug("%s: Initial DRAM base %lx size %lx\n", __func__,
+		      gd->ram_base, (unsigned long)gd->ram_size);
 	return 0;
 }
 
+int fdtdec_setup_mem_size_base_lowest(void)
+{
+	return fdtdec_setup_mem_size_base_superlative(true);
+}
+
+int fdtdec_setup_mem_size_base_highest(void)
+{
+	return fdtdec_setup_mem_size_base_superlative(false);
+}
+
 #if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
 # if CONFIG_IS_ENABLED(MULTI_DTB_FIT_GZIP) ||\
 	CONFIG_IS_ENABLED(MULTI_DTB_FIT_LZO)
-- 
2.28.0

[PATCH v2 09/16] test: Add a test for fdtdec_setup_mem_size_base et al.

[Sean Anderson]

This adds a test for the various methods of extracting ram_base and
ram_size from a device tree.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---

(no changes since v1)

 arch/sandbox/dts/test.dts          | 12 ++++++++++
 configs/sandbox64_defconfig        |  2 +-
 configs/sandbox_defconfig          |  2 +-
 configs/sandbox_flattree_defconfig |  2 +-
 test/dm/fdtdec.c                   | 38 ++++++++++++++++++++++++++++++
 5 files changed, 53 insertions(+), 3 deletions(-)

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index c7d1376911..f13bbdca7d 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -1221,6 +1221,18 @@
 			compatible = "sandbox,regmap_test";
 		};
 	};
+
+	memory at 0000 {
+		device_type = "memory";
+		reg = <0x1000 0x2000>,
+		      <0x0000 0x1000>;
+	};
+
+	memory at 8000 {
+		device_type = "memory";
+		reg = <0x8000 0x0000>,
+		      <0x4000 0x3000>;
+	};
 };
 
 #include "sandbox_pmic.dtsi"
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index c3ca796d51..6324961cf1 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -1,5 +1,5 @@
 CONFIG_SYS_TEXT_BASE=0
-CONFIG_NR_DRAM_BANKS=1
+CONFIG_NR_DRAM_BANKS=4
 CONFIG_ENV_SIZE=0x2000
 CONFIG_PRE_CON_BUF_ADDR=0x100000
 CONFIG_BOOTSTAGE_STASH_ADDR=0x0
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 18f787cb51..2f2333febc 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -1,5 +1,5 @@
 CONFIG_SYS_TEXT_BASE=0
-CONFIG_NR_DRAM_BANKS=1
+CONFIG_NR_DRAM_BANKS=4
 CONFIG_ENV_SIZE=0x2000
 CONFIG_PRE_CON_BUF_ADDR=0xf0000
 CONFIG_BOOTSTAGE_STASH_ADDR=0x0
diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig
index dd93167e1b..a4941b54d3 100644
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -1,5 +1,5 @@
 CONFIG_SYS_TEXT_BASE=0
-CONFIG_NR_DRAM_BANKS=1
+CONFIG_NR_DRAM_BANKS=4
 CONFIG_ENV_SIZE=0x2000
 CONFIG_BOOTSTAGE_STASH_ADDR=0x0
 CONFIG_DEFAULT_DEVICE_TREE="sandbox"
diff --git a/test/dm/fdtdec.c b/test/dm/fdtdec.c
index 017157a2ec..00ccb8c615 100644
--- a/test/dm/fdtdec.c
+++ b/test/dm/fdtdec.c
@@ -131,3 +131,41 @@ static int dm_test_fdtdec_add_reserved_memory(struct unit_test_state *uts)
 }
 DM_TEST(dm_test_fdtdec_add_reserved_memory,
 	UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE);
+
+static int _dm_test_fdtdec_setup_mem(struct unit_test_state *uts)
+{
+	ut_assertok(fdtdec_setup_mem_size_base());
+	ut_asserteq(0x1000, gd->ram_base);
+	ut_asserteq(0x2000, gd->ram_size);
+
+	ut_assertok(fdtdec_setup_mem_size_base_lowest());
+	ut_asserteq(0x0000, gd->ram_base);
+	ut_asserteq(0x1000, gd->ram_size);
+
+	ut_assertok(fdtdec_setup_mem_size_base_highest());
+	ut_asserteq(0x4000, gd->ram_base);
+	ut_asserteq(0x3000, gd->ram_size);
+
+	return 0;
+}
+
+/*
+ * We need to wrap the actual test so that we don't overwrite the ram parameters
+ * for the rest of U-Boot
+ */
+static int dm_test_fdtdec_setup_mem(struct unit_test_state *uts)
+{
+	int ret;
+	unsigned long base, size;
+
+	base = gd->ram_base;
+	size = gd->ram_size;
+
+	ret = _dm_test_fdtdec_setup_mem(uts);
+
+	gd->ram_base = base;
+	gd->ram_size = size;
+
+	return ret;
+}
+DM_TEST(dm_test_fdtdec_setup_mem, UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE);
-- 
2.28.0

[PATCH v2 10/16] ram: Add driver for K210 SRAM

[Sean Anderson]

This adds a driver to handle enabling the clock for the AI SRAM. This was
previously done in board_init, but it needs to happen before relocation
now. An alternative would be to move this to board_init_early_f, but by
doing it this way we can use clk_bulk.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---

(no changes since v1)

 MAINTAINERS            |  1 +
 drivers/ram/Kconfig    |  7 ++++++
 drivers/ram/Makefile   |  1 +
 drivers/ram/kendryte.c | 56 ++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 65 insertions(+)
 create mode 100644 drivers/ram/kendryte.c

diff --git a/MAINTAINERS b/MAINTAINERS
index fb9ba37984..166acb30c2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -938,6 +938,7 @@ F:	doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt
 F:	doc/device-tree-bindings/pinctrl/kendryte,k210-fpioa.txt
 F:	drivers/clk/kendryte/
 F:	drivers/pinctrl/kendryte/
+F:	drivers/ram/kendryte.c
 F:	include/kendryte/
 
 RNG
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index a270e13b26..075e6b5cd7 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -73,6 +73,13 @@ config IMXRT_SDRAM
 	  to support external memories like sdram, psram & nand.
 	  This driver is for the sdram memory interface with the SEMC.
 
+config K210_SRAM
+	bool "Enable Kendryte K210 SRAM support"
+	depends on RAM
+	help
+	  The Kendryte K210 has three banks of SRAM. This driver does the
+	  necessary initialization.
+
 source "drivers/ram/aspeed/Kconfig"
 source "drivers/ram/rockchip/Kconfig"
 source "drivers/ram/sifive/Kconfig"
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 209a78c06f..fdc9bbeb1f 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_ARCH_ASPEED) += aspeed/
 obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
 
 obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
+obj-$(CONFIG_K210_SRAM) += kendryte.o
 
 obj-$(CONFIG_RAM_SIFIVE) += sifive/
 
diff --git a/drivers/ram/kendryte.c b/drivers/ram/kendryte.c
new file mode 100644
index 0000000000..50818bf005
--- /dev/null
+++ b/drivers/ram/kendryte.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <ram.h>
+
+static int k210_sram_probe(struct udevice *dev)
+{
+	int ret;
+	struct clk_bulk clocks;
+
+	/* Relocate as high as possible to leave more space to load payloads */
+	ret = fdtdec_setup_mem_size_base_highest();
+	if (ret)
+		return ret;
+
+	/* Enable ram bank clocks */
+	ret = clk_get_bulk(dev, &clocks);
+	if (ret)
+		return ret;
+
+	ret = clk_enable_bulk(&clocks);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int k210_sram_get_info(struct udevice *dev, struct ram_info *info)
+{
+	info->base = gd->ram_base;
+	info->size = gd->ram_size;
+
+	return 0;
+}
+
+static struct ram_ops k210_sram_ops = {
+	.get_info = k210_sram_get_info,
+};
+
+static const struct udevice_id k210_sram_ids[] = {
+	{ .compatible = "kendryte,k210-sram" },
+	{ }
+};
+
+U_BOOT_DRIVER(fu540_ddr) = {
+	.name = "k210_sram",
+	.id = UCLASS_RAM,
+	.of_match = k210_sram_ids,
+	.ops = &k210_sram_ops,
+	.probe = k210_sram_probe,
+};
-- 
2.28.0

[PATCH v2 11/16] ram: sifive: Default to y only if compiling for fu540

[Sean Anderson]

Other RISC-V targets should not have RAM_SIFIVE enabled by default.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>
---

(no changes since v1)

 drivers/ram/sifive/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ram/sifive/Kconfig b/drivers/ram/sifive/Kconfig
index 6aca22ab2a..b24153d971 100644
--- a/drivers/ram/sifive/Kconfig
+++ b/drivers/ram/sifive/Kconfig
@@ -1,7 +1,7 @@
 config RAM_SIFIVE
 	bool "Ram drivers support for SiFive SoCs"
 	depends on RAM && RISCV
-	default y
+	default y if TARGET_SIFIVE_FU540
 	help
 	  This enables support for ram drivers of SiFive SoCs.
 
-- 
2.28.0

[PATCH v2 12/16] riscv: Probe ram in dram_init

[Sean Anderson]

If CONFIG_RAM is enabled, use the ram device to get the base/size of
memory. This provides an easy way for boards/cpus to hook into the
dram_init logic, without needing to provide a second SYS_CPU.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---

(no changes since v1)

 arch/riscv/cpu/generic/dram.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c
index 1dc77efeca..fbcd4ddf5f 100644
--- a/arch/riscv/cpu/generic/dram.c
+++ b/arch/riscv/cpu/generic/dram.c
@@ -4,15 +4,41 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <fdtdec.h>
 #include <init.h>
+#include <log.h>
+#include <ram.h>
 #include <linux/sizes.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
+#if CONFIG_IS_ENABLED(RAM)
+	int ret;
+	struct ram_info info;
+	struct udevice *dev;
+
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		debug("DRAM init failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = ram_get_info(dev, &info);
+	if (ret) {
+		debug("Cannot get DRAM size: %d\n", ret);
+		return ret;
+	}
+
+	gd->ram_base = info.base;
+	gd->ram_size = info.size;
+
+	return 0;
+#else
 	return fdtdec_setup_mem_size_base();
+#endif
 }
 
 int dram_init_banksize(void)
-- 
2.28.0

[PATCH v2 13/16] riscv: Enable AI ram on K210

[Sean Anderson]

CONFIG_SYS_SDRAM_{BASE,SIZE} are no longer necessary. The default
get_effective_memsize will also work. The clock driver creates a bunch of
devices, so we need to increase the pre-reloc malloc arena.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---

(no changes since v1)

 board/sipeed/maix/Kconfig          |  2 ++
 board/sipeed/maix/maix.c           | 26 --------------------------
 configs/sipeed_maix_bitm_defconfig |  1 +
 include/configs/sipeed-maix.h      |  4 ----
 4 files changed, 3 insertions(+), 30 deletions(-)

diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig
index 4c42dd2087..ba61810079 100644
--- a/board/sipeed/maix/Kconfig
+++ b/board/sipeed/maix/Kconfig
@@ -42,6 +42,8 @@ config BOARD_SPECIFIC_OPTIONS
 	imply CLK_K210
 	imply DM_RESET
 	imply RESET_SYSCON
+	imply RAM
+	imply K210_SRAM
 	imply SYSRESET
 	imply SYSRESET_SYSCON
 	imply PINCTRL
diff --git a/board/sipeed/maix/maix.c b/board/sipeed/maix/maix.c
index cbcb23cf5c..1b6f8a5115 100644
--- a/board/sipeed/maix/maix.c
+++ b/board/sipeed/maix/maix.c
@@ -9,33 +9,7 @@
 #include <fdt_support.h>
 #include <asm/io.h>
 
-phys_size_t get_effective_memsize(void)
-{
-	return CONFIG_SYS_SDRAM_SIZE;
-}
-
 int board_init(void)
 {
-	int ret, i;
-	const char * const banks[] = { "sram0", "sram1", "airam" };
-	ofnode memory;
-	struct clk clk;
-
-	/* Enable RAM clocks */
-	memory = ofnode_by_compatible(ofnode_null(), "kendryte,k210-sram");
-	if (ofnode_equal(memory, ofnode_null()))
-		return -ENOENT;
-
-	for (i = 0; i < ARRAY_SIZE(banks); i++) {
-		ret = clk_get_by_name_nodev(memory, banks[i], &clk);
-		if (ret)
-			continue;
-
-		ret = clk_enable(&clk);
-		clk_free(&clk);
-		if (ret)
-			return ret;
-	}
-
 	return 0;
 }
diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig
index 459bf0d530..d0100ad9e9 100644
--- a/configs/sipeed_maix_bitm_defconfig
+++ b/configs/sipeed_maix_bitm_defconfig
@@ -1,4 +1,5 @@
 CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_F_LEN=0x10000
 CONFIG_TARGET_SIPEED_MAIX=y
 CONFIG_ARCH_RV64I=y
 CONFIG_STACK_SIZE=0x100000
diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h
index 36ff522e4b..81956cccfd 100644
--- a/include/configs/sipeed-maix.h
+++ b/include/configs/sipeed-maix.h
@@ -14,10 +14,6 @@
 #define CONFIG_SYS_MALLOC_LEN SZ_128K
 #define CONFIG_SYS_CACHELINE_SIZE 64
 
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
-/* Don't relocate into AI ram since it isn't set up yet */
-#define CONFIG_SYS_SDRAM_SIZE (SZ_4M + SZ_2M)
-
 /* For early init */
 #define K210_SYSCTL_BASE 0x50440000
 
-- 
2.28.0

[PATCH v2 14/16] riscv: k210: Rename airam to aisram

[Sean Anderson]

This is more consistent with the naming of other ram banks, and matches
what Linux is doing.

Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com>
Signed-off-by: Sean Anderson <seanga2@gmail.com>
---

Changes in v2:
- New

 arch/riscv/dts/k210.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi
index 86d50f14e5..05f345f683 100644
--- a/arch/riscv/dts/k210.dtsi
+++ b/arch/riscv/dts/k210.dtsi
@@ -86,11 +86,11 @@
 		reg = <0x80000000 0x400000>,
 		      <0x80400000 0x200000>,
 		      <0x80600000 0x200000>;
-		reg-names = "sram0", "sram1", "airam";
+		reg-names = "sram0", "sram1", "aisram";
 		clocks = <&sysclk K210_CLK_SRAM0>,
 			 <&sysclk K210_CLK_SRAM1>,
 			 <&sysclk K210_CLK_PLL1>;
-		clock-names = "sram0", "sram1", "airam";
+		clock-names = "sram0", "sram1", "aisram";
 		u-boot,dm-pre-reloc;
 	};
 
-- 
2.28.0

[PATCH v2 15/16] riscv: k210: Use AI as the parent clock of aisram, not PLL1

[Sean Anderson]

Testing showed that disabling AI while leaving PLL1 enabled disabled the
aisram. This suggests that AI is a more appropriate clock for that ram
bank.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---

Changes in v2:
- New

 arch/riscv/dts/k210.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi
index 05f345f683..600fce26af 100644
--- a/arch/riscv/dts/k210.dtsi
+++ b/arch/riscv/dts/k210.dtsi
@@ -89,7 +89,7 @@
 		reg-names = "sram0", "sram1", "aisram";
 		clocks = <&sysclk K210_CLK_SRAM0>,
 			 <&sysclk K210_CLK_SRAM1>,
-			 <&sysclk K210_CLK_PLL1>;
+			 <&sysclk K210_CLK_AI>;
 		clock-names = "sram0", "sram1", "aisram";
 		u-boot,dm-pre-reloc;
 	};
-- 
2.28.0

[PATCH v2 16/16] riscv: Don't reserve AI ram in k210 dts

[Sean Anderson]

It is no longer necessary to disallow ai ram, since it is enabled by the
sram driver.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---

(no changes since v1)

 arch/riscv/dts/k210.dtsi | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi
index 600fce26af..66dd438d50 100644
--- a/arch/riscv/dts/k210.dtsi
+++ b/arch/riscv/dts/k210.dtsi
@@ -94,17 +94,6 @@
 		u-boot,dm-pre-reloc;
 	};
 
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		ai_reserved: ai at 80600000 {
-			reg = <0x80600000 0x200000>;
-			reusable;
-		};
-	};
-
 	clocks {
 		in0: osc {
 			compatible = "fixed-clock";
@@ -179,7 +168,6 @@
 			reg = <0x40800000 0xc00000>;
 			interrupts = <25>;
 			clocks = <&sysclk K210_CLK_AI>;
-			memory-region = <&ai_reserved>;
 			status = "disabled";
 		};
 
-- 
2.28.0

[PATCH v2 01/16] clk: k210: Fix PLLs not being enabled

[Rick Chen]

> After starting or setting the rate of a PLL, the enable bit must be set.
>
> This fixes a bug where the AI ram would not be accessible, because it
> requires PLL1 to be running.
>
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> ---
>
> (no changes since v1)
>
>  drivers/clk/kendryte/pll.c | 2 ++
>  1 file changed, 2 insertions(+)
>

Reviewed-by: Rick Chen <rick@andestech.com>

[PATCH v2 02/16] clk: k210: Fix PLL enable always getting taken

[Rick Chen]

> This conditional always evaluated as false, regardless of the value of reg.
> Fix it so that it properly tests the bits in the PLL register. Also test
> PLL_EN, now that we set it.
>
> Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com>
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> ---
>
> Changes in v2:
> - New
>
>  drivers/clk/kendryte/pll.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>

Reviewed-by: Rick Chen <rick@andestech.com>

[PATCH v2 07/16] riscv: Enable some devices pre-relocation

[Rick Chen]

> These devices are necessary for the clock driver, which is required by the
> sram driver, to run pre-relocation.
>
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> ---
>
> (no changes since v1)
>
>  arch/riscv/dts/k210.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
>

Reviewed-by: Rick Chen <rick@andestech.com>

[PATCH v2 06/16] clk: Add support for the k210 clock driver pre-relocation

[Rick Chen]

> Variables which had previously been stored in .bss are moved to .data. In
> addition, probed needs to be reset when the clock driver is re-bound
> post-relocation.
>
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> ---
>
> (no changes since v1)
>
>  drivers/clk/kendryte/clk.c | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
>

Reviewed-by: Rick Chen <rick@andestech.com>

[PATCH v2 08/16] lib: fdt: Add fdtdec_setup_mem_size_base_highest

[Rick Chen]

> This is very similar to fdtdec_setup_mem_size_base_lowest, except we pick
> the highest ram bank, instead of the lowest. This is helpful for boards
> which use separate but contiguous ram banks, as it leaves the most space
> for loading programs.
>
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
>
> (no changes since v1)
>
>  include/fdtdec.h | 19 ++++++++++++++++++-
>  lib/fdtdec.c     | 34 +++++++++++++++++++++++++++++-----
>  2 files changed, 47 insertions(+), 6 deletions(-)
>

Reviewed-by: Rick Chen <rick@andestech.com>

[PATCH v2 10/16] ram: Add driver for K210 SRAM

[Rick Chen]

> This adds a driver to handle enabling the clock for the AI SRAM. This was
> previously done in board_init, but it needs to happen before relocation
> now. An alternative would be to move this to board_init_early_f, but by
> doing it this way we can use clk_bulk.
>
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
>
> (no changes since v1)
>
>  MAINTAINERS            |  1 +
>  drivers/ram/Kconfig    |  7 ++++++
>  drivers/ram/Makefile   |  1 +
>  drivers/ram/kendryte.c | 56 ++++++++++++++++++++++++++++++++++++++++++
>  4 files changed, 65 insertions(+)
>  create mode 100644 drivers/ram/kendryte.c
>

Reviewed-by: Rick Chen <rick@andestech.com>

[PATCH v2 11/16] ram: sifive: Default to y only if compiling for fu540

[Rick Chen]

> Other RISC-V targets should not have RAM_SIFIVE enabled by default.
>
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>
> ---
>
> (no changes since v1)
>
>  drivers/ram/sifive/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Rick Chen <rick@andestech.com>

[PATCH v2 12/16] riscv: Probe ram in dram_init

[Rick Chen]

> If CONFIG_RAM is enabled, use the ram device to get the base/size of
> memory. This provides an easy way for boards/cpus to hook into the
> dram_init logic, without needing to provide a second SYS_CPU.
>
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> ---
>
> (no changes since v1)
>
>  arch/riscv/cpu/generic/dram.c | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
>

Reviewed-by: Rick Chen <rick@andestech.com>

[PATCH v2 13/16] riscv: Enable AI ram on K210

[Rick Chen]

> CONFIG_SYS_SDRAM_{BASE,SIZE} are no longer necessary. The default
> get_effective_memsize will also work. The clock driver creates a bunch of
> devices, so we need to increase the pre-reloc malloc arena.
>
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> ---
>
> (no changes since v1)
>
>  board/sipeed/maix/Kconfig          |  2 ++
>  board/sipeed/maix/maix.c           | 26 --------------------------
>  configs/sipeed_maix_bitm_defconfig |  1 +
>  include/configs/sipeed-maix.h      |  4 ----
>  4 files changed, 3 insertions(+), 30 deletions(-)
>

Reviewed-by: Rick Chen <rick@andestech.com>

[PATCH v2 14/16] riscv: k210: Rename airam to aisram

[Rick Chen]

> This is more consistent with the naming of other ram banks, and matches
> what Linux is doing.
>
> Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com>
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> ---
>
> Changes in v2:
> - New
>
>  arch/riscv/dts/k210.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>

Reviewed-by: Rick Chen <rick@andestech.com>

[PATCH v2 15/16] riscv: k210: Use AI as the parent clock of aisram, not PLL1

[Rick Chen]

> Testing showed that disabling AI while leaving PLL1 enabled disabled the
> aisram. This suggests that AI is a more appropriate clock for that ram
> bank.
>
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> ---
>
> Changes in v2:
> - New
>
>  arch/riscv/dts/k210.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Rick Chen <rick@andestech.com>

[PATCH v2 00/16] riscv: k210: Enable use of AI ram bank

[Sean Anderson]

On 10/12/20 2:13 PM, Sean Anderson wrote:
> This ram bank was previously unusable because PLL1 was not started correctly.
> This series fixes that bug, and allows U-Boot to relocate into the AI ram. This
> provides an extra 2M of space in which to load payloads.
> 
> Second time around and I realized that the bypass clock is no longer necessary
> (yay). This also necessitates a few more small fixups. I've also added some
> minor patches to bring the device tree and clock driver closer to what Linux has
> (or will have). This should be the last round of additions to this series.

I discovered that the clock changes I made cause problems with
non-default PLL frequencies (specifically the removal of the bypass
clock). I've been working on-and-off on a v3 to fix these problems.

--Sean

> Changes in v2:
> - Don't re-enable the PLL
> - Remove bypass clock, which is no longer necessary
> - Simplify PLL instantiation
> - Modify clock tree so clint is a child of aclk
> - Sync memory dts node with Linux
> - Use correct aisram clock
> 
> Sean Anderson (16):
>   clk: k210: Fix PLLs not being enabled
>   clk: k210: Fix PLL enable always getting taken
>   clk: k210: Remove bypass clock
>   clk: k210: Remove k210_register_pll
>   clk: k210: Move the clint clock to under aclk
>   clk: Add support for the k210 clock driver pre-relocation
>   riscv: Enable some devices pre-relocation
>   lib: fdt: Add fdtdec_setup_mem_size_base_highest
>   test: Add a test for fdtdec_setup_mem_size_base et al.
>   ram: Add driver for K210 SRAM
>   ram: sifive: Default to y only if compiling for fu540
>   riscv: Probe ram in dram_init
>   riscv: Enable AI ram on K210
>   riscv: k210: Rename airam to aisram
>   riscv: k210: Use AI as the parent clock of aisram, not PLL1
>   riscv: Don't reserve AI ram in k210 dts
> 
>  MAINTAINERS                        |   1 +
>  arch/riscv/cpu/generic/dram.c      |  26 +++
>  arch/riscv/dts/k210.dtsi           |  22 +--
>  arch/sandbox/dts/test.dts          |  12 ++
>  board/sipeed/maix/Kconfig          |   2 +
>  board/sipeed/maix/maix.c           |  26 ---
>  configs/sandbox64_defconfig        |   2 +-
>  configs/sandbox_defconfig          |   2 +-
>  configs/sandbox_flattree_defconfig |   2 +-
>  configs/sipeed_maix_bitm_defconfig |   1 +
>  drivers/clk/kendryte/Makefile      |   2 +-
>  drivers/clk/kendryte/bypass.c      | 273 -----------------------------
>  drivers/clk/kendryte/clk.c         |  61 +++----
>  drivers/clk/kendryte/pll.c         |  26 +--
>  drivers/ram/Kconfig                |   7 +
>  drivers/ram/Makefile               |   1 +
>  drivers/ram/kendryte.c             |  56 ++++++
>  drivers/ram/sifive/Kconfig         |   2 +-
>  include/configs/sipeed-maix.h      |   4 -
>  include/fdtdec.h                   |  19 +-
>  include/kendryte/bypass.h          |  31 ----
>  include/kendryte/pll.h             |   4 -
>  lib/fdtdec.c                       |  34 +++-
>  test/dm/fdtdec.c                   |  38 ++++
>  24 files changed, 230 insertions(+), 424 deletions(-)
>  delete mode 100644 drivers/clk/kendryte/bypass.c
>  create mode 100644 drivers/ram/kendryte.c
>  delete mode 100644 include/kendryte/bypass.h
>