From: Anand Moon <linux.amoon@gmail.com> To: Linux USB Mailing List <linux-usb@vger.kernel.org>, devicetree <devicetree@vger.kernel.org>, linux-arm-kernel <linux-arm-kernel@lists.infradead.org>, linux-samsung-soc@vger.kernel.org, Linux Kernel <linux-kernel@vger.kernel.org>, "open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org> Cc: Rob Herring <robh+dt@kernel.org>, Kukjin Kim <kgene@kernel.org>, Krzysztof Kozlowski <krzk@kernel.org>, Marek Szyprowski <m.szyprowski@samsung.com>, Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>, Felipe Balbi <balbi@kernel.org>, Sylwester Nawrocki <s.nawrocki@samsung.com>, Tomasz Figa <tomasz.figa@gmail.com>, Chanwoo Choi <cw00.choi@samsung.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org> Subject: Re: [PATCHv3 2/5] ARM: dts: exynos: Add missing usbdrd3 suspend clk Date: Sat, 14 Mar 2020 19:02:33 +0530 [thread overview] Message-ID: <CANAwSgR4fJK0uVANv-x-=iSL_hAKD8kvazACUsY9Meu5xonuqQ@mail.gmail.com> (raw) In-Reply-To: <20200310194854.831-3-linux.amoon@gmail.com> Hi Krzysztof, On Wed, 11 Mar 2020 at 01:19, Anand Moon <linux.amoon@gmail.com> wrote: > > Add new compatible strings for USBDRD3 for adding missing > suspend clk, exynos5422 usbdrd3 support two clk USBD300 and > SCLK_USBD300, so add missing suspemd_clk for Exynos542x DWC3 nodes. > > Signed-off-by: Anand Moon <linux.amoon@gmail.com> My assumption based on the FSYS clock source diagram below was bit wrong. [0] https://imgur.com/gallery/zAiBoyh And again re-looking into the driver source code, it turn out their are *6 clock* Here is the correct mapping as per the Exynos5420 clock driver. USB-(phy@12100000) |___________________CLK_SCLK_USBD300 |___________________CLK_SCLK_USBPHY300 USB-(phy@12500000) |___________________CLK_SCLK_USBD301 |___________________CLK_SCLK_USBPHY301 USB-(dwc3@12000000) |___________________CLK_USBD300 USB-(dwc3@12400000) |___________________CLK_USBD301 Note: As per Exynos 5422 user manual, There are some more USB CLK configuration missing in GATE_IP_FSYS. So we could enable another dwc3 clk, If needed I would like too add this missing clk code and enable this clk for dwc3 driver. For some reason we already use CLK_USBD300 and CLK_USBD301 for PHY nodes, which lead to this confusion. So we need to update PHY clock CLK_USBD300 with CLK_SCLK_USBD300 and clock CLK_USBD301 with CLK_SCLK_USBD301. Please share your thought on linking PHY nodes above and add new DWC3 clock and enable this clock. -Anand > --- > fix the commit message > --- > arch/arm/boot/dts/exynos5410.dtsi | 8 ++++---- > arch/arm/boot/dts/exynos5420.dtsi | 8 ++++---- > arch/arm/boot/dts/exynos54xx.dtsi | 4 ++-- > 3 files changed, 10 insertions(+), 10 deletions(-) > > diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi > index 2eab80bf5f3a..19845dcd528f 100644 > --- a/arch/arm/boot/dts/exynos5410.dtsi > +++ b/arch/arm/boot/dts/exynos5410.dtsi > @@ -396,8 +396,8 @@ &trng { > }; > > &usbdrd3_0 { > - clocks = <&clock CLK_USBD300>; > - clock-names = "usbdrd30"; > + clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBD300>; > + clock-names = "usbdrd30", "usbdrd30_susp_clk"; > }; > > &usbdrd_phy0 { > @@ -407,8 +407,8 @@ &usbdrd_phy0 { > }; > > &usbdrd3_1 { > - clocks = <&clock CLK_USBD301>; > - clock-names = "usbdrd30"; > + clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBD301>; > + clock-names = "usbdrd30", "usbdrd30_susp_clk"; > }; > > &usbdrd_dwc3_1 { > diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi > index b672080e7469..bd505256a223 100644 > --- a/arch/arm/boot/dts/exynos5420.dtsi > +++ b/arch/arm/boot/dts/exynos5420.dtsi > @@ -1372,8 +1372,8 @@ &trng { > }; > > &usbdrd3_0 { > - clocks = <&clock CLK_USBD300>; > - clock-names = "usbdrd30"; > + clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBD300>; > + clock-names = "usbdrd30", "usbdrd30_susp_clk"; > }; > > &usbdrd_phy0 { > @@ -1383,8 +1383,8 @@ &usbdrd_phy0 { > }; > > &usbdrd3_1 { > - clocks = <&clock CLK_USBD301>; > - clock-names = "usbdrd30"; > + clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBD301>; > + clock-names = "usbdrd30", "usbdrd30_susp_clk"; > }; > > &usbdrd_dwc3_1 { > diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi > index 8aa5117e58ce..0aac6255de5d 100644 > --- a/arch/arm/boot/dts/exynos54xx.dtsi > +++ b/arch/arm/boot/dts/exynos54xx.dtsi > @@ -143,7 +143,7 @@ hsi2c_7: i2c@12cd0000 { > }; > > usbdrd3_0: usb3-0 { > - compatible = "samsung,exynos5250-dwusb3"; > + compatible = "samsung,exynos5420-dwusb3"; > #address-cells = <1>; > #size-cells = <1>; > ranges; > @@ -165,7 +165,7 @@ usbdrd_phy0: phy@12100000 { > }; > > usbdrd3_1: usb3-1 { > - compatible = "samsung,exynos5250-dwusb3"; > + compatible = "samsung,exynos5420-dwusb3"; > #address-cells = <1>; > #size-cells = <1>; > ranges; > -- > 2.25.1 >
WARNING: multiple messages have this Message-ID (diff)
From: Anand Moon <linux.amoon@gmail.com> To: Linux USB Mailing List <linux-usb@vger.kernel.org>, devicetree <devicetree@vger.kernel.org>, linux-arm-kernel <linux-arm-kernel@lists.infradead.org>, linux-samsung-soc@vger.kernel.org, Linux Kernel <linux-kernel@vger.kernel.org>, "open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org> Cc: Felipe Balbi <balbi@kernel.org>, Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Tomasz Figa <tomasz.figa@gmail.com>, Krzysztof Kozlowski <krzk@kernel.org>, Chanwoo Choi <cw00.choi@samsung.com>, Rob Herring <robh+dt@kernel.org>, Kukjin Kim <kgene@kernel.org>, Sylwester Nawrocki <s.nawrocki@samsung.com>, Marek Szyprowski <m.szyprowski@samsung.com> Subject: Re: [PATCHv3 2/5] ARM: dts: exynos: Add missing usbdrd3 suspend clk Date: Sat, 14 Mar 2020 19:02:33 +0530 [thread overview] Message-ID: <CANAwSgR4fJK0uVANv-x-=iSL_hAKD8kvazACUsY9Meu5xonuqQ@mail.gmail.com> (raw) In-Reply-To: <20200310194854.831-3-linux.amoon@gmail.com> Hi Krzysztof, On Wed, 11 Mar 2020 at 01:19, Anand Moon <linux.amoon@gmail.com> wrote: > > Add new compatible strings for USBDRD3 for adding missing > suspend clk, exynos5422 usbdrd3 support two clk USBD300 and > SCLK_USBD300, so add missing suspemd_clk for Exynos542x DWC3 nodes. > > Signed-off-by: Anand Moon <linux.amoon@gmail.com> My assumption based on the FSYS clock source diagram below was bit wrong. [0] https://imgur.com/gallery/zAiBoyh And again re-looking into the driver source code, it turn out their are *6 clock* Here is the correct mapping as per the Exynos5420 clock driver. USB-(phy@12100000) |___________________CLK_SCLK_USBD300 |___________________CLK_SCLK_USBPHY300 USB-(phy@12500000) |___________________CLK_SCLK_USBD301 |___________________CLK_SCLK_USBPHY301 USB-(dwc3@12000000) |___________________CLK_USBD300 USB-(dwc3@12400000) |___________________CLK_USBD301 Note: As per Exynos 5422 user manual, There are some more USB CLK configuration missing in GATE_IP_FSYS. So we could enable another dwc3 clk, If needed I would like too add this missing clk code and enable this clk for dwc3 driver. For some reason we already use CLK_USBD300 and CLK_USBD301 for PHY nodes, which lead to this confusion. So we need to update PHY clock CLK_USBD300 with CLK_SCLK_USBD300 and clock CLK_USBD301 with CLK_SCLK_USBD301. Please share your thought on linking PHY nodes above and add new DWC3 clock and enable this clock. -Anand > --- > fix the commit message > --- > arch/arm/boot/dts/exynos5410.dtsi | 8 ++++---- > arch/arm/boot/dts/exynos5420.dtsi | 8 ++++---- > arch/arm/boot/dts/exynos54xx.dtsi | 4 ++-- > 3 files changed, 10 insertions(+), 10 deletions(-) > > diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi > index 2eab80bf5f3a..19845dcd528f 100644 > --- a/arch/arm/boot/dts/exynos5410.dtsi > +++ b/arch/arm/boot/dts/exynos5410.dtsi > @@ -396,8 +396,8 @@ &trng { > }; > > &usbdrd3_0 { > - clocks = <&clock CLK_USBD300>; > - clock-names = "usbdrd30"; > + clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBD300>; > + clock-names = "usbdrd30", "usbdrd30_susp_clk"; > }; > > &usbdrd_phy0 { > @@ -407,8 +407,8 @@ &usbdrd_phy0 { > }; > > &usbdrd3_1 { > - clocks = <&clock CLK_USBD301>; > - clock-names = "usbdrd30"; > + clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBD301>; > + clock-names = "usbdrd30", "usbdrd30_susp_clk"; > }; > > &usbdrd_dwc3_1 { > diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi > index b672080e7469..bd505256a223 100644 > --- a/arch/arm/boot/dts/exynos5420.dtsi > +++ b/arch/arm/boot/dts/exynos5420.dtsi > @@ -1372,8 +1372,8 @@ &trng { > }; > > &usbdrd3_0 { > - clocks = <&clock CLK_USBD300>; > - clock-names = "usbdrd30"; > + clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBD300>; > + clock-names = "usbdrd30", "usbdrd30_susp_clk"; > }; > > &usbdrd_phy0 { > @@ -1383,8 +1383,8 @@ &usbdrd_phy0 { > }; > > &usbdrd3_1 { > - clocks = <&clock CLK_USBD301>; > - clock-names = "usbdrd30"; > + clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBD301>; > + clock-names = "usbdrd30", "usbdrd30_susp_clk"; > }; > > &usbdrd_dwc3_1 { > diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi > index 8aa5117e58ce..0aac6255de5d 100644 > --- a/arch/arm/boot/dts/exynos54xx.dtsi > +++ b/arch/arm/boot/dts/exynos54xx.dtsi > @@ -143,7 +143,7 @@ hsi2c_7: i2c@12cd0000 { > }; > > usbdrd3_0: usb3-0 { > - compatible = "samsung,exynos5250-dwusb3"; > + compatible = "samsung,exynos5420-dwusb3"; > #address-cells = <1>; > #size-cells = <1>; > ranges; > @@ -165,7 +165,7 @@ usbdrd_phy0: phy@12100000 { > }; > > usbdrd3_1: usb3-1 { > - compatible = "samsung,exynos5250-dwusb3"; > + compatible = "samsung,exynos5420-dwusb3"; > #address-cells = <1>; > #size-cells = <1>; > ranges; > -- > 2.25.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-03-15 2:42 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-03-10 19:48 [PATCHv3 0/5] Add support for FSYS power domain and enable suspend clk for Exynos542x SoC Anand Moon 2020-03-10 19:48 ` Anand Moon 2020-03-10 19:48 ` [PATCHv3 1/5] devicetree: bindings: exynos: Add new compatible for Exynos5420 dwc3 clocks support Anand Moon 2020-03-10 19:48 ` Anand Moon 2020-03-15 9:07 ` Felipe Balbi 2020-03-15 9:07 ` Felipe Balbi 2020-03-15 9:25 ` Anand Moon 2020-03-15 9:25 ` Anand Moon 2020-03-17 8:42 ` Krzysztof Kozlowski 2020-03-17 8:42 ` Krzysztof Kozlowski 2020-03-10 19:48 ` [PATCHv3 2/5] ARM: dts: exynos: Add missing usbdrd3 suspend clk Anand Moon 2020-03-10 19:48 ` Anand Moon 2020-03-14 13:32 ` Anand Moon [this message] 2020-03-14 13:32 ` Anand Moon 2020-03-14 18:20 ` Krzysztof Kozlowski 2020-03-14 18:20 ` Krzysztof Kozlowski 2020-03-15 9:46 ` Anand Moon 2020-03-15 9:46 ` Anand Moon 2020-03-10 19:48 ` [PATCHv3 3/5] ARM: dts: exynos: Add FSYS power domain to Exynos542x USB nodes Anand Moon 2020-03-10 19:48 ` Anand Moon 2020-03-10 19:48 ` [PATCHv3 4/5] usb: dwc3: exynos: Add support for Exynos5422 suspend clk Anand Moon 2020-03-10 19:48 ` Anand Moon 2020-03-10 19:48 ` [PATCHv3 5/5] clk: samsung: exynos542x: Move FSYS subsystem clocks to its sub-CMU Anand Moon 2020-03-10 19:48 ` Anand Moon 2020-03-11 14:42 ` Krzysztof Kozlowski 2020-03-11 14:42 ` Krzysztof Kozlowski 2020-03-12 10:34 ` Anand Moon 2020-03-12 10:34 ` Anand Moon 2020-03-12 11:36 ` Krzysztof Kozlowski 2020-03-12 11:36 ` Krzysztof Kozlowski 2020-03-12 12:54 ` Anand Moon 2020-03-12 12:54 ` Anand Moon 2020-03-12 14:08 ` Anand Moon 2020-03-12 14:08 ` Anand Moon 2020-03-14 17:41 ` Krzysztof Kozlowski 2020-03-14 17:41 ` Krzysztof Kozlowski
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