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From: Geetha Akula <geethasowjanya.akula-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	devel-E0kO6a4B6psdnm+yROfE0A@public.gmane.org,
	Charles Garcia-Tobin
	<Charles.Garcia-Tobin-5wv7dgnIgG8@public.gmane.org>,
	Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org>,
	Linu Cherian
	<linu.cherian-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>,
	Robert Richter
	<robert.richter-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>,
	"Rafael J. Wysocki" <rjw-LthD3rsA81gm4RdzfppkhA@public.gmane.org>,
	Geetha sowjanya
	<gakula-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>,
	Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>,
	Robert Moore
	<robert.moore-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-acpi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	Linux IOMMU
	<iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>,
	Geetha Sowjanya
	<geethasowjanya.akula-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>,
	Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>,
	Sunil Goutham <sgoutham-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>,
	jcm-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org,
	Lv Zheng <lv.zheng-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Subject: Re: [PATCH v7 1/3] ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model
Date: Fri, 9 Jun 2017 11:30:53 +0530	[thread overview]
Message-ID: <CANHdaib+mNgVS7g=vft-5ZtabSKkeyXO7Jp1EQhL3jduhu5F7g@mail.gmail.com> (raw)
In-Reply-To: <20170608085857.GB8607@red-moon>

On Thu, Jun 8, 2017 at 2:28 PM, Lorenzo Pieralisi
<lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org> wrote:
> On Tue, May 30, 2017 at 05:33:39PM +0530, Geetha sowjanya wrote:
>> From: Linu Cherian <linu.cherian-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
>>
>> Cavium ThunderX2 implementation doesn't support second page in SMMU
>> register space. Hence, resource size is set as 64k for this model.
>>
>> Signed-off-by: Linu Cherian <linu.cherian-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
>> Signed-off-by: Geetha Sowjanya <geethasowjanya.akula-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
>> ---
>>  drivers/acpi/arm64/iort.c |   10 +++++++++-
>>  1 files changed, 9 insertions(+), 1 deletions(-)
>>
>> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
>> index c5fecf9..bba2b59 100644
>> --- a/drivers/acpi/arm64/iort.c
>> +++ b/drivers/acpi/arm64/iort.c
>> @@ -833,12 +833,20 @@ static void __init arm_smmu_v3_init_resources(struct resource *res,
>>  {
>>       struct acpi_iort_smmu_v3 *smmu;
>>       int num_res = 0;
>> +     unsigned long size = SZ_128K;
>>
>>       /* Retrieve SMMUv3 specific data */
>>       smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
>>
>> +     /*
>> +      * Override the size, for Cavium ThunderX2 implementation
>> +      * which doesn't support the page 1 SMMU register space.
>> +      */
>> +     if (smmu->model == ACPI_IORT_SMMU_CAVIUM_CN99XX)
>> +             size = SZ_64K;
>
> Nit: add a function, say arm_smmu_v3_resource_size() with the logic
> above that by default returns SZ_128K, I do not like this switch
> in the middle of this function.

I will resubmit the patch with suggested changes.


Thanks,
Geetha.
>
> Lorenzo
>
>> +
>>       res[num_res].start = smmu->base_address;
>> -     res[num_res].end = smmu->base_address + SZ_128K - 1;
>> +     res[num_res].end = smmu->base_address + size - 1;
>>       res[num_res].flags = IORESOURCE_MEM;
>>
>>       num_res++;
>> --
>> 1.7.1
>>

WARNING: multiple messages have this Message-ID (diff)
From: Geetha Akula <geethasowjanya.akula@gmail.com>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Geetha sowjanya <gakula@caviumnetworks.com>,
	Will Deacon <will.deacon@arm.com>,
	Robin Murphy <robin.murphy@arm.com>,
	Hanjun Guo <hanjun.guo@linaro.org>,
	Sudeep Holla <sudeep.holla@arm.com>,
	Linux IOMMU <iommu@lists.linux-foundation.org>,
	Robert Moore <robert.moore@intel.com>,
	Lv Zheng <lv.zheng@intel.com>,
	"Rafael J. Wysocki" <rjw@rjwysocki.net>,
	jcm@redhat.com, linux-kernel@vger.kernel.org,
	Robert Richter <robert.richter@cavium.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Sunil Goutham <sgoutham@cavium.com>,
	linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org,
	devel@acpica.org, Linu Cherian <linu.cherian@cavium.com>,
	Charles Garcia-Tobin <Charles.Garcia-Tobin@arm.com>,
	Rob Herring <robh@kernel.org>,
	Geetha Sowjanya <geethasowjanya.akula@cavium.com>
Subject: Re: [PATCH v7 1/3] ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model
Date: Fri, 9 Jun 2017 11:30:53 +0530	[thread overview]
Message-ID: <CANHdaib+mNgVS7g=vft-5ZtabSKkeyXO7Jp1EQhL3jduhu5F7g@mail.gmail.com> (raw)
In-Reply-To: <20170608085857.GB8607@red-moon>

On Thu, Jun 8, 2017 at 2:28 PM, Lorenzo Pieralisi
<lorenzo.pieralisi@arm.com> wrote:
> On Tue, May 30, 2017 at 05:33:39PM +0530, Geetha sowjanya wrote:
>> From: Linu Cherian <linu.cherian@cavium.com>
>>
>> Cavium ThunderX2 implementation doesn't support second page in SMMU
>> register space. Hence, resource size is set as 64k for this model.
>>
>> Signed-off-by: Linu Cherian <linu.cherian@cavium.com>
>> Signed-off-by: Geetha Sowjanya <geethasowjanya.akula@cavium.com>
>> ---
>>  drivers/acpi/arm64/iort.c |   10 +++++++++-
>>  1 files changed, 9 insertions(+), 1 deletions(-)
>>
>> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
>> index c5fecf9..bba2b59 100644
>> --- a/drivers/acpi/arm64/iort.c
>> +++ b/drivers/acpi/arm64/iort.c
>> @@ -833,12 +833,20 @@ static void __init arm_smmu_v3_init_resources(struct resource *res,
>>  {
>>       struct acpi_iort_smmu_v3 *smmu;
>>       int num_res = 0;
>> +     unsigned long size = SZ_128K;
>>
>>       /* Retrieve SMMUv3 specific data */
>>       smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
>>
>> +     /*
>> +      * Override the size, for Cavium ThunderX2 implementation
>> +      * which doesn't support the page 1 SMMU register space.
>> +      */
>> +     if (smmu->model == ACPI_IORT_SMMU_CAVIUM_CN99XX)
>> +             size = SZ_64K;
>
> Nit: add a function, say arm_smmu_v3_resource_size() with the logic
> above that by default returns SZ_128K, I do not like this switch
> in the middle of this function.

I will resubmit the patch with suggested changes.


Thanks,
Geetha.
>
> Lorenzo
>
>> +
>>       res[num_res].start = smmu->base_address;
>> -     res[num_res].end = smmu->base_address + SZ_128K - 1;
>> +     res[num_res].end = smmu->base_address + size - 1;
>>       res[num_res].flags = IORESOURCE_MEM;
>>
>>       num_res++;
>> --
>> 1.7.1
>>

WARNING: multiple messages have this Message-ID (diff)
From: geethasowjanya.akula@gmail.com (Geetha Akula)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v7 1/3] ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model
Date: Fri, 9 Jun 2017 11:30:53 +0530	[thread overview]
Message-ID: <CANHdaib+mNgVS7g=vft-5ZtabSKkeyXO7Jp1EQhL3jduhu5F7g@mail.gmail.com> (raw)
In-Reply-To: <20170608085857.GB8607@red-moon>

On Thu, Jun 8, 2017 at 2:28 PM, Lorenzo Pieralisi
<lorenzo.pieralisi@arm.com> wrote:
> On Tue, May 30, 2017 at 05:33:39PM +0530, Geetha sowjanya wrote:
>> From: Linu Cherian <linu.cherian@cavium.com>
>>
>> Cavium ThunderX2 implementation doesn't support second page in SMMU
>> register space. Hence, resource size is set as 64k for this model.
>>
>> Signed-off-by: Linu Cherian <linu.cherian@cavium.com>
>> Signed-off-by: Geetha Sowjanya <geethasowjanya.akula@cavium.com>
>> ---
>>  drivers/acpi/arm64/iort.c |   10 +++++++++-
>>  1 files changed, 9 insertions(+), 1 deletions(-)
>>
>> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
>> index c5fecf9..bba2b59 100644
>> --- a/drivers/acpi/arm64/iort.c
>> +++ b/drivers/acpi/arm64/iort.c
>> @@ -833,12 +833,20 @@ static void __init arm_smmu_v3_init_resources(struct resource *res,
>>  {
>>       struct acpi_iort_smmu_v3 *smmu;
>>       int num_res = 0;
>> +     unsigned long size = SZ_128K;
>>
>>       /* Retrieve SMMUv3 specific data */
>>       smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
>>
>> +     /*
>> +      * Override the size, for Cavium ThunderX2 implementation
>> +      * which doesn't support the page 1 SMMU register space.
>> +      */
>> +     if (smmu->model == ACPI_IORT_SMMU_CAVIUM_CN99XX)
>> +             size = SZ_64K;
>
> Nit: add a function, say arm_smmu_v3_resource_size() with the logic
> above that by default returns SZ_128K, I do not like this switch
> in the middle of this function.

I will resubmit the patch with suggested changes.


Thanks,
Geetha.
>
> Lorenzo
>
>> +
>>       res[num_res].start = smmu->base_address;
>> -     res[num_res].end = smmu->base_address + SZ_128K - 1;
>> +     res[num_res].end = smmu->base_address + size - 1;
>>       res[num_res].flags = IORESOURCE_MEM;
>>
>>       num_res++;
>> --
>> 1.7.1
>>

  reply	other threads:[~2017-06-09  6:00 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-05-30 12:03 [PATCH v7 0/3] Cavium ThunderX2 SMMUv3 errata workarounds Geetha sowjanya
2017-05-30 12:03 ` Geetha sowjanya
2017-05-30 12:03 ` [PATCH v7 1/3] ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model Geetha sowjanya
2017-05-30 12:03   ` Geetha sowjanya
     [not found]   ` <1496145821-3411-2-git-send-email-gakula-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
2017-06-08  8:58     ` Lorenzo Pieralisi
2017-06-08  8:58       ` [Devel] " Lorenzo Pieralisi
2017-06-08  8:58       ` Lorenzo Pieralisi
2017-06-08  8:58       ` Lorenzo Pieralisi
2017-06-09  6:00       ` Geetha Akula [this message]
2017-06-09  6:00         ` Geetha Akula
2017-06-09  6:00         ` Geetha Akula
2017-06-20  8:19     ` Robert Richter
2017-06-20  8:19       ` Robert Richter
2017-06-20  8:19       ` Robert Richter
     [not found]       ` <20170620081943.GT658-vWBEXY7mpu582hYKe6nXyg@public.gmane.org>
2017-06-20  8:51         ` Robert Richter
2017-06-20  8:51           ` Robert Richter
2017-06-20  8:51           ` Robert Richter
2017-06-20 10:31           ` Lorenzo Pieralisi
2017-06-20 10:31             ` [Devel] " Lorenzo Pieralisi
2017-06-20 10:31             ` Lorenzo Pieralisi
2017-05-30 12:03 ` [PATCH v7 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74 Geetha sowjanya
2017-05-30 12:03   ` Geetha sowjanya
     [not found]   ` <1496145821-3411-3-git-send-email-gakula-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
2017-06-09 10:28     ` Robin Murphy
2017-06-09 10:28       ` Robin Murphy
2017-06-09 10:28       ` Robin Murphy
     [not found]       ` <CA+7sy7C_44dTy0-nAE=b5BCXmc8ACQx2O6A1jCOCsemZDD5j4w@mail.gmail.com>
     [not found]         ` <CA+7sy7C_44dTy0-nAE=b5BCXmc8ACQx2O6A1jCOCsemZDD5j4w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-06-09 11:38           ` Fwd: " Jayachandran C
2017-06-09 11:38             ` Jayachandran C
2017-06-09 11:38             ` Jayachandran C
2017-06-09 15:43             ` Robin Murphy
2017-06-09 15:43               ` Robin Murphy
     [not found]               ` <ee0fb6c3-1c5c-f6d1-b063-ead8102d0c67-5wv7dgnIgG8@public.gmane.org>
2017-06-12  8:12                 ` Jayachandran C
2017-06-12  8:12                   ` Jayachandran C
2017-06-12  8:12                   ` Jayachandran C
     [not found] ` <1496145821-3411-1-git-send-email-gakula-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
2017-05-30 12:03   ` [PATCH v7 3/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126 Geetha sowjanya
2017-05-30 12:03     ` Geetha sowjanya
2017-05-30 12:03     ` Geetha sowjanya
     [not found]     ` <1496145821-3411-4-git-send-email-gakula-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
2017-06-06 11:03       ` John Garry
2017-06-06 11:03         ` John Garry
2017-06-06 11:03         ` John Garry
2017-06-09 10:00       ` Will Deacon
2017-06-09 10:00         ` Will Deacon
2017-06-09 10:00         ` Will Deacon
2017-05-30 14:11 ` [PATCH v7 0/3] Cavium ThunderX2 SMMUv3 errata workarounds Robert Richter
2017-05-30 14:11   ` Robert Richter
2017-06-08 16:32 ` Lorenzo Pieralisi
2017-06-08 16:32   ` [Devel] " Lorenzo Pieralisi
2017-06-08 16:32   ` Lorenzo Pieralisi
2017-06-08 17:13   ` Rafael J. Wysocki
2017-06-08 17:13     ` [Devel] " Rafael J. Wysocki
2017-06-08 17:13     ` Rafael J. Wysocki
2017-06-08 17:13     ` Rafael J. Wysocki
2017-06-08 17:22     ` Robin Murphy
2017-06-08 17:22       ` Robin Murphy
2017-06-08 17:22       ` Robin Murphy
     [not found]     ` <CAJZ5v0gnjxwBXEQ--u6Sbviks74MXLFWTfN+J90cdDZbO2Q7+w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-06-13 11:51       ` Lorenzo Pieralisi
2017-06-13 11:51         ` [Devel] " Lorenzo Pieralisi
2017-06-13 11:51         ` Lorenzo Pieralisi
2017-06-13 11:51         ` Lorenzo Pieralisi

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