* [PATCH 0/1] Xilinx Zynq Ultrascale+ MPSoc CoreSight DT nodes
@ 2020-01-30 15:36 ` Wojciech Żmuda
0 siblings, 0 replies; 14+ messages in thread
From: Wojciech Żmuda @ 2020-01-30 15:36 UTC (permalink / raw)
To: linux-arm-kernel, devicetree, coresight
Cc: robh+dt, mark.rutland, michal.simek, m.tretter, nava.manne,
antoine.tenart, t-kristo, rajan.vaja, mathieu.poirier,
Krzysztof Pilch, Michal Mosdorf, Michał Kurowski,
Wojciech Żmuda
From: Wojciech Zmuda <wzmuda@n7space.com>
This patch adds CoreSight nodes to Zynq US+ device tree. I tested in on
recent v5.5 tree, on Xilinx ZCU104 development board.
Tracing with perf:
root@zynq:~# perf record -e cs_etm/timestamp,cycacc,@tmc_etr0/u true
Couldn't synthesize bpf events.
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.073 MB perf.data ]
root@zynq:~# perf report --dump | grep "CoreSight ETM Trace data" -A10
. ... CoreSight ETM Trace data: size 74112 bytes
Idx:0; ID:14; I_ASYNC : Alignment Synchronisation.
Idx:12; ID:14; I_TRACE_INFO : Trace Info.; INFO=0x1 { CC.1 }; CC_THRESHOLD=0x100
Idx:19; ID:14; I_ADDR_L_64IS0 : Address, Long, 64 bit, IS0.; Addr=0xFFFF800010839BF8;
Idx:28; ID:14; I_TRACE_ON : Trace On.
Idx:29; ID:14; I_ADDR_CTXT_L_64IS0 : Address & Context, Long, 64 bit, IS0.; Addr=0x0000FFFF83F37080; Ctxt: AArch64,EL0, NS; CID=0x00000281;
Idx:44; ID:14; I_ATOM_F1 : Atom format 1.; E
Idx:45; ID:14; I_CCNT_F1 : Cycle Count format 1.; Count=0x0
Idx:46; ID:14; I_TIMESTAMP : Timestamp.; Updated val = 0x29aa0b739ec; CC=0x1
Idx:58; ID:14; I_EXCEPT : Exception.; Data Fault; Ret Addr Follows;
Idx:60; ID:14; I_ADDR_L_64IS0 : Address, Long, 64 bit, IS0.; Addr=0x0000FFFF83F37964;
Please note that to get non-zero timestamps on this platform, the timestamp
generator module needs to be explicitly enabled, e.g. from U-Boot, by writing
'1' to 0xfe900000.
Debug components:
root@zynq:~# echo 1 > /sys/kernel/debug/coresight_cpu_debug/enable
root@zynq:~# echo c > /proc/sysrq-trigger
[ 57.5093] ARM external debug module:
[ 57.513099] coresight-cpu-deb fec10000.debug0: CPU[0]:
[ 57.518407] coresight-cpu-debug fec10000.debug0: EDPRSR: 00000001 (Power:On DLK:Unlock
[ 57.526583] coresight-cpu-debug fec10000.debug0: EDPCSR: ocal_cpu_stop+0x2c/0x38
[ 57.534236] coresight-cpu-debug fec10000.debug0: EDCIDSR: 00000000
[ 57.540494] coresit-cpu-debug fec10000.debug0: EDVIDSR: 90000000 (State:Non-sece Mode:EL1/0 Width:64bits VMID:0)
[ 57.551095] coresight-cpu-debug fed10000.debug1: CPU[1]:
[ 57.556406] coresig-cpu-debug fed10000.debug1: EDPRSR: 00000001 (Power:On DLK:Uock)
[ 57.564584] coresight-cpu-debug fed10000.debug1: EDPCSR: local_cpu_stop+0x2c/0x38
[ 57.572237] coresightpu-debug fed10000.debug1: EDCIDSR: 00000000
[ 57.578494] cesight-cpu-debug fed10000.debug1: EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
[ 57.589096]oresight-cpu-debug fee10000.debug2: CPU[2]:
[ 57.594408] cosight-cpu-debug fee10000.debug2: EDPRSR: 00000001 (Power:On DLK:Unlock)
[ 57.602587] coresight-cpu-debug fee10000ebug2: EDPCSR: debug_notifier_call+0x2b8/0x3b0
[ 57.61084 coresight-cpu-debug fee10000.debug2: EDCIDSR: 00000170
[ 57.617103] coresight-cpu-debug fee10000.debug2: EDVIDSR90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
[ 57.627705] coresight-cpu-debug fef10000.debug3: CPU[3]:
[ 57.633016] coresight-cpu-debug fef10000.debug3: EDPRSR: 0000001 (Power:On DLK:Unlock)
[ 57.641193] coresight-cpu-deg fef10000.debug3: EDPCSR: local_cpu_stop+0x2c/0x38
[ 57.648846] coresight-cpu-debug fef10000.debug3: EDCIDSR: 000000
[ 57.655104] coresight-cpu-debug fef10000.debug3: EDDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
[ 57.665708] Rebooting in 60 seconds..
Wojciech Zmuda (1):
arm64: zynqmp: Add CoreSight components
arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi | 272 +++++++++++++++++++++++
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +
2 files changed, 274 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
--
2.11.0
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 0/1] Xilinx Zynq Ultrascale+ MPSoc CoreSight DT nodes
@ 2020-01-30 15:36 ` Wojciech Żmuda
0 siblings, 0 replies; 14+ messages in thread
From: Wojciech Żmuda @ 2020-01-30 15:36 UTC (permalink / raw)
To: linux-arm-kernel, devicetree, coresight
Cc: mark.rutland, mathieu.poirier, rajan.vaja, Michal Mosdorf,
antoine.tenart, nava.manne, michal.simek, m.tretter, t-kristo,
Krzysztof Pilch, Wojciech Żmuda, robh+dt,
Michał Kurowski
From: Wojciech Zmuda <wzmuda@n7space.com>
This patch adds CoreSight nodes to Zynq US+ device tree. I tested in on
recent v5.5 tree, on Xilinx ZCU104 development board.
Tracing with perf:
root@zynq:~# perf record -e cs_etm/timestamp,cycacc,@tmc_etr0/u true
Couldn't synthesize bpf events.
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.073 MB perf.data ]
root@zynq:~# perf report --dump | grep "CoreSight ETM Trace data" -A10
. ... CoreSight ETM Trace data: size 74112 bytes
Idx:0; ID:14; I_ASYNC : Alignment Synchronisation.
Idx:12; ID:14; I_TRACE_INFO : Trace Info.; INFO=0x1 { CC.1 }; CC_THRESHOLD=0x100
Idx:19; ID:14; I_ADDR_L_64IS0 : Address, Long, 64 bit, IS0.; Addr=0xFFFF800010839BF8;
Idx:28; ID:14; I_TRACE_ON : Trace On.
Idx:29; ID:14; I_ADDR_CTXT_L_64IS0 : Address & Context, Long, 64 bit, IS0.; Addr=0x0000FFFF83F37080; Ctxt: AArch64,EL0, NS; CID=0x00000281;
Idx:44; ID:14; I_ATOM_F1 : Atom format 1.; E
Idx:45; ID:14; I_CCNT_F1 : Cycle Count format 1.; Count=0x0
Idx:46; ID:14; I_TIMESTAMP : Timestamp.; Updated val = 0x29aa0b739ec; CC=0x1
Idx:58; ID:14; I_EXCEPT : Exception.; Data Fault; Ret Addr Follows;
Idx:60; ID:14; I_ADDR_L_64IS0 : Address, Long, 64 bit, IS0.; Addr=0x0000FFFF83F37964;
Please note that to get non-zero timestamps on this platform, the timestamp
generator module needs to be explicitly enabled, e.g. from U-Boot, by writing
'1' to 0xfe900000.
Debug components:
root@zynq:~# echo 1 > /sys/kernel/debug/coresight_cpu_debug/enable
root@zynq:~# echo c > /proc/sysrq-trigger
[ 57.5093] ARM external debug module:
[ 57.513099] coresight-cpu-deb fec10000.debug0: CPU[0]:
[ 57.518407] coresight-cpu-debug fec10000.debug0: EDPRSR: 00000001 (Power:On DLK:Unlock
[ 57.526583] coresight-cpu-debug fec10000.debug0: EDPCSR: ocal_cpu_stop+0x2c/0x38
[ 57.534236] coresight-cpu-debug fec10000.debug0: EDCIDSR: 00000000
[ 57.540494] coresit-cpu-debug fec10000.debug0: EDVIDSR: 90000000 (State:Non-sece Mode:EL1/0 Width:64bits VMID:0)
[ 57.551095] coresight-cpu-debug fed10000.debug1: CPU[1]:
[ 57.556406] coresig-cpu-debug fed10000.debug1: EDPRSR: 00000001 (Power:On DLK:Uock)
[ 57.564584] coresight-cpu-debug fed10000.debug1: EDPCSR: local_cpu_stop+0x2c/0x38
[ 57.572237] coresightpu-debug fed10000.debug1: EDCIDSR: 00000000
[ 57.578494] cesight-cpu-debug fed10000.debug1: EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
[ 57.589096]oresight-cpu-debug fee10000.debug2: CPU[2]:
[ 57.594408] cosight-cpu-debug fee10000.debug2: EDPRSR: 00000001 (Power:On DLK:Unlock)
[ 57.602587] coresight-cpu-debug fee10000ebug2: EDPCSR: debug_notifier_call+0x2b8/0x3b0
[ 57.61084 coresight-cpu-debug fee10000.debug2: EDCIDSR: 00000170
[ 57.617103] coresight-cpu-debug fee10000.debug2: EDVIDSR90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
[ 57.627705] coresight-cpu-debug fef10000.debug3: CPU[3]:
[ 57.633016] coresight-cpu-debug fef10000.debug3: EDPRSR: 0000001 (Power:On DLK:Unlock)
[ 57.641193] coresight-cpu-deg fef10000.debug3: EDPCSR: local_cpu_stop+0x2c/0x38
[ 57.648846] coresight-cpu-debug fef10000.debug3: EDCIDSR: 000000
[ 57.655104] coresight-cpu-debug fef10000.debug3: EDDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
[ 57.665708] Rebooting in 60 seconds..
Wojciech Zmuda (1):
arm64: zynqmp: Add CoreSight components
arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi | 272 +++++++++++++++++++++++
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +
2 files changed, 274 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
--
2.11.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/1] arm64: zynqmp: Add CoreSight components
2020-01-30 15:36 ` Wojciech Żmuda
@ 2020-01-30 15:36 ` Wojciech Żmuda
-1 siblings, 0 replies; 14+ messages in thread
From: Wojciech Żmuda @ 2020-01-30 15:36 UTC (permalink / raw)
To: linux-arm-kernel, devicetree, coresight
Cc: robh+dt, mark.rutland, michal.simek, m.tretter, nava.manne,
antoine.tenart, t-kristo, rajan.vaja, mathieu.poirier,
Krzysztof Pilch, Michal Mosdorf, Michał Kurowski,
Wojciech Żmuda
From: Wojciech Zmuda <wzmuda@n7space.com>
Add nodes for the following CoreSight components:
- ETMs for A53 cores
- debug components for A53 cores
- funnel gathering outputs from A53 ETMs and SoC-wide funnels
- the only replicator
- all TMCs: 4k ETF, 8k ETF and ETR
- TPIU
Signed-off-by: Wojciech Zmuda <wzmuda@n7space.com>
---
arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi | 272 +++++++++++++++++++++++
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +
2 files changed, 274 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
new file mode 100644
index 000000000000..8b7579ad89cc
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
@@ -0,0 +1,272 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * dtsi for Xilinx Ultrascale+ MPSoC CoreSight components
+ *
+ * Copyright (C) 2019-2020 N7 Space Sp. z o.o.
+ *
+ * Author: Wojciech Zmuda <wzmuda@n7space.com>
+ *
+ */
+/ {
+ etm0@fec40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xfec40000 0 0x1000>;
+ cpu = <&cpu0>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ out-ports {
+ port {
+ etm0_out_port: endpoint {
+ remote-endpoint = <&funnel1_in_port0>;
+ };
+ };
+ };
+ };
+
+ etm1@fed40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xfed40000 0 0x1000>;
+ cpu = <&cpu1>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ out-ports {
+ port {
+ etm1_out_port: endpoint {
+ remote-endpoint = <&funnel1_in_port1>;
+ };
+ };
+ };
+ };
+
+ etm2@fee40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xfee40000 0 0x1000>;
+ cpu = <&cpu2>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ out-ports {
+ port {
+ etm2_out_port: endpoint {
+ remote-endpoint = <&funnel1_in_port2>;
+ };
+ };
+ };
+ };
+
+ etm3@fef40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xfef40000 0 0x1000>;
+ cpu = <&cpu3>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ out-ports {
+ port {
+ etm3_out_port: endpoint {
+ remote-endpoint = <&funnel1_in_port3>;
+ };
+ };
+ };
+ };
+
+ debug0@fec10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfec10000 0 0x1000>;
+ cpu = <&cpu0>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ };
+
+ debug1@fed10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfed10000 0 0x1000>;
+ cpu = <&cpu1>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ };
+
+ debug2@fee10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfee10000 0 0x1000>;
+ cpu = <&cpu2>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ };
+
+ debug3@fee10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfef10000 0 0x1000>;
+ cpu = <&cpu3>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ };
+
+ funnel1@fe920000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0xfe920000 0 0x1000>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ in-ports {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ port@0 {
+ reg = <0x0>;
+ funnel1_in_port0: endpoint {
+ remote-endpoint = <&etm0_out_port>;
+ };
+ };
+ port@1 {
+ reg = <0x1>;
+ funnel1_in_port1: endpoint {
+ remote-endpoint = <&etm1_out_port>;
+ };
+ };
+ port@2 {
+ reg = <0x2>;
+ funnel1_in_port2: endpoint {
+ remote-endpoint = <&etm2_out_port>;
+ };
+ };
+ port@3 {
+ reg = <0x3>;
+ funnel1_in_port3: endpoint {
+ remote-endpoint = <&etm3_out_port>;
+ };
+ };
+ };
+ out-ports {
+ port {
+ funnel1_out_port0: endpoint {
+ remote-endpoint = <&etf1_in_port>;
+ };
+ };
+ };
+ };
+
+ funnel2@fe930000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0xfe930000 0 0x1000>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ in-ports {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ port@2 {
+ reg = <0x2>;
+ funnel2_in_port2: endpoint {
+ remote-endpoint = <&etf1_out_port>;
+ };
+ };
+ // Funnel2 has another input port connected to
+ // funnel0's output. Funnel0 gathers Cortex-R5 ETMs.
+ };
+ out-ports {
+ port {
+ funnel2_out_port0: endpoint {
+ remote-endpoint = <&etf2_in_port>;
+ };
+ };
+ };
+ };
+
+ etf1@fe940000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0xfe940000 0 0x1000>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ in-ports {
+ port {
+ etf1_in_port: endpoint {
+ remote-endpoint = <&funnel1_out_port0>;
+ };
+ };
+ };
+ out-ports {
+ port {
+ etf1_out_port: endpoint {
+ remote-endpoint = <&funnel2_in_port2>;
+ };
+ };
+ };
+ };
+
+ etf2@fe950000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0xfe950000 0 0x1000>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ in-ports {
+ port {
+ etf2_in_port: endpoint {
+ remote-endpoint = <&funnel2_out_port0>;
+ };
+ };
+ };
+ out-ports {
+ port {
+ etf2_out_port: endpoint {
+ remote-endpoint =
+ <&replicator_in_port0>;
+ };
+ };
+ };
+ };
+
+ replicator {
+ compatible = "arm,coresight-static-replicator";
+ in-ports {
+ port {
+ replicator_in_port0: endpoint {
+ remote-endpoint = <&etf2_out_port>;
+ };
+ };
+ };
+ out-ports {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ port@0 {
+ reg = <0x0>;
+ replicator_out_port0: endpoint {
+ remote-endpoint = <&etr_in_port>;
+ };
+ };
+ port@1 {
+ reg = <0x1>;
+ replicator_out_port1: endpoint {
+ remote-endpoint = <&tpiu_in_port>;
+ };
+ };
+ };
+ };
+
+ etr@fe970000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0xfe970000 0 0x1000>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ in-ports {
+ port {
+ etr_in_port: endpoint {
+ remote-endpoint =
+ <&replicator_out_port0>;
+ };
+ };
+ };
+ };
+
+ tpiu@fe980000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0 0xfe980000 0 0x1000>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ in-ports {
+ port {
+ tpiu_in_port: endpoint {
+ remote-endpoint =
+ <&replicator_out_port1>;
+ };
+ };
+ };
+ };
+};
+
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 3c731e73903a..ca0a6b9f4445 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -12,6 +12,8 @@
* the License, or (at your option) any later version.
*/
+#include "zynqmp-coresight.dtsi"
+
/ {
compatible = "xlnx,zynqmp";
#address-cells = <2>;
--
2.11.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 1/1] arm64: zynqmp: Add CoreSight components
@ 2020-01-30 15:36 ` Wojciech Żmuda
0 siblings, 0 replies; 14+ messages in thread
From: Wojciech Żmuda @ 2020-01-30 15:36 UTC (permalink / raw)
To: linux-arm-kernel, devicetree, coresight
Cc: mark.rutland, mathieu.poirier, rajan.vaja, Michal Mosdorf,
antoine.tenart, nava.manne, michal.simek, m.tretter, t-kristo,
Krzysztof Pilch, Wojciech Żmuda, robh+dt,
Michał Kurowski
From: Wojciech Zmuda <wzmuda@n7space.com>
Add nodes for the following CoreSight components:
- ETMs for A53 cores
- debug components for A53 cores
- funnel gathering outputs from A53 ETMs and SoC-wide funnels
- the only replicator
- all TMCs: 4k ETF, 8k ETF and ETR
- TPIU
Signed-off-by: Wojciech Zmuda <wzmuda@n7space.com>
---
arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi | 272 +++++++++++++++++++++++
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +
2 files changed, 274 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
new file mode 100644
index 000000000000..8b7579ad89cc
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
@@ -0,0 +1,272 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * dtsi for Xilinx Ultrascale+ MPSoC CoreSight components
+ *
+ * Copyright (C) 2019-2020 N7 Space Sp. z o.o.
+ *
+ * Author: Wojciech Zmuda <wzmuda@n7space.com>
+ *
+ */
+/ {
+ etm0@fec40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xfec40000 0 0x1000>;
+ cpu = <&cpu0>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ out-ports {
+ port {
+ etm0_out_port: endpoint {
+ remote-endpoint = <&funnel1_in_port0>;
+ };
+ };
+ };
+ };
+
+ etm1@fed40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xfed40000 0 0x1000>;
+ cpu = <&cpu1>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ out-ports {
+ port {
+ etm1_out_port: endpoint {
+ remote-endpoint = <&funnel1_in_port1>;
+ };
+ };
+ };
+ };
+
+ etm2@fee40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xfee40000 0 0x1000>;
+ cpu = <&cpu2>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ out-ports {
+ port {
+ etm2_out_port: endpoint {
+ remote-endpoint = <&funnel1_in_port2>;
+ };
+ };
+ };
+ };
+
+ etm3@fef40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xfef40000 0 0x1000>;
+ cpu = <&cpu3>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ out-ports {
+ port {
+ etm3_out_port: endpoint {
+ remote-endpoint = <&funnel1_in_port3>;
+ };
+ };
+ };
+ };
+
+ debug0@fec10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfec10000 0 0x1000>;
+ cpu = <&cpu0>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ };
+
+ debug1@fed10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfed10000 0 0x1000>;
+ cpu = <&cpu1>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ };
+
+ debug2@fee10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfee10000 0 0x1000>;
+ cpu = <&cpu2>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ };
+
+ debug3@fee10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0 0xfef10000 0 0x1000>;
+ cpu = <&cpu3>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ };
+
+ funnel1@fe920000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0xfe920000 0 0x1000>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ in-ports {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ port@0 {
+ reg = <0x0>;
+ funnel1_in_port0: endpoint {
+ remote-endpoint = <&etm0_out_port>;
+ };
+ };
+ port@1 {
+ reg = <0x1>;
+ funnel1_in_port1: endpoint {
+ remote-endpoint = <&etm1_out_port>;
+ };
+ };
+ port@2 {
+ reg = <0x2>;
+ funnel1_in_port2: endpoint {
+ remote-endpoint = <&etm2_out_port>;
+ };
+ };
+ port@3 {
+ reg = <0x3>;
+ funnel1_in_port3: endpoint {
+ remote-endpoint = <&etm3_out_port>;
+ };
+ };
+ };
+ out-ports {
+ port {
+ funnel1_out_port0: endpoint {
+ remote-endpoint = <&etf1_in_port>;
+ };
+ };
+ };
+ };
+
+ funnel2@fe930000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0xfe930000 0 0x1000>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ in-ports {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ port@2 {
+ reg = <0x2>;
+ funnel2_in_port2: endpoint {
+ remote-endpoint = <&etf1_out_port>;
+ };
+ };
+ // Funnel2 has another input port connected to
+ // funnel0's output. Funnel0 gathers Cortex-R5 ETMs.
+ };
+ out-ports {
+ port {
+ funnel2_out_port0: endpoint {
+ remote-endpoint = <&etf2_in_port>;
+ };
+ };
+ };
+ };
+
+ etf1@fe940000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0xfe940000 0 0x1000>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ in-ports {
+ port {
+ etf1_in_port: endpoint {
+ remote-endpoint = <&funnel1_out_port0>;
+ };
+ };
+ };
+ out-ports {
+ port {
+ etf1_out_port: endpoint {
+ remote-endpoint = <&funnel2_in_port2>;
+ };
+ };
+ };
+ };
+
+ etf2@fe950000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0xfe950000 0 0x1000>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ in-ports {
+ port {
+ etf2_in_port: endpoint {
+ remote-endpoint = <&funnel2_out_port0>;
+ };
+ };
+ };
+ out-ports {
+ port {
+ etf2_out_port: endpoint {
+ remote-endpoint =
+ <&replicator_in_port0>;
+ };
+ };
+ };
+ };
+
+ replicator {
+ compatible = "arm,coresight-static-replicator";
+ in-ports {
+ port {
+ replicator_in_port0: endpoint {
+ remote-endpoint = <&etf2_out_port>;
+ };
+ };
+ };
+ out-ports {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ port@0 {
+ reg = <0x0>;
+ replicator_out_port0: endpoint {
+ remote-endpoint = <&etr_in_port>;
+ };
+ };
+ port@1 {
+ reg = <0x1>;
+ replicator_out_port1: endpoint {
+ remote-endpoint = <&tpiu_in_port>;
+ };
+ };
+ };
+ };
+
+ etr@fe970000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0xfe970000 0 0x1000>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ in-ports {
+ port {
+ etr_in_port: endpoint {
+ remote-endpoint =
+ <&replicator_out_port0>;
+ };
+ };
+ };
+ };
+
+ tpiu@fe980000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0 0xfe980000 0 0x1000>;
+ clocks = <&clk100>;
+ clock-names = "apb_pclk";
+ in-ports {
+ port {
+ tpiu_in_port: endpoint {
+ remote-endpoint =
+ <&replicator_out_port1>;
+ };
+ };
+ };
+ };
+};
+
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 3c731e73903a..ca0a6b9f4445 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -12,6 +12,8 @@
* the License, or (at your option) any later version.
*/
+#include "zynqmp-coresight.dtsi"
+
/ {
compatible = "xlnx,zynqmp";
#address-cells = <2>;
--
2.11.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 1/1] arm64: zynqmp: Add CoreSight components
2020-01-30 15:36 ` Wojciech Żmuda
@ 2020-01-31 18:36 ` Mathieu Poirier
-1 siblings, 0 replies; 14+ messages in thread
From: Mathieu Poirier @ 2020-01-31 18:36 UTC (permalink / raw)
To: Wojciech Żmuda
Cc: linux-arm-kernel, devicetree, coresight, robh+dt, mark.rutland,
michal.simek, m.tretter, nava.manne, antoine.tenart, t-kristo,
rajan.vaja, Krzysztof Pilch, Michal Mosdorf,
Michał Kurowski
Hi Wojciech,
On Thu, Jan 30, 2020 at 03:36:27PM +0000, Wojciech Żmuda wrote:
> From: Wojciech Zmuda <wzmuda@n7space.com>
>
> Add nodes for the following CoreSight components:
> - ETMs for A53 cores
> - debug components for A53 cores
> - funnel gathering outputs from A53 ETMs and SoC-wide funnels
> - the only replicator
> - all TMCs: 4k ETF, 8k ETF and ETR
> - TPIU
>
> Signed-off-by: Wojciech Zmuda <wzmuda@n7space.com>
> ---
> arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi | 272 +++++++++++++++++++++++
> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +
> 2 files changed, 274 insertions(+)
> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
> new file mode 100644
> index 000000000000..8b7579ad89cc
> --- /dev/null
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
> @@ -0,0 +1,272 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
Looking at other Xilinx DT files there is no space between the SPDX identifier
and the header of the file.
> +/*
> + * dtsi for Xilinx Ultrascale+ MPSoC CoreSight components
> + *
> + * Copyright (C) 2019-2020 N7 Space Sp. z o.o.
> + *
> + * Author: Wojciech Zmuda <wzmuda@n7space.com>
> + *
> + */
> +/ {
> + etm0@fec40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xfec40000 0 0x1000>;
> + cpu = <&cpu0>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + out-ports {
> + port {
> + etm0_out_port: endpoint {
> + remote-endpoint = <&funnel1_in_port0>;
> + };
> + };
> + };
> + };
> +
> + etm1@fed40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xfed40000 0 0x1000>;
> + cpu = <&cpu1>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + out-ports {
> + port {
> + etm1_out_port: endpoint {
> + remote-endpoint = <&funnel1_in_port1>;
> + };
> + };
> + };
> + };
> +
> + etm2@fee40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xfee40000 0 0x1000>;
> + cpu = <&cpu2>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + out-ports {
> + port {
> + etm2_out_port: endpoint {
> + remote-endpoint = <&funnel1_in_port2>;
> + };
> + };
> + };
> + };
> +
> + etm3@fef40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xfef40000 0 0x1000>;
> + cpu = <&cpu3>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + out-ports {
> + port {
> + etm3_out_port: endpoint {
> + remote-endpoint = <&funnel1_in_port3>;
> + };
> + };
> + };
> + };
> +
> + debug0@fec10000 {
> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> + reg = <0 0xfec10000 0 0x1000>;
> + cpu = <&cpu0>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + };
> +
> + debug1@fed10000 {
> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> + reg = <0 0xfed10000 0 0x1000>;
> + cpu = <&cpu1>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + };
> +
> + debug2@fee10000 {
> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> + reg = <0 0xfee10000 0 0x1000>;
> + cpu = <&cpu2>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + };
> +
> + debug3@fee10000 {
> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> + reg = <0 0xfef10000 0 0x1000>;
> + cpu = <&cpu3>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + };
> +
> + funnel1@fe920000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + reg = <0 0xfe920000 0 0x1000>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + in-ports {
> + #address-cells = <0x1>;
> + #size-cells = <0x0>;
> + port@0 {
> + reg = <0x0>;
> + funnel1_in_port0: endpoint {
> + remote-endpoint = <&etm0_out_port>;
> + };
> + };
> + port@1 {
> + reg = <0x1>;
> + funnel1_in_port1: endpoint {
> + remote-endpoint = <&etm1_out_port>;
> + };
> + };
> + port@2 {
> + reg = <0x2>;
> + funnel1_in_port2: endpoint {
> + remote-endpoint = <&etm2_out_port>;
> + };
> + };
> + port@3 {
> + reg = <0x3>;
> + funnel1_in_port3: endpoint {
> + remote-endpoint = <&etm3_out_port>;
> + };
> + };
> + };
> + out-ports {
> + port {
> + funnel1_out_port0: endpoint {
> + remote-endpoint = <&etf1_in_port>;
> + };
> + };
> + };
> + };
> +
> + funnel2@fe930000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + reg = <0 0xfe930000 0 0x1000>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + in-ports {
> + #address-cells = <0x1>;
> + #size-cells = <0x0>;
> + port@2 {
> + reg = <0x2>;
> + funnel2_in_port2: endpoint {
> + remote-endpoint = <&etf1_out_port>;
> + };
> + };
> + // Funnel2 has another input port connected to
> + // funnel0's output. Funnel0 gathers Cortex-R5 ETMs.
C++ style comments.
> + };
> + out-ports {
> + port {
> + funnel2_out_port0: endpoint {
> + remote-endpoint = <&etf2_in_port>;
> + };
> + };
> + };
> + };
> +
> + etf1@fe940000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0xfe940000 0 0x1000>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + in-ports {
> + port {
> + etf1_in_port: endpoint {
> + remote-endpoint = <&funnel1_out_port0>;
> + };
> + };
> + };
> + out-ports {
> + port {
> + etf1_out_port: endpoint {
> + remote-endpoint = <&funnel2_in_port2>;
> + };
> + };
> + };
> + };
> +
> + etf2@fe950000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0xfe950000 0 0x1000>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + in-ports {
> + port {
> + etf2_in_port: endpoint {
> + remote-endpoint = <&funnel2_out_port0>;
> + };
> + };
> + };
> + out-ports {
> + port {
> + etf2_out_port: endpoint {
> + remote-endpoint =
> + <&replicator_in_port0>;
> + };
> + };
> + };
> + };
> +
> + replicator {
> + compatible = "arm,coresight-static-replicator";
> + in-ports {
> + port {
> + replicator_in_port0: endpoint {
> + remote-endpoint = <&etf2_out_port>;
> + };
> + };
> + };
> + out-ports {
> + #address-cells = <0x1>;
> + #size-cells = <0x0>;
> + port@0 {
> + reg = <0x0>;
> + replicator_out_port0: endpoint {
> + remote-endpoint = <&etr_in_port>;
> + };
> + };
> + port@1 {
> + reg = <0x1>;
> + replicator_out_port1: endpoint {
> + remote-endpoint = <&tpiu_in_port>;
> + };
> + };
> + };
> + };
> +
> + etr@fe970000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0xfe970000 0 0x1000>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + in-ports {
> + port {
> + etr_in_port: endpoint {
> + remote-endpoint =
> + <&replicator_out_port0>;
> + };
> + };
> + };
> + };
> +
> + tpiu@fe980000 {
> + compatible = "arm,coresight-tpiu", "arm,primecell";
> + reg = <0 0xfe980000 0 0x1000>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + in-ports {
> + port {
> + tpiu_in_port: endpoint {
> + remote-endpoint =
> + <&replicator_out_port1>;
> + };
> + };
> + };
> + };
> +};
> +
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> index 3c731e73903a..ca0a6b9f4445 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> @@ -12,6 +12,8 @@
> * the License, or (at your option) any later version.
> */
>
> +#include "zynqmp-coresight.dtsi"
> +
Those bindings are correctly used. If Michal doesn't mind the nit-picks I have
highlighted above then
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Otherwise feel free to add my tag to your next revision, which I advise you to
send out once v5.6-rc1 comes out.
Thanks,
Mathieu
> / {
> compatible = "xlnx,zynqmp";
> #address-cells = <2>;
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/1] arm64: zynqmp: Add CoreSight components
@ 2020-01-31 18:36 ` Mathieu Poirier
0 siblings, 0 replies; 14+ messages in thread
From: Mathieu Poirier @ 2020-01-31 18:36 UTC (permalink / raw)
To: Wojciech Żmuda
Cc: mark.rutland, devicetree, rajan.vaja, Michal Mosdorf,
antoine.tenart, nava.manne, coresight, michal.simek, m.tretter,
t-kristo, Krzysztof Pilch, robh+dt, Michał Kurowski,
linux-arm-kernel
Hi Wojciech,
On Thu, Jan 30, 2020 at 03:36:27PM +0000, Wojciech Żmuda wrote:
> From: Wojciech Zmuda <wzmuda@n7space.com>
>
> Add nodes for the following CoreSight components:
> - ETMs for A53 cores
> - debug components for A53 cores
> - funnel gathering outputs from A53 ETMs and SoC-wide funnels
> - the only replicator
> - all TMCs: 4k ETF, 8k ETF and ETR
> - TPIU
>
> Signed-off-by: Wojciech Zmuda <wzmuda@n7space.com>
> ---
> arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi | 272 +++++++++++++++++++++++
> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +
> 2 files changed, 274 insertions(+)
> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
> new file mode 100644
> index 000000000000..8b7579ad89cc
> --- /dev/null
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
> @@ -0,0 +1,272 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
Looking at other Xilinx DT files there is no space between the SPDX identifier
and the header of the file.
> +/*
> + * dtsi for Xilinx Ultrascale+ MPSoC CoreSight components
> + *
> + * Copyright (C) 2019-2020 N7 Space Sp. z o.o.
> + *
> + * Author: Wojciech Zmuda <wzmuda@n7space.com>
> + *
> + */
> +/ {
> + etm0@fec40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xfec40000 0 0x1000>;
> + cpu = <&cpu0>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + out-ports {
> + port {
> + etm0_out_port: endpoint {
> + remote-endpoint = <&funnel1_in_port0>;
> + };
> + };
> + };
> + };
> +
> + etm1@fed40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xfed40000 0 0x1000>;
> + cpu = <&cpu1>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + out-ports {
> + port {
> + etm1_out_port: endpoint {
> + remote-endpoint = <&funnel1_in_port1>;
> + };
> + };
> + };
> + };
> +
> + etm2@fee40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xfee40000 0 0x1000>;
> + cpu = <&cpu2>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + out-ports {
> + port {
> + etm2_out_port: endpoint {
> + remote-endpoint = <&funnel1_in_port2>;
> + };
> + };
> + };
> + };
> +
> + etm3@fef40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xfef40000 0 0x1000>;
> + cpu = <&cpu3>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + out-ports {
> + port {
> + etm3_out_port: endpoint {
> + remote-endpoint = <&funnel1_in_port3>;
> + };
> + };
> + };
> + };
> +
> + debug0@fec10000 {
> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> + reg = <0 0xfec10000 0 0x1000>;
> + cpu = <&cpu0>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + };
> +
> + debug1@fed10000 {
> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> + reg = <0 0xfed10000 0 0x1000>;
> + cpu = <&cpu1>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + };
> +
> + debug2@fee10000 {
> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> + reg = <0 0xfee10000 0 0x1000>;
> + cpu = <&cpu2>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + };
> +
> + debug3@fee10000 {
> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> + reg = <0 0xfef10000 0 0x1000>;
> + cpu = <&cpu3>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + };
> +
> + funnel1@fe920000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + reg = <0 0xfe920000 0 0x1000>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + in-ports {
> + #address-cells = <0x1>;
> + #size-cells = <0x0>;
> + port@0 {
> + reg = <0x0>;
> + funnel1_in_port0: endpoint {
> + remote-endpoint = <&etm0_out_port>;
> + };
> + };
> + port@1 {
> + reg = <0x1>;
> + funnel1_in_port1: endpoint {
> + remote-endpoint = <&etm1_out_port>;
> + };
> + };
> + port@2 {
> + reg = <0x2>;
> + funnel1_in_port2: endpoint {
> + remote-endpoint = <&etm2_out_port>;
> + };
> + };
> + port@3 {
> + reg = <0x3>;
> + funnel1_in_port3: endpoint {
> + remote-endpoint = <&etm3_out_port>;
> + };
> + };
> + };
> + out-ports {
> + port {
> + funnel1_out_port0: endpoint {
> + remote-endpoint = <&etf1_in_port>;
> + };
> + };
> + };
> + };
> +
> + funnel2@fe930000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + reg = <0 0xfe930000 0 0x1000>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + in-ports {
> + #address-cells = <0x1>;
> + #size-cells = <0x0>;
> + port@2 {
> + reg = <0x2>;
> + funnel2_in_port2: endpoint {
> + remote-endpoint = <&etf1_out_port>;
> + };
> + };
> + // Funnel2 has another input port connected to
> + // funnel0's output. Funnel0 gathers Cortex-R5 ETMs.
C++ style comments.
> + };
> + out-ports {
> + port {
> + funnel2_out_port0: endpoint {
> + remote-endpoint = <&etf2_in_port>;
> + };
> + };
> + };
> + };
> +
> + etf1@fe940000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0xfe940000 0 0x1000>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + in-ports {
> + port {
> + etf1_in_port: endpoint {
> + remote-endpoint = <&funnel1_out_port0>;
> + };
> + };
> + };
> + out-ports {
> + port {
> + etf1_out_port: endpoint {
> + remote-endpoint = <&funnel2_in_port2>;
> + };
> + };
> + };
> + };
> +
> + etf2@fe950000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0xfe950000 0 0x1000>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + in-ports {
> + port {
> + etf2_in_port: endpoint {
> + remote-endpoint = <&funnel2_out_port0>;
> + };
> + };
> + };
> + out-ports {
> + port {
> + etf2_out_port: endpoint {
> + remote-endpoint =
> + <&replicator_in_port0>;
> + };
> + };
> + };
> + };
> +
> + replicator {
> + compatible = "arm,coresight-static-replicator";
> + in-ports {
> + port {
> + replicator_in_port0: endpoint {
> + remote-endpoint = <&etf2_out_port>;
> + };
> + };
> + };
> + out-ports {
> + #address-cells = <0x1>;
> + #size-cells = <0x0>;
> + port@0 {
> + reg = <0x0>;
> + replicator_out_port0: endpoint {
> + remote-endpoint = <&etr_in_port>;
> + };
> + };
> + port@1 {
> + reg = <0x1>;
> + replicator_out_port1: endpoint {
> + remote-endpoint = <&tpiu_in_port>;
> + };
> + };
> + };
> + };
> +
> + etr@fe970000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0xfe970000 0 0x1000>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + in-ports {
> + port {
> + etr_in_port: endpoint {
> + remote-endpoint =
> + <&replicator_out_port0>;
> + };
> + };
> + };
> + };
> +
> + tpiu@fe980000 {
> + compatible = "arm,coresight-tpiu", "arm,primecell";
> + reg = <0 0xfe980000 0 0x1000>;
> + clocks = <&clk100>;
> + clock-names = "apb_pclk";
> + in-ports {
> + port {
> + tpiu_in_port: endpoint {
> + remote-endpoint =
> + <&replicator_out_port1>;
> + };
> + };
> + };
> + };
> +};
> +
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> index 3c731e73903a..ca0a6b9f4445 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> @@ -12,6 +12,8 @@
> * the License, or (at your option) any later version.
> */
>
> +#include "zynqmp-coresight.dtsi"
> +
Those bindings are correctly used. If Michal doesn't mind the nit-picks I have
highlighted above then
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Otherwise feel free to add my tag to your next revision, which I advise you to
send out once v5.6-rc1 comes out.
Thanks,
Mathieu
> / {
> compatible = "xlnx,zynqmp";
> #address-cells = <2>;
> --
> 2.11.0
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/1] arm64: zynqmp: Add CoreSight components
2020-01-31 18:36 ` Mathieu Poirier
@ 2020-01-31 18:47 ` Mathieu Poirier
-1 siblings, 0 replies; 14+ messages in thread
From: Mathieu Poirier @ 2020-01-31 18:47 UTC (permalink / raw)
To: Wojciech Żmuda
Cc: linux-arm-kernel, devicetree, coresight, robh+dt, mark.rutland,
michal.simek, m.tretter, nava.manne, antoine.tenart, t-kristo,
rajan.vaja, Krzysztof Pilch, Michal Mosdorf,
Michał Kurowski
On Fri, 31 Jan 2020 at 11:36, Mathieu Poirier
<mathieu.poirier@linaro.org> wrote:
>
> Hi Wojciech,
>
> On Thu, Jan 30, 2020 at 03:36:27PM +0000, Wojciech Żmuda wrote:
> > From: Wojciech Zmuda <wzmuda@n7space.com>
> >
> > Add nodes for the following CoreSight components:
> > - ETMs for A53 cores
> > - debug components for A53 cores
> > - funnel gathering outputs from A53 ETMs and SoC-wide funnels
> > - the only replicator
> > - all TMCs: 4k ETF, 8k ETF and ETR
> > - TPIU
> >
> > Signed-off-by: Wojciech Zmuda <wzmuda@n7space.com>
> > ---
> > arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi | 272 +++++++++++++++++++++++
> > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +
> > 2 files changed, 274 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
> > new file mode 100644
> > index 000000000000..8b7579ad89cc
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
> > @@ -0,0 +1,272 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +
>
> Looking at other Xilinx DT files there is no space between the SPDX identifier
> and the header of the file.
>
> > +/*
> > + * dtsi for Xilinx Ultrascale+ MPSoC CoreSight components
> > + *
> > + * Copyright (C) 2019-2020 N7 Space Sp. z o.o.
> > + *
> > + * Author: Wojciech Zmuda <wzmuda@n7space.com>
> > + *
> > + */
> > +/ {
> > + etm0@fec40000 {
> > + compatible = "arm,coresight-etm4x", "arm,primecell";
> > + reg = <0 0xfec40000 0 0x1000>;
> > + cpu = <&cpu0>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + out-ports {
> > + port {
> > + etm0_out_port: endpoint {
> > + remote-endpoint = <&funnel1_in_port0>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + etm1@fed40000 {
> > + compatible = "arm,coresight-etm4x", "arm,primecell";
> > + reg = <0 0xfed40000 0 0x1000>;
> > + cpu = <&cpu1>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + out-ports {
> > + port {
> > + etm1_out_port: endpoint {
> > + remote-endpoint = <&funnel1_in_port1>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + etm2@fee40000 {
> > + compatible = "arm,coresight-etm4x", "arm,primecell";
> > + reg = <0 0xfee40000 0 0x1000>;
> > + cpu = <&cpu2>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + out-ports {
> > + port {
> > + etm2_out_port: endpoint {
> > + remote-endpoint = <&funnel1_in_port2>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + etm3@fef40000 {
> > + compatible = "arm,coresight-etm4x", "arm,primecell";
> > + reg = <0 0xfef40000 0 0x1000>;
> > + cpu = <&cpu3>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + out-ports {
> > + port {
> > + etm3_out_port: endpoint {
> > + remote-endpoint = <&funnel1_in_port3>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + debug0@fec10000 {
> > + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> > + reg = <0 0xfec10000 0 0x1000>;
> > + cpu = <&cpu0>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + };
> > +
> > + debug1@fed10000 {
> > + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> > + reg = <0 0xfed10000 0 0x1000>;
> > + cpu = <&cpu1>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + };
> > +
> > + debug2@fee10000 {
> > + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> > + reg = <0 0xfee10000 0 0x1000>;
> > + cpu = <&cpu2>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + };
> > +
> > + debug3@fee10000 {
> > + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> > + reg = <0 0xfef10000 0 0x1000>;
> > + cpu = <&cpu3>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + };
> > +
> > + funnel1@fe920000 {
> > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> > + reg = <0 0xfe920000 0 0x1000>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + in-ports {
> > + #address-cells = <0x1>;
> > + #size-cells = <0x0>;
> > + port@0 {
> > + reg = <0x0>;
> > + funnel1_in_port0: endpoint {
> > + remote-endpoint = <&etm0_out_port>;
> > + };
> > + };
> > + port@1 {
> > + reg = <0x1>;
> > + funnel1_in_port1: endpoint {
> > + remote-endpoint = <&etm1_out_port>;
> > + };
> > + };
> > + port@2 {
> > + reg = <0x2>;
> > + funnel1_in_port2: endpoint {
> > + remote-endpoint = <&etm2_out_port>;
> > + };
> > + };
> > + port@3 {
> > + reg = <0x3>;
> > + funnel1_in_port3: endpoint {
> > + remote-endpoint = <&etm3_out_port>;
> > + };
> > + };
> > + };
> > + out-ports {
> > + port {
> > + funnel1_out_port0: endpoint {
> > + remote-endpoint = <&etf1_in_port>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + funnel2@fe930000 {
> > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> > + reg = <0 0xfe930000 0 0x1000>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + in-ports {
> > + #address-cells = <0x1>;
> > + #size-cells = <0x0>;
> > + port@2 {
> > + reg = <0x2>;
> > + funnel2_in_port2: endpoint {
> > + remote-endpoint = <&etf1_out_port>;
> > + };
> > + };
> > + // Funnel2 has another input port connected to
> > + // funnel0's output. Funnel0 gathers Cortex-R5 ETMs.
>
> C++ style comments.
>
> > + };
> > + out-ports {
> > + port {
> > + funnel2_out_port0: endpoint {
> > + remote-endpoint = <&etf2_in_port>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + etf1@fe940000 {
> > + compatible = "arm,coresight-tmc", "arm,primecell";
> > + reg = <0 0xfe940000 0 0x1000>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + in-ports {
> > + port {
> > + etf1_in_port: endpoint {
> > + remote-endpoint = <&funnel1_out_port0>;
> > + };
> > + };
> > + };
> > + out-ports {
> > + port {
> > + etf1_out_port: endpoint {
> > + remote-endpoint = <&funnel2_in_port2>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + etf2@fe950000 {
> > + compatible = "arm,coresight-tmc", "arm,primecell";
> > + reg = <0 0xfe950000 0 0x1000>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + in-ports {
> > + port {
> > + etf2_in_port: endpoint {
> > + remote-endpoint = <&funnel2_out_port0>;
> > + };
> > + };
> > + };
> > + out-ports {
> > + port {
> > + etf2_out_port: endpoint {
> > + remote-endpoint =
> > + <&replicator_in_port0>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + replicator {
> > + compatible = "arm,coresight-static-replicator";
> > + in-ports {
> > + port {
> > + replicator_in_port0: endpoint {
> > + remote-endpoint = <&etf2_out_port>;
> > + };
> > + };
> > + };
> > + out-ports {
> > + #address-cells = <0x1>;
> > + #size-cells = <0x0>;
> > + port@0 {
> > + reg = <0x0>;
> > + replicator_out_port0: endpoint {
> > + remote-endpoint = <&etr_in_port>;
> > + };
> > + };
> > + port@1 {
> > + reg = <0x1>;
> > + replicator_out_port1: endpoint {
> > + remote-endpoint = <&tpiu_in_port>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + etr@fe970000 {
> > + compatible = "arm,coresight-tmc", "arm,primecell";
> > + reg = <0 0xfe970000 0 0x1000>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + in-ports {
> > + port {
> > + etr_in_port: endpoint {
> > + remote-endpoint =
> > + <&replicator_out_port0>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + tpiu@fe980000 {
> > + compatible = "arm,coresight-tpiu", "arm,primecell";
> > + reg = <0 0xfe980000 0 0x1000>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + in-ports {
> > + port {
> > + tpiu_in_port: endpoint {
> > + remote-endpoint =
> > + <&replicator_out_port1>;
> > + };
> > + };
> > + };
> > + };
> > +};
> > +
> > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> > index 3c731e73903a..ca0a6b9f4445 100644
> > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> > @@ -12,6 +12,8 @@
> > * the License, or (at your option) any later version.
> > */
> >
> > +#include "zynqmp-coresight.dtsi"
> > +
>
> Those bindings are correctly used. If Michal doesn't mind the nit-picks I have
> highlighted above then
>
> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
>
> Otherwise feel free to add my tag to your next revision, which I advise you to
> send out once v5.6-rc1 comes out.
I forgot... How does power management work on this board? Is the
power domain where the CS blocks are powered up by the FW? And what
about state retention when processors go idle? Should this be taken
care of in the drivers or is the PMIC properly handling low retention
states? Failure to properly address both cases will likely hang the
board (at boot time of when processors are idled).
>
> Thanks,
> Mathieu
>
> > / {
> > compatible = "xlnx,zynqmp";
> > #address-cells = <2>;
> > --
> > 2.11.0
> >
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/1] arm64: zynqmp: Add CoreSight components
@ 2020-01-31 18:47 ` Mathieu Poirier
0 siblings, 0 replies; 14+ messages in thread
From: Mathieu Poirier @ 2020-01-31 18:47 UTC (permalink / raw)
To: Wojciech Żmuda
Cc: mark.rutland, devicetree, rajan.vaja, Michal Mosdorf,
antoine.tenart, nava.manne, coresight, michal.simek, m.tretter,
t-kristo, Krzysztof Pilch, robh+dt, Michał Kurowski,
linux-arm-kernel
On Fri, 31 Jan 2020 at 11:36, Mathieu Poirier
<mathieu.poirier@linaro.org> wrote:
>
> Hi Wojciech,
>
> On Thu, Jan 30, 2020 at 03:36:27PM +0000, Wojciech Żmuda wrote:
> > From: Wojciech Zmuda <wzmuda@n7space.com>
> >
> > Add nodes for the following CoreSight components:
> > - ETMs for A53 cores
> > - debug components for A53 cores
> > - funnel gathering outputs from A53 ETMs and SoC-wide funnels
> > - the only replicator
> > - all TMCs: 4k ETF, 8k ETF and ETR
> > - TPIU
> >
> > Signed-off-by: Wojciech Zmuda <wzmuda@n7space.com>
> > ---
> > arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi | 272 +++++++++++++++++++++++
> > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +
> > 2 files changed, 274 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
> > new file mode 100644
> > index 000000000000..8b7579ad89cc
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
> > @@ -0,0 +1,272 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +
>
> Looking at other Xilinx DT files there is no space between the SPDX identifier
> and the header of the file.
>
> > +/*
> > + * dtsi for Xilinx Ultrascale+ MPSoC CoreSight components
> > + *
> > + * Copyright (C) 2019-2020 N7 Space Sp. z o.o.
> > + *
> > + * Author: Wojciech Zmuda <wzmuda@n7space.com>
> > + *
> > + */
> > +/ {
> > + etm0@fec40000 {
> > + compatible = "arm,coresight-etm4x", "arm,primecell";
> > + reg = <0 0xfec40000 0 0x1000>;
> > + cpu = <&cpu0>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + out-ports {
> > + port {
> > + etm0_out_port: endpoint {
> > + remote-endpoint = <&funnel1_in_port0>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + etm1@fed40000 {
> > + compatible = "arm,coresight-etm4x", "arm,primecell";
> > + reg = <0 0xfed40000 0 0x1000>;
> > + cpu = <&cpu1>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + out-ports {
> > + port {
> > + etm1_out_port: endpoint {
> > + remote-endpoint = <&funnel1_in_port1>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + etm2@fee40000 {
> > + compatible = "arm,coresight-etm4x", "arm,primecell";
> > + reg = <0 0xfee40000 0 0x1000>;
> > + cpu = <&cpu2>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + out-ports {
> > + port {
> > + etm2_out_port: endpoint {
> > + remote-endpoint = <&funnel1_in_port2>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + etm3@fef40000 {
> > + compatible = "arm,coresight-etm4x", "arm,primecell";
> > + reg = <0 0xfef40000 0 0x1000>;
> > + cpu = <&cpu3>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + out-ports {
> > + port {
> > + etm3_out_port: endpoint {
> > + remote-endpoint = <&funnel1_in_port3>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + debug0@fec10000 {
> > + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> > + reg = <0 0xfec10000 0 0x1000>;
> > + cpu = <&cpu0>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + };
> > +
> > + debug1@fed10000 {
> > + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> > + reg = <0 0xfed10000 0 0x1000>;
> > + cpu = <&cpu1>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + };
> > +
> > + debug2@fee10000 {
> > + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> > + reg = <0 0xfee10000 0 0x1000>;
> > + cpu = <&cpu2>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + };
> > +
> > + debug3@fee10000 {
> > + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> > + reg = <0 0xfef10000 0 0x1000>;
> > + cpu = <&cpu3>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + };
> > +
> > + funnel1@fe920000 {
> > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> > + reg = <0 0xfe920000 0 0x1000>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + in-ports {
> > + #address-cells = <0x1>;
> > + #size-cells = <0x0>;
> > + port@0 {
> > + reg = <0x0>;
> > + funnel1_in_port0: endpoint {
> > + remote-endpoint = <&etm0_out_port>;
> > + };
> > + };
> > + port@1 {
> > + reg = <0x1>;
> > + funnel1_in_port1: endpoint {
> > + remote-endpoint = <&etm1_out_port>;
> > + };
> > + };
> > + port@2 {
> > + reg = <0x2>;
> > + funnel1_in_port2: endpoint {
> > + remote-endpoint = <&etm2_out_port>;
> > + };
> > + };
> > + port@3 {
> > + reg = <0x3>;
> > + funnel1_in_port3: endpoint {
> > + remote-endpoint = <&etm3_out_port>;
> > + };
> > + };
> > + };
> > + out-ports {
> > + port {
> > + funnel1_out_port0: endpoint {
> > + remote-endpoint = <&etf1_in_port>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + funnel2@fe930000 {
> > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> > + reg = <0 0xfe930000 0 0x1000>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + in-ports {
> > + #address-cells = <0x1>;
> > + #size-cells = <0x0>;
> > + port@2 {
> > + reg = <0x2>;
> > + funnel2_in_port2: endpoint {
> > + remote-endpoint = <&etf1_out_port>;
> > + };
> > + };
> > + // Funnel2 has another input port connected to
> > + // funnel0's output. Funnel0 gathers Cortex-R5 ETMs.
>
> C++ style comments.
>
> > + };
> > + out-ports {
> > + port {
> > + funnel2_out_port0: endpoint {
> > + remote-endpoint = <&etf2_in_port>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + etf1@fe940000 {
> > + compatible = "arm,coresight-tmc", "arm,primecell";
> > + reg = <0 0xfe940000 0 0x1000>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + in-ports {
> > + port {
> > + etf1_in_port: endpoint {
> > + remote-endpoint = <&funnel1_out_port0>;
> > + };
> > + };
> > + };
> > + out-ports {
> > + port {
> > + etf1_out_port: endpoint {
> > + remote-endpoint = <&funnel2_in_port2>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + etf2@fe950000 {
> > + compatible = "arm,coresight-tmc", "arm,primecell";
> > + reg = <0 0xfe950000 0 0x1000>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + in-ports {
> > + port {
> > + etf2_in_port: endpoint {
> > + remote-endpoint = <&funnel2_out_port0>;
> > + };
> > + };
> > + };
> > + out-ports {
> > + port {
> > + etf2_out_port: endpoint {
> > + remote-endpoint =
> > + <&replicator_in_port0>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + replicator {
> > + compatible = "arm,coresight-static-replicator";
> > + in-ports {
> > + port {
> > + replicator_in_port0: endpoint {
> > + remote-endpoint = <&etf2_out_port>;
> > + };
> > + };
> > + };
> > + out-ports {
> > + #address-cells = <0x1>;
> > + #size-cells = <0x0>;
> > + port@0 {
> > + reg = <0x0>;
> > + replicator_out_port0: endpoint {
> > + remote-endpoint = <&etr_in_port>;
> > + };
> > + };
> > + port@1 {
> > + reg = <0x1>;
> > + replicator_out_port1: endpoint {
> > + remote-endpoint = <&tpiu_in_port>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + etr@fe970000 {
> > + compatible = "arm,coresight-tmc", "arm,primecell";
> > + reg = <0 0xfe970000 0 0x1000>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + in-ports {
> > + port {
> > + etr_in_port: endpoint {
> > + remote-endpoint =
> > + <&replicator_out_port0>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + tpiu@fe980000 {
> > + compatible = "arm,coresight-tpiu", "arm,primecell";
> > + reg = <0 0xfe980000 0 0x1000>;
> > + clocks = <&clk100>;
> > + clock-names = "apb_pclk";
> > + in-ports {
> > + port {
> > + tpiu_in_port: endpoint {
> > + remote-endpoint =
> > + <&replicator_out_port1>;
> > + };
> > + };
> > + };
> > + };
> > +};
> > +
> > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> > index 3c731e73903a..ca0a6b9f4445 100644
> > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> > @@ -12,6 +12,8 @@
> > * the License, or (at your option) any later version.
> > */
> >
> > +#include "zynqmp-coresight.dtsi"
> > +
>
> Those bindings are correctly used. If Michal doesn't mind the nit-picks I have
> highlighted above then
>
> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
>
> Otherwise feel free to add my tag to your next revision, which I advise you to
> send out once v5.6-rc1 comes out.
I forgot... How does power management work on this board? Is the
power domain where the CS blocks are powered up by the FW? And what
about state retention when processors go idle? Should this be taken
care of in the drivers or is the PMIC properly handling low retention
states? Failure to properly address both cases will likely hang the
board (at boot time of when processors are idled).
>
> Thanks,
> Mathieu
>
> > / {
> > compatible = "xlnx,zynqmp";
> > #address-cells = <2>;
> > --
> > 2.11.0
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/1] arm64: zynqmp: Add CoreSight components
2020-01-31 18:47 ` Mathieu Poirier
@ 2020-01-31 19:37 ` Wojciech Żmuda
-1 siblings, 0 replies; 14+ messages in thread
From: Wojciech Żmuda @ 2020-01-31 19:37 UTC (permalink / raw)
To: Mathieu Poirier
Cc: linux-arm-kernel, devicetree, coresight, robh+dt, mark.rutland,
michal.simek, m.tretter, nava.manne, antoine.tenart, t-kristo,
rajan.vaja, Krzysztof Pilch, Michal Mosdorf,
Michał Kurowski
Hello Mathieu, thank you for quick review!
Please see my responses inline
On 31/01/2020, 19:47, "Mathieu Poirier" <mathieu.poirier@linaro.org> wrote:
> On Fri, 31 Jan 2020 at 11:36, Mathieu Poirier
> <mathieu.poirier@linaro.org> wrote:
>
> > Hi Wojciech,
> >
> > On Thu, Jan 30, 2020 at 03:36:27PM +0000, Wojciech Żmuda wrote:
> > > From: Wojciech Zmuda <wzmuda@n7space.com>
> > >
> > > Add nodes for the following CoreSight components:
> > > - ETMs for A53 cores
> > > - debug components for A53 cores
> > > - funnel gathering outputs from A53 ETMs and SoC-wide funnels
> > > - the only replicator
> > > - all TMCs: 4k ETF, 8k ETF and ETR
> > > - TPIU
> > >
> > > Signed-off-by: Wojciech Zmuda <wzmuda@n7space.com>
> > > ---
> > > arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi | 272 +++++++++++++++++++++++
> > > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +
> > > 2 files changed, 274 insertions(+)
> > > create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
> > >
> > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
> > > new file mode 100644
> > > index 000000000000..8b7579ad89cc
> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
> > > @@ -0,0 +1,272 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +
> >
> > Looking at other Xilinx DT files there is no space between the SPDX identifier
> > and the header of the file.
Ok, I'll remove the extra space.
> >
> > > +/*
> > > + * dtsi for Xilinx Ultrascale+ MPSoC CoreSight components
> > > + *
> > > + * Copyright (C) 2019-2020 N7 Space Sp. z o.o.
> > > + *
> > > + * Author: Wojciech Zmuda <wzmuda@n7space.com>
> > > + *
> > > + */
> > > +/ {
> > > + etm0@fec40000 {
> > > + compatible = "arm,coresight-etm4x", "arm,primecell";
> > > + reg = <0 0xfec40000 0 0x1000>;
> > > + cpu = <&cpu0>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + out-ports {
> > > + port {
> > > + etm0_out_port: endpoint {
> > > + remote-endpoint = <&funnel1_in_port0>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > + etm1@fed40000 {
> > > + compatible = "arm,coresight-etm4x", "arm,primecell";
> > > + reg = <0 0xfed40000 0 0x1000>;
> > > + cpu = <&cpu1>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + out-ports {
> > > + port {
> > > + etm1_out_port: endpoint {
> > > + remote-endpoint = <&funnel1_in_port1>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > + etm2@fee40000 {
> > > + compatible = "arm,coresight-etm4x", "arm,primecell";
> > > + reg = <0 0xfee40000 0 0x1000>;
> > > + cpu = <&cpu2>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + out-ports {
> > > + port {
> > > + etm2_out_port: endpoint {
> > > + remote-endpoint = <&funnel1_in_port2>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > + etm3@fef40000 {
> > > + compatible = "arm,coresight-etm4x", "arm,primecell";
> > > + reg = <0 0xfef40000 0 0x1000>;
> > > + cpu = <&cpu3>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + out-ports {
> > > + port {
> > > + etm3_out_port: endpoint {
> > > + remote-endpoint = <&funnel1_in_port3>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > + debug0@fec10000 {
> > > + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> > > + reg = <0 0xfec10000 0 0x1000>;
> > > + cpu = <&cpu0>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + };
> > > +
> > > + debug1@fed10000 {
> > > + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> > > + reg = <0 0xfed10000 0 0x1000>;
> > > + cpu = <&cpu1>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + };
> > > +
> > > + debug2@fee10000 {
> > > + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> > > + reg = <0 0xfee10000 0 0x1000>;
> > > + cpu = <&cpu2>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + };
> > > +
> > > + debug3@fee10000 {
> > > + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> > > + reg = <0 0xfef10000 0 0x1000>;
> > > + cpu = <&cpu3>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + };
> > > +
> > > + funnel1@fe920000 {
> > > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> > > + reg = <0 0xfe920000 0 0x1000>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + in-ports {
> > > + #address-cells = <0x1>;
> > > + #size-cells = <0x0>;
> > > + port@0 {
> > > + reg = <0x0>;
> > > + funnel1_in_port0: endpoint {
> > > + remote-endpoint = <&etm0_out_port>;
> > > + };
> > > + };
> > > + port@1 {
> > > + reg = <0x1>;
> > > + funnel1_in_port1: endpoint {
> > > + remote-endpoint = <&etm1_out_port>;
> > > + };
> > > + };
> > > + port@2 {
> > > + reg = <0x2>;
> > > + funnel1_in_port2: endpoint {
> > > + remote-endpoint = <&etm2_out_port>;
> > > + };
> > > + };
> > > + port@3 {
> > > + reg = <0x3>;
> > > + funnel1_in_port3: endpoint {
> > > + remote-endpoint = <&etm3_out_port>;
> > > + };
> > > + };
> > > + };
> > > + out-ports {
> > > + port {
> > > + funnel1_out_port0: endpoint {
> > > + remote-endpoint = <&etf1_in_port>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > + funnel2@fe930000 {
> > > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> > > + reg = <0 0xfe930000 0 0x1000>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + in-ports {
> > > + #address-cells = <0x1>;
> > > + #size-cells = <0x0>;
> > > + port@2 {
> > > + reg = <0x2>;
> > > + funnel2_in_port2: endpoint {
> > > + remote-endpoint = <&etf1_out_port>;
> > > + };
> > > + };
> > > + // Funnel2 has another input port connected to
> > > + // funnel0's output. Funnel0 gathers Cortex-R5 ETMs.
> >
> > C++ style comments.
> >
Ok, I'll go with:
/*
* Funnel2 has another input port connected to
* funnel0's output. Funnel0 gathers Cortex-R5 ETMs.
*/
> > > + };
> > > + out-ports {
> > > + port {
> > > + funnel2_out_port0: endpoint {
> > > + remote-endpoint = <&etf2_in_port>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > + etf1@fe940000 {
> > > + compatible = "arm,coresight-tmc", "arm,primecell";
> > > + reg = <0 0xfe940000 0 0x1000>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + in-ports {
> > > + port {
> > > + etf1_in_port: endpoint {
> > > + remote-endpoint = <&funnel1_out_port0>;
> > > + };
> > > + };
> > > + };
> > > + out-ports {
> > > + port {
> > > + etf1_out_port: endpoint {
> > > + remote-endpoint = <&funnel2_in_port2>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > + etf2@fe950000 {
> > > + compatible = "arm,coresight-tmc", "arm,primecell";
> > > + reg = <0 0xfe950000 0 0x1000>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + in-ports {
> > > + port {
> > > + etf2_in_port: endpoint {
> > > + remote-endpoint = <&funnel2_out_port0>;
> > > + };
> > > + };
> > > + };
> > > + out-ports {
> > > + port {
> > > + etf2_out_port: endpoint {
> > > + remote-endpoint =
> > > + <&replicator_in_port0>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > + replicator {
> > > + compatible = "arm,coresight-static-replicator";
> > > + in-ports {
> > > + port {
> > > + replicator_in_port0: endpoint {
> > > + remote-endpoint = <&etf2_out_port>;
> > > + };
> > > + };
> > > + };
> > > + out-ports {
> > > + #address-cells = <0x1>;
> > > + #size-cells = <0x0>;
> > > + port@0 {
> > > + reg = <0x0>;
> > > + replicator_out_port0: endpoint {
> > > + remote-endpoint = <&etr_in_port>;
> > > + };
> > > + };
> > > + port@1 {
> > > + reg = <0x1>;
> > > + replicator_out_port1: endpoint {
> > > + remote-endpoint = <&tpiu_in_port>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > + etr@fe970000 {
> > > + compatible = "arm,coresight-tmc", "arm,primecell";
> > > + reg = <0 0xfe970000 0 0x1000>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + in-ports {
> > > + port {
> > > + etr_in_port: endpoint {
> > > + remote-endpoint =
> > > + <&replicator_out_port0>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > + tpiu@fe980000 {
> > > + compatible = "arm,coresight-tpiu", "arm,primecell";
> > > + reg = <0 0xfe980000 0 0x1000>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + in-ports {
> > > + port {
> > > + tpiu_in_port: endpoint {
> > > + remote-endpoint =
> > > + <&replicator_out_port1>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +};
> > > +
> > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> > > index 3c731e73903a..ca0a6b9f4445 100644
> > > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> > > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> > > @@ -12,6 +12,8 @@
> > > * the License, or (at your option) any later version.
> > > */
>> >
> > > +#include "zynqmp-coresight.dtsi"
> > > +
> >
> > Those bindings are correctly used. If Michal doesn't mind the nit-picks I have
> > highlighted above then
> >
> > Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> >
> > Otherwise feel free to add my tag to your next revision, which I advise you to
> > send out once v5.6-rc1 comes out.
Great, thanks. I'll keep an eye for v5.6-rc1.
>
> I forgot... How does power management work on this board? Is the
> power domain where the CS blocks are powered up by the FW? And what
> about state retention when processors go idle? Should this be taken
> care of in the drivers or is the PMIC properly handling low retention
> states? Failure to properly address both cases will likely hang the
> board (at boot time of when processors are idled).
To be honest, I don't know. I use kernel with CPU idle permanently disabled, as was
advised somewhere in CoreSight-related documents I found at the beginning of my
experiments. It might've been a presentation from Linaro Connect, either yours or Leo's.
I didn't do any extra steps to power CS blocks on, so I guess they're either powered on
by default, or it's taken care of by either FSBL, U-boot or ATF. I use those three provided
by Xilinx. I didn't experiment with vanilla U-boot or ATF.
Can you please suggest some experiments I in this matter? Would turning off CPU idle
in kernel's config and tracing a migrating process be sufficient for such test?
Best regards,
Wojciech
>
> >
> > Thanks,
> > Mathieu
> >
> > > / {
> > > compatible = "xlnx,zynqmp";
> > > #address-cells = <2>;
> > > --
> > > 2.11.0
> > >
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/1] arm64: zynqmp: Add CoreSight components
@ 2020-01-31 19:37 ` Wojciech Żmuda
0 siblings, 0 replies; 14+ messages in thread
From: Wojciech Żmuda @ 2020-01-31 19:37 UTC (permalink / raw)
To: Mathieu Poirier
Cc: mark.rutland, devicetree, rajan.vaja, Michal Mosdorf,
antoine.tenart, nava.manne, coresight, michal.simek, m.tretter,
t-kristo, Krzysztof Pilch, robh+dt, Michał Kurowski,
linux-arm-kernel
Hello Mathieu, thank you for quick review!
Please see my responses inline
On 31/01/2020, 19:47, "Mathieu Poirier" <mathieu.poirier@linaro.org> wrote:
> On Fri, 31 Jan 2020 at 11:36, Mathieu Poirier
> <mathieu.poirier@linaro.org> wrote:
>
> > Hi Wojciech,
> >
> > On Thu, Jan 30, 2020 at 03:36:27PM +0000, Wojciech Żmuda wrote:
> > > From: Wojciech Zmuda <wzmuda@n7space.com>
> > >
> > > Add nodes for the following CoreSight components:
> > > - ETMs for A53 cores
> > > - debug components for A53 cores
> > > - funnel gathering outputs from A53 ETMs and SoC-wide funnels
> > > - the only replicator
> > > - all TMCs: 4k ETF, 8k ETF and ETR
> > > - TPIU
> > >
> > > Signed-off-by: Wojciech Zmuda <wzmuda@n7space.com>
> > > ---
> > > arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi | 272 +++++++++++++++++++++++
> > > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +
> > > 2 files changed, 274 insertions(+)
> > > create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
> > >
> > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
> > > new file mode 100644
> > > index 000000000000..8b7579ad89cc
> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
> > > @@ -0,0 +1,272 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +
> >
> > Looking at other Xilinx DT files there is no space between the SPDX identifier
> > and the header of the file.
Ok, I'll remove the extra space.
> >
> > > +/*
> > > + * dtsi for Xilinx Ultrascale+ MPSoC CoreSight components
> > > + *
> > > + * Copyright (C) 2019-2020 N7 Space Sp. z o.o.
> > > + *
> > > + * Author: Wojciech Zmuda <wzmuda@n7space.com>
> > > + *
> > > + */
> > > +/ {
> > > + etm0@fec40000 {
> > > + compatible = "arm,coresight-etm4x", "arm,primecell";
> > > + reg = <0 0xfec40000 0 0x1000>;
> > > + cpu = <&cpu0>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + out-ports {
> > > + port {
> > > + etm0_out_port: endpoint {
> > > + remote-endpoint = <&funnel1_in_port0>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > + etm1@fed40000 {
> > > + compatible = "arm,coresight-etm4x", "arm,primecell";
> > > + reg = <0 0xfed40000 0 0x1000>;
> > > + cpu = <&cpu1>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + out-ports {
> > > + port {
> > > + etm1_out_port: endpoint {
> > > + remote-endpoint = <&funnel1_in_port1>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > + etm2@fee40000 {
> > > + compatible = "arm,coresight-etm4x", "arm,primecell";
> > > + reg = <0 0xfee40000 0 0x1000>;
> > > + cpu = <&cpu2>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + out-ports {
> > > + port {
> > > + etm2_out_port: endpoint {
> > > + remote-endpoint = <&funnel1_in_port2>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > + etm3@fef40000 {
> > > + compatible = "arm,coresight-etm4x", "arm,primecell";
> > > + reg = <0 0xfef40000 0 0x1000>;
> > > + cpu = <&cpu3>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + out-ports {
> > > + port {
> > > + etm3_out_port: endpoint {
> > > + remote-endpoint = <&funnel1_in_port3>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > + debug0@fec10000 {
> > > + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> > > + reg = <0 0xfec10000 0 0x1000>;
> > > + cpu = <&cpu0>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + };
> > > +
> > > + debug1@fed10000 {
> > > + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> > > + reg = <0 0xfed10000 0 0x1000>;
> > > + cpu = <&cpu1>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + };
> > > +
> > > + debug2@fee10000 {
> > > + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> > > + reg = <0 0xfee10000 0 0x1000>;
> > > + cpu = <&cpu2>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + };
> > > +
> > > + debug3@fee10000 {
> > > + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> > > + reg = <0 0xfef10000 0 0x1000>;
> > > + cpu = <&cpu3>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + };
> > > +
> > > + funnel1@fe920000 {
> > > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> > > + reg = <0 0xfe920000 0 0x1000>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + in-ports {
> > > + #address-cells = <0x1>;
> > > + #size-cells = <0x0>;
> > > + port@0 {
> > > + reg = <0x0>;
> > > + funnel1_in_port0: endpoint {
> > > + remote-endpoint = <&etm0_out_port>;
> > > + };
> > > + };
> > > + port@1 {
> > > + reg = <0x1>;
> > > + funnel1_in_port1: endpoint {
> > > + remote-endpoint = <&etm1_out_port>;
> > > + };
> > > + };
> > > + port@2 {
> > > + reg = <0x2>;
> > > + funnel1_in_port2: endpoint {
> > > + remote-endpoint = <&etm2_out_port>;
> > > + };
> > > + };
> > > + port@3 {
> > > + reg = <0x3>;
> > > + funnel1_in_port3: endpoint {
> > > + remote-endpoint = <&etm3_out_port>;
> > > + };
> > > + };
> > > + };
> > > + out-ports {
> > > + port {
> > > + funnel1_out_port0: endpoint {
> > > + remote-endpoint = <&etf1_in_port>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > + funnel2@fe930000 {
> > > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> > > + reg = <0 0xfe930000 0 0x1000>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + in-ports {
> > > + #address-cells = <0x1>;
> > > + #size-cells = <0x0>;
> > > + port@2 {
> > > + reg = <0x2>;
> > > + funnel2_in_port2: endpoint {
> > > + remote-endpoint = <&etf1_out_port>;
> > > + };
> > > + };
> > > + // Funnel2 has another input port connected to
> > > + // funnel0's output. Funnel0 gathers Cortex-R5 ETMs.
> >
> > C++ style comments.
> >
Ok, I'll go with:
/*
* Funnel2 has another input port connected to
* funnel0's output. Funnel0 gathers Cortex-R5 ETMs.
*/
> > > + };
> > > + out-ports {
> > > + port {
> > > + funnel2_out_port0: endpoint {
> > > + remote-endpoint = <&etf2_in_port>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > + etf1@fe940000 {
> > > + compatible = "arm,coresight-tmc", "arm,primecell";
> > > + reg = <0 0xfe940000 0 0x1000>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + in-ports {
> > > + port {
> > > + etf1_in_port: endpoint {
> > > + remote-endpoint = <&funnel1_out_port0>;
> > > + };
> > > + };
> > > + };
> > > + out-ports {
> > > + port {
> > > + etf1_out_port: endpoint {
> > > + remote-endpoint = <&funnel2_in_port2>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > + etf2@fe950000 {
> > > + compatible = "arm,coresight-tmc", "arm,primecell";
> > > + reg = <0 0xfe950000 0 0x1000>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + in-ports {
> > > + port {
> > > + etf2_in_port: endpoint {
> > > + remote-endpoint = <&funnel2_out_port0>;
> > > + };
> > > + };
> > > + };
> > > + out-ports {
> > > + port {
> > > + etf2_out_port: endpoint {
> > > + remote-endpoint =
> > > + <&replicator_in_port0>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > + replicator {
> > > + compatible = "arm,coresight-static-replicator";
> > > + in-ports {
> > > + port {
> > > + replicator_in_port0: endpoint {
> > > + remote-endpoint = <&etf2_out_port>;
> > > + };
> > > + };
> > > + };
> > > + out-ports {
> > > + #address-cells = <0x1>;
> > > + #size-cells = <0x0>;
> > > + port@0 {
> > > + reg = <0x0>;
> > > + replicator_out_port0: endpoint {
> > > + remote-endpoint = <&etr_in_port>;
> > > + };
> > > + };
> > > + port@1 {
> > > + reg = <0x1>;
> > > + replicator_out_port1: endpoint {
> > > + remote-endpoint = <&tpiu_in_port>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > + etr@fe970000 {
> > > + compatible = "arm,coresight-tmc", "arm,primecell";
> > > + reg = <0 0xfe970000 0 0x1000>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + in-ports {
> > > + port {
> > > + etr_in_port: endpoint {
> > > + remote-endpoint =
> > > + <&replicator_out_port0>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > + tpiu@fe980000 {
> > > + compatible = "arm,coresight-tpiu", "arm,primecell";
> > > + reg = <0 0xfe980000 0 0x1000>;
> > > + clocks = <&clk100>;
> > > + clock-names = "apb_pclk";
> > > + in-ports {
> > > + port {
> > > + tpiu_in_port: endpoint {
> > > + remote-endpoint =
> > > + <&replicator_out_port1>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +};
> > > +
> > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> > > index 3c731e73903a..ca0a6b9f4445 100644
> > > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> > > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> > > @@ -12,6 +12,8 @@
> > > * the License, or (at your option) any later version.
> > > */
>> >
> > > +#include "zynqmp-coresight.dtsi"
> > > +
> >
> > Those bindings are correctly used. If Michal doesn't mind the nit-picks I have
> > highlighted above then
> >
> > Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> >
> > Otherwise feel free to add my tag to your next revision, which I advise you to
> > send out once v5.6-rc1 comes out.
Great, thanks. I'll keep an eye for v5.6-rc1.
>
> I forgot... How does power management work on this board? Is the
> power domain where the CS blocks are powered up by the FW? And what
> about state retention when processors go idle? Should this be taken
> care of in the drivers or is the PMIC properly handling low retention
> states? Failure to properly address both cases will likely hang the
> board (at boot time of when processors are idled).
To be honest, I don't know. I use kernel with CPU idle permanently disabled, as was
advised somewhere in CoreSight-related documents I found at the beginning of my
experiments. It might've been a presentation from Linaro Connect, either yours or Leo's.
I didn't do any extra steps to power CS blocks on, so I guess they're either powered on
by default, or it's taken care of by either FSBL, U-boot or ATF. I use those three provided
by Xilinx. I didn't experiment with vanilla U-boot or ATF.
Can you please suggest some experiments I in this matter? Would turning off CPU idle
in kernel's config and tracing a migrating process be sufficient for such test?
Best regards,
Wojciech
>
> >
> > Thanks,
> > Mathieu
> >
> > > / {
> > > compatible = "xlnx,zynqmp";
> > > #address-cells = <2>;
> > > --
> > > 2.11.0
> > >
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/1] arm64: zynqmp: Add CoreSight components
2020-01-31 19:37 ` Wojciech Żmuda
@ 2020-02-03 7:12 ` Michal Simek
-1 siblings, 0 replies; 14+ messages in thread
From: Michal Simek @ 2020-02-03 7:12 UTC (permalink / raw)
To: Wojciech Żmuda, Mathieu Poirier
Cc: linux-arm-kernel, devicetree, coresight, robh+dt, mark.rutland,
michal.simek, m.tretter, nava.manne, antoine.tenart, t-kristo,
rajan.vaja, Krzysztof Pilch, Michal Mosdorf,
Michał Kurowski, Jolly Shah
On 31. 01. 20 20:37, Wojciech Żmuda wrote:
> Hello Mathieu, thank you for quick review!
> Please see my responses inline
>
> On 31/01/2020, 19:47, "Mathieu Poirier" <mathieu.poirier@linaro.org> wrote:
>> On Fri, 31 Jan 2020 at 11:36, Mathieu Poirier
>> <mathieu.poirier@linaro.org> wrote:
>>
>>> Hi Wojciech,
>>>
>>> On Thu, Jan 30, 2020 at 03:36:27PM +0000, Wojciech Żmuda wrote:
>>>> From: Wojciech Zmuda <wzmuda@n7space.com>
>>>>
>>>> Add nodes for the following CoreSight components:
>>>> - ETMs for A53 cores
>>>> - debug components for A53 cores
>>>> - funnel gathering outputs from A53 ETMs and SoC-wide funnels
>>>> - the only replicator
>>>> - all TMCs: 4k ETF, 8k ETF and ETR
>>>> - TPIU
>>>>
>>>> Signed-off-by: Wojciech Zmuda <wzmuda@n7space.com>
>>>> ---
>>>> arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi | 272 +++++++++++++++++++++++
>>>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +
>>>> 2 files changed, 274 insertions(+)
>>>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
>>>>
>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
>>>> new file mode 100644
>>>> index 000000000000..8b7579ad89cc
>>>> --- /dev/null
>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
>>>> @@ -0,0 +1,272 @@
>>>> +// SPDX-License-Identifier: GPL-2.0+
>>>> +
>>>
>>> Looking at other Xilinx DT files there is no space between the SPDX identifier
>>> and the header of the file.
>
> Ok, I'll remove the extra space.
>
>>>
>>>> +/*
>>>> + * dtsi for Xilinx Ultrascale+ MPSoC CoreSight components
>>>> + *
>>>> + * Copyright (C) 2019-2020 N7 Space Sp. z o.o.
>>>> + *
>>>> + * Author: Wojciech Zmuda <wzmuda@n7space.com>
>>>> + *
>>>> + */
>>>> +/ {
>>>> + etm0@fec40000 {
>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>> + reg = <0 0xfec40000 0 0x1000>;
>>>> + cpu = <&cpu0>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + out-ports {
>>>> + port {
>>>> + etm0_out_port: endpoint {
>>>> + remote-endpoint = <&funnel1_in_port0>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + etm1@fed40000 {
>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>> + reg = <0 0xfed40000 0 0x1000>;
>>>> + cpu = <&cpu1>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + out-ports {
>>>> + port {
>>>> + etm1_out_port: endpoint {
>>>> + remote-endpoint = <&funnel1_in_port1>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + etm2@fee40000 {
>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>> + reg = <0 0xfee40000 0 0x1000>;
>>>> + cpu = <&cpu2>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + out-ports {
>>>> + port {
>>>> + etm2_out_port: endpoint {
>>>> + remote-endpoint = <&funnel1_in_port2>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + etm3@fef40000 {
>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>> + reg = <0 0xfef40000 0 0x1000>;
>>>> + cpu = <&cpu3>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + out-ports {
>>>> + port {
>>>> + etm3_out_port: endpoint {
>>>> + remote-endpoint = <&funnel1_in_port3>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + debug0@fec10000 {
>>>> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
>>>> + reg = <0 0xfec10000 0 0x1000>;
>>>> + cpu = <&cpu0>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + };
>>>> +
>>>> + debug1@fed10000 {
>>>> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
>>>> + reg = <0 0xfed10000 0 0x1000>;
>>>> + cpu = <&cpu1>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + };
>>>> +
>>>> + debug2@fee10000 {
>>>> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
>>>> + reg = <0 0xfee10000 0 0x1000>;
>>>> + cpu = <&cpu2>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + };
>>>> +
>>>> + debug3@fee10000 {
>>>> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
>>>> + reg = <0 0xfef10000 0 0x1000>;
>>>> + cpu = <&cpu3>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + };
>>>> +
>>>> + funnel1@fe920000 {
>>>> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
>>>> + reg = <0 0xfe920000 0 0x1000>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + in-ports {
>>>> + #address-cells = <0x1>;
>>>> + #size-cells = <0x0>;
>>>> + port@0 {
>>>> + reg = <0x0>;
>>>> + funnel1_in_port0: endpoint {
>>>> + remote-endpoint = <&etm0_out_port>;
>>>> + };
>>>> + };
>>>> + port@1 {
>>>> + reg = <0x1>;
>>>> + funnel1_in_port1: endpoint {
>>>> + remote-endpoint = <&etm1_out_port>;
>>>> + };
>>>> + };
>>>> + port@2 {
>>>> + reg = <0x2>;
>>>> + funnel1_in_port2: endpoint {
>>>> + remote-endpoint = <&etm2_out_port>;
>>>> + };
>>>> + };
>>>> + port@3 {
>>>> + reg = <0x3>;
>>>> + funnel1_in_port3: endpoint {
>>>> + remote-endpoint = <&etm3_out_port>;
>>>> + };
>>>> + };
>>>> + };
>>>> + out-ports {
>>>> + port {
>>>> + funnel1_out_port0: endpoint {
>>>> + remote-endpoint = <&etf1_in_port>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + funnel2@fe930000 {
>>>> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
>>>> + reg = <0 0xfe930000 0 0x1000>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + in-ports {
>>>> + #address-cells = <0x1>;
>>>> + #size-cells = <0x0>;
>>>> + port@2 {
>>>> + reg = <0x2>;
>>>> + funnel2_in_port2: endpoint {
>>>> + remote-endpoint = <&etf1_out_port>;
>>>> + };
>>>> + };
>>>> + // Funnel2 has another input port connected to
>>>> + // funnel0's output. Funnel0 gathers Cortex-R5 ETMs.
>>>
>>> C++ style comments.
>>>
>
> Ok, I'll go with:
> /*
> * Funnel2 has another input port connected to
> * funnel0's output. Funnel0 gathers Cortex-R5 ETMs.
> */
>
>>>> + };
>>>> + out-ports {
>>>> + port {
>>>> + funnel2_out_port0: endpoint {
>>>> + remote-endpoint = <&etf2_in_port>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + etf1@fe940000 {
>>>> + compatible = "arm,coresight-tmc", "arm,primecell";
>>>> + reg = <0 0xfe940000 0 0x1000>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + in-ports {
>>>> + port {
>>>> + etf1_in_port: endpoint {
>>>> + remote-endpoint = <&funnel1_out_port0>;
>>>> + };
>>>> + };
>>>> + };
>>>> + out-ports {
>>>> + port {
>>>> + etf1_out_port: endpoint {
>>>> + remote-endpoint = <&funnel2_in_port2>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + etf2@fe950000 {
>>>> + compatible = "arm,coresight-tmc", "arm,primecell";
>>>> + reg = <0 0xfe950000 0 0x1000>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + in-ports {
>>>> + port {
>>>> + etf2_in_port: endpoint {
>>>> + remote-endpoint = <&funnel2_out_port0>;
>>>> + };
>>>> + };
>>>> + };
>>>> + out-ports {
>>>> + port {
>>>> + etf2_out_port: endpoint {
>>>> + remote-endpoint =
>>>> + <&replicator_in_port0>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + replicator {
>>>> + compatible = "arm,coresight-static-replicator";
>>>> + in-ports {
>>>> + port {
>>>> + replicator_in_port0: endpoint {
>>>> + remote-endpoint = <&etf2_out_port>;
>>>> + };
>>>> + };
>>>> + };
>>>> + out-ports {
>>>> + #address-cells = <0x1>;
>>>> + #size-cells = <0x0>;
>>>> + port@0 {
>>>> + reg = <0x0>;
>>>> + replicator_out_port0: endpoint {
>>>> + remote-endpoint = <&etr_in_port>;
>>>> + };
>>>> + };
>>>> + port@1 {
>>>> + reg = <0x1>;
>>>> + replicator_out_port1: endpoint {
>>>> + remote-endpoint = <&tpiu_in_port>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + etr@fe970000 {
>>>> + compatible = "arm,coresight-tmc", "arm,primecell";
>>>> + reg = <0 0xfe970000 0 0x1000>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + in-ports {
>>>> + port {
>>>> + etr_in_port: endpoint {
>>>> + remote-endpoint =
>>>> + <&replicator_out_port0>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + tpiu@fe980000 {
>>>> + compatible = "arm,coresight-tpiu", "arm,primecell";
>>>> + reg = <0 0xfe980000 0 0x1000>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + in-ports {
>>>> + port {
>>>> + tpiu_in_port: endpoint {
>>>> + remote-endpoint =
>>>> + <&replicator_out_port1>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +};
>>>> +
>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>> index 3c731e73903a..ca0a6b9f4445 100644
>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>> @@ -12,6 +12,8 @@
>>>> * the License, or (at your option) any later version.
>>>> */
>>> >
>>>> +#include "zynqmp-coresight.dtsi"
>>>> +
>>>
>>> Those bindings are correctly used. If Michal doesn't mind the nit-picks I have
>>> highlighted above then
>>>
>>> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
>>>
>>> Otherwise feel free to add my tag to your next revision, which I advise you to
>>> send out once v5.6-rc1 comes out.
>
> Great, thanks. I'll keep an eye for v5.6-rc1.
>
>>
>> I forgot... How does power management work on this board? Is the
>> power domain where the CS blocks are powered up by the FW? And what
>> about state retention when processors go idle? Should this be taken
>> care of in the drivers or is the PMIC properly handling low retention
>> states? Failure to properly address both cases will likely hang the
>> board (at boot time of when processors are idled).
>
> To be honest, I don't know. I use kernel with CPU idle permanently disabled, as was
> advised somewhere in CoreSight-related documents I found at the beginning of my
> experiments. It might've been a presentation from Linaro Connect, either yours or Leo's.
> I didn't do any extra steps to power CS blocks on, so I guess they're either powered on
> by default, or it's taken care of by either FSBL, U-boot or ATF. I use those three provided
> by Xilinx. I didn't experiment with vanilla U-boot or ATF.
>
> Can you please suggest some experiments I in this matter? Would turning off CPU idle
> in kernel's config and tracing a migrating process be sufficient for such test?
Jolly: Can you please take a look how this block is powered and how
power stuff should be handled?
Thanks,
Michal
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/1] arm64: zynqmp: Add CoreSight components
@ 2020-02-03 7:12 ` Michal Simek
0 siblings, 0 replies; 14+ messages in thread
From: Michal Simek @ 2020-02-03 7:12 UTC (permalink / raw)
To: Wojciech Żmuda, Mathieu Poirier
Cc: mark.rutland, devicetree, rajan.vaja, Michal Mosdorf,
antoine.tenart, nava.manne, coresight, michal.simek, m.tretter,
t-kristo, Krzysztof Pilch, robh+dt, Jolly Shah,
Michał Kurowski, linux-arm-kernel
On 31. 01. 20 20:37, Wojciech Żmuda wrote:
> Hello Mathieu, thank you for quick review!
> Please see my responses inline
>
> On 31/01/2020, 19:47, "Mathieu Poirier" <mathieu.poirier@linaro.org> wrote:
>> On Fri, 31 Jan 2020 at 11:36, Mathieu Poirier
>> <mathieu.poirier@linaro.org> wrote:
>>
>>> Hi Wojciech,
>>>
>>> On Thu, Jan 30, 2020 at 03:36:27PM +0000, Wojciech Żmuda wrote:
>>>> From: Wojciech Zmuda <wzmuda@n7space.com>
>>>>
>>>> Add nodes for the following CoreSight components:
>>>> - ETMs for A53 cores
>>>> - debug components for A53 cores
>>>> - funnel gathering outputs from A53 ETMs and SoC-wide funnels
>>>> - the only replicator
>>>> - all TMCs: 4k ETF, 8k ETF and ETR
>>>> - TPIU
>>>>
>>>> Signed-off-by: Wojciech Zmuda <wzmuda@n7space.com>
>>>> ---
>>>> arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi | 272 +++++++++++++++++++++++
>>>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +
>>>> 2 files changed, 274 insertions(+)
>>>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
>>>>
>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
>>>> new file mode 100644
>>>> index 000000000000..8b7579ad89cc
>>>> --- /dev/null
>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
>>>> @@ -0,0 +1,272 @@
>>>> +// SPDX-License-Identifier: GPL-2.0+
>>>> +
>>>
>>> Looking at other Xilinx DT files there is no space between the SPDX identifier
>>> and the header of the file.
>
> Ok, I'll remove the extra space.
>
>>>
>>>> +/*
>>>> + * dtsi for Xilinx Ultrascale+ MPSoC CoreSight components
>>>> + *
>>>> + * Copyright (C) 2019-2020 N7 Space Sp. z o.o.
>>>> + *
>>>> + * Author: Wojciech Zmuda <wzmuda@n7space.com>
>>>> + *
>>>> + */
>>>> +/ {
>>>> + etm0@fec40000 {
>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>> + reg = <0 0xfec40000 0 0x1000>;
>>>> + cpu = <&cpu0>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + out-ports {
>>>> + port {
>>>> + etm0_out_port: endpoint {
>>>> + remote-endpoint = <&funnel1_in_port0>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + etm1@fed40000 {
>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>> + reg = <0 0xfed40000 0 0x1000>;
>>>> + cpu = <&cpu1>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + out-ports {
>>>> + port {
>>>> + etm1_out_port: endpoint {
>>>> + remote-endpoint = <&funnel1_in_port1>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + etm2@fee40000 {
>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>> + reg = <0 0xfee40000 0 0x1000>;
>>>> + cpu = <&cpu2>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + out-ports {
>>>> + port {
>>>> + etm2_out_port: endpoint {
>>>> + remote-endpoint = <&funnel1_in_port2>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + etm3@fef40000 {
>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>> + reg = <0 0xfef40000 0 0x1000>;
>>>> + cpu = <&cpu3>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + out-ports {
>>>> + port {
>>>> + etm3_out_port: endpoint {
>>>> + remote-endpoint = <&funnel1_in_port3>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + debug0@fec10000 {
>>>> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
>>>> + reg = <0 0xfec10000 0 0x1000>;
>>>> + cpu = <&cpu0>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + };
>>>> +
>>>> + debug1@fed10000 {
>>>> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
>>>> + reg = <0 0xfed10000 0 0x1000>;
>>>> + cpu = <&cpu1>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + };
>>>> +
>>>> + debug2@fee10000 {
>>>> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
>>>> + reg = <0 0xfee10000 0 0x1000>;
>>>> + cpu = <&cpu2>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + };
>>>> +
>>>> + debug3@fee10000 {
>>>> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
>>>> + reg = <0 0xfef10000 0 0x1000>;
>>>> + cpu = <&cpu3>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + };
>>>> +
>>>> + funnel1@fe920000 {
>>>> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
>>>> + reg = <0 0xfe920000 0 0x1000>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + in-ports {
>>>> + #address-cells = <0x1>;
>>>> + #size-cells = <0x0>;
>>>> + port@0 {
>>>> + reg = <0x0>;
>>>> + funnel1_in_port0: endpoint {
>>>> + remote-endpoint = <&etm0_out_port>;
>>>> + };
>>>> + };
>>>> + port@1 {
>>>> + reg = <0x1>;
>>>> + funnel1_in_port1: endpoint {
>>>> + remote-endpoint = <&etm1_out_port>;
>>>> + };
>>>> + };
>>>> + port@2 {
>>>> + reg = <0x2>;
>>>> + funnel1_in_port2: endpoint {
>>>> + remote-endpoint = <&etm2_out_port>;
>>>> + };
>>>> + };
>>>> + port@3 {
>>>> + reg = <0x3>;
>>>> + funnel1_in_port3: endpoint {
>>>> + remote-endpoint = <&etm3_out_port>;
>>>> + };
>>>> + };
>>>> + };
>>>> + out-ports {
>>>> + port {
>>>> + funnel1_out_port0: endpoint {
>>>> + remote-endpoint = <&etf1_in_port>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + funnel2@fe930000 {
>>>> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
>>>> + reg = <0 0xfe930000 0 0x1000>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + in-ports {
>>>> + #address-cells = <0x1>;
>>>> + #size-cells = <0x0>;
>>>> + port@2 {
>>>> + reg = <0x2>;
>>>> + funnel2_in_port2: endpoint {
>>>> + remote-endpoint = <&etf1_out_port>;
>>>> + };
>>>> + };
>>>> + // Funnel2 has another input port connected to
>>>> + // funnel0's output. Funnel0 gathers Cortex-R5 ETMs.
>>>
>>> C++ style comments.
>>>
>
> Ok, I'll go with:
> /*
> * Funnel2 has another input port connected to
> * funnel0's output. Funnel0 gathers Cortex-R5 ETMs.
> */
>
>>>> + };
>>>> + out-ports {
>>>> + port {
>>>> + funnel2_out_port0: endpoint {
>>>> + remote-endpoint = <&etf2_in_port>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + etf1@fe940000 {
>>>> + compatible = "arm,coresight-tmc", "arm,primecell";
>>>> + reg = <0 0xfe940000 0 0x1000>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + in-ports {
>>>> + port {
>>>> + etf1_in_port: endpoint {
>>>> + remote-endpoint = <&funnel1_out_port0>;
>>>> + };
>>>> + };
>>>> + };
>>>> + out-ports {
>>>> + port {
>>>> + etf1_out_port: endpoint {
>>>> + remote-endpoint = <&funnel2_in_port2>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + etf2@fe950000 {
>>>> + compatible = "arm,coresight-tmc", "arm,primecell";
>>>> + reg = <0 0xfe950000 0 0x1000>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + in-ports {
>>>> + port {
>>>> + etf2_in_port: endpoint {
>>>> + remote-endpoint = <&funnel2_out_port0>;
>>>> + };
>>>> + };
>>>> + };
>>>> + out-ports {
>>>> + port {
>>>> + etf2_out_port: endpoint {
>>>> + remote-endpoint =
>>>> + <&replicator_in_port0>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + replicator {
>>>> + compatible = "arm,coresight-static-replicator";
>>>> + in-ports {
>>>> + port {
>>>> + replicator_in_port0: endpoint {
>>>> + remote-endpoint = <&etf2_out_port>;
>>>> + };
>>>> + };
>>>> + };
>>>> + out-ports {
>>>> + #address-cells = <0x1>;
>>>> + #size-cells = <0x0>;
>>>> + port@0 {
>>>> + reg = <0x0>;
>>>> + replicator_out_port0: endpoint {
>>>> + remote-endpoint = <&etr_in_port>;
>>>> + };
>>>> + };
>>>> + port@1 {
>>>> + reg = <0x1>;
>>>> + replicator_out_port1: endpoint {
>>>> + remote-endpoint = <&tpiu_in_port>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + etr@fe970000 {
>>>> + compatible = "arm,coresight-tmc", "arm,primecell";
>>>> + reg = <0 0xfe970000 0 0x1000>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + in-ports {
>>>> + port {
>>>> + etr_in_port: endpoint {
>>>> + remote-endpoint =
>>>> + <&replicator_out_port0>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + tpiu@fe980000 {
>>>> + compatible = "arm,coresight-tpiu", "arm,primecell";
>>>> + reg = <0 0xfe980000 0 0x1000>;
>>>> + clocks = <&clk100>;
>>>> + clock-names = "apb_pclk";
>>>> + in-ports {
>>>> + port {
>>>> + tpiu_in_port: endpoint {
>>>> + remote-endpoint =
>>>> + <&replicator_out_port1>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +};
>>>> +
>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>> index 3c731e73903a..ca0a6b9f4445 100644
>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>> @@ -12,6 +12,8 @@
>>>> * the License, or (at your option) any later version.
>>>> */
>>> >
>>>> +#include "zynqmp-coresight.dtsi"
>>>> +
>>>
>>> Those bindings are correctly used. If Michal doesn't mind the nit-picks I have
>>> highlighted above then
>>>
>>> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
>>>
>>> Otherwise feel free to add my tag to your next revision, which I advise you to
>>> send out once v5.6-rc1 comes out.
>
> Great, thanks. I'll keep an eye for v5.6-rc1.
>
>>
>> I forgot... How does power management work on this board? Is the
>> power domain where the CS blocks are powered up by the FW? And what
>> about state retention when processors go idle? Should this be taken
>> care of in the drivers or is the PMIC properly handling low retention
>> states? Failure to properly address both cases will likely hang the
>> board (at boot time of when processors are idled).
>
> To be honest, I don't know. I use kernel with CPU idle permanently disabled, as was
> advised somewhere in CoreSight-related documents I found at the beginning of my
> experiments. It might've been a presentation from Linaro Connect, either yours or Leo's.
> I didn't do any extra steps to power CS blocks on, so I guess they're either powered on
> by default, or it's taken care of by either FSBL, U-boot or ATF. I use those three provided
> by Xilinx. I didn't experiment with vanilla U-boot or ATF.
>
> Can you please suggest some experiments I in this matter? Would turning off CPU idle
> in kernel's config and tracing a migrating process be sufficient for such test?
Jolly: Can you please take a look how this block is powered and how
power stuff should be handled?
Thanks,
Michal
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/1] arm64: zynqmp: Add CoreSight components
2020-02-03 7:12 ` Michal Simek
@ 2020-02-03 17:57 ` Mathieu Poirier
-1 siblings, 0 replies; 14+ messages in thread
From: Mathieu Poirier @ 2020-02-03 17:57 UTC (permalink / raw)
To: Michal Simek
Cc: Wojciech Żmuda, linux-arm-kernel, devicetree, coresight,
robh+dt, mark.rutland, m.tretter, nava.manne, antoine.tenart,
t-kristo, rajan.vaja, Krzysztof Pilch, Michal Mosdorf,
Michał Kurowski, Jolly Shah
On Mon, 3 Feb 2020 at 00:12, Michal Simek <michal.simek@xilinx.com> wrote:
>
> On 31. 01. 20 20:37, Wojciech Żmuda wrote:
> > Hello Mathieu, thank you for quick review!
> > Please see my responses inline
> >
> > On 31/01/2020, 19:47, "Mathieu Poirier" <mathieu.poirier@linaro.org> wrote:
> >> On Fri, 31 Jan 2020 at 11:36, Mathieu Poirier
> >> <mathieu.poirier@linaro.org> wrote:
> >>
> >>> Hi Wojciech,
> >>>
> >>> On Thu, Jan 30, 2020 at 03:36:27PM +0000, Wojciech Żmuda wrote:
> >>>> From: Wojciech Zmuda <wzmuda@n7space.com>
> >>>>
> >>>> Add nodes for the following CoreSight components:
> >>>> - ETMs for A53 cores
> >>>> - debug components for A53 cores
> >>>> - funnel gathering outputs from A53 ETMs and SoC-wide funnels
> >>>> - the only replicator
> >>>> - all TMCs: 4k ETF, 8k ETF and ETR
> >>>> - TPIU
> >>>>
> >>>> Signed-off-by: Wojciech Zmuda <wzmuda@n7space.com>
> >>>> ---
> >>>> arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi | 272 +++++++++++++++++++++++
> >>>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +
> >>>> 2 files changed, 274 insertions(+)
> >>>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
> >>>>
> >>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
> >>>> new file mode 100644
> >>>> index 000000000000..8b7579ad89cc
> >>>> --- /dev/null
> >>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
> >>>> @@ -0,0 +1,272 @@
> >>>> +// SPDX-License-Identifier: GPL-2.0+
> >>>> +
> >>>
> >>> Looking at other Xilinx DT files there is no space between the SPDX identifier
> >>> and the header of the file.
> >
> > Ok, I'll remove the extra space.
> >
> >>>
> >>>> +/*
> >>>> + * dtsi for Xilinx Ultrascale+ MPSoC CoreSight components
> >>>> + *
> >>>> + * Copyright (C) 2019-2020 N7 Space Sp. z o.o.
> >>>> + *
> >>>> + * Author: Wojciech Zmuda <wzmuda@n7space.com>
> >>>> + *
> >>>> + */
> >>>> +/ {
> >>>> + etm0@fec40000 {
> >>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
> >>>> + reg = <0 0xfec40000 0 0x1000>;
> >>>> + cpu = <&cpu0>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + out-ports {
> >>>> + port {
> >>>> + etm0_out_port: endpoint {
> >>>> + remote-endpoint = <&funnel1_in_port0>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + etm1@fed40000 {
> >>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
> >>>> + reg = <0 0xfed40000 0 0x1000>;
> >>>> + cpu = <&cpu1>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + out-ports {
> >>>> + port {
> >>>> + etm1_out_port: endpoint {
> >>>> + remote-endpoint = <&funnel1_in_port1>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + etm2@fee40000 {
> >>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
> >>>> + reg = <0 0xfee40000 0 0x1000>;
> >>>> + cpu = <&cpu2>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + out-ports {
> >>>> + port {
> >>>> + etm2_out_port: endpoint {
> >>>> + remote-endpoint = <&funnel1_in_port2>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + etm3@fef40000 {
> >>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
> >>>> + reg = <0 0xfef40000 0 0x1000>;
> >>>> + cpu = <&cpu3>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + out-ports {
> >>>> + port {
> >>>> + etm3_out_port: endpoint {
> >>>> + remote-endpoint = <&funnel1_in_port3>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + debug0@fec10000 {
> >>>> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> >>>> + reg = <0 0xfec10000 0 0x1000>;
> >>>> + cpu = <&cpu0>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + };
> >>>> +
> >>>> + debug1@fed10000 {
> >>>> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> >>>> + reg = <0 0xfed10000 0 0x1000>;
> >>>> + cpu = <&cpu1>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + };
> >>>> +
> >>>> + debug2@fee10000 {
> >>>> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> >>>> + reg = <0 0xfee10000 0 0x1000>;
> >>>> + cpu = <&cpu2>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + };
> >>>> +
> >>>> + debug3@fee10000 {
> >>>> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> >>>> + reg = <0 0xfef10000 0 0x1000>;
> >>>> + cpu = <&cpu3>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + };
> >>>> +
> >>>> + funnel1@fe920000 {
> >>>> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> >>>> + reg = <0 0xfe920000 0 0x1000>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + in-ports {
> >>>> + #address-cells = <0x1>;
> >>>> + #size-cells = <0x0>;
> >>>> + port@0 {
> >>>> + reg = <0x0>;
> >>>> + funnel1_in_port0: endpoint {
> >>>> + remote-endpoint = <&etm0_out_port>;
> >>>> + };
> >>>> + };
> >>>> + port@1 {
> >>>> + reg = <0x1>;
> >>>> + funnel1_in_port1: endpoint {
> >>>> + remote-endpoint = <&etm1_out_port>;
> >>>> + };
> >>>> + };
> >>>> + port@2 {
> >>>> + reg = <0x2>;
> >>>> + funnel1_in_port2: endpoint {
> >>>> + remote-endpoint = <&etm2_out_port>;
> >>>> + };
> >>>> + };
> >>>> + port@3 {
> >>>> + reg = <0x3>;
> >>>> + funnel1_in_port3: endpoint {
> >>>> + remote-endpoint = <&etm3_out_port>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + out-ports {
> >>>> + port {
> >>>> + funnel1_out_port0: endpoint {
> >>>> + remote-endpoint = <&etf1_in_port>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + funnel2@fe930000 {
> >>>> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> >>>> + reg = <0 0xfe930000 0 0x1000>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + in-ports {
> >>>> + #address-cells = <0x1>;
> >>>> + #size-cells = <0x0>;
> >>>> + port@2 {
> >>>> + reg = <0x2>;
> >>>> + funnel2_in_port2: endpoint {
> >>>> + remote-endpoint = <&etf1_out_port>;
> >>>> + };
> >>>> + };
> >>>> + // Funnel2 has another input port connected to
> >>>> + // funnel0's output. Funnel0 gathers Cortex-R5 ETMs.
> >>>
> >>> C++ style comments.
> >>>
> >
> > Ok, I'll go with:
> > /*
> > * Funnel2 has another input port connected to
> > * funnel0's output. Funnel0 gathers Cortex-R5 ETMs.
> > */
> >
> >>>> + };
> >>>> + out-ports {
> >>>> + port {
> >>>> + funnel2_out_port0: endpoint {
> >>>> + remote-endpoint = <&etf2_in_port>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + etf1@fe940000 {
> >>>> + compatible = "arm,coresight-tmc", "arm,primecell";
> >>>> + reg = <0 0xfe940000 0 0x1000>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + in-ports {
> >>>> + port {
> >>>> + etf1_in_port: endpoint {
> >>>> + remote-endpoint = <&funnel1_out_port0>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + out-ports {
> >>>> + port {
> >>>> + etf1_out_port: endpoint {
> >>>> + remote-endpoint = <&funnel2_in_port2>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + etf2@fe950000 {
> >>>> + compatible = "arm,coresight-tmc", "arm,primecell";
> >>>> + reg = <0 0xfe950000 0 0x1000>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + in-ports {
> >>>> + port {
> >>>> + etf2_in_port: endpoint {
> >>>> + remote-endpoint = <&funnel2_out_port0>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + out-ports {
> >>>> + port {
> >>>> + etf2_out_port: endpoint {
> >>>> + remote-endpoint =
> >>>> + <&replicator_in_port0>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + replicator {
> >>>> + compatible = "arm,coresight-static-replicator";
> >>>> + in-ports {
> >>>> + port {
> >>>> + replicator_in_port0: endpoint {
> >>>> + remote-endpoint = <&etf2_out_port>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + out-ports {
> >>>> + #address-cells = <0x1>;
> >>>> + #size-cells = <0x0>;
> >>>> + port@0 {
> >>>> + reg = <0x0>;
> >>>> + replicator_out_port0: endpoint {
> >>>> + remote-endpoint = <&etr_in_port>;
> >>>> + };
> >>>> + };
> >>>> + port@1 {
> >>>> + reg = <0x1>;
> >>>> + replicator_out_port1: endpoint {
> >>>> + remote-endpoint = <&tpiu_in_port>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + etr@fe970000 {
> >>>> + compatible = "arm,coresight-tmc", "arm,primecell";
> >>>> + reg = <0 0xfe970000 0 0x1000>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + in-ports {
> >>>> + port {
> >>>> + etr_in_port: endpoint {
> >>>> + remote-endpoint =
> >>>> + <&replicator_out_port0>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + tpiu@fe980000 {
> >>>> + compatible = "arm,coresight-tpiu", "arm,primecell";
> >>>> + reg = <0 0xfe980000 0 0x1000>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + in-ports {
> >>>> + port {
> >>>> + tpiu_in_port: endpoint {
> >>>> + remote-endpoint =
> >>>> + <&replicator_out_port1>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> +};
> >>>> +
> >>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> >>>> index 3c731e73903a..ca0a6b9f4445 100644
> >>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> >>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> >>>> @@ -12,6 +12,8 @@
> >>>> * the License, or (at your option) any later version.
> >>>> */
> >>> >
> >>>> +#include "zynqmp-coresight.dtsi"
> >>>> +
> >>>
> >>> Those bindings are correctly used. If Michal doesn't mind the nit-picks I have
> >>> highlighted above then
> >>>
> >>> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> >>>
> >>> Otherwise feel free to add my tag to your next revision, which I advise you to
> >>> send out once v5.6-rc1 comes out.
> >
> > Great, thanks. I'll keep an eye for v5.6-rc1.
> >
> >>
> >> I forgot... How does power management work on this board? Is the
> >> power domain where the CS blocks are powered up by the FW? And what
> >> about state retention when processors go idle? Should this be taken
> >> care of in the drivers or is the PMIC properly handling low retention
> >> states? Failure to properly address both cases will likely hang the
> >> board (at boot time of when processors are idled).
> >
> > To be honest, I don't know. I use kernel with CPU idle permanently disabled, as was
> > advised somewhere in CoreSight-related documents I found at the beginning of my
> > experiments. It might've been a presentation from Linaro Connect, either yours or Leo's.
> > I didn't do any extra steps to power CS blocks on, so I guess they're either powered on
> > by default, or it's taken care of by either FSBL, U-boot or ATF. I use those three provided
> > by Xilinx. I didn't experiment with vanilla U-boot or ATF.
> >
> > Can you please suggest some experiments I in this matter? Would turning off CPU idle
> > in kernel's config and tracing a migrating process be sufficient for such test?
This is a fairly new feature that Andrew finished in September [1].
It allows to save/restore the coresight tracers' configuration when
CPUs enter idle states, allowing coresight to be used when CPUIdle is
enabled. This is necessary when the HW line driven by the PU bit of
configuration register TRCPDCR is not connected to a PMIC or the
PMIC's firmware is ignoring the signal. It is very likely that either
one of those scenarios are enacted on this platform.
To deal with power management issues on the ETM blocks, re-enable
CPUIdle and add "arm,coresight-loses-context-with-cpu;" to each of the
ETM node specification in the DT (see bindings for details). That
should take care of the ETMs only, which are usually in the CPU power
domain. The rest of the coresight blocks are generally located in the
debug power domain, something I can't help with. It is either enabled
at boot time by the boot loader or the kernel, or handled dynamically
at run time. See the "power-domains" property in the Juno coresight
specification[2].
[1]. https://www.spinics.net/lists/devicetree/msg309139.html
[2]. https://elixir.bootlin.com/linux/latest/source/arch/arm64/boot/dts/arm/juno-base.dtsi#L169
>
> Jolly: Can you please take a look how this block is powered and how
> power stuff should be handled?
>
> Thanks,
> Michal
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/1] arm64: zynqmp: Add CoreSight components
@ 2020-02-03 17:57 ` Mathieu Poirier
0 siblings, 0 replies; 14+ messages in thread
From: Mathieu Poirier @ 2020-02-03 17:57 UTC (permalink / raw)
To: Michal Simek
Cc: mark.rutland, devicetree, rajan.vaja, Wojciech Żmuda,
Michal Mosdorf, antoine.tenart, nava.manne, coresight, m.tretter,
t-kristo, Krzysztof Pilch, robh+dt, Jolly Shah,
Michał Kurowski, linux-arm-kernel
On Mon, 3 Feb 2020 at 00:12, Michal Simek <michal.simek@xilinx.com> wrote:
>
> On 31. 01. 20 20:37, Wojciech Żmuda wrote:
> > Hello Mathieu, thank you for quick review!
> > Please see my responses inline
> >
> > On 31/01/2020, 19:47, "Mathieu Poirier" <mathieu.poirier@linaro.org> wrote:
> >> On Fri, 31 Jan 2020 at 11:36, Mathieu Poirier
> >> <mathieu.poirier@linaro.org> wrote:
> >>
> >>> Hi Wojciech,
> >>>
> >>> On Thu, Jan 30, 2020 at 03:36:27PM +0000, Wojciech Żmuda wrote:
> >>>> From: Wojciech Zmuda <wzmuda@n7space.com>
> >>>>
> >>>> Add nodes for the following CoreSight components:
> >>>> - ETMs for A53 cores
> >>>> - debug components for A53 cores
> >>>> - funnel gathering outputs from A53 ETMs and SoC-wide funnels
> >>>> - the only replicator
> >>>> - all TMCs: 4k ETF, 8k ETF and ETR
> >>>> - TPIU
> >>>>
> >>>> Signed-off-by: Wojciech Zmuda <wzmuda@n7space.com>
> >>>> ---
> >>>> arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi | 272 +++++++++++++++++++++++
> >>>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +
> >>>> 2 files changed, 274 insertions(+)
> >>>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
> >>>>
> >>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
> >>>> new file mode 100644
> >>>> index 000000000000..8b7579ad89cc
> >>>> --- /dev/null
> >>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi
> >>>> @@ -0,0 +1,272 @@
> >>>> +// SPDX-License-Identifier: GPL-2.0+
> >>>> +
> >>>
> >>> Looking at other Xilinx DT files there is no space between the SPDX identifier
> >>> and the header of the file.
> >
> > Ok, I'll remove the extra space.
> >
> >>>
> >>>> +/*
> >>>> + * dtsi for Xilinx Ultrascale+ MPSoC CoreSight components
> >>>> + *
> >>>> + * Copyright (C) 2019-2020 N7 Space Sp. z o.o.
> >>>> + *
> >>>> + * Author: Wojciech Zmuda <wzmuda@n7space.com>
> >>>> + *
> >>>> + */
> >>>> +/ {
> >>>> + etm0@fec40000 {
> >>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
> >>>> + reg = <0 0xfec40000 0 0x1000>;
> >>>> + cpu = <&cpu0>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + out-ports {
> >>>> + port {
> >>>> + etm0_out_port: endpoint {
> >>>> + remote-endpoint = <&funnel1_in_port0>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + etm1@fed40000 {
> >>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
> >>>> + reg = <0 0xfed40000 0 0x1000>;
> >>>> + cpu = <&cpu1>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + out-ports {
> >>>> + port {
> >>>> + etm1_out_port: endpoint {
> >>>> + remote-endpoint = <&funnel1_in_port1>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + etm2@fee40000 {
> >>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
> >>>> + reg = <0 0xfee40000 0 0x1000>;
> >>>> + cpu = <&cpu2>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + out-ports {
> >>>> + port {
> >>>> + etm2_out_port: endpoint {
> >>>> + remote-endpoint = <&funnel1_in_port2>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + etm3@fef40000 {
> >>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
> >>>> + reg = <0 0xfef40000 0 0x1000>;
> >>>> + cpu = <&cpu3>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + out-ports {
> >>>> + port {
> >>>> + etm3_out_port: endpoint {
> >>>> + remote-endpoint = <&funnel1_in_port3>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + debug0@fec10000 {
> >>>> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> >>>> + reg = <0 0xfec10000 0 0x1000>;
> >>>> + cpu = <&cpu0>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + };
> >>>> +
> >>>> + debug1@fed10000 {
> >>>> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> >>>> + reg = <0 0xfed10000 0 0x1000>;
> >>>> + cpu = <&cpu1>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + };
> >>>> +
> >>>> + debug2@fee10000 {
> >>>> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> >>>> + reg = <0 0xfee10000 0 0x1000>;
> >>>> + cpu = <&cpu2>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + };
> >>>> +
> >>>> + debug3@fee10000 {
> >>>> + compatible = "arm,coresight-cpu-debug", "arm,primecell";
> >>>> + reg = <0 0xfef10000 0 0x1000>;
> >>>> + cpu = <&cpu3>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + };
> >>>> +
> >>>> + funnel1@fe920000 {
> >>>> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> >>>> + reg = <0 0xfe920000 0 0x1000>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + in-ports {
> >>>> + #address-cells = <0x1>;
> >>>> + #size-cells = <0x0>;
> >>>> + port@0 {
> >>>> + reg = <0x0>;
> >>>> + funnel1_in_port0: endpoint {
> >>>> + remote-endpoint = <&etm0_out_port>;
> >>>> + };
> >>>> + };
> >>>> + port@1 {
> >>>> + reg = <0x1>;
> >>>> + funnel1_in_port1: endpoint {
> >>>> + remote-endpoint = <&etm1_out_port>;
> >>>> + };
> >>>> + };
> >>>> + port@2 {
> >>>> + reg = <0x2>;
> >>>> + funnel1_in_port2: endpoint {
> >>>> + remote-endpoint = <&etm2_out_port>;
> >>>> + };
> >>>> + };
> >>>> + port@3 {
> >>>> + reg = <0x3>;
> >>>> + funnel1_in_port3: endpoint {
> >>>> + remote-endpoint = <&etm3_out_port>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + out-ports {
> >>>> + port {
> >>>> + funnel1_out_port0: endpoint {
> >>>> + remote-endpoint = <&etf1_in_port>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + funnel2@fe930000 {
> >>>> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> >>>> + reg = <0 0xfe930000 0 0x1000>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + in-ports {
> >>>> + #address-cells = <0x1>;
> >>>> + #size-cells = <0x0>;
> >>>> + port@2 {
> >>>> + reg = <0x2>;
> >>>> + funnel2_in_port2: endpoint {
> >>>> + remote-endpoint = <&etf1_out_port>;
> >>>> + };
> >>>> + };
> >>>> + // Funnel2 has another input port connected to
> >>>> + // funnel0's output. Funnel0 gathers Cortex-R5 ETMs.
> >>>
> >>> C++ style comments.
> >>>
> >
> > Ok, I'll go with:
> > /*
> > * Funnel2 has another input port connected to
> > * funnel0's output. Funnel0 gathers Cortex-R5 ETMs.
> > */
> >
> >>>> + };
> >>>> + out-ports {
> >>>> + port {
> >>>> + funnel2_out_port0: endpoint {
> >>>> + remote-endpoint = <&etf2_in_port>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + etf1@fe940000 {
> >>>> + compatible = "arm,coresight-tmc", "arm,primecell";
> >>>> + reg = <0 0xfe940000 0 0x1000>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + in-ports {
> >>>> + port {
> >>>> + etf1_in_port: endpoint {
> >>>> + remote-endpoint = <&funnel1_out_port0>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + out-ports {
> >>>> + port {
> >>>> + etf1_out_port: endpoint {
> >>>> + remote-endpoint = <&funnel2_in_port2>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + etf2@fe950000 {
> >>>> + compatible = "arm,coresight-tmc", "arm,primecell";
> >>>> + reg = <0 0xfe950000 0 0x1000>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + in-ports {
> >>>> + port {
> >>>> + etf2_in_port: endpoint {
> >>>> + remote-endpoint = <&funnel2_out_port0>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + out-ports {
> >>>> + port {
> >>>> + etf2_out_port: endpoint {
> >>>> + remote-endpoint =
> >>>> + <&replicator_in_port0>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + replicator {
> >>>> + compatible = "arm,coresight-static-replicator";
> >>>> + in-ports {
> >>>> + port {
> >>>> + replicator_in_port0: endpoint {
> >>>> + remote-endpoint = <&etf2_out_port>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + out-ports {
> >>>> + #address-cells = <0x1>;
> >>>> + #size-cells = <0x0>;
> >>>> + port@0 {
> >>>> + reg = <0x0>;
> >>>> + replicator_out_port0: endpoint {
> >>>> + remote-endpoint = <&etr_in_port>;
> >>>> + };
> >>>> + };
> >>>> + port@1 {
> >>>> + reg = <0x1>;
> >>>> + replicator_out_port1: endpoint {
> >>>> + remote-endpoint = <&tpiu_in_port>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + etr@fe970000 {
> >>>> + compatible = "arm,coresight-tmc", "arm,primecell";
> >>>> + reg = <0 0xfe970000 0 0x1000>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + in-ports {
> >>>> + port {
> >>>> + etr_in_port: endpoint {
> >>>> + remote-endpoint =
> >>>> + <&replicator_out_port0>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> +
> >>>> + tpiu@fe980000 {
> >>>> + compatible = "arm,coresight-tpiu", "arm,primecell";
> >>>> + reg = <0 0xfe980000 0 0x1000>;
> >>>> + clocks = <&clk100>;
> >>>> + clock-names = "apb_pclk";
> >>>> + in-ports {
> >>>> + port {
> >>>> + tpiu_in_port: endpoint {
> >>>> + remote-endpoint =
> >>>> + <&replicator_out_port1>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> +};
> >>>> +
> >>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> >>>> index 3c731e73903a..ca0a6b9f4445 100644
> >>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> >>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> >>>> @@ -12,6 +12,8 @@
> >>>> * the License, or (at your option) any later version.
> >>>> */
> >>> >
> >>>> +#include "zynqmp-coresight.dtsi"
> >>>> +
> >>>
> >>> Those bindings are correctly used. If Michal doesn't mind the nit-picks I have
> >>> highlighted above then
> >>>
> >>> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> >>>
> >>> Otherwise feel free to add my tag to your next revision, which I advise you to
> >>> send out once v5.6-rc1 comes out.
> >
> > Great, thanks. I'll keep an eye for v5.6-rc1.
> >
> >>
> >> I forgot... How does power management work on this board? Is the
> >> power domain where the CS blocks are powered up by the FW? And what
> >> about state retention when processors go idle? Should this be taken
> >> care of in the drivers or is the PMIC properly handling low retention
> >> states? Failure to properly address both cases will likely hang the
> >> board (at boot time of when processors are idled).
> >
> > To be honest, I don't know. I use kernel with CPU idle permanently disabled, as was
> > advised somewhere in CoreSight-related documents I found at the beginning of my
> > experiments. It might've been a presentation from Linaro Connect, either yours or Leo's.
> > I didn't do any extra steps to power CS blocks on, so I guess they're either powered on
> > by default, or it's taken care of by either FSBL, U-boot or ATF. I use those three provided
> > by Xilinx. I didn't experiment with vanilla U-boot or ATF.
> >
> > Can you please suggest some experiments I in this matter? Would turning off CPU idle
> > in kernel's config and tracing a migrating process be sufficient for such test?
This is a fairly new feature that Andrew finished in September [1].
It allows to save/restore the coresight tracers' configuration when
CPUs enter idle states, allowing coresight to be used when CPUIdle is
enabled. This is necessary when the HW line driven by the PU bit of
configuration register TRCPDCR is not connected to a PMIC or the
PMIC's firmware is ignoring the signal. It is very likely that either
one of those scenarios are enacted on this platform.
To deal with power management issues on the ETM blocks, re-enable
CPUIdle and add "arm,coresight-loses-context-with-cpu;" to each of the
ETM node specification in the DT (see bindings for details). That
should take care of the ETMs only, which are usually in the CPU power
domain. The rest of the coresight blocks are generally located in the
debug power domain, something I can't help with. It is either enabled
at boot time by the boot loader or the kernel, or handled dynamically
at run time. See the "power-domains" property in the Juno coresight
specification[2].
[1]. https://www.spinics.net/lists/devicetree/msg309139.html
[2]. https://elixir.bootlin.com/linux/latest/source/arch/arm64/boot/dts/arm/juno-base.dtsi#L169
>
> Jolly: Can you please take a look how this block is powered and how
> power stuff should be handled?
>
> Thanks,
> Michal
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2020-02-03 17:57 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-30 15:36 [PATCH 0/1] Xilinx Zynq Ultrascale+ MPSoc CoreSight DT nodes Wojciech Żmuda
2020-01-30 15:36 ` Wojciech Żmuda
2020-01-30 15:36 ` [PATCH 1/1] arm64: zynqmp: Add CoreSight components Wojciech Żmuda
2020-01-30 15:36 ` Wojciech Żmuda
2020-01-31 18:36 ` Mathieu Poirier
2020-01-31 18:36 ` Mathieu Poirier
2020-01-31 18:47 ` Mathieu Poirier
2020-01-31 18:47 ` Mathieu Poirier
2020-01-31 19:37 ` Wojciech Żmuda
2020-01-31 19:37 ` Wojciech Żmuda
2020-02-03 7:12 ` Michal Simek
2020-02-03 7:12 ` Michal Simek
2020-02-03 17:57 ` Mathieu Poirier
2020-02-03 17:57 ` Mathieu Poirier
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