* [PATCH 1/2] KVM: LAPIC: Prevent setting the tscdeadline timer if the lapic is hw disabled @ 2020-07-21 9:24 Wanpeng Li 2020-07-21 9:24 ` [PATCH 2/2] KVM: LAPIC: Set the TDCR settable bits Wanpeng Li 2020-07-21 10:35 ` [PATCH 1/2] KVM: LAPIC: Prevent setting the tscdeadline timer if the lapic is hw disabled Vitaly Kuznetsov 0 siblings, 2 replies; 7+ messages in thread From: Wanpeng Li @ 2020-07-21 9:24 UTC (permalink / raw) To: linux-kernel, kvm Cc: Paolo Bonzini, Sean Christopherson, Vitaly Kuznetsov, Wanpeng Li, Jim Mattson, Joerg Roedel From: Wanpeng Li <wanpengli@tencent.com> Prevent setting the tscdeadline timer if the lapic is hw disabled. Signed-off-by: Wanpeng Li <wanpengli@tencent.com> --- arch/x86/kvm/lapic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 5bf72fc..4ce2ddd 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -2195,7 +2195,7 @@ void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data) { struct kvm_lapic *apic = vcpu->arch.apic; - if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) || + if (!kvm_apic_present(vcpu) || apic_lvtt_oneshot(apic) || apic_lvtt_period(apic)) return; -- 2.7.4 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] KVM: LAPIC: Set the TDCR settable bits 2020-07-21 9:24 [PATCH 1/2] KVM: LAPIC: Prevent setting the tscdeadline timer if the lapic is hw disabled Wanpeng Li @ 2020-07-21 9:24 ` Wanpeng Li 2020-07-21 10:51 ` Vitaly Kuznetsov 2020-07-21 10:35 ` [PATCH 1/2] KVM: LAPIC: Prevent setting the tscdeadline timer if the lapic is hw disabled Vitaly Kuznetsov 1 sibling, 1 reply; 7+ messages in thread From: Wanpeng Li @ 2020-07-21 9:24 UTC (permalink / raw) To: linux-kernel, kvm Cc: Paolo Bonzini, Sean Christopherson, Vitaly Kuznetsov, Wanpeng Li, Jim Mattson, Joerg Roedel From: Wanpeng Li <wanpengli@tencent.com> Only bits 0, 1, and 3 are settable, others are reserved for APIC_TDCR. Let's record the settable value in the virtual apic page. Signed-off-by: Wanpeng Li <wanpengli@tencent.com> --- arch/x86/kvm/lapic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 4ce2ddd..8f7a14d 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -2068,7 +2068,7 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) case APIC_TDCR: { uint32_t old_divisor = apic->divide_count; - kvm_lapic_set_reg(apic, APIC_TDCR, val); + kvm_lapic_set_reg(apic, APIC_TDCR, val & 0xb); update_divide_count(apic); if (apic->divide_count != old_divisor && apic->lapic_timer.period) { -- 2.7.4 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] KVM: LAPIC: Set the TDCR settable bits 2020-07-21 9:24 ` [PATCH 2/2] KVM: LAPIC: Set the TDCR settable bits Wanpeng Li @ 2020-07-21 10:51 ` Vitaly Kuznetsov 2020-07-27 3:29 ` Wanpeng Li 0 siblings, 1 reply; 7+ messages in thread From: Vitaly Kuznetsov @ 2020-07-21 10:51 UTC (permalink / raw) To: Wanpeng Li, linux-kernel, kvm Cc: Paolo Bonzini, Sean Christopherson, Wanpeng Li, Jim Mattson, Joerg Roedel Wanpeng Li <kernellwp@gmail.com> writes: > From: Wanpeng Li <wanpengli@tencent.com> > > Only bits 0, 1, and 3 are settable, others are reserved for APIC_TDCR. > Let's record the settable value in the virtual apic page. > > Signed-off-by: Wanpeng Li <wanpengli@tencent.com> > --- > arch/x86/kvm/lapic.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c > index 4ce2ddd..8f7a14d 100644 > --- a/arch/x86/kvm/lapic.c > +++ b/arch/x86/kvm/lapic.c > @@ -2068,7 +2068,7 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) > case APIC_TDCR: { > uint32_t old_divisor = apic->divide_count; > > - kvm_lapic_set_reg(apic, APIC_TDCR, val); > + kvm_lapic_set_reg(apic, APIC_TDCR, val & 0xb); > update_divide_count(apic); > if (apic->divide_count != old_divisor && > apic->lapic_timer.period) { AFAIU bit 2 should be 0 and other upper bits are reserved. Checking on bare hardware, # wrmsr 0x83e 0xb # rdmsr 0x83e b # wrmsr 0x83e 0xc wrmsr: CPU 0 cannot set MSR 0x0000083e to 0x000000000000000c # rdmsr 0x83e b Shouldn't we fail the write in case (val & ~0xb) ? -- Vitaly ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] KVM: LAPIC: Set the TDCR settable bits 2020-07-21 10:51 ` Vitaly Kuznetsov @ 2020-07-27 3:29 ` Wanpeng Li 0 siblings, 0 replies; 7+ messages in thread From: Wanpeng Li @ 2020-07-27 3:29 UTC (permalink / raw) To: Vitaly Kuznetsov Cc: LKML, kvm, Paolo Bonzini, Sean Christopherson, Wanpeng Li, Jim Mattson, Joerg Roedel On Tue, 21 Jul 2020 at 18:51, Vitaly Kuznetsov <vkuznets@redhat.com> wrote: > > Wanpeng Li <kernellwp@gmail.com> writes: > > > From: Wanpeng Li <wanpengli@tencent.com> > > > > Only bits 0, 1, and 3 are settable, others are reserved for APIC_TDCR. > > Let's record the settable value in the virtual apic page. > > > > Signed-off-by: Wanpeng Li <wanpengli@tencent.com> > > --- > > arch/x86/kvm/lapic.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c > > index 4ce2ddd..8f7a14d 100644 > > --- a/arch/x86/kvm/lapic.c > > +++ b/arch/x86/kvm/lapic.c > > @@ -2068,7 +2068,7 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) > > case APIC_TDCR: { > > uint32_t old_divisor = apic->divide_count; > > > > - kvm_lapic_set_reg(apic, APIC_TDCR, val); > > + kvm_lapic_set_reg(apic, APIC_TDCR, val & 0xb); > > update_divide_count(apic); > > if (apic->divide_count != old_divisor && > > apic->lapic_timer.period) { > > AFAIU bit 2 should be 0 and other upper bits are reserved. Checking on > bare hardware, > > # wrmsr 0x83e 0xb > # rdmsr 0x83e > b > # wrmsr 0x83e 0xc > wrmsr: CPU 0 cannot set MSR 0x0000083e to 0x000000000000000c > # rdmsr 0x83e > b > > Shouldn't we fail the write in case (val & ~0xb) ? Sorry for the late response since I just come back from vacation. I can remove the "others are reserved" in patch description for the next version. It is a little different between Intel and AMD, Intel's bit 2 is 0 and AMD is reserved. On bare-metal, Intel will refuse to set APIC_TDCR once bits except 0, 1, 3 are setting, however, AMD will accept bits 0, 1, 3 and ignore other bits setting as patch does. Before the patch, we can get back anything what we set to the APIC_TDCR, this patch improves it. Wanpeng ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] KVM: LAPIC: Prevent setting the tscdeadline timer if the lapic is hw disabled 2020-07-21 9:24 [PATCH 1/2] KVM: LAPIC: Prevent setting the tscdeadline timer if the lapic is hw disabled Wanpeng Li 2020-07-21 9:24 ` [PATCH 2/2] KVM: LAPIC: Set the TDCR settable bits Wanpeng Li @ 2020-07-21 10:35 ` Vitaly Kuznetsov 2020-07-21 15:25 ` Sean Christopherson 1 sibling, 1 reply; 7+ messages in thread From: Vitaly Kuznetsov @ 2020-07-21 10:35 UTC (permalink / raw) To: Wanpeng Li, linux-kernel, kvm Cc: Paolo Bonzini, Sean Christopherson, Wanpeng Li, Jim Mattson, Joerg Roedel Wanpeng Li <kernellwp@gmail.com> writes: > From: Wanpeng Li <wanpengli@tencent.com> > > Prevent setting the tscdeadline timer if the lapic is hw disabled. > > Signed-off-by: Wanpeng Li <wanpengli@tencent.com> > --- > arch/x86/kvm/lapic.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c > index 5bf72fc..4ce2ddd 100644 > --- a/arch/x86/kvm/lapic.c > +++ b/arch/x86/kvm/lapic.c > @@ -2195,7 +2195,7 @@ void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data) > { > struct kvm_lapic *apic = vcpu->arch.apic; > > - if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) || > + if (!kvm_apic_present(vcpu) || apic_lvtt_oneshot(apic) || > apic_lvtt_period(apic)) > return; Out of pure curiosity, what is the architectural behavior if I disable LAPIC, write to IA32_TSC_DEADLINE and then re-enable LAPIC before the timer was supposed to fire? -- Vitaly ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] KVM: LAPIC: Prevent setting the tscdeadline timer if the lapic is hw disabled 2020-07-21 10:35 ` [PATCH 1/2] KVM: LAPIC: Prevent setting the tscdeadline timer if the lapic is hw disabled Vitaly Kuznetsov @ 2020-07-21 15:25 ` Sean Christopherson 2020-07-27 6:18 ` Wanpeng Li 0 siblings, 1 reply; 7+ messages in thread From: Sean Christopherson @ 2020-07-21 15:25 UTC (permalink / raw) To: Vitaly Kuznetsov Cc: Wanpeng Li, linux-kernel, kvm, Paolo Bonzini, Wanpeng Li, Jim Mattson, Joerg Roedel On Tue, Jul 21, 2020 at 12:35:01PM +0200, Vitaly Kuznetsov wrote: > Wanpeng Li <kernellwp@gmail.com> writes: > > > From: Wanpeng Li <wanpengli@tencent.com> > > > > Prevent setting the tscdeadline timer if the lapic is hw disabled. > > > > Signed-off-by: Wanpeng Li <wanpengli@tencent.com> A Fixes and/or Cc stable is probably needed for this. > > --- > > arch/x86/kvm/lapic.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c > > index 5bf72fc..4ce2ddd 100644 > > --- a/arch/x86/kvm/lapic.c > > +++ b/arch/x86/kvm/lapic.c > > @@ -2195,7 +2195,7 @@ void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data) > > { > > struct kvm_lapic *apic = vcpu->arch.apic; > > > > - if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) || > > + if (!kvm_apic_present(vcpu) || apic_lvtt_oneshot(apic) || > > apic_lvtt_period(apic)) > > return; > > Out of pure curiosity, what is the architectural behavior if I disable > LAPIC, write to IA32_TSC_DEADLINE and then re-enable LAPIC before the > timer was supposed to fire? Intel's SDM reserves the right for the CPU to do whatever it wants :-) When IA32_APIC_BASE[11] is set to 0, prior initialization to the APIC may be lost and the APIC may return to the state described in Section 10.4.7.1, “Local APIC State After Power-Up or Reset.” Practically speaking, resetting APIC state seems like the sane approach, i.e. KVM should probably call kvm_lapic_reset() when the APIC transitions from HW enabled -> disabled. Maybe in a follow-up patch to this one? ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] KVM: LAPIC: Prevent setting the tscdeadline timer if the lapic is hw disabled 2020-07-21 15:25 ` Sean Christopherson @ 2020-07-27 6:18 ` Wanpeng Li 0 siblings, 0 replies; 7+ messages in thread From: Wanpeng Li @ 2020-07-27 6:18 UTC (permalink / raw) To: Sean Christopherson Cc: Vitaly Kuznetsov, LKML, kvm, Paolo Bonzini, Wanpeng Li, Jim Mattson, Joerg Roedel On Tue, 21 Jul 2020 at 23:25, Sean Christopherson <sean.j.christopherson@intel.com> wrote: > > On Tue, Jul 21, 2020 at 12:35:01PM +0200, Vitaly Kuznetsov wrote: > > Wanpeng Li <kernellwp@gmail.com> writes: > > > > > From: Wanpeng Li <wanpengli@tencent.com> > > > > > > Prevent setting the tscdeadline timer if the lapic is hw disabled. > > > > > > Signed-off-by: Wanpeng Li <wanpengli@tencent.com> > > A Fixes and/or Cc stable is probably needed for this. > > > > --- > > > arch/x86/kvm/lapic.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c > > > index 5bf72fc..4ce2ddd 100644 > > > --- a/arch/x86/kvm/lapic.c > > > +++ b/arch/x86/kvm/lapic.c > > > @@ -2195,7 +2195,7 @@ void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data) > > > { > > > struct kvm_lapic *apic = vcpu->arch.apic; > > > > > > - if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) || > > > + if (!kvm_apic_present(vcpu) || apic_lvtt_oneshot(apic) || > > > apic_lvtt_period(apic)) > > > return; > > > > Out of pure curiosity, what is the architectural behavior if I disable > > LAPIC, write to IA32_TSC_DEADLINE and then re-enable LAPIC before the > > timer was supposed to fire? > > Intel's SDM reserves the right for the CPU to do whatever it wants :-) > > When IA32_APIC_BASE[11] is set to 0, prior initialization to the APIC > may be lost and the APIC may return to the state described in Section > 10.4.7.1, “Local APIC State After Power-Up or Reset.” > > Practically speaking, resetting APIC state seems like the sane approach, > i.e. KVM should probably call kvm_lapic_reset() when the APIC transitions > from HW enabled -> disabled. Maybe in a follow-up patch to this one? kvm_lapic_reset() will call the set base logic, a little recursive in the codes, it can be done after this recursion is solved. Wanpeng ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-07-27 6:19 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-07-21 9:24 [PATCH 1/2] KVM: LAPIC: Prevent setting the tscdeadline timer if the lapic is hw disabled Wanpeng Li 2020-07-21 9:24 ` [PATCH 2/2] KVM: LAPIC: Set the TDCR settable bits Wanpeng Li 2020-07-21 10:51 ` Vitaly Kuznetsov 2020-07-27 3:29 ` Wanpeng Li 2020-07-21 10:35 ` [PATCH 1/2] KVM: LAPIC: Prevent setting the tscdeadline timer if the lapic is hw disabled Vitaly Kuznetsov 2020-07-21 15:25 ` Sean Christopherson 2020-07-27 6:18 ` Wanpeng Li
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