From: Alan Tull <atull@kernel.org> To: "Wu, Hao" <hao.wu@intel.com> Cc: Moritz Fischer <mdf@kernel.org>, "linux-fpga@vger.kernel.org" <linux-fpga@vger.kernel.org>, linux-kernel <linux-kernel@vger.kernel.org>, "linux-api@vger.kernel.org" <linux-api@vger.kernel.org>, "Kang, Luwei" <luwei.kang@intel.com>, "Zhang, Yi Z" <yi.z.zhang@intel.com>, "Whisonant, Tim" <tim.whisonant@intel.com>, "Luebbers, Enno" <enno.luebbers@intel.com>, "Rao, Shiva" <shiva.rao@intel.com>, "Rauer, Christopher" <christopher.rauer@intel.com>, Xiao Guangrong <guangrong.xiao@linux.intel.com> Subject: Re: [PATCH v2 12/22] fpga: intel: fme: add header sub feature support Date: Tue, 18 Jul 2017 09:33:59 -0500 [thread overview] Message-ID: <CANk1AXTL-G589ysWrW2zvHMUSm8ADh=KwVHBpGR10Dt_Z1Ox3Q@mail.gmail.com> (raw) In-Reply-To: <BE8371DA886269458E0220A16DC1F8277E058300@SHSMSX104.ccr.corp.intel.com> On Mon, Jul 17, 2017 at 8:17 PM, Wu, Hao <hao.wu@intel.com> wrote: >> On Sun, Jun 25, 2017 at 8:52 PM, Wu Hao <hao.wu@intel.com> wrote: >> >> Hi Hao, >> >> I'm making my way through this (very large) patchset. Some minor >> comments below. >> > > Hi Alan > > Thanks for your review. : ) Hi Hao, Thanks, this looks good and will be helpful for folks who are new to this. Alan > >> > From: Kang Luwei <luwei.kang@intel.com> >> > >> > The header register set is always present for FPGA Management Engine (FME), >> > this patch implements init and uinit function for header sub feature and >> > introduce several read-only sysfs interfaces for the capability and status. >> > >> > Sysfs interfaces: >> > * /sys/class/fpga/<fpga.x>/<intel-fpga-fme.x>/ports_num >> > Read-only. Number of ports implemented >> > >> > * /sys/class/fpga/<fpga.x>/<intel-fpga-fme.x>/bitstream_id >> > Read-only. Blue Bitstream identifier number >> >> Blue and Green bitstreams are an Intel implementation terminology. I >> see that you've defined them in drivers/fpga, but it will be helpful >> to add in "static region" and "partial reconfiguration region" added >> in any API documentation files that use the green/blue terminology to >> keep it accessible. >> > > Sure, thanks for your suggestion, will update it like this. > > * /sys/class/fpga/<fpga.x>/<intel-fpga-fme.x>/bitstream_id > Read-only. Blue Bitstream (static FPGA region) identifier number > > * /sys/class/fpga/<fpga.x>/<intel-fpga-fme.x>/bitstream_metadata > Read-only. Blue Bitstream (static FPGA region) meta data > >> > >> > Signed-off-by: Tim Whisonant <tim.whisonant@intel.com> >> > Signed-off-by: Enno Luebbers <enno.luebbers@intel.com> >> > Signed-off-by: Shiva Rao <shiva.rao@intel.com> >> > Signed-off-by: Christopher Rauer <christopher.rauer@intel.com> >> > Signed-off-by: Kang Luwei <luwei.kang@intel.com> >> > Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> >> > Signed-off-by: Wu Hao <hao.wu@intel.com> >> > --- >> > v2: add sysfs documentation >> > --- >> > .../ABI/testing/sysfs-platform-intel-fpga-fme | 19 ++++++++ >> > drivers/fpga/intel-feature-dev.h | 3 ++ >> > drivers/fpga/intel-fme-main.c | 55 ++++++++++++++++++++++ >> > 3 files changed, 77 insertions(+) >> > create mode 100644 Documentation/ABI/testing/sysfs-platform-intel-fpga- >> fme >> > >> > diff --git a/Documentation/ABI/testing/sysfs-platform-intel-fpga-fme >> b/Documentation/ABI/testing/sysfs-platform-intel-fpga-fme >> > new file mode 100644 >> > index 0000000..783cfa9 >> > --- /dev/null >> > +++ b/Documentation/ABI/testing/sysfs-platform-intel-fpga-fme >> > @@ -0,0 +1,19 @@ >> > +What: /sys/bus/platform/devices/intel-fpga-fme.0/ports_num >> > +Date: June 2017 >> > +KernelVersion: 4.12 >> > +Contact: Wu Hao <hao.wu@intel.com> >> > +Description: Read-only. One Intel FPGA device may have more than 1 >> > + port/Accelerator Function Unit (AFU). It returns the >> > + number of ports on the FPGA device when read it. >> > + >> > +What: /sys/bus/platform/devices/intel-fpga-fme.0/bitstream_id >> > +Date: June 2017 >> > +KernelVersion: 4.12 >> > +Contact: Wu Hao <hao.wu@intel.com> >> > +Description: Read-only. It returns Blue Bitstream identifier number. >> >> Here > > Will update this patch as below. > > +Description: Read-only. It returns Blue Bitstream (static FPGA region) > + identifier number. > >> >> > + >> > +What: /sys/bus/platform/devices/intel-fpga-fme.0/bitstream_meta >> > +Date: June 2017 >> > +KernelVersion: 4.12 >> > +Contact: Wu Hao <hao.wu@intel.com> >> > +Description: Read-only. It returns Blue Bitstream meta data. >> >> And here > > Will update this patch as below. > > +Description: Read-only. It returns Blue Bitstream (static FPGA region) > + meta data. > > Thanks > Hao
WARNING: multiple messages have this Message-ID (diff)
From: Alan Tull <atull-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> To: "Wu, Hao" <hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> Cc: Moritz Fischer <mdf-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>, "linux-fpga-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" <linux-fpga-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>, linux-kernel <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>, "linux-api-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" <linux-api-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>, "Kang, Luwei" <luwei.kang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>, "Zhang, Yi Z" <yi.z.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>, "Whisonant, Tim" <tim.whisonant-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>, "Luebbers, Enno" <enno.luebbers-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>, "Rao, Shiva" <shiva.rao-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>, "Rauer, Christopher" <christopher.rauer-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>, Xiao Guangrong <guangrong.xiao-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> Subject: Re: [PATCH v2 12/22] fpga: intel: fme: add header sub feature support Date: Tue, 18 Jul 2017 09:33:59 -0500 [thread overview] Message-ID: <CANk1AXTL-G589ysWrW2zvHMUSm8ADh=KwVHBpGR10Dt_Z1Ox3Q@mail.gmail.com> (raw) In-Reply-To: <BE8371DA886269458E0220A16DC1F8277E058300-0J0gbvR4kTg/UvCtAeCM4rfspsVTdybXVpNB7YpNyf8@public.gmane.org> On Mon, Jul 17, 2017 at 8:17 PM, Wu, Hao <hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> wrote: >> On Sun, Jun 25, 2017 at 8:52 PM, Wu Hao <hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> wrote: >> >> Hi Hao, >> >> I'm making my way through this (very large) patchset. Some minor >> comments below. >> > > Hi Alan > > Thanks for your review. : ) Hi Hao, Thanks, this looks good and will be helpful for folks who are new to this. Alan > >> > From: Kang Luwei <luwei.kang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> >> > >> > The header register set is always present for FPGA Management Engine (FME), >> > this patch implements init and uinit function for header sub feature and >> > introduce several read-only sysfs interfaces for the capability and status. >> > >> > Sysfs interfaces: >> > * /sys/class/fpga/<fpga.x>/<intel-fpga-fme.x>/ports_num >> > Read-only. Number of ports implemented >> > >> > * /sys/class/fpga/<fpga.x>/<intel-fpga-fme.x>/bitstream_id >> > Read-only. Blue Bitstream identifier number >> >> Blue and Green bitstreams are an Intel implementation terminology. I >> see that you've defined them in drivers/fpga, but it will be helpful >> to add in "static region" and "partial reconfiguration region" added >> in any API documentation files that use the green/blue terminology to >> keep it accessible. >> > > Sure, thanks for your suggestion, will update it like this. > > * /sys/class/fpga/<fpga.x>/<intel-fpga-fme.x>/bitstream_id > Read-only. Blue Bitstream (static FPGA region) identifier number > > * /sys/class/fpga/<fpga.x>/<intel-fpga-fme.x>/bitstream_metadata > Read-only. Blue Bitstream (static FPGA region) meta data > >> > >> > Signed-off-by: Tim Whisonant <tim.whisonant-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> >> > Signed-off-by: Enno Luebbers <enno.luebbers-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> >> > Signed-off-by: Shiva Rao <shiva.rao-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> >> > Signed-off-by: Christopher Rauer <christopher.rauer-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> >> > Signed-off-by: Kang Luwei <luwei.kang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> >> > Signed-off-by: Xiao Guangrong <guangrong.xiao-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> >> > Signed-off-by: Wu Hao <hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> >> > --- >> > v2: add sysfs documentation >> > --- >> > .../ABI/testing/sysfs-platform-intel-fpga-fme | 19 ++++++++ >> > drivers/fpga/intel-feature-dev.h | 3 ++ >> > drivers/fpga/intel-fme-main.c | 55 ++++++++++++++++++++++ >> > 3 files changed, 77 insertions(+) >> > create mode 100644 Documentation/ABI/testing/sysfs-platform-intel-fpga- >> fme >> > >> > diff --git a/Documentation/ABI/testing/sysfs-platform-intel-fpga-fme >> b/Documentation/ABI/testing/sysfs-platform-intel-fpga-fme >> > new file mode 100644 >> > index 0000000..783cfa9 >> > --- /dev/null >> > +++ b/Documentation/ABI/testing/sysfs-platform-intel-fpga-fme >> > @@ -0,0 +1,19 @@ >> > +What: /sys/bus/platform/devices/intel-fpga-fme.0/ports_num >> > +Date: June 2017 >> > +KernelVersion: 4.12 >> > +Contact: Wu Hao <hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> >> > +Description: Read-only. One Intel FPGA device may have more than 1 >> > + port/Accelerator Function Unit (AFU). It returns the >> > + number of ports on the FPGA device when read it. >> > + >> > +What: /sys/bus/platform/devices/intel-fpga-fme.0/bitstream_id >> > +Date: June 2017 >> > +KernelVersion: 4.12 >> > +Contact: Wu Hao <hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> >> > +Description: Read-only. It returns Blue Bitstream identifier number. >> >> Here > > Will update this patch as below. > > +Description: Read-only. It returns Blue Bitstream (static FPGA region) > + identifier number. > >> >> > + >> > +What: /sys/bus/platform/devices/intel-fpga-fme.0/bitstream_meta >> > +Date: June 2017 >> > +KernelVersion: 4.12 >> > +Contact: Wu Hao <hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> >> > +Description: Read-only. It returns Blue Bitstream meta data. >> >> And here > > Will update this patch as below. > > +Description: Read-only. It returns Blue Bitstream (static FPGA region) > + meta data. > > Thanks > Hao
next prev parent reply other threads:[~2017-07-18 14:34 UTC|newest] Thread overview: 150+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-06-26 1:51 [PATCH v2 00/22] Intel FPGA Device Drivers Wu Hao 2017-06-26 1:51 ` Wu Hao 2017-06-26 1:51 ` [PATCH v2 01/22] docs: fpga: add a document for Intel FPGA driver overview Wu Hao 2017-06-26 1:51 ` Wu Hao 2017-07-12 14:51 ` Alan Tull 2017-07-13 4:25 ` Wu Hao 2017-07-13 4:25 ` Wu Hao 2017-07-14 23:59 ` Luebbers, Enno 2017-07-17 20:14 ` Alan Tull 2017-07-18 5:22 ` Greg KH 2017-07-18 5:22 ` Greg KH 2017-07-18 14:32 ` Alan Tull 2017-07-18 14:32 ` Alan Tull 2017-06-26 1:51 ` [PATCH v2 02/22] fpga: add FPGA device framework Wu Hao 2017-06-26 1:51 ` Wu Hao 2017-07-27 16:35 ` Alan Tull 2017-07-27 19:10 ` Rob Herring 2017-07-27 19:10 ` Rob Herring 2017-07-31 21:40 ` Alan Tull 2017-07-31 21:40 ` Alan Tull 2017-08-01 8:43 ` Wu Hao 2017-08-01 8:43 ` Wu Hao 2017-08-01 21:04 ` Alan Tull 2017-08-02 14:07 ` Wu Hao 2017-08-02 21:01 ` Alan Tull 2017-08-02 21:01 ` Alan Tull 2017-08-07 15:13 ` Alan Tull 2017-08-07 15:13 ` Alan Tull 2017-07-27 16:44 ` Alan Tull 2017-07-28 7:55 ` Wu Hao 2017-07-28 7:55 ` Wu Hao 2017-06-26 1:51 ` [PATCH v2 03/22] fpga: bridge: remove OF dependency for fpga-bridge Wu Hao 2017-06-26 1:51 ` Wu Hao 2017-08-02 21:21 ` Alan Tull 2017-09-25 16:34 ` Moritz Fischer 2017-09-21 19:11 ` Moritz Fischer 2017-09-21 19:11 ` Moritz Fischer 2017-09-21 19:50 ` Alan Tull 2017-09-22 2:15 ` Wu Hao 2017-09-22 2:15 ` Wu Hao 2017-09-23 1:53 ` Alan Tull 2017-09-23 1:53 ` Alan Tull 2017-06-26 1:52 ` [PATCH v2 04/22] fpga: mgr: add region_id to fpga_image_info Wu Hao 2017-06-26 1:52 ` Wu Hao 2017-07-26 18:33 ` Alan Tull 2017-07-26 18:33 ` Alan Tull 2017-07-27 5:14 ` Wu Hao 2017-07-27 5:14 ` Wu Hao 2017-06-26 1:52 ` [PATCH v2 05/22] fpga: mgr: add status for fpga-mgr Wu Hao 2017-07-12 15:22 ` Alan Tull 2017-07-12 15:22 ` Alan Tull 2017-07-13 3:11 ` Wu Hao 2017-07-13 3:11 ` Wu Hao 2017-06-26 1:52 ` [PATCH v2 06/22] fpga: intel: add FPGA PCIe device driver Wu Hao 2017-08-07 20:43 ` Alan Tull 2017-08-14 12:33 ` Wu, Hao 2017-08-14 12:33 ` Wu, Hao 2017-08-14 12:33 ` Wu, Hao 2017-06-26 1:52 ` [PATCH v2 07/22] fpga: intel: pcie: parse feature list and create platform device for features Wu Hao 2017-06-26 18:42 ` Moritz Fischer 2017-06-27 3:17 ` Wu Hao 2017-06-27 15:34 ` Alan Tull 2017-06-27 15:34 ` Alan Tull 2017-07-13 17:52 ` Alan Tull 2017-07-13 17:52 ` Alan Tull 2017-07-14 9:22 ` Wu Hao 2017-07-14 9:22 ` Wu Hao 2017-07-17 19:15 ` Alan Tull 2017-07-18 2:29 ` Wu, Hao 2017-09-20 21:24 ` Alan Tull 2017-09-21 19:58 ` Alan Tull 2017-09-22 7:33 ` Wu Hao 2017-09-22 7:33 ` Wu Hao 2017-09-22 7:28 ` Wu Hao 2017-09-27 20:27 ` Alan Tull 2017-09-27 20:27 ` Alan Tull 2017-09-28 9:32 ` Wu Hao 2017-09-28 9:32 ` Wu Hao 2017-06-26 1:52 ` [PATCH v2 08/22] fpga: intel: pcie: add chardev support for feature devices Wu Hao 2017-06-26 1:52 ` [PATCH v2 09/22] fpga: intel: pcie: adds fpga_for_each_port callback for fme device Wu Hao 2017-06-26 1:52 ` Wu Hao 2017-08-17 21:31 ` Alan Tull 2017-08-18 7:03 ` Wu Hao 2017-08-18 7:03 ` Wu Hao 2017-06-26 1:52 ` [PATCH v2 10/22] fpga: intel: add feature device infrastructure Wu Hao 2017-06-26 1:52 ` Wu Hao 2017-06-26 1:52 ` [PATCH v2 11/22] fpga: intel: add FPGA Management Engine driver basic framework Wu Hao 2017-06-26 1:52 ` [PATCH v2 12/22] fpga: intel: fme: add header sub feature support Wu Hao 2017-06-26 1:52 ` Wu Hao 2017-07-17 18:53 ` Alan Tull 2017-07-18 1:17 ` Wu, Hao 2017-07-18 1:17 ` Wu, Hao 2017-07-18 14:33 ` Alan Tull [this message] 2017-07-18 14:33 ` Alan Tull 2017-06-26 1:52 ` [PATCH v2 13/22] fpga: intel: fme: add FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support Wu Hao 2017-08-17 19:11 ` Alan Tull 2017-06-26 1:52 ` [PATCH v2 14/22] fpga: intel: fme: add partial reconfiguration sub feature support Wu Hao 2017-06-26 1:52 ` Wu Hao 2017-06-26 1:52 ` [PATCH v2 15/22] fpga: intel: add fpga manager platform driver for FME Wu Hao 2017-09-25 21:24 ` Moritz Fischer 2017-09-27 1:18 ` Wu Hao 2017-09-27 1:18 ` Wu Hao 2017-09-27 18:54 ` Alan Tull 2017-09-28 8:25 ` Wu Hao 2017-09-28 8:25 ` Wu Hao 2017-06-26 1:52 ` [PATCH v2 16/22] fpga: intel: add fpga bridge " Wu Hao 2017-06-26 1:52 ` Wu Hao 2017-08-17 19:34 ` Alan Tull 2017-08-17 19:34 ` Alan Tull 2017-08-17 19:55 ` Moritz Fischer 2017-08-18 3:06 ` Wu Hao 2017-06-26 1:52 ` [PATCH v2 17/22] fpga: intel: add fpga region " Wu Hao 2017-07-12 16:09 ` Alan Tull 2017-07-12 16:09 ` Alan Tull 2017-07-13 2:31 ` Wu Hao 2017-07-13 2:31 ` Wu Hao 2017-06-26 1:52 ` [PATCH v2 18/22] fpga: intel: add FPGA Accelerated Function Unit driver basic framework Wu Hao 2017-06-26 1:52 ` Wu Hao 2017-08-17 19:00 ` Alan Tull 2017-08-17 19:00 ` Alan Tull 2017-08-18 6:40 ` Wu Hao 2017-08-18 6:40 ` Wu Hao 2017-08-17 19:09 ` Moritz Fischer 2017-08-18 6:42 ` Wu Hao 2017-08-18 6:42 ` Wu Hao 2017-06-26 1:52 ` [PATCH v2 19/22] fpga: intel: afu: add header sub feature support Wu Hao 2017-06-26 1:52 ` Wu Hao 2017-08-14 21:37 ` Alan Tull 2017-08-16 5:11 ` Wu, Hao 2017-08-16 5:11 ` Wu, Hao 2017-08-16 5:11 ` Wu, Hao 2017-08-17 21:41 ` Alan Tull 2017-06-26 1:52 ` [PATCH v2 20/22] fpga: intel: afu add FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support Wu Hao 2017-06-26 1:52 ` Wu Hao 2017-08-17 19:07 ` Alan Tull 2017-08-17 19:12 ` Moritz Fischer 2017-08-18 3:20 ` Wu Hao 2017-08-18 3:20 ` Wu Hao 2017-06-26 1:52 ` [PATCH v2 21/22] fpga: intel: afu: add user afu sub feature support Wu Hao 2017-06-26 1:52 ` Wu Hao 2017-06-26 1:52 ` [PATCH v2 22/22] fpga: intel: afu: add FPGA_PORT_DMA_MAP/UNMAP ioctls support Wu Hao 2017-06-26 1:52 ` Wu Hao 2017-07-31 21:41 ` Alan Tull 2017-08-01 7:21 ` Wu Hao 2017-08-01 7:21 ` Wu Hao 2017-08-01 18:15 ` Moritz Fischer 2017-08-02 7:30 ` Wu Hao 2017-08-02 7:30 ` Wu Hao 2017-07-28 13:28 ` [PATCH v2 00/22] Intel FPGA Device Drivers Alan Tull 2017-07-28 13:28 ` Alan Tull
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