* [Qemu-devel] [PATCH for 4.1] target/riscv: More accurate handling of `sip` CSR
@ 2019-05-06 15:52 ` Jonathan Behrens
0 siblings, 0 replies; 6+ messages in thread
From: Jonathan Behrens @ 2019-05-06 15:52 UTC (permalink / raw)
To: qemu-devel@nongnu.org Developers
Cc: Alistair Francis, Palmer Dabbelt, open list:RISC-V,
Sagar Karandikar, Bastian Koppelmann
According to the spec, "All bits besides SSIP, USIP, and UEIP in the sip
register are read-only." Further, if an interrupt is not delegated to mode
x,
then "the corresponding bits in xip [...] should appear to be hardwired to
zero. This patch implements both of those requirements.
Signed-off-by: Jonathan Behrens <fintelia@gmail.com>
---
target/riscv/csr.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 1ec1222da1..fff7d834e8 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -246,6 +246,7 @@ static const target_ulong sstatus_v1_9_mask =
SSTATUS_SIE | SSTATUS_SPIE |
static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
+static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP |
MIP_UEIP;
#if defined(TARGET_RISCV32)
static const char valid_vm_1_09[16] = {
@@ -694,8 +695,10 @@ static int write_sbadaddr(CPURISCVState *env, int
csrno, target_ulong val)
static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask)
{
- return rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
- write_mask & env->mideleg);
+ int ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
+ write_mask & env->mideleg & sip_writable_mask);
+ *ret_value &= env->mideleg;
+ return ret;
}
/* Supervisor Protection and Translation */
--
2.20.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Qemu-riscv] [PATCH for 4.1] target/riscv: More accurate handling of `sip` CSR
@ 2019-05-06 15:52 ` Jonathan Behrens
0 siblings, 0 replies; 6+ messages in thread
From: Jonathan Behrens @ 2019-05-06 15:52 UTC (permalink / raw)
To: qemu-devel@nongnu.org Developers
Cc: open list:RISC-V, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann
[-- Attachment #1: Type: text/plain, Size: 1598 bytes --]
According to the spec, "All bits besides SSIP, USIP, and UEIP in the sip
register are read-only." Further, if an interrupt is not delegated to mode
x,
then "the corresponding bits in xip [...] should appear to be hardwired to
zero. This patch implements both of those requirements.
Signed-off-by: Jonathan Behrens <fintelia@gmail.com>
---
target/riscv/csr.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 1ec1222da1..fff7d834e8 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -246,6 +246,7 @@ static const target_ulong sstatus_v1_9_mask =
SSTATUS_SIE | SSTATUS_SPIE |
static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
+static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP |
MIP_UEIP;
#if defined(TARGET_RISCV32)
static const char valid_vm_1_09[16] = {
@@ -694,8 +695,10 @@ static int write_sbadaddr(CPURISCVState *env, int
csrno, target_ulong val)
static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask)
{
- return rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
- write_mask & env->mideleg);
+ int ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
+ write_mask & env->mideleg & sip_writable_mask);
+ *ret_value &= env->mideleg;
+ return ret;
}
/* Supervisor Protection and Translation */
--
2.20.1
[-- Attachment #2: Type: text/html, Size: 1946 bytes --]
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH for 4.1] target/riscv: More accurate handling of `sip` CSR
2019-05-06 15:52 ` [Qemu-riscv] " Jonathan Behrens
@ 2019-05-07 17:52 ` Palmer Dabbelt
-1 siblings, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2019-05-07 17:52 UTC (permalink / raw)
To: fintelia
Cc: Alistair Francis, qemu-riscv, qemu-devel, sagark, Bastian Koppelmann
On Mon, 06 May 2019 08:52:43 PDT (-0700), fintelia@gmail.com wrote:
> According to the spec, "All bits besides SSIP, USIP, and UEIP in the sip
> register are read-only." Further, if an interrupt is not delegated to mode
> x,
> then "the corresponding bits in xip [...] should appear to be hardwired to
> zero. This patch implements both of those requirements.
>
> Signed-off-by: Jonathan Behrens <fintelia@gmail.com>
> ---
> target/riscv/csr.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 1ec1222da1..fff7d834e8 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -246,6 +246,7 @@ static const target_ulong sstatus_v1_9_mask =
> SSTATUS_SIE | SSTATUS_SPIE |
> static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
> SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
> SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
> +static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP |
> MIP_UEIP;
>
> #if defined(TARGET_RISCV32)
> static const char valid_vm_1_09[16] = {
> @@ -694,8 +695,10 @@ static int write_sbadaddr(CPURISCVState *env, int
> csrno, target_ulong val)
> static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
> target_ulong new_value, target_ulong write_mask)
> {
> - return rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
> - write_mask & env->mideleg);
> + int ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
> + write_mask & env->mideleg & sip_writable_mask);
> + *ret_value &= env->mideleg;
> + return ret;
> }
>
> /* Supervisor Protection and Translation */
This patch (and your previous one) don't apply for me. I don't see the
git-send-email tags in your messages, are you trying to do something like paste
them into gmail? If so I think they're getting line wrapped.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-riscv] [PATCH for 4.1] target/riscv: More accurate handling of `sip` CSR
@ 2019-05-07 17:52 ` Palmer Dabbelt
0 siblings, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2019-05-07 17:52 UTC (permalink / raw)
To: fintelia
Cc: qemu-devel, qemu-riscv, Alistair Francis, sagark, Bastian Koppelmann
On Mon, 06 May 2019 08:52:43 PDT (-0700), fintelia@gmail.com wrote:
> According to the spec, "All bits besides SSIP, USIP, and UEIP in the sip
> register are read-only." Further, if an interrupt is not delegated to mode
> x,
> then "the corresponding bits in xip [...] should appear to be hardwired to
> zero. This patch implements both of those requirements.
>
> Signed-off-by: Jonathan Behrens <fintelia@gmail.com>
> ---
> target/riscv/csr.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 1ec1222da1..fff7d834e8 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -246,6 +246,7 @@ static const target_ulong sstatus_v1_9_mask =
> SSTATUS_SIE | SSTATUS_SPIE |
> static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
> SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
> SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
> +static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP |
> MIP_UEIP;
>
> #if defined(TARGET_RISCV32)
> static const char valid_vm_1_09[16] = {
> @@ -694,8 +695,10 @@ static int write_sbadaddr(CPURISCVState *env, int
> csrno, target_ulong val)
> static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
> target_ulong new_value, target_ulong write_mask)
> {
> - return rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
> - write_mask & env->mideleg);
> + int ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
> + write_mask & env->mideleg & sip_writable_mask);
> + *ret_value &= env->mideleg;
> + return ret;
> }
>
> /* Supervisor Protection and Translation */
This patch (and your previous one) don't apply for me. I don't see the
git-send-email tags in your messages, are you trying to do something like paste
them into gmail? If so I think they're getting line wrapped.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH for 4.1] target/riscv: More accurate handling of `sip` CSR
2019-05-07 17:52 ` [Qemu-riscv] " Palmer Dabbelt
@ 2019-05-07 22:39 ` Jonathan Behrens
-1 siblings, 0 replies; 6+ messages in thread
From: Jonathan Behrens @ 2019-05-07 22:39 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Alistair Francis, open list:RISC-V,
qemu-devel@nongnu.org Developers, Sagar Karandikar,
Bastian Koppelmann
Yes, I was pasting the output of `git format-patch`. Gmail displays
properly for me, but seems to have hard-wrapped the plaintext version of my
outgoing message to 78 characters. I've tried re-sending from a different
address where I can use `git send-email` directly, please let me know if it
works and I'll resend the other patch the same way. Sorry about this!
Jonathan
On Tue, May 7, 2019 at 1:52 PM Palmer Dabbelt <palmer@sifive.com> wrote:
> On Mon, 06 May 2019 08:52:43 PDT (-0700), fintelia@gmail.com wrote:
> > According to the spec, "All bits besides SSIP, USIP, and UEIP in the sip
> > register are read-only." Further, if an interrupt is not delegated to
> mode
> > x,
> > then "the corresponding bits in xip [...] should appear to be hardwired
> to
> > zero. This patch implements both of those requirements.
> >
> > Signed-off-by: Jonathan Behrens <fintelia@gmail.com>
> > ---
> > target/riscv/csr.c | 7 +++++--
> > 1 file changed, 5 insertions(+), 2 deletions(-)
> >
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index 1ec1222da1..fff7d834e8 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -246,6 +246,7 @@ static const target_ulong sstatus_v1_9_mask =
> > SSTATUS_SIE | SSTATUS_SPIE |
> > static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE |
> SSTATUS_SPIE |
> > SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
> > SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
> > +static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP |
> > MIP_UEIP;
> >
> > #if defined(TARGET_RISCV32)
> > static const char valid_vm_1_09[16] = {
> > @@ -694,8 +695,10 @@ static int write_sbadaddr(CPURISCVState *env, int
> > csrno, target_ulong val)
> > static int rmw_sip(CPURISCVState *env, int csrno, target_ulong
> *ret_value,
> > target_ulong new_value, target_ulong write_mask)
> > {
> > - return rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
> > - write_mask & env->mideleg);
> > + int ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
> > + write_mask & env->mideleg & sip_writable_mask);
> > + *ret_value &= env->mideleg;
> > + return ret;
> > }
> >
> > /* Supervisor Protection and Translation */
>
> This patch (and your previous one) don't apply for me. I don't see the
> git-send-email tags in your messages, are you trying to do something like
> paste
> them into gmail? If so I think they're getting line wrapped.
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-riscv] [PATCH for 4.1] target/riscv: More accurate handling of `sip` CSR
@ 2019-05-07 22:39 ` Jonathan Behrens
0 siblings, 0 replies; 6+ messages in thread
From: Jonathan Behrens @ 2019-05-07 22:39 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Alistair Francis, Sagar Karandikar, Bastian Koppelmann
[-- Attachment #1: Type: text/plain, Size: 2493 bytes --]
Yes, I was pasting the output of `git format-patch`. Gmail displays
properly for me, but seems to have hard-wrapped the plaintext version of my
outgoing message to 78 characters. I've tried re-sending from a different
address where I can use `git send-email` directly, please let me know if it
works and I'll resend the other patch the same way. Sorry about this!
Jonathan
On Tue, May 7, 2019 at 1:52 PM Palmer Dabbelt <palmer@sifive.com> wrote:
> On Mon, 06 May 2019 08:52:43 PDT (-0700), fintelia@gmail.com wrote:
> > According to the spec, "All bits besides SSIP, USIP, and UEIP in the sip
> > register are read-only." Further, if an interrupt is not delegated to
> mode
> > x,
> > then "the corresponding bits in xip [...] should appear to be hardwired
> to
> > zero. This patch implements both of those requirements.
> >
> > Signed-off-by: Jonathan Behrens <fintelia@gmail.com>
> > ---
> > target/riscv/csr.c | 7 +++++--
> > 1 file changed, 5 insertions(+), 2 deletions(-)
> >
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index 1ec1222da1..fff7d834e8 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -246,6 +246,7 @@ static const target_ulong sstatus_v1_9_mask =
> > SSTATUS_SIE | SSTATUS_SPIE |
> > static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE |
> SSTATUS_SPIE |
> > SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
> > SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
> > +static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP |
> > MIP_UEIP;
> >
> > #if defined(TARGET_RISCV32)
> > static const char valid_vm_1_09[16] = {
> > @@ -694,8 +695,10 @@ static int write_sbadaddr(CPURISCVState *env, int
> > csrno, target_ulong val)
> > static int rmw_sip(CPURISCVState *env, int csrno, target_ulong
> *ret_value,
> > target_ulong new_value, target_ulong write_mask)
> > {
> > - return rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
> > - write_mask & env->mideleg);
> > + int ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
> > + write_mask & env->mideleg & sip_writable_mask);
> > + *ret_value &= env->mideleg;
> > + return ret;
> > }
> >
> > /* Supervisor Protection and Translation */
>
> This patch (and your previous one) don't apply for me. I don't see the
> git-send-email tags in your messages, are you trying to do something like
> paste
> them into gmail? If so I think they're getting line wrapped.
>
[-- Attachment #2: Type: text/html, Size: 3285 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-05-07 22:41 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-05-06 15:52 [Qemu-devel] [PATCH for 4.1] target/riscv: More accurate handling of `sip` CSR Jonathan Behrens
2019-05-06 15:52 ` [Qemu-riscv] " Jonathan Behrens
2019-05-07 17:52 ` [Qemu-devel] " Palmer Dabbelt
2019-05-07 17:52 ` [Qemu-riscv] " Palmer Dabbelt
2019-05-07 22:39 ` [Qemu-devel] " Jonathan Behrens
2019-05-07 22:39 ` [Qemu-riscv] " Jonathan Behrens
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