[U-Boot] [PATCH v1 1/2] odroid: pmic77686: allow bucket voltage settings

[U-Boot] [PATCH v1 1/2] odroid: pmic77686: allow bucket voltage settings

[Suriyan Ramasami]

Allow to set the bucket voltage for the max77686.
This will be used to reset the SMC LAN9730 ethernet on the odroids.

Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
---
 drivers/power/pmic/pmic_max77686.c | 48 +++++++++++++++++++++++++++++++++++++-
 include/power/max77686_pmic.h      |  3 +++
 2 files changed, 50 insertions(+), 1 deletion(-)

diff --git a/drivers/power/pmic/pmic_max77686.c b/drivers/power/pmic/pmic_max77686.c
index df1fd91..1aeadb4 100644
--- a/drivers/power/pmic/pmic_max77686.c
+++ b/drivers/power/pmic/pmic_max77686.c
@@ -42,6 +42,25 @@ static unsigned int max77686_ldo_volt2hex(int ldo, ulong uV)
 	return 0;
 }
 
+static unsigned int max77686_buck_volt2hex(int buck, ulong uV)
+{
+	unsigned int hex = 0;
+
+	if (buck < 5 || buck > 9) {
+		debug("%s: buck %d is not supported\n", __func__, buck);
+		return 0;
+	}
+
+	hex = (uV - 750000) / 50000;
+
+	if (hex >= 0 && hex <= MAX77686_BUCK_VOLT_MAX_HEX)
+		return hex;
+
+	debug("%s: %ld is wrong voltage value for BUCK%d\n",
+	      __func__, uV, buck);
+	return MAX77686_BUCK_VOLT_MAX_HEX + 1;
+}
+
 int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV)
 {
 	unsigned int val, ret, hex, adr;
@@ -68,6 +87,33 @@ int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV)
 	return ret;
 }
 
+int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV)
+{
+	unsigned int val, ret, hex, adr;
+
+	if (buck < 5 && buck > 9) {
+		printf("%s: %d is an unsupported bucket number\n",
+		       __func__, buck);
+		return -1;
+	}
+
+	adr = max77686_buck_addr[buck] + 1;
+	hex = max77686_buck_volt2hex(buck, uV);
+
+	if (hex == MAX77686_BUCK_VOLT_MAX_HEX + 1)
+		return -1;
+
+	ret = pmic_reg_read(p, adr, &val);
+	if (ret)
+		return ret;
+
+	val &= ~MAX77686_BUCK_VOLT_MASK;
+	val |= hex;
+	ret |= pmic_reg_write(p, adr, val);
+
+	return ret;
+}
+
 int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode)
 {
 	unsigned int val, ret, adr, mode;
@@ -157,7 +203,7 @@ int max77686_set_buck_mode(struct pmic *p, int buck, char opmode)
 	/* mode */
 	switch (opmode) {
 	case OPMODE_OFF:
-		mode = MAX77686_BUCK_MODE_OFF;
+		mode = MAX77686_BUCK_MODE_OFF << mode_shift;
 		break;
 	case OPMODE_STANDBY:
 		switch (buck) {
diff --git a/include/power/max77686_pmic.h b/include/power/max77686_pmic.h
index c2a772a..b0e4255 100644
--- a/include/power/max77686_pmic.h
+++ b/include/power/max77686_pmic.h
@@ -150,6 +150,7 @@ enum {
 
 int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV);
 int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode);
+int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV);
 int max77686_set_buck_mode(struct pmic *p, int buck, char opmode);
 
 #define MAX77686_LDO_VOLT_MAX_HEX	0x3f
@@ -159,6 +160,8 @@ int max77686_set_buck_mode(struct pmic *p, int buck, char opmode);
 #define MAX77686_LDO_MODE_STANDBY	(0x01 << 0x06)
 #define MAX77686_LDO_MODE_LPM		(0x02 << 0x06)
 #define MAX77686_LDO_MODE_ON		(0x03 << 0x06)
+#define MAX77686_BUCK_VOLT_MAX_HEX	0x3f
+#define MAX77686_BUCK_VOLT_MASK		0x3f
 #define MAX77686_BUCK_MODE_MASK		0x03
 #define MAX77686_BUCK_MODE_SHIFT_1	0x00
 #define MAX77686_BUCK_MODE_SHIFT_2	0x04
-- 
1.9.1

[U-Boot] [PATCH v1 2/2] odroid: usb: add support for usb host including ethernet

[Suriyan Ramasami]

This change adds support for enabling the USB host features of the board.
This includes the USB3503A hub and the SMC LAN9730 ethernet controller
as well.

Credit goes to Tushar Behera (Linaro) for the function set_usb_ethaddr().

Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
---
 arch/arm/cpu/armv7/exynos/power.c        | 26 +++++++++++++++
 arch/arm/dts/exynos4412-odroid.dts       | 11 +++++++
 arch/arm/include/asm/arch-exynos/cpu.h   |  2 ++
 arch/arm/include/asm/arch-exynos/ehci.h  | 13 ++++++++
 arch/arm/include/asm/arch-exynos/power.h |  7 ++++
 board/samsung/odroid/odroid.c            | 55 ++++++++++++++++++++++++++++++++
 drivers/usb/host/ehci-exynos.c           | 52 +++++++++++++++++++++++++-----
 include/configs/odroid.h                 | 13 ++++++++
 8 files changed, 171 insertions(+), 8 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c
index e1ab3d6..6578a07 100644
--- a/arch/arm/cpu/armv7/exynos/power.c
+++ b/arch/arm/cpu/armv7/exynos/power.c
@@ -53,10 +53,36 @@ void exynos5_set_usbhost_phy_ctrl(unsigned int enable)
 	}
 }
 
+void exynos4412_set_usbhost_phy_ctrl(unsigned int enable)
+{
+	struct exynos4412_power *power =
+		(struct exynos4412_power *)samsung_get_base_power();
+
+	if (enable) {
+		/* Enabling USBHOST_PHY */
+		setbits_le32(&power->usbhost_phy_control,
+			     POWER_USB_HOST_PHY_CTRL_EN);
+		setbits_le32(&power->hsic1_phy_control,
+			     POWER_USB_HOST_PHY_CTRL_EN);
+		setbits_le32(&power->hsic2_phy_control,
+			     POWER_USB_HOST_PHY_CTRL_EN);
+	} else {
+		/* Disabling USBHOST_PHY */
+		clrbits_le32(&power->usbhost_phy_control,
+			     POWER_USB_HOST_PHY_CTRL_EN);
+		clrbits_le32(&power->hsic1_phy_control,
+			     POWER_USB_HOST_PHY_CTRL_EN);
+		clrbits_le32(&power->hsic2_phy_control,
+			     POWER_USB_HOST_PHY_CTRL_EN);
+	}
+}
+
 void set_usbhost_phy_ctrl(unsigned int enable)
 {
 	if (cpu_is_exynos5())
 		exynos5_set_usbhost_phy_ctrl(enable);
+	else if (proid_is_exynos4412())
+		exynos4412_set_usbhost_phy_ctrl(enable);
 }
 
 static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable)
diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts
index 24d0bf1..8da8568 100644
--- a/arch/arm/dts/exynos4412-odroid.dts
+++ b/arch/arm/dts/exynos4412-odroid.dts
@@ -67,4 +67,15 @@
 		div = <0x3>;
 		index = <4>;
 	};
+
+        ehci at 12580000 {
+                compatible = "samsung,exynos-ehci";
+                reg = <0x12580000 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+                phy {
+                        compatible = "samsung,exynos-usb-phy";
+                        reg = <0x125B0000 0x100>;
+                };
+        };
 };
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index ba71714..fda21fb 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -18,6 +18,8 @@
 
 #define EXYNOS4_GPIO_PART3_BASE		0x03860000
 #define EXYNOS4_PRO_ID			0x10000000
+#define EXYNOS4_GUID_LOW		0x10000014
+#define EXYNOS4_GUID_HIGH		0x10000018
 #define EXYNOS4_SYSREG_BASE		0x10010000
 #define EXYNOS4_POWER_BASE		0x10020000
 #define EXYNOS4_SWRESET			0x10020400
diff --git a/arch/arm/include/asm/arch-exynos/ehci.h b/arch/arm/include/asm/arch-exynos/ehci.h
index d2d70bd..3800fa9 100644
--- a/arch/arm/include/asm/arch-exynos/ehci.h
+++ b/arch/arm/include/asm/arch-exynos/ehci.h
@@ -12,6 +12,13 @@
 
 #define CLK_24MHZ		5
 
+#define PHYPWR_NORMAL_MASK_PHY0                 (0x39 << 0)
+#define PHYPWR_NORMAL_MASK_PHY1                 (0x7 << 6)
+#define PHYPWR_NORMAL_MASK_HSIC0                (0x7 << 9)
+#define PHYPWR_NORMAL_MASK_HSIC1                (0x7 << 12)
+#define RSTCON_HOSTPHY_SWRST                    (0xf << 3)
+#define RSTCON_SWRST                            (0x1 << 0)
+
 #define HOST_CTRL0_PHYSWRSTALL			(1 << 31)
 #define HOST_CTRL0_COMMONON_N			(1 << 9)
 #define HOST_CTRL0_SIDDQ			(1 << 6)
@@ -61,6 +68,12 @@ struct exynos_usb_phy {
 	unsigned int usbotgtune;
 };
 
+struct exynos4412_usb_phy {
+	unsigned int usbphyctrl;
+	unsigned int usbphyclk;
+	unsigned int usbphyrstcon;
+};
+
 /* Switch on the VBUS power. */
 int board_usb_vbus_init(void);
 
diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h
index e8a98a5..3f97b31 100644
--- a/arch/arm/include/asm/arch-exynos/power.h
+++ b/arch/arm/include/asm/arch-exynos/power.h
@@ -210,6 +210,13 @@ struct exynos4_power {
 	unsigned int	gps_alive_option;
 };
 
+struct exynos4412_power {
+	unsigned char	res1[0x0704];
+	unsigned int	usbhost_phy_control;
+	unsigned int	hsic1_phy_control;
+	unsigned int	hsic2_phy_control;
+};
+
 struct exynos5_power {
 	unsigned int	om_stat;
 	unsigned char	res1[0x18];
diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c
index fd5d2d2..4764a71 100644
--- a/board/samsung/odroid/odroid.c
+++ b/board/samsung/odroid/odroid.c
@@ -453,9 +453,64 @@ struct s3c_plat_otg_data s5pc210_otg_data = {
 	.usb_phy_ctrl	= EXYNOS4X12_USBPHY_CONTROL,
 	.usb_flags	= PHY0_SLEEP,
 };
+#endif
+
+#if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB)
+
+#ifdef CONFIG_CMD_USB
+static void set_usb_ethaddr(void)
+{
+	int i;
+	uchar mac[6];
+	unsigned int guid_high = readl(EXYNOS4_GUID_HIGH);
+	unsigned int guid_low = readl(EXYNOS4_GUID_LOW);
+
+	for (i = 0; i < 2; i++)
+		mac[i] = (guid_high >> (8 * (1 - i))) & 0xFF;
+
+	for (i = 0; i < 4; i++)
+		mac[i+2] = (guid_low >> (8 * (3 - i))) & 0xFF;
+
+	/* mark it as not multicast and outside official 80211 MAC namespace */
+	mac[0] = (mac[0] & ~0x1) | 0x2;
+
+	eth_setenv_enetaddr("ethaddr", mac);
+	eth_setenv_enetaddr("usbethaddr", mac);
+}
+#endif
 
 int board_usb_init(int index, enum usb_init_type init)
 {
+#ifdef CONFIG_CMD_USB
+	struct pmic *p_pmic;
+
+	/* Set Ref freq 0 => 24MHz, 1 => 26MHz*/
+	/* Odroid Us have it at 24MHz, Odroid Xs at 26MHz */
+	if (gd->board_type == ODROID_TYPE_U3)
+		gpio_direction_output(EXYNOS4X12_GPIO_X30, 0);
+	else
+		gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
+
+	/* Disconnect, Reset, Connect */
+	gpio_direction_output(EXYNOS4X12_GPIO_X34, 0);
+	gpio_direction_output(EXYNOS4X12_GPIO_X35, 0);
+	gpio_direction_output(EXYNOS4X12_GPIO_X35, 1);
+	gpio_direction_output(EXYNOS4X12_GPIO_X34, 1);
+
+	/* Power off and on BUCK8 for LAN9730 */
+	debug("LAN9730 - Turning power buck 8 OFF and ON.\n");
+
+	p_pmic = pmic_get("MAX77686_PMIC");
+	if (p_pmic && !pmic_probe(p_pmic)) {
+		max77686_set_buck_mode(p_pmic, 8, OPMODE_OFF);
+		max77686_set_buck_voltage(p_pmic, 8, 750000);
+		max77686_set_buck_voltage(p_pmic, 8, 3300000);
+		max77686_set_buck_mode(p_pmic, 8, OPMODE_ON);
+	}
+
+	set_usb_ethaddr();
+#endif
+
 	debug("USB_udc_probe\n");
 	return s3c_udc_probe(&s5pc210_otg_data);
 }
diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
index edd91a8..91f3c72 100644
--- a/drivers/usb/host/ehci-exynos.c
+++ b/drivers/usb/host/ehci-exynos.c
@@ -19,6 +19,7 @@
 #include <asm/gpio.h>
 #include <asm-generic/errno.h>
 #include <linux/compat.h>
+#include <power/max77686_pmic.h>
 #include "ehci.h"
 
 /* Declare global data pointer */
@@ -85,15 +86,10 @@ static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos)
 }
 #endif
 
-/* Setup the EHCI host controller. */
-static void setup_usb_phy(struct exynos_usb_phy *usb)
+static void exynos5_setup_usb_phy(struct exynos_usb_phy *usb)
 {
 	u32 hsic_ctrl;
 
-	set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
-
-	set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
-
 	clrbits_le32(&usb->usbphyctrl0,
 			HOST_CTRL0_FSEL_MASK |
 			HOST_CTRL0_COMMONON_N |
@@ -150,8 +146,32 @@ static void setup_usb_phy(struct exynos_usb_phy *usb)
 			EHCICTRL_ENAINCR16);
 }
 
-/* Reset the EHCI host controller. */
-static void reset_usb_phy(struct exynos_usb_phy *usb)
+static void exynos4412_setup_usb_phy(struct exynos4412_usb_phy *usb)
+{
+	writel(CLK_24MHZ, &usb->usbphyclk);
+
+	clrbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
+		PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
+		PHYPWR_NORMAL_MASK_PHY0));
+
+	setbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
+	udelay(10);
+	clrbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
+}
+
+static void setup_usb_phy(struct exynos_usb_phy *usb)
+{
+	set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
+
+	set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
+
+	if (cpu_is_exynos5())
+		exynos5_setup_usb_phy(usb);
+	else if (proid_is_exynos4412())
+		exynos4412_setup_usb_phy((struct exynos4412_usb_phy *)usb);
+}
+
+static void exynos5_reset_usb_phy(struct exynos_usb_phy *usb)
 {
 	u32 hsic_ctrl;
 
@@ -171,6 +191,22 @@ static void reset_usb_phy(struct exynos_usb_phy *usb)
 
 	setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
 	setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
+}
+
+static void exynos4412_reset_usb_phy(struct exynos4412_usb_phy *usb)
+{
+	setbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
+		PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
+		PHYPWR_NORMAL_MASK_PHY0));
+}
+
+/* Reset the EHCI host controller. */
+static void reset_usb_phy(struct exynos_usb_phy *usb)
+{
+	if (cpu_is_exynos5())
+		exynos5_reset_usb_phy(usb);
+	else if (proid_is_exynos4412())
+		exynos4412_reset_usb_phy((struct exynos4412_usb_phy *)usb);
 
 	set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE);
 }
diff --git a/include/configs/odroid.h b/include/configs/odroid.h
index b616ac2..3fc0508 100644
--- a/include/configs/odroid.h
+++ b/include/configs/odroid.h
@@ -200,6 +200,19 @@
 
 #define CONFIG_CMD_GPIO
 
+/* USB */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_EXYNOS
+#define CONFIG_USB_STORAGE
+
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	3
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+
 /*
  * Supported Odroid boards: X3, U3
  * TODO: Add Odroid X support
-- 
1.9.1

[U-Boot] [PATCH v1 1/2] odroid: pmic77686: allow bucket voltage settings

[Przemyslaw Marczak]

Dear Suriyan,

I will try to test it after the weekend.

I'm working on a PMIC framework V3 with Trats2 as a base and the buck 
mode/voltage for Max77686 are yet implemented in my code.

But this is okay because the new driver is fully reworked into new file 
and the support to the old PMIC framework will be still keept before 
move all the drivers to PMIC v3.

The RFC will send soon.

On 10/02/2014 03:45 PM, Suriyan Ramasami wrote:
> Allow to set the bucket voltage for the max77686.
> This will be used to reset the SMC LAN9730 ethernet on the odroids.
>
> Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
> ---
>   drivers/power/pmic/pmic_max77686.c | 48 +++++++++++++++++++++++++++++++++++++-
>   include/power/max77686_pmic.h      |  3 +++
>   2 files changed, 50 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/power/pmic/pmic_max77686.c b/drivers/power/pmic/pmic_max77686.c
> index df1fd91..1aeadb4 100644
> --- a/drivers/power/pmic/pmic_max77686.c
> +++ b/drivers/power/pmic/pmic_max77686.c
> @@ -42,6 +42,25 @@ static unsigned int max77686_ldo_volt2hex(int ldo, ulong uV)
>   	return 0;
>   }
>
> +static unsigned int max77686_buck_volt2hex(int buck, ulong uV)
> +{
> +	unsigned int hex = 0;
> +
> +	if (buck < 5 || buck > 9) {
> +		debug("%s: buck %d is not supported\n", __func__, buck);
> +		return 0;
> +	}
> +
> +	hex = (uV - 750000) / 50000;
> +
> +	if (hex >= 0 && hex <= MAX77686_BUCK_VOLT_MAX_HEX)
> +		return hex;
> +
> +	debug("%s: %ld is wrong voltage value for BUCK%d\n",
> +	      __func__, uV, buck);
> +	return MAX77686_BUCK_VOLT_MAX_HEX + 1;
> +}
> +
>   int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV)
>   {
>   	unsigned int val, ret, hex, adr;
> @@ -68,6 +87,33 @@ int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV)
>   	return ret;
>   }
>
> +int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV)
> +{
> +	unsigned int val, ret, hex, adr;
> +
> +	if (buck < 5 && buck > 9) {
> +		printf("%s: %d is an unsupported bucket number\n",
> +		       __func__, buck);
> +		return -1;
> +	}
> +
> +	adr = max77686_buck_addr[buck] + 1;
> +	hex = max77686_buck_volt2hex(buck, uV);
> +
> +	if (hex == MAX77686_BUCK_VOLT_MAX_HEX + 1)
> +		return -1;
> +
> +	ret = pmic_reg_read(p, adr, &val);
> +	if (ret)
> +		return ret;
> +
> +	val &= ~MAX77686_BUCK_VOLT_MASK;
> +	val |= hex;
> +	ret |= pmic_reg_write(p, adr, val);
> +
> +	return ret;
> +}
> +
>   int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode)
>   {
>   	unsigned int val, ret, adr, mode;
> @@ -157,7 +203,7 @@ int max77686_set_buck_mode(struct pmic *p, int buck, char opmode)
>   	/* mode */
>   	switch (opmode) {
>   	case OPMODE_OFF:
> -		mode = MAX77686_BUCK_MODE_OFF;
> +		mode = MAX77686_BUCK_MODE_OFF << mode_shift;
>   		break;
>   	case OPMODE_STANDBY:
>   		switch (buck) {
> diff --git a/include/power/max77686_pmic.h b/include/power/max77686_pmic.h
> index c2a772a..b0e4255 100644
> --- a/include/power/max77686_pmic.h
> +++ b/include/power/max77686_pmic.h
> @@ -150,6 +150,7 @@ enum {
>
>   int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV);
>   int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode);
> +int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV);
>   int max77686_set_buck_mode(struct pmic *p, int buck, char opmode);
>
>   #define MAX77686_LDO_VOLT_MAX_HEX	0x3f
> @@ -159,6 +160,8 @@ int max77686_set_buck_mode(struct pmic *p, int buck, char opmode);
>   #define MAX77686_LDO_MODE_STANDBY	(0x01 << 0x06)
>   #define MAX77686_LDO_MODE_LPM		(0x02 << 0x06)
>   #define MAX77686_LDO_MODE_ON		(0x03 << 0x06)
> +#define MAX77686_BUCK_VOLT_MAX_HEX	0x3f
> +#define MAX77686_BUCK_VOLT_MASK		0x3f
>   #define MAX77686_BUCK_MODE_MASK		0x03
>   #define MAX77686_BUCK_MODE_SHIFT_1	0x00
>   #define MAX77686_BUCK_MODE_SHIFT_2	0x04
>

Best regards,
-- 
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com

[U-Boot] [PATCH v1 1/2] odroid: pmic77686: allow bucket voltage settings

[Albert ARIBAUD]

Hi Suriyan,

On Thu,  2 Oct 2014 06:45:58 -0700, Suriyan Ramasami
<suriyan.r@gmail.com> wrote:

> Allow to set the bucket voltage for the max77686.
> This will be used to reset the SMC LAN9730 ethernet on the odroids.

I believe the correct term is "buck", not "bucket".

> Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
> ---
>  drivers/power/pmic/pmic_max77686.c | 48 +++++++++++++++++++++++++++++++++++++-
>  include/power/max77686_pmic.h      |  3 +++
>  2 files changed, 50 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/power/pmic/pmic_max77686.c b/drivers/power/pmic/pmic_max77686.c
> index df1fd91..1aeadb4 100644
> --- a/drivers/power/pmic/pmic_max77686.c
> +++ b/drivers/power/pmic/pmic_max77686.c
> @@ -42,6 +42,25 @@ static unsigned int max77686_ldo_volt2hex(int ldo, ulong uV)
>  	return 0;
>  }
>  
> +static unsigned int max77686_buck_volt2hex(int buck, ulong uV)
> +{
> +	unsigned int hex = 0;
> +
> +	if (buck < 5 || buck > 9) {
> +		debug("%s: buck %d is not supported\n", __func__, buck);
> +		return 0;
> +	}
> +
> +	hex = (uV - 750000) / 50000;
> +
> +	if (hex >= 0 && hex <= MAX77686_BUCK_VOLT_MAX_HEX)
> +		return hex;
> +
> +	debug("%s: %ld is wrong voltage value for BUCK%d\n",
> +	      __func__, uV, buck);
> +	return MAX77686_BUCK_VOLT_MAX_HEX + 1;
> +}
> +
>  int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV)
>  {
>  	unsigned int val, ret, hex, adr;
> @@ -68,6 +87,33 @@ int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV)
>  	return ret;
>  }
>  
> +int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV)
> +{
> +	unsigned int val, ret, hex, adr;
> +
> +	if (buck < 5 && buck > 9) {
> +		printf("%s: %d is an unsupported bucket number\n",
> +		       __func__, buck);
> +		return -1;
> +	}
> +
> +	adr = max77686_buck_addr[buck] + 1;
> +	hex = max77686_buck_volt2hex(buck, uV);
> +
> +	if (hex == MAX77686_BUCK_VOLT_MAX_HEX + 1)
> +		return -1;
> +
> +	ret = pmic_reg_read(p, adr, &val);
> +	if (ret)
> +		return ret;
> +
> +	val &= ~MAX77686_BUCK_VOLT_MASK;
> +	val |= hex;
> +	ret |= pmic_reg_write(p, adr, val);
> +
> +	return ret;
> +}
> +
>  int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode)
>  {
>  	unsigned int val, ret, adr, mode;
> @@ -157,7 +203,7 @@ int max77686_set_buck_mode(struct pmic *p, int buck, char opmode)
>  	/* mode */
>  	switch (opmode) {
>  	case OPMODE_OFF:
> -		mode = MAX77686_BUCK_MODE_OFF;
> +		mode = MAX77686_BUCK_MODE_OFF << mode_shift;
>  		break;
>  	case OPMODE_STANDBY:
>  		switch (buck) {
> diff --git a/include/power/max77686_pmic.h b/include/power/max77686_pmic.h
> index c2a772a..b0e4255 100644
> --- a/include/power/max77686_pmic.h
> +++ b/include/power/max77686_pmic.h
> @@ -150,6 +150,7 @@ enum {
>  
>  int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV);
>  int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode);
> +int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV);
>  int max77686_set_buck_mode(struct pmic *p, int buck, char opmode);
>  
>  #define MAX77686_LDO_VOLT_MAX_HEX	0x3f
> @@ -159,6 +160,8 @@ int max77686_set_buck_mode(struct pmic *p, int buck, char opmode);
>  #define MAX77686_LDO_MODE_STANDBY	(0x01 << 0x06)
>  #define MAX77686_LDO_MODE_LPM		(0x02 << 0x06)
>  #define MAX77686_LDO_MODE_ON		(0x03 << 0x06)
> +#define MAX77686_BUCK_VOLT_MAX_HEX	0x3f
> +#define MAX77686_BUCK_VOLT_MASK		0x3f
>  #define MAX77686_BUCK_MODE_MASK		0x03
>  #define MAX77686_BUCK_MODE_SHIFT_1	0x00
>  #define MAX77686_BUCK_MODE_SHIFT_2	0x04


Amicalement,
-- 
Albert.

[U-Boot] [PATCH v1 1/2] odroid: pmic77686: allow bucket voltage settings

[Suriyan Ramasami]

On Thu, Oct 2, 2014 at 2:03 PM, Albert ARIBAUD
<albert.u.boot@aribaud.net> wrote:
> Hi Suriyan,
>
> On Thu,  2 Oct 2014 06:45:58 -0700, Suriyan Ramasami
> <suriyan.r@gmail.com> wrote:
>
>> Allow to set the bucket voltage for the max77686.
>> This will be used to reset the SMC LAN9730 ethernet on the odroids.
>
> I believe the correct term is "buck", not "bucket".
>

Thanks Albert,
   I always thought they stood for bucket! This prompted me to read up
on BUCK regulators. Thank you. I shall correct it in my next version.

- Suriyan

>> Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
>> ---
>>  drivers/power/pmic/pmic_max77686.c | 48 +++++++++++++++++++++++++++++++++++++-
>>  include/power/max77686_pmic.h      |  3 +++
>>  2 files changed, 50 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/power/pmic/pmic_max77686.c b/drivers/power/pmic/pmic_max77686.c
>> index df1fd91..1aeadb4 100644
>> --- a/drivers/power/pmic/pmic_max77686.c
>> +++ b/drivers/power/pmic/pmic_max77686.c
>> @@ -42,6 +42,25 @@ static unsigned int max77686_ldo_volt2hex(int ldo, ulong uV)
>>       return 0;
>>  }
>>
>> +static unsigned int max77686_buck_volt2hex(int buck, ulong uV)
>> +{
>> +     unsigned int hex = 0;
>> +
>> +     if (buck < 5 || buck > 9) {
>> +             debug("%s: buck %d is not supported\n", __func__, buck);
>> +             return 0;
>> +     }
>> +
>> +     hex = (uV - 750000) / 50000;
>> +
>> +     if (hex >= 0 && hex <= MAX77686_BUCK_VOLT_MAX_HEX)
>> +             return hex;
>> +
>> +     debug("%s: %ld is wrong voltage value for BUCK%d\n",
>> +           __func__, uV, buck);
>> +     return MAX77686_BUCK_VOLT_MAX_HEX + 1;
>> +}
>> +
>>  int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV)
>>  {
>>       unsigned int val, ret, hex, adr;
>> @@ -68,6 +87,33 @@ int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV)
>>       return ret;
>>  }
>>
>> +int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV)
>> +{
>> +     unsigned int val, ret, hex, adr;
>> +
>> +     if (buck < 5 && buck > 9) {
>> +             printf("%s: %d is an unsupported bucket number\n",
>> +                    __func__, buck);
>> +             return -1;
>> +     }
>> +
>> +     adr = max77686_buck_addr[buck] + 1;
>> +     hex = max77686_buck_volt2hex(buck, uV);
>> +
>> +     if (hex == MAX77686_BUCK_VOLT_MAX_HEX + 1)
>> +             return -1;
>> +
>> +     ret = pmic_reg_read(p, adr, &val);
>> +     if (ret)
>> +             return ret;
>> +
>> +     val &= ~MAX77686_BUCK_VOLT_MASK;
>> +     val |= hex;
>> +     ret |= pmic_reg_write(p, adr, val);
>> +
>> +     return ret;
>> +}
>> +
>>  int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode)
>>  {
>>       unsigned int val, ret, adr, mode;
>> @@ -157,7 +203,7 @@ int max77686_set_buck_mode(struct pmic *p, int buck, char opmode)
>>       /* mode */
>>       switch (opmode) {
>>       case OPMODE_OFF:
>> -             mode = MAX77686_BUCK_MODE_OFF;
>> +             mode = MAX77686_BUCK_MODE_OFF << mode_shift;
>>               break;
>>       case OPMODE_STANDBY:
>>               switch (buck) {
>> diff --git a/include/power/max77686_pmic.h b/include/power/max77686_pmic.h
>> index c2a772a..b0e4255 100644
>> --- a/include/power/max77686_pmic.h
>> +++ b/include/power/max77686_pmic.h
>> @@ -150,6 +150,7 @@ enum {
>>
>>  int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV);
>>  int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode);
>> +int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV);
>>  int max77686_set_buck_mode(struct pmic *p, int buck, char opmode);
>>
>>  #define MAX77686_LDO_VOLT_MAX_HEX    0x3f
>> @@ -159,6 +160,8 @@ int max77686_set_buck_mode(struct pmic *p, int buck, char opmode);
>>  #define MAX77686_LDO_MODE_STANDBY    (0x01 << 0x06)
>>  #define MAX77686_LDO_MODE_LPM                (0x02 << 0x06)
>>  #define MAX77686_LDO_MODE_ON         (0x03 << 0x06)
>> +#define MAX77686_BUCK_VOLT_MAX_HEX   0x3f
>> +#define MAX77686_BUCK_VOLT_MASK              0x3f
>>  #define MAX77686_BUCK_MODE_MASK              0x03
>>  #define MAX77686_BUCK_MODE_SHIFT_1   0x00
>>  #define MAX77686_BUCK_MODE_SHIFT_2   0x04
>
>
> Amicalement,
> --
> Albert.

[U-Boot] [PATCH v1 1/2] odroid: pmic77686: allow bucket voltage settings

[Suriyan Ramasami]

On Thu, Oct 2, 2014 at 7:31 AM, Przemyslaw Marczak
<p.marczak@samsung.com> wrote:
> Dear Suriyan,
>
> I will try to test it after the weekend.
>
> I'm working on a PMIC framework V3 with Trats2 as a base and the buck
> mode/voltage for Max77686 are yet implemented in my code.
>
> But this is okay because the new driver is fully reworked into new file and
> the support to the old PMIC framework will be still keept before move all
> the drivers to PMIC v3.
>
> The RFC will send soon.
>

Thanks Przemyslaw,
   Just FYI, I tested the USB host on the Odroid U2, a U3 and an X2.

Regards
- Suriyan

>
> On 10/02/2014 03:45 PM, Suriyan Ramasami wrote:
>>
>> Allow to set the bucket voltage for the max77686.
>> This will be used to reset the SMC LAN9730 ethernet on the odroids.
>>
>> Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
>> ---
>>   drivers/power/pmic/pmic_max77686.c | 48
>> +++++++++++++++++++++++++++++++++++++-
>>   include/power/max77686_pmic.h      |  3 +++
>>   2 files changed, 50 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/power/pmic/pmic_max77686.c
>> b/drivers/power/pmic/pmic_max77686.c
>> index df1fd91..1aeadb4 100644
>> --- a/drivers/power/pmic/pmic_max77686.c
>> +++ b/drivers/power/pmic/pmic_max77686.c
>> @@ -42,6 +42,25 @@ static unsigned int max77686_ldo_volt2hex(int ldo,
>> ulong uV)
>>         return 0;
>>   }
>>
>> +static unsigned int max77686_buck_volt2hex(int buck, ulong uV)
>> +{
>> +       unsigned int hex = 0;
>> +
>> +       if (buck < 5 || buck > 9) {
>> +               debug("%s: buck %d is not supported\n", __func__, buck);
>> +               return 0;
>> +       }
>> +
>> +       hex = (uV - 750000) / 50000;
>> +
>> +       if (hex >= 0 && hex <= MAX77686_BUCK_VOLT_MAX_HEX)
>> +               return hex;
>> +
>> +       debug("%s: %ld is wrong voltage value for BUCK%d\n",
>> +             __func__, uV, buck);
>> +       return MAX77686_BUCK_VOLT_MAX_HEX + 1;
>> +}
>> +
>>   int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV)
>>   {
>>         unsigned int val, ret, hex, adr;
>> @@ -68,6 +87,33 @@ int max77686_set_ldo_voltage(struct pmic *p, int ldo,
>> ulong uV)
>>         return ret;
>>   }
>>
>> +int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV)
>> +{
>> +       unsigned int val, ret, hex, adr;
>> +
>> +       if (buck < 5 && buck > 9) {
>> +               printf("%s: %d is an unsupported bucket number\n",
>> +                      __func__, buck);
>> +               return -1;
>> +       }
>> +
>> +       adr = max77686_buck_addr[buck] + 1;
>> +       hex = max77686_buck_volt2hex(buck, uV);
>> +
>> +       if (hex == MAX77686_BUCK_VOLT_MAX_HEX + 1)
>> +               return -1;
>> +
>> +       ret = pmic_reg_read(p, adr, &val);
>> +       if (ret)
>> +               return ret;
>> +
>> +       val &= ~MAX77686_BUCK_VOLT_MASK;
>> +       val |= hex;
>> +       ret |= pmic_reg_write(p, adr, val);
>> +
>> +       return ret;
>> +}
>> +
>>   int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode)
>>   {
>>         unsigned int val, ret, adr, mode;
>> @@ -157,7 +203,7 @@ int max77686_set_buck_mode(struct pmic *p, int buck,
>> char opmode)
>>         /* mode */
>>         switch (opmode) {
>>         case OPMODE_OFF:
>> -               mode = MAX77686_BUCK_MODE_OFF;
>> +               mode = MAX77686_BUCK_MODE_OFF << mode_shift;
>>                 break;
>>         case OPMODE_STANDBY:
>>                 switch (buck) {
>> diff --git a/include/power/max77686_pmic.h b/include/power/max77686_pmic.h
>> index c2a772a..b0e4255 100644
>> --- a/include/power/max77686_pmic.h
>> +++ b/include/power/max77686_pmic.h
>> @@ -150,6 +150,7 @@ enum {
>>
>>   int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV);
>>   int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode);
>> +int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV);
>>   int max77686_set_buck_mode(struct pmic *p, int buck, char opmode);
>>
>>   #define MAX77686_LDO_VOLT_MAX_HEX     0x3f
>> @@ -159,6 +160,8 @@ int max77686_set_buck_mode(struct pmic *p, int buck,
>> char opmode);
>>   #define MAX77686_LDO_MODE_STANDBY     (0x01 << 0x06)
>>   #define MAX77686_LDO_MODE_LPM         (0x02 << 0x06)
>>   #define MAX77686_LDO_MODE_ON          (0x03 << 0x06)
>> +#define MAX77686_BUCK_VOLT_MAX_HEX     0x3f
>> +#define MAX77686_BUCK_VOLT_MASK                0x3f
>>   #define MAX77686_BUCK_MODE_MASK               0x03
>>   #define MAX77686_BUCK_MODE_SHIFT_1    0x00
>>   #define MAX77686_BUCK_MODE_SHIFT_2    0x04
>>
>
> Best regards,
> --
> Przemyslaw Marczak
> Samsung R&D Institute Poland
> Samsung Electronics
> p.marczak at samsung.com

[U-Boot] [PATCH v1 2/2] odroid: usb: add support for usb host including ethernet

[Jaehoon Chung]

Hi, Suriyan.

This patch can be separated.

On 10/02/2014 10:45 PM, Suriyan Ramasami wrote:
> This change adds support for enabling the USB host features of the board.
> This includes the USB3503A hub and the SMC LAN9730 ethernet controller
> as well.
> 
> Credit goes to Tushar Behera (Linaro) for the function set_usb_ethaddr().
> 
> Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
> ---
>  arch/arm/cpu/armv7/exynos/power.c        | 26 +++++++++++++++
>  arch/arm/dts/exynos4412-odroid.dts       | 11 +++++++
>  arch/arm/include/asm/arch-exynos/cpu.h   |  2 ++
>  arch/arm/include/asm/arch-exynos/ehci.h  | 13 ++++++++
>  arch/arm/include/asm/arch-exynos/power.h |  7 ++++
>  board/samsung/odroid/odroid.c            | 55 ++++++++++++++++++++++++++++++++
>  drivers/usb/host/ehci-exynos.c           | 52 +++++++++++++++++++++++++-----
>  include/configs/odroid.h                 | 13 ++++++++
>  8 files changed, 171 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c
> index e1ab3d6..6578a07 100644
> --- a/arch/arm/cpu/armv7/exynos/power.c
> +++ b/arch/arm/cpu/armv7/exynos/power.c
> @@ -53,10 +53,36 @@ void exynos5_set_usbhost_phy_ctrl(unsigned int enable)
>  	}
>  }
>  
> +void exynos4412_set_usbhost_phy_ctrl(unsigned int enable)
> +{
> +	struct exynos4412_power *power =
> +		(struct exynos4412_power *)samsung_get_base_power();
> +
> +	if (enable) {
> +		/* Enabling USBHOST_PHY */
> +		setbits_le32(&power->usbhost_phy_control,
> +			     POWER_USB_HOST_PHY_CTRL_EN);
> +		setbits_le32(&power->hsic1_phy_control,
> +			     POWER_USB_HOST_PHY_CTRL_EN);
> +		setbits_le32(&power->hsic2_phy_control,
> +			     POWER_USB_HOST_PHY_CTRL_EN);
> +	} else {
> +		/* Disabling USBHOST_PHY */
> +		clrbits_le32(&power->usbhost_phy_control,
> +			     POWER_USB_HOST_PHY_CTRL_EN);
> +		clrbits_le32(&power->hsic1_phy_control,
> +			     POWER_USB_HOST_PHY_CTRL_EN);
> +		clrbits_le32(&power->hsic2_phy_control,
> +			     POWER_USB_HOST_PHY_CTRL_EN);
> +	}
> +}
> +
>  void set_usbhost_phy_ctrl(unsigned int enable)
>  {
>  	if (cpu_is_exynos5())
>  		exynos5_set_usbhost_phy_ctrl(enable);
> +	else if (proid_is_exynos4412())
> +		exynos4412_set_usbhost_phy_ctrl(enable);
>  }
>  
>  static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable)
> diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts
> index 24d0bf1..8da8568 100644
> --- a/arch/arm/dts/exynos4412-odroid.dts
> +++ b/arch/arm/dts/exynos4412-odroid.dts
> @@ -67,4 +67,15 @@
>  		div = <0x3>;
>  		index = <4>;
>  	};
> +
> +        ehci at 12580000 {
> +                compatible = "samsung,exynos-ehci";
> +                reg = <0x12580000 0x100>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +                phy {
> +                        compatible = "samsung,exynos-usb-phy";
> +                        reg = <0x125B0000 0x100>;
> +                };
> +        };

Fix the indentation.

Best Regards,
Jaehoon Chung

>  };
> diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
> index ba71714..fda21fb 100644
> --- a/arch/arm/include/asm/arch-exynos/cpu.h
> +++ b/arch/arm/include/asm/arch-exynos/cpu.h
> @@ -18,6 +18,8 @@
>  
>  #define EXYNOS4_GPIO_PART3_BASE		0x03860000
>  #define EXYNOS4_PRO_ID			0x10000000
> +#define EXYNOS4_GUID_LOW		0x10000014
> +#define EXYNOS4_GUID_HIGH		0x10000018
>  #define EXYNOS4_SYSREG_BASE		0x10010000
>  #define EXYNOS4_POWER_BASE		0x10020000
>  #define EXYNOS4_SWRESET			0x10020400
> diff --git a/arch/arm/include/asm/arch-exynos/ehci.h b/arch/arm/include/asm/arch-exynos/ehci.h
> index d2d70bd..3800fa9 100644
> --- a/arch/arm/include/asm/arch-exynos/ehci.h
> +++ b/arch/arm/include/asm/arch-exynos/ehci.h
> @@ -12,6 +12,13 @@
>  
>  #define CLK_24MHZ		5
>  
> +#define PHYPWR_NORMAL_MASK_PHY0                 (0x39 << 0)
> +#define PHYPWR_NORMAL_MASK_PHY1                 (0x7 << 6)
> +#define PHYPWR_NORMAL_MASK_HSIC0                (0x7 << 9)
> +#define PHYPWR_NORMAL_MASK_HSIC1                (0x7 << 12)
> +#define RSTCON_HOSTPHY_SWRST                    (0xf << 3)
> +#define RSTCON_SWRST                            (0x1 << 0)
> +
>  #define HOST_CTRL0_PHYSWRSTALL			(1 << 31)
>  #define HOST_CTRL0_COMMONON_N			(1 << 9)
>  #define HOST_CTRL0_SIDDQ			(1 << 6)
> @@ -61,6 +68,12 @@ struct exynos_usb_phy {
>  	unsigned int usbotgtune;
>  };
>  
> +struct exynos4412_usb_phy {
> +	unsigned int usbphyctrl;
> +	unsigned int usbphyclk;
> +	unsigned int usbphyrstcon;
> +};
> +
>  /* Switch on the VBUS power. */
>  int board_usb_vbus_init(void);
>  
> diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h
> index e8a98a5..3f97b31 100644
> --- a/arch/arm/include/asm/arch-exynos/power.h
> +++ b/arch/arm/include/asm/arch-exynos/power.h
> @@ -210,6 +210,13 @@ struct exynos4_power {
>  	unsigned int	gps_alive_option;
>  };
>  
> +struct exynos4412_power {
> +	unsigned char	res1[0x0704];
> +	unsigned int	usbhost_phy_control;
> +	unsigned int	hsic1_phy_control;
> +	unsigned int	hsic2_phy_control;
> +};
> +
>  struct exynos5_power {
>  	unsigned int	om_stat;
>  	unsigned char	res1[0x18];
> diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c
> index fd5d2d2..4764a71 100644
> --- a/board/samsung/odroid/odroid.c
> +++ b/board/samsung/odroid/odroid.c
> @@ -453,9 +453,64 @@ struct s3c_plat_otg_data s5pc210_otg_data = {
>  	.usb_phy_ctrl	= EXYNOS4X12_USBPHY_CONTROL,
>  	.usb_flags	= PHY0_SLEEP,
>  };
> +#endif
> +
> +#if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB)
> +
> +#ifdef CONFIG_CMD_USB
> +static void set_usb_ethaddr(void)
> +{
> +	int i;
> +	uchar mac[6];
> +	unsigned int guid_high = readl(EXYNOS4_GUID_HIGH);
> +	unsigned int guid_low = readl(EXYNOS4_GUID_LOW);
> +
> +	for (i = 0; i < 2; i++)
> +		mac[i] = (guid_high >> (8 * (1 - i))) & 0xFF;
> +
> +	for (i = 0; i < 4; i++)
> +		mac[i+2] = (guid_low >> (8 * (3 - i))) & 0xFF;
> +
> +	/* mark it as not multicast and outside official 80211 MAC namespace */
> +	mac[0] = (mac[0] & ~0x1) | 0x2;
> +
> +	eth_setenv_enetaddr("ethaddr", mac);
> +	eth_setenv_enetaddr("usbethaddr", mac);
> +}
> +#endif
>  
>  int board_usb_init(int index, enum usb_init_type init)
>  {
> +#ifdef CONFIG_CMD_USB
> +	struct pmic *p_pmic;
> +
> +	/* Set Ref freq 0 => 24MHz, 1 => 26MHz*/
> +	/* Odroid Us have it at 24MHz, Odroid Xs at 26MHz */
> +	if (gd->board_type == ODROID_TYPE_U3)
> +		gpio_direction_output(EXYNOS4X12_GPIO_X30, 0);
> +	else
> +		gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
> +
> +	/* Disconnect, Reset, Connect */
> +	gpio_direction_output(EXYNOS4X12_GPIO_X34, 0);
> +	gpio_direction_output(EXYNOS4X12_GPIO_X35, 0);
> +	gpio_direction_output(EXYNOS4X12_GPIO_X35, 1);
> +	gpio_direction_output(EXYNOS4X12_GPIO_X34, 1);
> +
> +	/* Power off and on BUCK8 for LAN9730 */
> +	debug("LAN9730 - Turning power buck 8 OFF and ON.\n");
> +
> +	p_pmic = pmic_get("MAX77686_PMIC");
> +	if (p_pmic && !pmic_probe(p_pmic)) {
> +		max77686_set_buck_mode(p_pmic, 8, OPMODE_OFF);
> +		max77686_set_buck_voltage(p_pmic, 8, 750000);
> +		max77686_set_buck_voltage(p_pmic, 8, 3300000);
> +		max77686_set_buck_mode(p_pmic, 8, OPMODE_ON);
> +	}
> +
> +	set_usb_ethaddr();
> +#endif
> +
>  	debug("USB_udc_probe\n");
>  	return s3c_udc_probe(&s5pc210_otg_data);
>  }
> diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
> index edd91a8..91f3c72 100644
> --- a/drivers/usb/host/ehci-exynos.c
> +++ b/drivers/usb/host/ehci-exynos.c
> @@ -19,6 +19,7 @@
>  #include <asm/gpio.h>
>  #include <asm-generic/errno.h>
>  #include <linux/compat.h>
> +#include <power/max77686_pmic.h>
>  #include "ehci.h"
>  
>  /* Declare global data pointer */
> @@ -85,15 +86,10 @@ static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos)
>  }
>  #endif
>  
> -/* Setup the EHCI host controller. */
> -static void setup_usb_phy(struct exynos_usb_phy *usb)
> +static void exynos5_setup_usb_phy(struct exynos_usb_phy *usb)
>  {
>  	u32 hsic_ctrl;
>  
> -	set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
> -
> -	set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
> -
>  	clrbits_le32(&usb->usbphyctrl0,
>  			HOST_CTRL0_FSEL_MASK |
>  			HOST_CTRL0_COMMONON_N |
> @@ -150,8 +146,32 @@ static void setup_usb_phy(struct exynos_usb_phy *usb)
>  			EHCICTRL_ENAINCR16);
>  }
>  
> -/* Reset the EHCI host controller. */
> -static void reset_usb_phy(struct exynos_usb_phy *usb)
> +static void exynos4412_setup_usb_phy(struct exynos4412_usb_phy *usb)
> +{
> +	writel(CLK_24MHZ, &usb->usbphyclk);
> +
> +	clrbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
> +		PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
> +		PHYPWR_NORMAL_MASK_PHY0));
> +
> +	setbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
> +	udelay(10);
> +	clrbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
> +}
> +
> +static void setup_usb_phy(struct exynos_usb_phy *usb)
> +{
> +	set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
> +
> +	set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
> +
> +	if (cpu_is_exynos5())
> +		exynos5_setup_usb_phy(usb);
> +	else if (proid_is_exynos4412())
> +		exynos4412_setup_usb_phy((struct exynos4412_usb_phy *)usb);
> +}
> +
> +static void exynos5_reset_usb_phy(struct exynos_usb_phy *usb)
>  {
>  	u32 hsic_ctrl;
>  
> @@ -171,6 +191,22 @@ static void reset_usb_phy(struct exynos_usb_phy *usb)
>  
>  	setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
>  	setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
> +}
> +
> +static void exynos4412_reset_usb_phy(struct exynos4412_usb_phy *usb)
> +{
> +	setbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
> +		PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
> +		PHYPWR_NORMAL_MASK_PHY0));
> +}
> +
> +/* Reset the EHCI host controller. */
> +static void reset_usb_phy(struct exynos_usb_phy *usb)
> +{
> +	if (cpu_is_exynos5())
> +		exynos5_reset_usb_phy(usb);
> +	else if (proid_is_exynos4412())
> +		exynos4412_reset_usb_phy((struct exynos4412_usb_phy *)usb);
>  
>  	set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE);
>  }
> diff --git a/include/configs/odroid.h b/include/configs/odroid.h
> index b616ac2..3fc0508 100644
> --- a/include/configs/odroid.h
> +++ b/include/configs/odroid.h
> @@ -200,6 +200,19 @@
>  
>  #define CONFIG_CMD_GPIO
>  
> +/* USB */
> +#define CONFIG_CMD_USB
> +#define CONFIG_USB_EHCI
> +#define CONFIG_USB_EHCI_EXYNOS
> +#define CONFIG_USB_STORAGE
> +
> +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	3
> +#define CONFIG_CMD_NET
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_USB_HOST_ETHER
> +#define CONFIG_USB_ETHER_SMSC95XX
> +
>  /*
>   * Supported Odroid boards: X3, U3
>   * TODO: Add Odroid X support
> 

[U-Boot] [PATCH v1 2/2] odroid: usb: add support for usb host including ethernet

[Suriyan Ramasami]

Hello Jaehoon,

On Fri, Oct 17, 2014 at 1:52 AM, Jaehoon Chung <jh80.chung@samsung.com> wrote:
> Hi, Suriyan.
>
> This patch can be separated.
>

OK, I shall separate out the power.c/power.h changes for enabling and
disabling the usbhost phy.

> On 10/02/2014 10:45 PM, Suriyan Ramasami wrote:
>> This change adds support for enabling the USB host features of the board.
>> This includes the USB3503A hub and the SMC LAN9730 ethernet controller
>> as well.
>>
>> Credit goes to Tushar Behera (Linaro) for the function set_usb_ethaddr().
>>
>> Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
>> ---
>>  arch/arm/cpu/armv7/exynos/power.c        | 26 +++++++++++++++
>>  arch/arm/dts/exynos4412-odroid.dts       | 11 +++++++
>>  arch/arm/include/asm/arch-exynos/cpu.h   |  2 ++
>>  arch/arm/include/asm/arch-exynos/ehci.h  | 13 ++++++++
>>  arch/arm/include/asm/arch-exynos/power.h |  7 ++++
>>  board/samsung/odroid/odroid.c            | 55 ++++++++++++++++++++++++++++++++
>>  drivers/usb/host/ehci-exynos.c           | 52 +++++++++++++++++++++++++-----
>>  include/configs/odroid.h                 | 13 ++++++++
>>  8 files changed, 171 insertions(+), 8 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c
>> index e1ab3d6..6578a07 100644
>> --- a/arch/arm/cpu/armv7/exynos/power.c
>> +++ b/arch/arm/cpu/armv7/exynos/power.c
>> @@ -53,10 +53,36 @@ void exynos5_set_usbhost_phy_ctrl(unsigned int enable)
>>       }
>>  }
>>
>> +void exynos4412_set_usbhost_phy_ctrl(unsigned int enable)
>> +{
>> +     struct exynos4412_power *power =
>> +             (struct exynos4412_power *)samsung_get_base_power();
>> +
>> +     if (enable) {
>> +             /* Enabling USBHOST_PHY */
>> +             setbits_le32(&power->usbhost_phy_control,
>> +                          POWER_USB_HOST_PHY_CTRL_EN);
>> +             setbits_le32(&power->hsic1_phy_control,
>> +                          POWER_USB_HOST_PHY_CTRL_EN);
>> +             setbits_le32(&power->hsic2_phy_control,
>> +                          POWER_USB_HOST_PHY_CTRL_EN);
>> +     } else {
>> +             /* Disabling USBHOST_PHY */
>> +             clrbits_le32(&power->usbhost_phy_control,
>> +                          POWER_USB_HOST_PHY_CTRL_EN);
>> +             clrbits_le32(&power->hsic1_phy_control,
>> +                          POWER_USB_HOST_PHY_CTRL_EN);
>> +             clrbits_le32(&power->hsic2_phy_control,
>> +                          POWER_USB_HOST_PHY_CTRL_EN);
>> +     }
>> +}
>> +
>>  void set_usbhost_phy_ctrl(unsigned int enable)
>>  {
>>       if (cpu_is_exynos5())
>>               exynos5_set_usbhost_phy_ctrl(enable);
>> +     else if (proid_is_exynos4412())
>> +             exynos4412_set_usbhost_phy_ctrl(enable);
>>  }
>>
>>  static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable)
>> diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts
>> index 24d0bf1..8da8568 100644
>> --- a/arch/arm/dts/exynos4412-odroid.dts
>> +++ b/arch/arm/dts/exynos4412-odroid.dts
>> @@ -67,4 +67,15 @@
>>               div = <0x3>;
>>               index = <4>;
>>       };
>> +
>> +        ehci at 12580000 {
>> +                compatible = "samsung,exynos-ehci";
>> +                reg = <0x12580000 0x100>;
>> +             #address-cells = <1>;
>> +             #size-cells = <1>;
>> +                phy {
>> +                        compatible = "samsung,exynos-usb-phy";
>> +                        reg = <0x125B0000 0x100>;
>> +                };
>> +        };
>
> Fix the indentation.
>

Shall do that.

Thanks
- Suriyan

> Best Regards,
> Jaehoon Chung
>
>>  };
>> diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
>> index ba71714..fda21fb 100644
>> --- a/arch/arm/include/asm/arch-exynos/cpu.h
>> +++ b/arch/arm/include/asm/arch-exynos/cpu.h
>> @@ -18,6 +18,8 @@
>>
>>  #define EXYNOS4_GPIO_PART3_BASE              0x03860000
>>  #define EXYNOS4_PRO_ID                       0x10000000
>> +#define EXYNOS4_GUID_LOW             0x10000014
>> +#define EXYNOS4_GUID_HIGH            0x10000018
>>  #define EXYNOS4_SYSREG_BASE          0x10010000
>>  #define EXYNOS4_POWER_BASE           0x10020000
>>  #define EXYNOS4_SWRESET                      0x10020400
>> diff --git a/arch/arm/include/asm/arch-exynos/ehci.h b/arch/arm/include/asm/arch-exynos/ehci.h
>> index d2d70bd..3800fa9 100644
>> --- a/arch/arm/include/asm/arch-exynos/ehci.h
>> +++ b/arch/arm/include/asm/arch-exynos/ehci.h
>> @@ -12,6 +12,13 @@
>>
>>  #define CLK_24MHZ            5
>>
>> +#define PHYPWR_NORMAL_MASK_PHY0                 (0x39 << 0)
>> +#define PHYPWR_NORMAL_MASK_PHY1                 (0x7 << 6)
>> +#define PHYPWR_NORMAL_MASK_HSIC0                (0x7 << 9)
>> +#define PHYPWR_NORMAL_MASK_HSIC1                (0x7 << 12)
>> +#define RSTCON_HOSTPHY_SWRST                    (0xf << 3)
>> +#define RSTCON_SWRST                            (0x1 << 0)
>> +
>>  #define HOST_CTRL0_PHYSWRSTALL                       (1 << 31)
>>  #define HOST_CTRL0_COMMONON_N                        (1 << 9)
>>  #define HOST_CTRL0_SIDDQ                     (1 << 6)
>> @@ -61,6 +68,12 @@ struct exynos_usb_phy {
>>       unsigned int usbotgtune;
>>  };
>>
>> +struct exynos4412_usb_phy {
>> +     unsigned int usbphyctrl;
>> +     unsigned int usbphyclk;
>> +     unsigned int usbphyrstcon;
>> +};
>> +
>>  /* Switch on the VBUS power. */
>>  int board_usb_vbus_init(void);
>>
>> diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h
>> index e8a98a5..3f97b31 100644
>> --- a/arch/arm/include/asm/arch-exynos/power.h
>> +++ b/arch/arm/include/asm/arch-exynos/power.h
>> @@ -210,6 +210,13 @@ struct exynos4_power {
>>       unsigned int    gps_alive_option;
>>  };
>>
>> +struct exynos4412_power {
>> +     unsigned char   res1[0x0704];
>> +     unsigned int    usbhost_phy_control;
>> +     unsigned int    hsic1_phy_control;
>> +     unsigned int    hsic2_phy_control;
>> +};
>> +
>>  struct exynos5_power {
>>       unsigned int    om_stat;
>>       unsigned char   res1[0x18];
>> diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c
>> index fd5d2d2..4764a71 100644
>> --- a/board/samsung/odroid/odroid.c
>> +++ b/board/samsung/odroid/odroid.c
>> @@ -453,9 +453,64 @@ struct s3c_plat_otg_data s5pc210_otg_data = {
>>       .usb_phy_ctrl   = EXYNOS4X12_USBPHY_CONTROL,
>>       .usb_flags      = PHY0_SLEEP,
>>  };
>> +#endif
>> +
>> +#if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB)
>> +
>> +#ifdef CONFIG_CMD_USB
>> +static void set_usb_ethaddr(void)
>> +{
>> +     int i;
>> +     uchar mac[6];
>> +     unsigned int guid_high = readl(EXYNOS4_GUID_HIGH);
>> +     unsigned int guid_low = readl(EXYNOS4_GUID_LOW);
>> +
>> +     for (i = 0; i < 2; i++)
>> +             mac[i] = (guid_high >> (8 * (1 - i))) & 0xFF;
>> +
>> +     for (i = 0; i < 4; i++)
>> +             mac[i+2] = (guid_low >> (8 * (3 - i))) & 0xFF;
>> +
>> +     /* mark it as not multicast and outside official 80211 MAC namespace */
>> +     mac[0] = (mac[0] & ~0x1) | 0x2;
>> +
>> +     eth_setenv_enetaddr("ethaddr", mac);
>> +     eth_setenv_enetaddr("usbethaddr", mac);
>> +}
>> +#endif
>>
>>  int board_usb_init(int index, enum usb_init_type init)
>>  {
>> +#ifdef CONFIG_CMD_USB
>> +     struct pmic *p_pmic;
>> +
>> +     /* Set Ref freq 0 => 24MHz, 1 => 26MHz*/
>> +     /* Odroid Us have it at 24MHz, Odroid Xs at 26MHz */
>> +     if (gd->board_type == ODROID_TYPE_U3)
>> +             gpio_direction_output(EXYNOS4X12_GPIO_X30, 0);
>> +     else
>> +             gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
>> +
>> +     /* Disconnect, Reset, Connect */
>> +     gpio_direction_output(EXYNOS4X12_GPIO_X34, 0);
>> +     gpio_direction_output(EXYNOS4X12_GPIO_X35, 0);
>> +     gpio_direction_output(EXYNOS4X12_GPIO_X35, 1);
>> +     gpio_direction_output(EXYNOS4X12_GPIO_X34, 1);
>> +
>> +     /* Power off and on BUCK8 for LAN9730 */
>> +     debug("LAN9730 - Turning power buck 8 OFF and ON.\n");
>> +
>> +     p_pmic = pmic_get("MAX77686_PMIC");
>> +     if (p_pmic && !pmic_probe(p_pmic)) {
>> +             max77686_set_buck_mode(p_pmic, 8, OPMODE_OFF);
>> +             max77686_set_buck_voltage(p_pmic, 8, 750000);
>> +             max77686_set_buck_voltage(p_pmic, 8, 3300000);
>> +             max77686_set_buck_mode(p_pmic, 8, OPMODE_ON);
>> +     }
>> +
>> +     set_usb_ethaddr();
>> +#endif
>> +
>>       debug("USB_udc_probe\n");
>>       return s3c_udc_probe(&s5pc210_otg_data);
>>  }
>> diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
>> index edd91a8..91f3c72 100644
>> --- a/drivers/usb/host/ehci-exynos.c
>> +++ b/drivers/usb/host/ehci-exynos.c
>> @@ -19,6 +19,7 @@
>>  #include <asm/gpio.h>
>>  #include <asm-generic/errno.h>
>>  #include <linux/compat.h>
>> +#include <power/max77686_pmic.h>
>>  #include "ehci.h"
>>
>>  /* Declare global data pointer */
>> @@ -85,15 +86,10 @@ static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos)
>>  }
>>  #endif
>>
>> -/* Setup the EHCI host controller. */
>> -static void setup_usb_phy(struct exynos_usb_phy *usb)
>> +static void exynos5_setup_usb_phy(struct exynos_usb_phy *usb)
>>  {
>>       u32 hsic_ctrl;
>>
>> -     set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
>> -
>> -     set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
>> -
>>       clrbits_le32(&usb->usbphyctrl0,
>>                       HOST_CTRL0_FSEL_MASK |
>>                       HOST_CTRL0_COMMONON_N |
>> @@ -150,8 +146,32 @@ static void setup_usb_phy(struct exynos_usb_phy *usb)
>>                       EHCICTRL_ENAINCR16);
>>  }
>>
>> -/* Reset the EHCI host controller. */
>> -static void reset_usb_phy(struct exynos_usb_phy *usb)
>> +static void exynos4412_setup_usb_phy(struct exynos4412_usb_phy *usb)
>> +{
>> +     writel(CLK_24MHZ, &usb->usbphyclk);
>> +
>> +     clrbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
>> +             PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
>> +             PHYPWR_NORMAL_MASK_PHY0));
>> +
>> +     setbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
>> +     udelay(10);
>> +     clrbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
>> +}
>> +
>> +static void setup_usb_phy(struct exynos_usb_phy *usb)
>> +{
>> +     set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
>> +
>> +     set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
>> +
>> +     if (cpu_is_exynos5())
>> +             exynos5_setup_usb_phy(usb);
>> +     else if (proid_is_exynos4412())
>> +             exynos4412_setup_usb_phy((struct exynos4412_usb_phy *)usb);
>> +}
>> +
>> +static void exynos5_reset_usb_phy(struct exynos_usb_phy *usb)
>>  {
>>       u32 hsic_ctrl;
>>
>> @@ -171,6 +191,22 @@ static void reset_usb_phy(struct exynos_usb_phy *usb)
>>
>>       setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
>>       setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
>> +}
>> +
>> +static void exynos4412_reset_usb_phy(struct exynos4412_usb_phy *usb)
>> +{
>> +     setbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
>> +             PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
>> +             PHYPWR_NORMAL_MASK_PHY0));
>> +}
>> +
>> +/* Reset the EHCI host controller. */
>> +static void reset_usb_phy(struct exynos_usb_phy *usb)
>> +{
>> +     if (cpu_is_exynos5())
>> +             exynos5_reset_usb_phy(usb);
>> +     else if (proid_is_exynos4412())
>> +             exynos4412_reset_usb_phy((struct exynos4412_usb_phy *)usb);
>>
>>       set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE);
>>  }
>> diff --git a/include/configs/odroid.h b/include/configs/odroid.h
>> index b616ac2..3fc0508 100644
>> --- a/include/configs/odroid.h
>> +++ b/include/configs/odroid.h
>> @@ -200,6 +200,19 @@
>>
>>  #define CONFIG_CMD_GPIO
>>
>> +/* USB */
>> +#define CONFIG_CMD_USB
>> +#define CONFIG_USB_EHCI
>> +#define CONFIG_USB_EHCI_EXYNOS
>> +#define CONFIG_USB_STORAGE
>> +
>> +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS   3
>> +#define CONFIG_CMD_NET
>> +#define CONFIG_CMD_PING
>> +#define CONFIG_CMD_DHCP
>> +#define CONFIG_USB_HOST_ETHER
>> +#define CONFIG_USB_ETHER_SMSC95XX
>> +
>>  /*
>>   * Supported Odroid boards: X3, U3
>>   * TODO: Add Odroid X support
>>
>