Cache flush questions of Intel IOMMU

Cache flush questions of Intel IOMMU

[Kai Huang]

Hi all,

I am working on Intel iommu staff and I have two questions -- just
send to kvm list as I am not sure which mail list should I send to,
and it will be very appreciated if you could help to forward to
related mail list. Thank you!

1) I see in Intel iommu's manual, caching behavior is reported by CM
bit in Capability register and Coherency bit in Extended register. My
question is from hardware's point of view, in case of CM=0, when some
specific address mapping changed (ex, set up new mapping, modify or
free existing mapping), do we need to flush IOTLB cache for that
address range, considering both C bit is 0 and 1? I guess if C=0, we
need to flush, and if C=1, we don't have to, right? And I guess this
should also be true for context cache?

Cache Mode bit in Capability register:

    0: Not-present and erroneous entries are
    not cached in any of the remapping caches.
    Invalidations are not required for
    modifications to individual not present or
    invalid entries. However, any modifications
    that result in decreasing the effective
    permissions or partial permission increases
    require invalidations for them to be
    effective.

    1: Not-present and erroneous mappings
    may be cached in the remapping caches.
    Any software updates to the remapping
    structures (including updates to “not-
    present” or erroneous entries) require
    explicit invalidation

Coherency bit in Extended Capability register:

    This field indicates if hardware access to the
    root, context, page-table and interrupt-
    remap structures are coherent (snooped) or
    not.
    • 0:Indicates hardware accesses to
      remapping structures are non-coherent.
    • 1:Indicates hardware accesses to
      remapping structures are coherent.

2) I see in domain_flush_cache, when !domain->iommu_coherency
(actually it is the Coherency bit in Extended Capability register),
clflush_cache_range is called, but the clflush is used to flush cache
in CPU, not in IOMMU, why flush CPU cache, not IOMMU cache here?

static int domain_init(struct dmar_domain *domain, int guest_width)
{
        ....
        if (ecap_coherent(iommu->ecap))
                domain->iommu_coherency = 1;
        else
                domain->iommu_coherency = 0;
        ...
}

static void domain_flush_cache(struct dmar_domain *domain,
                               void *addr, int size)
{
        if (!domain->iommu_coherency)
                clflush_cache_range(addr, size);
}

Thanks,
Cody