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* [U-Boot] [PATCH] drivers: net: cpsw: always flush cache with cache line aligned
@ 2016-08-08  6:22 Lokesh Vutla
  2016-08-08 16:46 ` Joe Hershberger
  0 siblings, 1 reply; 3+ messages in thread
From: Lokesh Vutla @ 2016-08-08  6:22 UTC (permalink / raw)
  To: u-boot

cpsw tries to flush dcache which is not in the range of cache line size.
Because of this the following warning comes while flushing:

CACHE: Misaligned operation at range [dffecec0, dffed016]

Fix it by flushing cache range which is cache line size aligned.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 drivers/net/cpsw.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index 2ce4ec6..631544a 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -905,9 +905,14 @@ static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length)
 	void *buffer;
 	int len;
 	int timeout = CPDMA_TIMEOUT;
+	unsigned long pstart, pend;
 
-	flush_dcache_range((unsigned long)packet,
-			   (unsigned long)packet + length);
+	/*
+	 *  Make sure range is cache line aligned.
+	 */
+	pstart = (unsigned long)packet & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+	pend = ALIGN((unsigned long)packet + length, CONFIG_SYS_CACHELINE_SIZE);
+	flush_dcache_range(pstart, pend);
 
 	/* first reap completed packets */
 	while (timeout-- &&
-- 
2.9.2

^ permalink raw reply related	[flat|nested] 3+ messages in thread

* [U-Boot] [PATCH] drivers: net: cpsw: always flush cache with cache line aligned
  2016-08-08  6:22 [U-Boot] [PATCH] drivers: net: cpsw: always flush cache with cache line aligned Lokesh Vutla
@ 2016-08-08 16:46 ` Joe Hershberger
  2016-08-09  5:48   ` Lokesh Vutla
  0 siblings, 1 reply; 3+ messages in thread
From: Joe Hershberger @ 2016-08-08 16:46 UTC (permalink / raw)
  To: u-boot

Hi Lokesh,

On Mon, Aug 8, 2016 at 1:22 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
> cpsw tries to flush dcache which is not in the range of cache line size.
> Because of this the following warning comes while flushing:
>
> CACHE: Misaligned operation at range [dffecec0, dffed016]
>
> Fix it by flushing cache range which is cache line size aligned.

This is the send case... the transmit packet buffer from the network
subsystem is already aligned. You only need to align the size of the
packet. Also, please use PKTALIGN.

Thanks,
-Joe

^ permalink raw reply	[flat|nested] 3+ messages in thread

* [U-Boot] [PATCH] drivers: net: cpsw: always flush cache with cache line aligned
  2016-08-08 16:46 ` Joe Hershberger
@ 2016-08-09  5:48   ` Lokesh Vutla
  0 siblings, 0 replies; 3+ messages in thread
From: Lokesh Vutla @ 2016-08-09  5:48 UTC (permalink / raw)
  To: u-boot



On Monday 08 August 2016 10:16 PM, Joe Hershberger wrote:
> Hi Lokesh,
> 
> On Mon, Aug 8, 2016 at 1:22 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
>> cpsw tries to flush dcache which is not in the range of cache line size.
>> Because of this the following warning comes while flushing:
>>
>> CACHE: Misaligned operation at range [dffecec0, dffed016]
>>
>> Fix it by flushing cache range which is cache line size aligned.
> 
> This is the send case... the transmit packet buffer from the network
> subsystem is already aligned. You only need to align the size of the
> packet. Also, please use PKTALIGN.

You are right. Just posted a patch addressing your comments.

Thanks and regards,
Lokesh

> 
> Thanks,
> -Joe
> 

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2016-08-09  5:48 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2016-08-08  6:22 [U-Boot] [PATCH] drivers: net: cpsw: always flush cache with cache line aligned Lokesh Vutla
2016-08-08 16:46 ` Joe Hershberger
2016-08-09  5:48   ` Lokesh Vutla

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