[PATCH] ARM: dts: imx51: add CodaHx4 VPU

[PATCH] ARM: dts: imx51: add CodaHx4 VPU

[Philipp Zabel]

Add the CodaHx4 VPU to the i.MX51 device tree.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
This patch should only be applied once the patch to fix VPU register access on
i.MX51 [1] is merged. The coda driver with patches [2] applied will start
accessing VPU registers on i.MX51, which hangs the system without [1].

[1] https://patchwork.kernel.org/patch/10109781/
    ("clk: imx51: uart4, uart5 gates only exist on imx50, imx53")
[2] https://patchwork.linuxtv.org/patch/45929/
    ("media: dt-bindings: coda: Add compatible for CodaHx4 on i.MX51")
    https://patchwork.linuxtv.org/patch/45930/
    ("media: coda: Add i.MX51 (CodaHx4) support")
---
 arch/arm/boot/dts/imx51.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 378be720b3c76..6d6c19ede2be0 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -597,6 +597,17 @@
 				clock-names = "ipg", "ahb", "ptp";
 				status = "disabled";
 			};
+
+			vpu at 83ff4000 {
+				compatible = "fsl,imx51-vpu", "cnm,codahx4";
+				reg = <0x83ff4000 0x1000>;
+				interrupts = <9>;
+				clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
+					 <&clks IMX5_CLK_VPU_GATE>;
+				clock-names = "per", "ahb";
+				resets = <&src 1>;
+				iram = <&iram>;
+			};
 		};
 	};
 };
-- 
2.11.0

[PATCH] ARM: dts: imx51: add CodaHx4 VPU

[Shawn Guo]

On Wed, Dec 13, 2017 at 03:24:06PM +0100, Philipp Zabel wrote:
> Add the CodaHx4 VPU to the i.MX51 device tree.
> 
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> ---
> This patch should only be applied once the patch to fix VPU register access on
> i.MX51 [1] is merged. The coda driver with patches [2] applied will start
> accessing VPU registers on i.MX51, which hangs the system without [1].

Ping me when it can be safely applied on IMX tree.

Shawn

[PATCH] ARM: dts: imx51: add CodaHx4 VPU

[Philipp Zabel]

Hi Shawn,

On Tue, 2017-12-26 at 12:15 +0800, Shawn Guo wrote:
> On Wed, Dec 13, 2017 at 03:24:06PM +0100, Philipp Zabel wrote:
> > Add the CodaHx4 VPU to the i.MX51 device tree.
> > 
> > Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> > ---
> > This patch should only be applied once the patch to fix VPU register access on
> > i.MX51 [1] is merged. The coda driver with patches [2] applied will start
> > accessing VPU registers on i.MX51, which hangs the system without [1].
> 
> Ping me when it can be safely applied on IMX tree.

I forgot about this between the years, this patch is safe to be applied.

regards
Philipp

[PATCH] ARM: dts: imx51: add CodaHx4 VPU

[Fabio Estevam]

Hi Philipp,

On Thu, Jun 21, 2018 at 4:54 PM, Philipp Zabel <p.zabel@pengutronix.de> wrote:

> I forgot about this between the years, this patch is safe to be applied.

In order to get the internal RAM to be functional, I think we also
need to pass the IRAM clock in the iram node:

  iram: iram at 1ffe0000 {
      compatible = "mmio-sram";
      reg = <0x1ffe0000 0x20000>;
  +  clocks = <&clks IMX5_CLK_OCRAM>;
  };

Thanks

[PATCH] ARM: dts: imx51: add CodaHx4 VPU

[Philipp Zabel]

Hi Fabio,

On Thu, 2018-06-21 at 17:01 -0300, Fabio Estevam wrote:
> Hi Philipp,
> 
> On Thu, Jun 21, 2018 at 4:54 PM, Philipp Zabel <p.zabel@pengutronix.de> wrote:
> 
> > I forgot about this between the years, this patch is safe to be applied.
> 
> In order to get the internal RAM to be functional, I think we also
> need to pass the IRAM clock in the iram node:
> 
>   iram: iram at 1ffe0000 {
>       compatible = "mmio-sram";
>       reg = <0x1ffe0000 0x20000>;
>   +  clocks = <&clks IMX5_CLK_OCRAM>;
>   };
> 
> Thanks

I think i.MX51 doesn't have that clock gate:

????????clk[IMX5_CLK_OCRAM]?????????????= imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2);

is added for i.MX53 only. CCGR6 CG1 (bits 3:2) is documented as
"no longer supported, should be cleared" in the i.MX51 reference
manual. I can't find any mention of a gate for the SCC RAM.

regards
Philipp

[PATCH] ARM: dts: imx51: add CodaHx4 VPU

[Fabio Estevam]

Hi Philipp,

On Fri, Jun 22, 2018 at 6:43 AM, Philipp Zabel <p.zabel@pengutronix.de> wrote:

> I think i.MX51 doesn't have that clock gate:
>
>         clk[IMX5_CLK_OCRAM]             = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2);
>
> is added for i.MX53 only. CCGR6 CG1 (bits 3:2) is documented as
> "no longer supported, should be cleared" in the i.MX51 reference
> manual. I can't find any mention of a gate for the SCC RAM.

That's true. This gate is only present on i.MX53, so:

Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

Thanks for the clarification

[PATCH] ARM: dts: imx51: add CodaHx4 VPU

[Shawn Guo]

On Wed, Dec 13, 2017 at 03:24:06PM +0100, Philipp Zabel wrote:
> Add the CodaHx4 VPU to the i.MX51 device tree.
> 
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

Applied, thanks.