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* [PATCH] irqchip: gic-v3-its: fix entry size mask for GITS_BASER
@ 2016-10-17 15:00 ` Vladimir Murzin
  0 siblings, 0 replies; 6+ messages in thread
From: Vladimir Murzin @ 2016-10-17 15:00 UTC (permalink / raw)
  To: linux-kernel; +Cc: linux-arm-kernel, marc.zyngier

Entry Size in GITS_BASER<n> occupies 5 bits [52:48], but we mask out 8
bits.

Fixes: cc2d3216f53c ("irqchip: GICv3: ITS command queue")

Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
 include/linux/irqchip/arm-gic-v3.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 7dec96f..5118d3a 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -290,7 +290,7 @@
 #define GITS_BASER_TYPE_SHIFT			(56)
 #define GITS_BASER_TYPE(r)		(((r) >> GITS_BASER_TYPE_SHIFT) & 7)
 #define GITS_BASER_ENTRY_SIZE_SHIFT		(48)
-#define GITS_BASER_ENTRY_SIZE(r)	((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0xff) + 1)
+#define GITS_BASER_ENTRY_SIZE(r)	((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
 #define GITS_BASER_SHAREABILITY_SHIFT	(10)
 #define GITS_BASER_InnerShareable					\
 	GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [PATCH] irqchip: gic-v3-its: fix entry size mask for GITS_BASER
@ 2016-10-17 15:00 ` Vladimir Murzin
  0 siblings, 0 replies; 6+ messages in thread
From: Vladimir Murzin @ 2016-10-17 15:00 UTC (permalink / raw)
  To: linux-arm-kernel

Entry Size in GITS_BASER<n> occupies 5 bits [52:48], but we mask out 8
bits.

Fixes: cc2d3216f53c ("irqchip: GICv3: ITS command queue")

Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
 include/linux/irqchip/arm-gic-v3.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 7dec96f..5118d3a 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -290,7 +290,7 @@
 #define GITS_BASER_TYPE_SHIFT			(56)
 #define GITS_BASER_TYPE(r)		(((r) >> GITS_BASER_TYPE_SHIFT) & 7)
 #define GITS_BASER_ENTRY_SIZE_SHIFT		(48)
-#define GITS_BASER_ENTRY_SIZE(r)	((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0xff) + 1)
+#define GITS_BASER_ENTRY_SIZE(r)	((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
 #define GITS_BASER_SHAREABILITY_SHIFT	(10)
 #define GITS_BASER_InnerShareable					\
 	GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 6+ messages in thread

* Re: [PATCH] irqchip: gic-v3-its: fix entry size mask for GITS_BASER
  2016-10-17 15:00 ` Vladimir Murzin
@ 2016-10-17 15:07   ` Marc Zyngier
  -1 siblings, 0 replies; 6+ messages in thread
From: Marc Zyngier @ 2016-10-17 15:07 UTC (permalink / raw)
  To: Vladimir Murzin, linux-kernel; +Cc: linux-arm-kernel

On 17/10/16 16:00, Vladimir Murzin wrote:
> Entry Size in GITS_BASER<n> occupies 5 bits [52:48], but we mask out 8
> bits.
> 
> Fixes: cc2d3216f53c ("irqchip: GICv3: ITS command queue")
> 
> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
> ---
>  include/linux/irqchip/arm-gic-v3.h |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
> index 7dec96f..5118d3a 100644
> --- a/include/linux/irqchip/arm-gic-v3.h
> +++ b/include/linux/irqchip/arm-gic-v3.h
> @@ -290,7 +290,7 @@
>  #define GITS_BASER_TYPE_SHIFT			(56)
>  #define GITS_BASER_TYPE(r)		(((r) >> GITS_BASER_TYPE_SHIFT) & 7)
>  #define GITS_BASER_ENTRY_SIZE_SHIFT		(48)
> -#define GITS_BASER_ENTRY_SIZE(r)	((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0xff) + 1)
> +#define GITS_BASER_ENTRY_SIZE(r)	((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
>  #define GITS_BASER_SHAREABILITY_SHIFT	(10)
>  #define GITS_BASER_InnerShareable					\
>  	GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
> 

Nice catch. I'll queue that in my fix branch (and add a Cc to stable,
since this is a 2 year old bug...).

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH] irqchip: gic-v3-its: fix entry size mask for GITS_BASER
@ 2016-10-17 15:07   ` Marc Zyngier
  0 siblings, 0 replies; 6+ messages in thread
From: Marc Zyngier @ 2016-10-17 15:07 UTC (permalink / raw)
  To: linux-arm-kernel

On 17/10/16 16:00, Vladimir Murzin wrote:
> Entry Size in GITS_BASER<n> occupies 5 bits [52:48], but we mask out 8
> bits.
> 
> Fixes: cc2d3216f53c ("irqchip: GICv3: ITS command queue")
> 
> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
> ---
>  include/linux/irqchip/arm-gic-v3.h |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
> index 7dec96f..5118d3a 100644
> --- a/include/linux/irqchip/arm-gic-v3.h
> +++ b/include/linux/irqchip/arm-gic-v3.h
> @@ -290,7 +290,7 @@
>  #define GITS_BASER_TYPE_SHIFT			(56)
>  #define GITS_BASER_TYPE(r)		(((r) >> GITS_BASER_TYPE_SHIFT) & 7)
>  #define GITS_BASER_ENTRY_SIZE_SHIFT		(48)
> -#define GITS_BASER_ENTRY_SIZE(r)	((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0xff) + 1)
> +#define GITS_BASER_ENTRY_SIZE(r)	((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
>  #define GITS_BASER_SHAREABILITY_SHIFT	(10)
>  #define GITS_BASER_InnerShareable					\
>  	GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
> 

Nice catch. I'll queue that in my fix branch (and add a Cc to stable,
since this is a 2 year old bug...).

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH] irqchip: gic-v3-its: fix entry size mask for GITS_BASER
  2016-10-17 15:00 ` Vladimir Murzin
@ 2016-10-17 15:11   ` Fabio Estevam
  -1 siblings, 0 replies; 6+ messages in thread
From: Fabio Estevam @ 2016-10-17 15:11 UTC (permalink / raw)
  To: Vladimir Murzin; +Cc: linux-kernel, Marc Zyngier, linux-arm-kernel

On Mon, Oct 17, 2016 at 1:00 PM, Vladimir Murzin
<vladimir.murzin@arm.com> wrote:
> Entry Size in GITS_BASER<n> occupies 5 bits [52:48], but we mask out 8
> bits.
>
> Fixes: cc2d3216f53c ("irqchip: GICv3: ITS command queue")

Looks like it needs the following tag then:

Cc: <stable@vger.kernel.org> # 3.19+

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH] irqchip: gic-v3-its: fix entry size mask for GITS_BASER
@ 2016-10-17 15:11   ` Fabio Estevam
  0 siblings, 0 replies; 6+ messages in thread
From: Fabio Estevam @ 2016-10-17 15:11 UTC (permalink / raw)
  To: linux-arm-kernel

On Mon, Oct 17, 2016 at 1:00 PM, Vladimir Murzin
<vladimir.murzin@arm.com> wrote:
> Entry Size in GITS_BASER<n> occupies 5 bits [52:48], but we mask out 8
> bits.
>
> Fixes: cc2d3216f53c ("irqchip: GICv3: ITS command queue")

Looks like it needs the following tag then:

Cc: <stable@vger.kernel.org> # 3.19+

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2016-10-17 15:11 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-10-17 15:00 [PATCH] irqchip: gic-v3-its: fix entry size mask for GITS_BASER Vladimir Murzin
2016-10-17 15:00 ` Vladimir Murzin
2016-10-17 15:07 ` Marc Zyngier
2016-10-17 15:07   ` Marc Zyngier
2016-10-17 15:11 ` Fabio Estevam
2016-10-17 15:11   ` Fabio Estevam

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