[U-Boot] [PATCH 1/2] imx: imx6sx-sdb: Enable DM QSPI driver

[U-Boot] [PATCH 1/2] imx: imx6sx-sdb: Enable DM QSPI driver

[Ye Li]

To support DM QSPI driver
 - Add spi0 and spi1 alias for qspi1 and qspi2.
 - Modify n25q256a at 0 and n25q256a at 1 compatible string to "spi-flash"
 - Enable DM SPI/QSPI relavent configurations
 - Remove iomux settings of qspi2 in board codes which is not needed
   for DM driver.
 - Add sf default settings. So running "sf probe" can detect the flash

Signed-off-by: Ye Li <ye.li@nxp.com>
---
 arch/arm/dts/imx6sx-sdb.dts                 |  4 ++--
 arch/arm/dts/imx6sx.dtsi                    | 12 +++++++-----
 board/freescale/mx6sxsabresd/mx6sxsabresd.c | 25 -------------------------
 configs/mx6sxsabresd_defconfig              |  7 +++++++
 include/configs/mx6sxsabresd.h              |  4 ++++
 5 files changed, 20 insertions(+), 32 deletions(-)

diff --git a/arch/arm/dts/imx6sx-sdb.dts b/arch/arm/dts/imx6sx-sdb.dts
index 6dd9beb..a04b00d 100644
--- a/arch/arm/dts/imx6sx-sdb.dts
+++ b/arch/arm/dts/imx6sx-sdb.dts
@@ -115,7 +115,7 @@
 	flash0: n25q256a at 0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "micron,n25q256a", "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <29000000>;
 		reg = <0>;
 	};
@@ -123,7 +123,7 @@
 	flash1: n25q256a at 1 {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "micron,n25q256a", "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <29000000>;
 		reg = <1>;
 	};
diff --git a/arch/arm/dts/imx6sx.dtsi b/arch/arm/dts/imx6sx.dtsi
index 1a473e8..8ccf264 100644
--- a/arch/arm/dts/imx6sx.dtsi
+++ b/arch/arm/dts/imx6sx.dtsi
@@ -40,11 +40,13 @@
 		serial3 = &uart4;
 		serial4 = &uart5;
 		serial5 = &uart6;
-		spi0 = &ecspi1;
-		spi1 = &ecspi2;
-		spi2 = &ecspi3;
-		spi3 = &ecspi4;
-		spi4 = &ecspi5;
+		spi0 = &qspi1;
+		spi1 = &qspi2;
+		spi2 = &ecspi1;
+		spi3 = &ecspi2;
+		spi4 = &ecspi3;
+		spi5 = &ecspi4;
+		spi6 = &ecspi5;
 		usbphy0 = &usbphy1;
 		usbphy1 = &usbphy2;
 	};
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index d56e235..3e10c7f 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -205,33 +205,8 @@ int board_mmc_get_env_dev(int devno)
 
 #ifdef CONFIG_FSL_QSPI
 
-#define QSPI_PAD_CTRL1	\
-	(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
-	 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
-
-static iomux_v3_cfg_t const quadspi_pads[] = {
-	MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_ALE__QSPI2_A_SS0_B		| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_CLE__QSPI2_A_SCLK		| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_DATA07__QSPI2_A_DQS	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_DATA02__QSPI2_B_SCLK	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_DATA05__QSPI2_B_DQS	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-};
-
 int board_qspi_init(void)
 {
-	/* Set the iomux */
-	imx_iomux_v3_setup_multiple_pads(quadspi_pads,
-					 ARRAY_SIZE(quadspi_pads));
-
 	/* Set the clock */
 	enable_qspi_clk(1);
 
diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig
index 6ea92bb..9e4b13b 100644
--- a/configs/mx6sxsabresd_defconfig
+++ b/configs/mx6sxsabresd_defconfig
@@ -14,6 +14,7 @@ CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_SF=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PART=y
 CONFIG_CMD_PCI=y
@@ -36,8 +37,14 @@ CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_FSL_QSPI=y
 CONFIG_PHYLIB=y
 CONFIG_PCI=y
 CONFIG_PINCTRL=y
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index f5ca2fc..4506acb 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -186,6 +186,10 @@
 #define FSL_QSPI_FLASH_SIZE		SZ_32M
 #endif
 #define FSL_QSPI_FLASH_NUM		2
+#define CONFIG_SF_DEFAULT_BUS		1
+#define CONFIG_SF_DEFAULT_CS		0
+#define CONFIG_SF_DEFAULT_SPEED	40000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #endif
 
 #ifndef CONFIG_SPL_BUILD
-- 
2.7.4

[U-Boot] [PATCH 2/2] imx: imx6sx-sabreauto: convert to use DM QSPI driver

[Ye Li]

To support DM QSPI driver:
 - Modify n25q256a at 0 and n25q256a at 1 compatible string to "spi-flash"
 - Enable DM SPI and DM SPI FLASH configurations
 - Remove iomux settings of qspi1 in board codes which is not needed
   for DM driver.

Signed-off-by: Ye Li <ye.li@nxp.com>
---
 arch/arm/dts/imx6sx-sabreauto.dts               | 40 +++++++++++++++++++++++++
 board/freescale/mx6sxsabreauto/mx6sxsabreauto.c | 24 ---------------
 configs/mx6sxsabreauto_defconfig                |  2 ++
 3 files changed, 42 insertions(+), 24 deletions(-)

diff --git a/arch/arm/dts/imx6sx-sabreauto.dts b/arch/arm/dts/imx6sx-sabreauto.dts
index a4c2627..ee5c349 100644
--- a/arch/arm/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/dts/imx6sx-sabreauto.dts
@@ -96,6 +96,29 @@
 	};
 };
 
+&qspi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi1_1>;
+	status = "okay";
+	ddrsmp=<2>;
+
+	flash0: n25q256a at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <29000000>;
+		reg = <0>;
+	};
+
+	flash1: n25q256a at 1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <29000000>;
+		reg = <1>;
+	};
+};
+
 &iomuxc {
 	imx6x-sabreauto {
 		pinctrl_i2c2_1: i2c2grp-1 {
@@ -112,6 +135,23 @@
 			>;
 		};
 
+		pinctrl_qspi1_1: qspi1grp_1 {
+			fsl,pins = <
+				MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0  0x70a1
+				MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1  0x70a1
+				MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2  0x70a1
+				MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3  0x70a1
+				MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK     0x70a1
+				MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B   0x70a1
+				MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0  0x70a1
+				MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1  0x70a1
+				MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2  0x70a1
+				MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3  0x70a1
+				MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK     0x70a1
+				MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B   0x70a1
+			>;
+		};
+
 		pinctrl_uart1: uart1grp {
 			fsl,pins = <
 				MX6SX_PAD_GPIO1_IO04__UART1_TX		0x1b0b1
diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
index 975af2c..6e606da 100644
--- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
+++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
@@ -218,32 +218,8 @@ int board_early_init_f(void)
 }
 
 #ifdef CONFIG_FSL_QSPI
-
-#define QSPI_PAD_CTRL1	\
-	(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
-	 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
-
-static iomux_v3_cfg_t const quadspi_pads[] = {
-	MX6_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_QSPI1A_SCLK__QSPI1_A_SCLK     | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_QSPI1B_SCLK__QSPI1_B_SCLK     | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-};
-
 int board_qspi_init(void)
 {
-	/* Set the iomux */
-	imx_iomux_v3_setup_multiple_pads(quadspi_pads,
-					 ARRAY_SIZE(quadspi_pads));
-
 	/* Set the clock */
 	enable_qspi_clk(0);
 
diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig
index be95cc0..d7941e8 100644
--- a/configs/mx6sxsabreauto_defconfig
+++ b/configs/mx6sxsabreauto_defconfig
@@ -35,6 +35,8 @@ CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_STMICRO=y
-- 
2.7.4

[U-Boot] [PATCH 1/2] imx: imx6sx-sdb: Enable DM QSPI driver

[Fabio Estevam]

Hi Ye Li,

On Wed, Jun 27, 2018 at 3:48 AM, Ye Li <ye.li@nxp.com> wrote:
> To support DM QSPI driver
>  - Add spi0 and spi1 alias for qspi1 and qspi2.
>  - Modify n25q256a at 0 and n25q256a at 1 compatible string to "spi-flash"
>  - Enable DM SPI/QSPI relavent configurations
>  - Remove iomux settings of qspi2 in board codes which is not needed
>    for DM driver.
>  - Add sf default settings. So running "sf probe" can detect the flash
>
> Signed-off-by: Ye Li <ye.li@nxp.com>
> ---
>  arch/arm/dts/imx6sx-sdb.dts                 |  4 ++--
>  arch/arm/dts/imx6sx.dtsi                    | 12 +++++++-----
>  board/freescale/mx6sxsabresd/mx6sxsabresd.c | 25 -------------------------
>  configs/mx6sxsabresd_defconfig              |  7 +++++++
>  include/configs/mx6sxsabresd.h              |  4 ++++
>  5 files changed, 20 insertions(+), 32 deletions(-)
>
> diff --git a/arch/arm/dts/imx6sx-sdb.dts b/arch/arm/dts/imx6sx-sdb.dts
> index 6dd9beb..a04b00d 100644
> --- a/arch/arm/dts/imx6sx-sdb.dts
> +++ b/arch/arm/dts/imx6sx-sdb.dts
> @@ -115,7 +115,7 @@
>         flash0: n25q256a at 0 {
>                 #address-cells = <1>;
>                 #size-cells = <1>;
> -               compatible = "micron,n25q256a", "jedec,spi-nor";
> +               compatible = "spi-flash";

I don't see "spi-flash" compatible documented in the kernel bindings.

Please clarify why we are deviating from Linux here.

Thanks

[U-Boot] [PATCH 1/2] imx: imx6sx-sdb: Enable DM QSPI driver

[Jagan Teki]

On Wed, Jun 27, 2018 at 3:29 PM, Fabio Estevam <festevam@gmail.com> wrote:
> Hi Ye Li,
>
> On Wed, Jun 27, 2018 at 3:48 AM, Ye Li <ye.li@nxp.com> wrote:
>> To support DM QSPI driver
>>  - Add spi0 and spi1 alias for qspi1 and qspi2.
>>  - Modify n25q256a at 0 and n25q256a at 1 compatible string to "spi-flash"
>>  - Enable DM SPI/QSPI relavent configurations
>>  - Remove iomux settings of qspi2 in board codes which is not needed
>>    for DM driver.
>>  - Add sf default settings. So running "sf probe" can detect the flash
>>
>> Signed-off-by: Ye Li <ye.li@nxp.com>
>> ---
>>  arch/arm/dts/imx6sx-sdb.dts                 |  4 ++--
>>  arch/arm/dts/imx6sx.dtsi                    | 12 +++++++-----
>>  board/freescale/mx6sxsabresd/mx6sxsabresd.c | 25 -------------------------
>>  configs/mx6sxsabresd_defconfig              |  7 +++++++
>>  include/configs/mx6sxsabresd.h              |  4 ++++
>>  5 files changed, 20 insertions(+), 32 deletions(-)
>>
>> diff --git a/arch/arm/dts/imx6sx-sdb.dts b/arch/arm/dts/imx6sx-sdb.dts
>> index 6dd9beb..a04b00d 100644
>> --- a/arch/arm/dts/imx6sx-sdb.dts
>> +++ b/arch/arm/dts/imx6sx-sdb.dts
>> @@ -115,7 +115,7 @@
>>         flash0: n25q256a at 0 {
>>                 #address-cells = <1>;
>>                 #size-cells = <1>;
>> -               compatible = "micron,n25q256a", "jedec,spi-nor";
>> +               compatible = "spi-flash";
>
> I don't see "spi-flash" compatible documented in the kernel bindings.
>
> Please clarify why we are deviating from Linux here.

We still not sync with Linux on this area, better to append or add
-u-boot.dtsi for this change. will remove once synced.

[U-Boot] [PATCH 1/2] imx: imx6sx-sdb: Enable DM QSPI driver

[Ye Li]

On 6/27/2018 6:28 PM, Jagan Teki wrote:
> On Wed, Jun 27, 2018 at 3:29 PM, Fabio Estevam <festevam@gmail.com> wrote:
>> Hi Ye Li,
>>
>> On Wed, Jun 27, 2018 at 3:48 AM, Ye Li <ye.li@nxp.com> wrote:
>>> To support DM QSPI driver
>>>  - Add spi0 and spi1 alias for qspi1 and qspi2.
>>>  - Modify n25q256a at 0 and n25q256a at 1 compatible string to "spi-flash"
>>>  - Enable DM SPI/QSPI relavent configurations
>>>  - Remove iomux settings of qspi2 in board codes which is not needed
>>>    for DM driver.
>>>  - Add sf default settings. So running "sf probe" can detect the flash
>>>
>>> Signed-off-by: Ye Li <ye.li@nxp.com>
>>> ---
>>>  arch/arm/dts/imx6sx-sdb.dts                 |  4 ++--
>>>  arch/arm/dts/imx6sx.dtsi                    | 12 +++++++-----
>>>  board/freescale/mx6sxsabresd/mx6sxsabresd.c | 25 -------------------------
>>>  configs/mx6sxsabresd_defconfig              |  7 +++++++
>>>  include/configs/mx6sxsabresd.h              |  4 ++++
>>>  5 files changed, 20 insertions(+), 32 deletions(-)
>>>
>>> diff --git a/arch/arm/dts/imx6sx-sdb.dts b/arch/arm/dts/imx6sx-sdb.dts
>>> index 6dd9beb..a04b00d 100644
>>> --- a/arch/arm/dts/imx6sx-sdb.dts
>>> +++ b/arch/arm/dts/imx6sx-sdb.dts
>>> @@ -115,7 +115,7 @@
>>>         flash0: n25q256a at 0 {
>>>                 #address-cells = <1>;
>>>                 #size-cells = <1>;
>>> -               compatible = "micron,n25q256a", "jedec,spi-nor";
>>> +               compatible = "spi-flash";
>>
>> I don't see "spi-flash" compatible documented in the kernel bindings.
>>
>> Please clarify why we are deviating from Linux here.
> 
> We still not sync with Linux on this area, better to append or add
> -u-boot.dtsi for this change. will remove once synced.
> 
I will move it to imx6sx-sdb-u-boot.dtsi in V2.

Best regards,
Ye Li

[U-Boot] [PATCH 1/2] imx: imx6sx-sdb: Enable DM QSPI driver

[Fabio Estevam]

Hi Jagan,

On Wed, Jun 27, 2018 at 7:27 AM, Jagan Teki <jagan@amarulasolutions.com> wrote:

> We still not sync with Linux on this area, better to append or add
> -u-boot.dtsi for this change. will remove once synced.

This is not good.

Why U-Boot needs its own spi flash bindings?

Why can't it use the same bindings used in the kernel?

[U-Boot] [PATCH 1/2] imx: imx6sx-sdb: Enable DM QSPI driver

[Jagan Teki]

On Wed, Jun 27, 2018 at 7:21 PM, Fabio Estevam <festevam@gmail.com> wrote:
> Hi Jagan,
>
> On Wed, Jun 27, 2018 at 7:27 AM, Jagan Teki <jagan@amarulasolutions.com> wrote:
>
>> We still not sync with Linux on this area, better to append or add
>> -u-boot.dtsi for this change. will remove once synced.
>
> This is not good.
>
> Why U-Boot needs its own spi flash bindings?

Since we have dm with spi-flash which is different in naming
convention when compared to Linux spi-nor so it is treated as
"spi-flash"

>
> Why can't it use the same bindings used in the kernel?

Yes, we are the process of syncing changes wrt dm, hopefully after
v2018.09. So Linux binding will update accordingly.

Jagan.

[U-Boot] [PATCH 1/2] imx: imx6sx-sdb: Enable DM QSPI driver

[Ye Li]

To support DM QSPI driver
 - Add spi0 and spi1 alias for qspi1 and qspi2.
 - Modify n25q256a at 0 and n25q256a at 1 compatible string to "spi-flash"
 - Enable DM SPI/QSPI relavent configurations
 - Remove iomux settings of qspi2 in board codes which is not needed
   for DM driver.
 - Add sf default settings. So running "sf probe" can detect the flash

Signed-off-by: Ye Li <ye.li@nxp.com>
---
 arch/arm/dts/imx6sx-sdb.dts                 |  4 ++--
 arch/arm/dts/imx6sx.dtsi                    | 12 +++++++-----
 board/freescale/mx6sxsabresd/mx6sxsabresd.c | 25 -------------------------
 configs/mx6sxsabresd_defconfig              |  7 +++++++
 include/configs/mx6sxsabresd.h              |  4 ++++
 5 files changed, 20 insertions(+), 32 deletions(-)

diff --git a/arch/arm/dts/imx6sx-sdb.dts b/arch/arm/dts/imx6sx-sdb.dts
index 6dd9beb..a04b00d 100644
--- a/arch/arm/dts/imx6sx-sdb.dts
+++ b/arch/arm/dts/imx6sx-sdb.dts
@@ -115,7 +115,7 @@
 	flash0: n25q256a at 0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "micron,n25q256a", "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <29000000>;
 		reg = <0>;
 	};
@@ -123,7 +123,7 @@
 	flash1: n25q256a at 1 {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "micron,n25q256a", "jedec,spi-nor";
+		compatible = "spi-flash";
 		spi-max-frequency = <29000000>;
 		reg = <1>;
 	};
diff --git a/arch/arm/dts/imx6sx.dtsi b/arch/arm/dts/imx6sx.dtsi
index 1a473e8..8ccf264 100644
--- a/arch/arm/dts/imx6sx.dtsi
+++ b/arch/arm/dts/imx6sx.dtsi
@@ -40,11 +40,13 @@
 		serial3 = &uart4;
 		serial4 = &uart5;
 		serial5 = &uart6;
-		spi0 = &ecspi1;
-		spi1 = &ecspi2;
-		spi2 = &ecspi3;
-		spi3 = &ecspi4;
-		spi4 = &ecspi5;
+		spi0 = &qspi1;
+		spi1 = &qspi2;
+		spi2 = &ecspi1;
+		spi3 = &ecspi2;
+		spi4 = &ecspi3;
+		spi5 = &ecspi4;
+		spi6 = &ecspi5;
 		usbphy0 = &usbphy1;
 		usbphy1 = &usbphy2;
 	};
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index d56e235..3e10c7f 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -205,33 +205,8 @@ int board_mmc_get_env_dev(int devno)
 
 #ifdef CONFIG_FSL_QSPI
 
-#define QSPI_PAD_CTRL1	\
-	(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
-	 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
-
-static iomux_v3_cfg_t const quadspi_pads[] = {
-	MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_ALE__QSPI2_A_SS0_B		| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_CLE__QSPI2_A_SCLK		| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_DATA07__QSPI2_A_DQS	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_DATA02__QSPI2_B_SCLK	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-	MX6_PAD_NAND_DATA05__QSPI2_B_DQS	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-};
-
 int board_qspi_init(void)
 {
-	/* Set the iomux */
-	imx_iomux_v3_setup_multiple_pads(quadspi_pads,
-					 ARRAY_SIZE(quadspi_pads));
-
 	/* Set the clock */
 	enable_qspi_clk(1);
 
diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig
index 6ea92bb..9e4b13b 100644
--- a/configs/mx6sxsabresd_defconfig
+++ b/configs/mx6sxsabresd_defconfig
@@ -14,6 +14,7 @@ CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_SF=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PART=y
 CONFIG_CMD_PCI=y
@@ -36,8 +37,14 @@ CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_FSL_QSPI=y
 CONFIG_PHYLIB=y
 CONFIG_PCI=y
 CONFIG_PINCTRL=y
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index f5ca2fc..4506acb 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -186,6 +186,10 @@
 #define FSL_QSPI_FLASH_SIZE		SZ_32M
 #endif
 #define FSL_QSPI_FLASH_NUM		2
+#define CONFIG_SF_DEFAULT_BUS		1
+#define CONFIG_SF_DEFAULT_CS		0
+#define CONFIG_SF_DEFAULT_SPEED	40000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #endif
 
 #ifndef CONFIG_SPL_BUILD
-- 
2.7.4