[U-Boot] [PATCH] ARM: mx6: Add support for Kosagi Novena

[Fabio Estevam <festevam@gmail.com>]

On Sat, Aug 30, 2014 at 11:22 AM, Marek Vasut <marex@denx.de> wrote:
> On Saturday, August 30, 2014 at 04:12:09 PM, Fabio Estevam wrote:
>> On Fri, Aug 29, 2014 at 6:30 AM, Marek Vasut <marex@denx.de> wrote:
>> > Add support for the Kosagi Novena board. Currently supported are:
>> > - I2C busses
>> > - FEC Ethernet
>> > - MMC0, MMC1, Booting from MMC
>> > - SATA
>> > - USB ports
>> > - USB Ethernet
>>
>> LVDS seems to be missing in the list.
>
> It's only HDMI that is supported right now.

In this case you don't need to turn on the LVDS clocks then:

+       /* Turn on LDB0,IPU,IPU DI0 clocks */
+       setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
+
+       /* set LDB0, LDB1 clk select to 011/011 */
+       clrsetbits_le32(&mxc_ccm->
cs2cdr,
+                       MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
+                       MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK,
+                       (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
+                       (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET));
+
+       setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+
+       setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 <<
+                    MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+
+       writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
+              IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
+              IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
+              IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
+              IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
+              IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+              IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
+              IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
+              IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
+              &iomux->gpr[2]);
+
+       clrsetbits_le32(&iomux->gpr[3], IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
+                       IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+                       IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)