From: Fabio Estevam <festevam@gmail.com>
To: Dong Aisheng <dongas86@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>, Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <kernel@pengutronix.de>,
Stephen Boyd <sboyd@codeaurora.org>,
Dong Aisheng <aisheng.dong@nxp.com>,
Fabio Estevam <fabio.estevam@nxp.com>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
linux-clk@vger.kernel.org,
linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/2] ARM: dts: imx7: add USDHC NAND clock to SDHC instances
Date: Tue, 11 Apr 2017 20:23:19 -0300 [thread overview]
Message-ID: <CAOMZO5DOib3PfCOQ-yqKAJnKRJZ2eBnMJnA84y=sv+vsYdbbBQ@mail.gmail.com> (raw)
In-Reply-To: <20170411025956.GA9067@b29396-OptiPlex-7040>
On Mon, Apr 10, 2017 at 11:59 PM, Dong Aisheng <dongas86@gmail.com> wrote:
> This is caused by ahb_root_clk gets disabled accidently and system hangs.
>
> Because this patch defines ipg_root_clk earlier before its parent
> (ahb_root_clk) got registered, then it will be marked as a orphan clk
> temporarily. Until the parent ahb_root_clk got registered, the clk core
> will reparent it to the newly found parent. (see __clk_core_init() function).
>
> Due to CLK_SET_RATE_PARENT flag, the ahb clk will be enabled during
> set_parent operation and then disabled after that.
> Then system hang cause we still get no chance to run init_on clks.
>
> I just send out a proper fix patch with correct register sequence.
Excellent, thanks!
WARNING: multiple messages have this Message-ID (diff)
From: Fabio Estevam <festevam@gmail.com>
To: Dong Aisheng <dongas86@gmail.com>
Cc: Dong Aisheng <aisheng.dong@nxp.com>,
Mark Rutland <mark.rutland@arm.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
Stephen Boyd <sboyd@codeaurora.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
Stefan Agner <stefan@agner.ch>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
Sascha Hauer <kernel@pengutronix.de>,
Fabio Estevam <fabio.estevam@nxp.com>,
Shawn Guo <shawnguo@kernel.org>,
linux-clk@vger.kernel.org,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 2/2] ARM: dts: imx7: add USDHC NAND clock to SDHC instances
Date: Tue, 11 Apr 2017 20:23:19 -0300 [thread overview]
Message-ID: <CAOMZO5DOib3PfCOQ-yqKAJnKRJZ2eBnMJnA84y=sv+vsYdbbBQ@mail.gmail.com> (raw)
In-Reply-To: <20170411025956.GA9067@b29396-OptiPlex-7040>
On Mon, Apr 10, 2017 at 11:59 PM, Dong Aisheng <dongas86@gmail.com> wrote:
> This is caused by ahb_root_clk gets disabled accidently and system hangs.
>
> Because this patch defines ipg_root_clk earlier before its parent
> (ahb_root_clk) got registered, then it will be marked as a orphan clk
> temporarily. Until the parent ahb_root_clk got registered, the clk core
> will reparent it to the newly found parent. (see __clk_core_init() function).
>
> Due to CLK_SET_RATE_PARENT flag, the ahb clk will be enabled during
> set_parent operation and then disabled after that.
> Then system hang cause we still get no chance to run init_on clks.
>
> I just send out a proper fix patch with correct register sequence.
Excellent, thanks!
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: festevam@gmail.com (Fabio Estevam)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/2] ARM: dts: imx7: add USDHC NAND clock to SDHC instances
Date: Tue, 11 Apr 2017 20:23:19 -0300 [thread overview]
Message-ID: <CAOMZO5DOib3PfCOQ-yqKAJnKRJZ2eBnMJnA84y=sv+vsYdbbBQ@mail.gmail.com> (raw)
In-Reply-To: <20170411025956.GA9067@b29396-OptiPlex-7040>
On Mon, Apr 10, 2017 at 11:59 PM, Dong Aisheng <dongas86@gmail.com> wrote:
> This is caused by ahb_root_clk gets disabled accidently and system hangs.
>
> Because this patch defines ipg_root_clk earlier before its parent
> (ahb_root_clk) got registered, then it will be marked as a orphan clk
> temporarily. Until the parent ahb_root_clk got registered, the clk core
> will reparent it to the newly found parent. (see __clk_core_init() function).
>
> Due to CLK_SET_RATE_PARENT flag, the ahb clk will be enabled during
> set_parent operation and then disabled after that.
> Then system hang cause we still get no chance to run init_on clks.
>
> I just send out a proper fix patch with correct register sequence.
Excellent, thanks!
next prev parent reply other threads:[~2017-04-11 23:23 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-30 0:50 [PATCH 1/2] clk: imx7d: fix USDHC NAND clock Stefan Agner
2017-03-30 0:50 ` Stefan Agner
2017-03-30 0:50 ` Stefan Agner
2017-03-30 0:50 ` [PATCH 2/2] ARM: dts: imx7: add USDHC NAND clock to SDHC instances Stefan Agner
2017-03-30 0:50 ` Stefan Agner
2017-04-01 3:03 ` Dong Aisheng
2017-04-01 3:03 ` Dong Aisheng
2017-04-01 3:03 ` Dong Aisheng
2017-04-01 4:15 ` Stefan Agner
2017-04-01 4:15 ` Stefan Agner
2017-04-01 4:15 ` Stefan Agner
2017-04-02 17:02 ` Fabio Estevam
2017-04-02 17:02 ` Fabio Estevam
2017-04-02 17:02 ` Fabio Estevam
2017-04-02 17:02 ` Fabio Estevam
2017-04-05 2:15 ` Fabio Estevam
2017-04-05 2:15 ` Fabio Estevam
2017-04-05 2:15 ` Fabio Estevam
2017-04-05 2:15 ` Fabio Estevam
2017-04-05 2:36 ` Stefan Agner
2017-04-05 2:36 ` Stefan Agner
2017-04-05 2:36 ` Stefan Agner
2017-04-11 2:59 ` Dong Aisheng
2017-04-11 2:59 ` Dong Aisheng
2017-04-11 23:23 ` Fabio Estevam [this message]
2017-04-11 23:23 ` Fabio Estevam
2017-04-11 23:23 ` Fabio Estevam
2017-04-11 23:23 ` Fabio Estevam
2017-04-01 3:00 ` [PATCH 1/2] clk: imx7d: fix USDHC NAND clock Dong Aisheng
2017-04-01 3:00 ` Dong Aisheng
2017-04-01 3:00 ` Dong Aisheng
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