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From: Fabio Estevam <festevam@gmail.com>
To: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>,
	Nikita Yushchenko <nikita.yoush@cogentembedded.com>,
	Mark Rutland <mark.rutland@arm.com>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
	<devicetree@vger.kernel.org>,
	linux-kernel <linux-kernel@vger.kernel.org>,
	Rob Herring <robh+dt@kernel.org>, Andrew Lunn <andrew@lunn.ch>,
	"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
	<linux-arm-kernel@lists.infradead.org>,
	Fabio Estevam <fabio.estevam@nxp.com>,
	Chris Healy <cphealy@gmail.com>,
	Lucas Stach <l.stach@pengutronix.de>
Subject: Re: [PATCH 1/2] ARM: dts: imx51-zii-scu3-esb: Add switch IRQ line pinumx config
Date: Thu, 12 Jul 2018 10:37:47 -0300	[thread overview]
Message-ID: <CAOMZO5DfHqKjF6xykJtoC-aA-ATWM6mCZR0VzPVpSDOt-Fs6bQ@mail.gmail.com> (raw)
In-Reply-To: <20180712023337.30112-2-andrew.smirnov@gmail.com>

Hi Andrey,

On Wed, Jul 11, 2018 at 11:33 PM, Andrey Smirnov
<andrew.smirnov@gmail.com> wrote:

> +       pinctrl_switch: switchgrp {
> +               fsl,pins = <
> +                       MX51_PAD_AUD3_BB_CK__GPIO4_20           0xc5

The i.MX51 Reference Manual states that 0xa5 is the default reset
value for the register IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_CK.

By reading your commit log I had the impression you wanted to provide
the default value explicitly.

Please clarify.

WARNING: multiple messages have this Message-ID (diff)
From: festevam@gmail.com (Fabio Estevam)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/2] ARM: dts: imx51-zii-scu3-esb: Add switch IRQ line pinumx config
Date: Thu, 12 Jul 2018 10:37:47 -0300	[thread overview]
Message-ID: <CAOMZO5DfHqKjF6xykJtoC-aA-ATWM6mCZR0VzPVpSDOt-Fs6bQ@mail.gmail.com> (raw)
In-Reply-To: <20180712023337.30112-2-andrew.smirnov@gmail.com>

Hi Andrey,

On Wed, Jul 11, 2018 at 11:33 PM, Andrey Smirnov
<andrew.smirnov@gmail.com> wrote:

> +       pinctrl_switch: switchgrp {
> +               fsl,pins = <
> +                       MX51_PAD_AUD3_BB_CK__GPIO4_20           0xc5

The i.MX51 Reference Manual states that 0xa5 is the default reset
value for the register IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_CK.

By reading your commit log I had the impression you wanted to provide
the default value explicitly.

Please clarify.

  parent reply	other threads:[~2018-07-12 13:37 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-12  2:33 [PATCH 0/2] Follow up fixes for SCU3 ESB Andrey Smirnov
2018-07-12  2:33 ` Andrey Smirnov
2018-07-12  2:33 ` [PATCH 1/2] ARM: dts: imx51-zii-scu3-esb: Add switch IRQ line pinumx config Andrey Smirnov
2018-07-12  2:33   ` Andrey Smirnov
2018-07-12 13:30   ` Andrew Lunn
2018-07-12 13:30     ` Andrew Lunn
2018-07-12 13:37   ` Fabio Estevam [this message]
2018-07-12 13:37     ` Fabio Estevam
2018-07-12 13:37     ` Fabio Estevam
2018-07-13  5:15     ` Andrey Smirnov
2018-07-13  5:15       ` Andrey Smirnov
2018-07-13  5:15       ` Andrey Smirnov
2018-07-13 11:02       ` Fabio Estevam
2018-07-13 11:02         ` Fabio Estevam
2018-07-13 11:02         ` Fabio Estevam
2018-07-12  2:33 ` [PATCH 2/2] ARM: dts: imx51-zii-scu3-esb: Fix RAVE SP watchdog compatible string Andrey Smirnov
2018-07-12  2:33   ` Andrey Smirnov
2018-07-12 17:15   ` Chris Healy
2018-07-12 17:15     ` Chris Healy

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