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From: Fabio Estevam <festevam@gmail.com>
To: Abel Vesa <abel.vesa@nxp.com>
Cc: Mike Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
	Sascha Hauer <kernel@pengutronix.de>,
	Fabio Estevam <fabio.estevam@nxp.com>,
	Peng Fan <peng.fan@nxp.com>, Dong Aisheng <aisheng.dong@nxp.com>,
	Anson Huang <anson.huang@nxp.com>,
	Lucas Stach <l.stach@pengutronix.de>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	linux-clk <linux-clk@vger.kernel.org>,
	"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
	<linux-arm-kernel@lists.infradead.org>,
	NXP Linux Team <linux-imx@nxp.com>
Subject: Re: [PATCH] clk: imx8mq: Fix usdhc parents order
Date: Thu, 15 Oct 2020 08:22:28 -0300	[thread overview]
Message-ID: <CAOMZO5DxZN_cniuy2xhYGWAr3rjNBZNJAJvYcH+KNBa+S7S2mg@mail.gmail.com> (raw)
In-Reply-To: <1602753944-30757-1-git-send-email-abel.vesa@nxp.com>

Hi Abel,

On Thu, Oct 15, 2020 at 6:26 AM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> According to the latest RM (see Table 5-1. Clock Root Table),
> both usdhc root clocks have the parent order as follows:
>
> 000 - 25M_REF_CLK
> 001 - SYSTEM_PLL1_DIV2
> 010 - SYSTEM_PLL1_CLK
> 011 - SYSTEM_PLL2_DIV2
> 100 - SYSTEM_PLL3_CLK
> 101 - SYSTEM_PLL1_DIV3
> 110 - AUDIO_PLL2_CLK
> 111 - SYSTEM_PLL1_DIV8
>
> So the audio_pll2_out and sys3_pll_out have to be swapped.
>
> Fixes: b80522040cd3 ("clk: imx: Add clock driver for i.MX8MQ CCM")
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reported-by: Cosmin Stefan Stoica <cosmin.stoica@nxp.com>

Thanks for the fix:

Reviewed-by: Fabio Estevam <festevam@gmail.com>

WARNING: multiple messages have this Message-ID (diff)
From: Fabio Estevam <festevam@gmail.com>
To: Abel Vesa <abel.vesa@nxp.com>
Cc: Dong Aisheng <aisheng.dong@nxp.com>, Peng Fan <peng.fan@nxp.com>,
	Anson Huang <anson.huang@nxp.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Mike Turquette <mturquette@baylibre.com>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	NXP Linux Team <linux-imx@nxp.com>,
	Sascha Hauer <kernel@pengutronix.de>,
	Fabio Estevam <fabio.estevam@nxp.com>,
	Shawn Guo <shawnguo@kernel.org>,
	linux-clk <linux-clk@vger.kernel.org>,
	"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
	<linux-arm-kernel@lists.infradead.org>,
	Lucas Stach <l.stach@pengutronix.de>
Subject: Re: [PATCH] clk: imx8mq: Fix usdhc parents order
Date: Thu, 15 Oct 2020 08:22:28 -0300	[thread overview]
Message-ID: <CAOMZO5DxZN_cniuy2xhYGWAr3rjNBZNJAJvYcH+KNBa+S7S2mg@mail.gmail.com> (raw)
In-Reply-To: <1602753944-30757-1-git-send-email-abel.vesa@nxp.com>

Hi Abel,

On Thu, Oct 15, 2020 at 6:26 AM Abel Vesa <abel.vesa@nxp.com> wrote:
>
> According to the latest RM (see Table 5-1. Clock Root Table),
> both usdhc root clocks have the parent order as follows:
>
> 000 - 25M_REF_CLK
> 001 - SYSTEM_PLL1_DIV2
> 010 - SYSTEM_PLL1_CLK
> 011 - SYSTEM_PLL2_DIV2
> 100 - SYSTEM_PLL3_CLK
> 101 - SYSTEM_PLL1_DIV3
> 110 - AUDIO_PLL2_CLK
> 111 - SYSTEM_PLL1_DIV8
>
> So the audio_pll2_out and sys3_pll_out have to be swapped.
>
> Fixes: b80522040cd3 ("clk: imx: Add clock driver for i.MX8MQ CCM")
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Reported-by: Cosmin Stefan Stoica <cosmin.stoica@nxp.com>

Thanks for the fix:

Reviewed-by: Fabio Estevam <festevam@gmail.com>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2020-10-15 11:22 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-15  9:25 [PATCH] clk: imx8mq: Fix usdhc parents order Abel Vesa
2020-10-15  9:25 ` Abel Vesa
2020-10-15 11:22 ` Fabio Estevam [this message]
2020-10-15 11:22   ` Fabio Estevam
2020-10-20 16:29 ` Stephen Boyd
2020-10-20 16:29   ` Stephen Boyd

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